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2b511edb SN |
1 | /* |
2 | * Register interface file for EXYNOS FIMC-LITE (camera interface) driver | |
3 | * | |
4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. | |
086eca29 | 5 | * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> |
2b511edb SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
086eca29 | 12 | #include <linux/bitops.h> |
2b511edb | 13 | #include <linux/delay.h> |
086eca29 | 14 | #include <linux/io.h> |
2b511edb SN |
15 | #include <media/s5p_fimc.h> |
16 | ||
17 | #include "fimc-lite-reg.h" | |
18 | #include "fimc-lite.h" | |
19 | #include "fimc-core.h" | |
20 | ||
21 | #define FLITE_RESET_TIMEOUT 50 /* in ms */ | |
22 | ||
23 | void flite_hw_reset(struct fimc_lite *dev) | |
24 | { | |
25 | unsigned long end = jiffies + msecs_to_jiffies(FLITE_RESET_TIMEOUT); | |
26 | u32 cfg; | |
27 | ||
28 | cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
29 | cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; | |
30 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
31 | ||
32 | while (time_is_after_jiffies(end)) { | |
33 | cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
34 | if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) | |
35 | break; | |
36 | usleep_range(1000, 5000); | |
37 | } | |
38 | ||
39 | cfg |= FLITE_REG_CIGCTRL_SWRST; | |
40 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
41 | } | |
42 | ||
43 | void flite_hw_clear_pending_irq(struct fimc_lite *dev) | |
44 | { | |
45 | u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); | |
46 | cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; | |
47 | writel(cfg, dev->regs + FLITE_REG_CISTATUS); | |
48 | } | |
49 | ||
50 | u32 flite_hw_get_interrupt_source(struct fimc_lite *dev) | |
51 | { | |
52 | u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); | |
53 | return intsrc & FLITE_REG_CISTATUS_IRQ_MASK; | |
54 | } | |
55 | ||
56 | void flite_hw_clear_last_capture_end(struct fimc_lite *dev) | |
57 | { | |
58 | ||
59 | u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); | |
60 | cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND; | |
61 | writel(cfg, dev->regs + FLITE_REG_CISTATUS2); | |
62 | } | |
63 | ||
64 | void flite_hw_set_interrupt_mask(struct fimc_lite *dev) | |
65 | { | |
66 | u32 cfg, intsrc; | |
67 | ||
68 | /* Select interrupts to be enabled for each output mode */ | |
03878bb4 | 69 | if (atomic_read(&dev->out_path) == FIMC_IO_DMA) { |
2b511edb SN |
70 | intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN | |
71 | FLITE_REG_CIGCTRL_IRQ_LASTEN | | |
086eca29 SN |
72 | FLITE_REG_CIGCTRL_IRQ_STARTEN | |
73 | FLITE_REG_CIGCTRL_IRQ_ENDEN; | |
2b511edb SN |
74 | } else { |
75 | /* An output to the FIMC-IS */ | |
76 | intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN | | |
77 | FLITE_REG_CIGCTRL_IRQ_LASTEN; | |
78 | } | |
79 | ||
80 | cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
81 | cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK; | |
82 | cfg &= ~intsrc; | |
83 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
84 | } | |
85 | ||
86 | void flite_hw_capture_start(struct fimc_lite *dev) | |
87 | { | |
88 | u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); | |
89 | cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN; | |
90 | writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); | |
91 | } | |
92 | ||
93 | void flite_hw_capture_stop(struct fimc_lite *dev) | |
94 | { | |
95 | u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); | |
96 | cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN; | |
97 | writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); | |
98 | } | |
99 | ||
100 | /* | |
101 | * Test pattern (color bars) enable/disable. External sensor | |
102 | * pixel clock must be active for the test pattern to work. | |
103 | */ | |
104 | void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on) | |
105 | { | |
106 | u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
107 | if (on) | |
108 | cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR; | |
109 | else | |
110 | cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR; | |
111 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
112 | } | |
113 | ||
114 | static const u32 src_pixfmt_map[8][3] = { | |
115 | { V4L2_MBUS_FMT_YUYV8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR, | |
116 | FLITE_REG_CIGCTRL_YUV422_1P }, | |
117 | { V4L2_MBUS_FMT_YVYU8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB, | |
118 | FLITE_REG_CIGCTRL_YUV422_1P }, | |
119 | { V4L2_MBUS_FMT_UYVY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY, | |
120 | FLITE_REG_CIGCTRL_YUV422_1P }, | |
121 | { V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY, | |
122 | FLITE_REG_CIGCTRL_YUV422_1P }, | |
b98192cb SN |
123 | { V4L2_MBUS_FMT_SGRBG8_1X8, 0, FLITE_REG_CIGCTRL_RAW8 }, |
124 | { V4L2_MBUS_FMT_SGRBG10_1X10, 0, FLITE_REG_CIGCTRL_RAW10 }, | |
125 | { V4L2_MBUS_FMT_SGRBG12_1X12, 0, FLITE_REG_CIGCTRL_RAW12 }, | |
2b511edb SN |
126 | { V4L2_MBUS_FMT_JPEG_1X8, 0, FLITE_REG_CIGCTRL_USER(1) }, |
127 | }; | |
128 | ||
129 | /* Set camera input pixel format and resolution */ | |
130 | void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f) | |
131 | { | |
e90ad659 | 132 | enum v4l2_mbus_pixelcode pixelcode = f->fmt->mbus_code; |
6a536096 | 133 | int i = ARRAY_SIZE(src_pixfmt_map); |
2b511edb SN |
134 | u32 cfg; |
135 | ||
6a536096 | 136 | while (--i >= 0) { |
2b511edb SN |
137 | if (src_pixfmt_map[i][0] == pixelcode) |
138 | break; | |
139 | } | |
140 | ||
141 | if (i == 0 && src_pixfmt_map[i][0] != pixelcode) { | |
bc7584b0 | 142 | v4l2_err(&dev->ve.vdev, |
2b511edb SN |
143 | "Unsupported pixel code, falling back to %#08x\n", |
144 | src_pixfmt_map[i][0]); | |
145 | } | |
146 | ||
147 | cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
148 | cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK; | |
149 | cfg |= src_pixfmt_map[i][2]; | |
150 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
151 | ||
152 | cfg = readl(dev->regs + FLITE_REG_CISRCSIZE); | |
153 | cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK | | |
154 | FLITE_REG_CISRCSIZE_SIZE_CAM_MASK); | |
155 | cfg |= (f->f_width << 16) | f->f_height; | |
156 | cfg |= src_pixfmt_map[i][1]; | |
157 | writel(cfg, dev->regs + FLITE_REG_CISRCSIZE); | |
158 | } | |
159 | ||
160 | /* Set the camera host input window offsets (cropping) */ | |
161 | void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f) | |
162 | { | |
163 | u32 hoff2, voff2; | |
164 | u32 cfg; | |
165 | ||
166 | cfg = readl(dev->regs + FLITE_REG_CIWDOFST); | |
167 | cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK; | |
168 | cfg |= (f->rect.left << 16) | f->rect.top; | |
169 | cfg |= FLITE_REG_CIWDOFST_WINOFSEN; | |
170 | writel(cfg, dev->regs + FLITE_REG_CIWDOFST); | |
171 | ||
172 | hoff2 = f->f_width - f->rect.width - f->rect.left; | |
173 | voff2 = f->f_height - f->rect.height - f->rect.top; | |
174 | ||
175 | cfg = (hoff2 << 16) | voff2; | |
176 | writel(cfg, dev->regs + FLITE_REG_CIWDOFST2); | |
177 | } | |
178 | ||
179 | /* Select camera port (A, B) */ | |
180 | static void flite_hw_set_camera_port(struct fimc_lite *dev, int id) | |
181 | { | |
182 | u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL); | |
183 | if (id == 0) | |
184 | cfg &= ~FLITE_REG_CIGENERAL_CAM_B; | |
185 | else | |
186 | cfg |= FLITE_REG_CIGENERAL_CAM_B; | |
187 | writel(cfg, dev->regs + FLITE_REG_CIGENERAL); | |
188 | } | |
189 | ||
190 | /* Select serial or parallel bus, camera port (A,B) and set signals polarity */ | |
191 | void flite_hw_set_camera_bus(struct fimc_lite *dev, | |
56bc911a | 192 | struct fimc_source_info *si) |
2b511edb SN |
193 | { |
194 | u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
56bc911a | 195 | unsigned int flags = si->flags; |
2b511edb | 196 | |
56bc911a | 197 | if (si->sensor_bus_type != FIMC_BUS_TYPE_MIPI_CSI2) { |
2b511edb SN |
198 | cfg &= ~(FLITE_REG_CIGCTRL_SELCAM_MIPI | |
199 | FLITE_REG_CIGCTRL_INVPOLPCLK | | |
200 | FLITE_REG_CIGCTRL_INVPOLVSYNC | | |
201 | FLITE_REG_CIGCTRL_INVPOLHREF); | |
202 | ||
203 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
204 | cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK; | |
205 | ||
206 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) | |
207 | cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC; | |
208 | ||
209 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | |
210 | cfg |= FLITE_REG_CIGCTRL_INVPOLHREF; | |
211 | } else { | |
212 | cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI; | |
213 | } | |
214 | ||
215 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
216 | ||
56bc911a | 217 | flite_hw_set_camera_port(dev, si->mux_id); |
2b511edb SN |
218 | } |
219 | ||
086eca29 SN |
220 | static void flite_hw_set_pack12(struct fimc_lite *dev, int on) |
221 | { | |
222 | u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); | |
223 | ||
224 | cfg &= ~FLITE_REG_CIODMAFMT_PACK12; | |
225 | ||
226 | if (on) | |
227 | cfg |= FLITE_REG_CIODMAFMT_PACK12; | |
228 | ||
229 | writel(cfg, dev->regs + FLITE_REG_CIODMAFMT); | |
230 | } | |
231 | ||
7e566be2 | 232 | static void flite_hw_set_out_order(struct fimc_lite *dev, struct flite_frame *f) |
2b511edb SN |
233 | { |
234 | static const u32 pixcode[4][2] = { | |
235 | { V4L2_MBUS_FMT_YUYV8_2X8, FLITE_REG_CIODMAFMT_YCBYCR }, | |
236 | { V4L2_MBUS_FMT_YVYU8_2X8, FLITE_REG_CIODMAFMT_YCRYCB }, | |
237 | { V4L2_MBUS_FMT_UYVY8_2X8, FLITE_REG_CIODMAFMT_CBYCRY }, | |
238 | { V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CIODMAFMT_CRYCBY }, | |
239 | }; | |
240 | u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); | |
6a536096 | 241 | int i = ARRAY_SIZE(pixcode); |
2b511edb | 242 | |
6a536096 | 243 | while (--i >= 0) |
e90ad659 | 244 | if (pixcode[i][0] == f->fmt->mbus_code) |
2b511edb SN |
245 | break; |
246 | cfg &= ~FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK; | |
247 | writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT); | |
248 | } | |
249 | ||
250 | void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f) | |
251 | { | |
252 | u32 cfg; | |
253 | ||
254 | /* Maximum output pixel size */ | |
255 | cfg = readl(dev->regs + FLITE_REG_CIOCAN); | |
256 | cfg &= ~FLITE_REG_CIOCAN_MASK; | |
257 | cfg = (f->f_height << 16) | f->f_width; | |
258 | writel(cfg, dev->regs + FLITE_REG_CIOCAN); | |
259 | ||
260 | /* DMA offsets */ | |
261 | cfg = readl(dev->regs + FLITE_REG_CIOOFF); | |
262 | cfg &= ~FLITE_REG_CIOOFF_MASK; | |
263 | cfg |= (f->rect.top << 16) | f->rect.left; | |
264 | writel(cfg, dev->regs + FLITE_REG_CIOOFF); | |
265 | } | |
266 | ||
086eca29 SN |
267 | void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf) |
268 | { | |
269 | unsigned int index; | |
270 | u32 cfg; | |
271 | ||
272 | if (dev->dd->max_dma_bufs == 1) | |
273 | index = 0; | |
274 | else | |
275 | index = buf->index; | |
276 | ||
277 | if (index == 0) | |
278 | writel(buf->paddr, dev->regs + FLITE_REG_CIOSA); | |
279 | else | |
280 | writel(buf->paddr, dev->regs + FLITE_REG_CIOSAN(index - 1)); | |
281 | ||
282 | cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ); | |
283 | cfg |= BIT(index); | |
284 | writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); | |
285 | } | |
286 | ||
287 | void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index) | |
288 | { | |
289 | u32 cfg; | |
290 | ||
291 | if (dev->dd->max_dma_bufs == 1) | |
292 | index = 0; | |
293 | ||
294 | cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ); | |
295 | cfg &= ~BIT(index); | |
296 | writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); | |
297 | } | |
298 | ||
2b511edb SN |
299 | /* Enable/disable output DMA, set output pixel size and offsets (composition) */ |
300 | void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f, | |
301 | bool enable) | |
302 | { | |
303 | u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); | |
304 | ||
305 | if (!enable) { | |
306 | cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE; | |
307 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
308 | return; | |
309 | } | |
310 | ||
311 | cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE; | |
312 | writel(cfg, dev->regs + FLITE_REG_CIGCTRL); | |
313 | ||
314 | flite_hw_set_out_order(dev, f); | |
315 | flite_hw_set_dma_window(dev, f); | |
086eca29 | 316 | flite_hw_set_pack12(dev, 0); |
2b511edb SN |
317 | } |
318 | ||
319 | void flite_hw_dump_regs(struct fimc_lite *dev, const char *label) | |
320 | { | |
321 | struct { | |
322 | u32 offset; | |
323 | const char * const name; | |
324 | } registers[] = { | |
325 | { 0x00, "CISRCSIZE" }, | |
326 | { 0x04, "CIGCTRL" }, | |
327 | { 0x08, "CIIMGCPT" }, | |
328 | { 0x0c, "CICPTSEQ" }, | |
329 | { 0x10, "CIWDOFST" }, | |
330 | { 0x14, "CIWDOFST2" }, | |
331 | { 0x18, "CIODMAFMT" }, | |
332 | { 0x20, "CIOCAN" }, | |
333 | { 0x24, "CIOOFF" }, | |
334 | { 0x30, "CIOSA" }, | |
335 | { 0x40, "CISTATUS" }, | |
336 | { 0x44, "CISTATUS2" }, | |
337 | { 0xf0, "CITHOLD" }, | |
338 | { 0xfc, "CIGENERAL" }, | |
339 | }; | |
340 | u32 i; | |
341 | ||
a62082ff SN |
342 | v4l2_info(&dev->subdev, "--- %s ---\n", label); |
343 | ||
2b511edb SN |
344 | for (i = 0; i < ARRAY_SIZE(registers); i++) { |
345 | u32 cfg = readl(dev->regs + registers[i].offset); | |
a62082ff SN |
346 | v4l2_info(&dev->subdev, "%9s: 0x%08x\n", |
347 | registers[i].name, cfg); | |
2b511edb SN |
348 | } |
349 | } |