Commit | Line | Data |
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b5f1220d SN |
1 | /* |
2 | * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver | |
3 | * | |
a1212162 | 4 | * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd. |
29de2337 | 5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> |
b5f1220d SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/memory.h> | |
21 | #include <linux/module.h> | |
02399e35 SN |
22 | #include <linux/of.h> |
23 | #include <linux/platform_data/mipi-csis.h> | |
b5f1220d SN |
24 | #include <linux/platform_device.h> |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/regulator/consumer.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/videodev2.h> | |
02399e35 SN |
30 | #include <media/s5p_fimc.h> |
31 | #include <media/v4l2-of.h> | |
b5f1220d | 32 | #include <media/v4l2-subdev.h> |
02399e35 | 33 | |
b5f1220d SN |
34 | #include "mipi-csis.h" |
35 | ||
36 | static int debug; | |
37 | module_param(debug, int, 0644); | |
99c6902c | 38 | MODULE_PARM_DESC(debug, "Debug level (0-2)"); |
b5f1220d SN |
39 | |
40 | /* Register map definition */ | |
41 | ||
42 | /* CSIS global control */ | |
43 | #define S5PCSIS_CTRL 0x00 | |
44 | #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31) | |
45 | #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31) | |
46 | #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20) | |
47 | #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16) | |
48 | #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8) | |
49 | #define S5PCSIS_CTRL_RESET (1 << 4) | |
50 | #define S5PCSIS_CTRL_ENABLE (1 << 0) | |
51 | ||
52 | /* D-PHY control */ | |
53 | #define S5PCSIS_DPHYCTRL 0x04 | |
54 | #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27) | |
55 | #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0) | |
56 | ||
57 | #define S5PCSIS_CONFIG 0x08 | |
58 | #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2) | |
59 | #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2) | |
60 | #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2) | |
61 | #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2) | |
62 | /* User defined formats, x = 1...4 */ | |
63 | #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2) | |
64 | #define S5PCSIS_CFG_FMT_MASK (0x3f << 2) | |
65 | #define S5PCSIS_CFG_NR_LANE_MASK 3 | |
66 | ||
99c6902c | 67 | /* Interrupt mask */ |
b5f1220d | 68 | #define S5PCSIS_INTMSK 0x10 |
99c6902c SN |
69 | #define S5PCSIS_INTMSK_EN_ALL 0xf000103f |
70 | #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31) | |
71 | #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30) | |
72 | #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29) | |
73 | #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28) | |
74 | #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12) | |
75 | #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5) | |
76 | #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4) | |
77 | #define S5PCSIS_INTMSK_ERR_OVER (1 << 3) | |
78 | #define S5PCSIS_INTMSK_ERR_ECC (1 << 2) | |
79 | #define S5PCSIS_INTMSK_ERR_CRC (1 << 1) | |
80 | #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0) | |
81 | ||
82 | /* Interrupt source */ | |
b5f1220d | 83 | #define S5PCSIS_INTSRC 0x14 |
99c6902c SN |
84 | #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31) |
85 | #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30) | |
86 | #define S5PCSIS_INTSRC_EVEN (0x3 << 30) | |
87 | #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29) | |
88 | #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28) | |
89 | #define S5PCSIS_INTSRC_ODD (0x3 << 28) | |
90 | #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28) | |
91 | #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12) | |
92 | #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5) | |
93 | #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4) | |
94 | #define S5PCSIS_INTSRC_ERR_OVER (1 << 3) | |
95 | #define S5PCSIS_INTSRC_ERR_ECC (1 << 2) | |
96 | #define S5PCSIS_INTSRC_ERR_CRC (1 << 1) | |
97 | #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0) | |
98 | #define S5PCSIS_INTSRC_ERRORS 0xf03f | |
b5f1220d SN |
99 | |
100 | /* Pixel resolution */ | |
101 | #define S5PCSIS_RESOL 0x2c | |
102 | #define CSIS_MAX_PIX_WIDTH 0xffff | |
103 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
104 | ||
36fa8092 SN |
105 | /* Non-image packet data buffers */ |
106 | #define S5PCSIS_PKTDATA_ODD 0x2000 | |
107 | #define S5PCSIS_PKTDATA_EVEN 0x3000 | |
108 | #define S5PCSIS_PKTDATA_SIZE SZ_4K | |
109 | ||
b5f1220d SN |
110 | enum { |
111 | CSIS_CLK_MUX, | |
112 | CSIS_CLK_GATE, | |
113 | }; | |
114 | ||
115 | static char *csi_clock_name[] = { | |
116 | [CSIS_CLK_MUX] = "sclk_csis", | |
117 | [CSIS_CLK_GATE] = "csis", | |
118 | }; | |
119 | #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name) | |
02399e35 | 120 | #define DEFAULT_SCLK_CSIS_FREQ 166000000UL |
b5f1220d | 121 | |
438df3eb | 122 | static const char * const csis_supply_name[] = { |
29de2337 SN |
123 | "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */ |
124 | "vddio", /* CSIS I/O and PLL (1.8V) supply */ | |
438df3eb SN |
125 | }; |
126 | #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name) | |
127 | ||
b5f1220d SN |
128 | enum { |
129 | ST_POWERED = 1, | |
130 | ST_STREAMING = 2, | |
131 | ST_SUSPENDED = 4, | |
132 | }; | |
133 | ||
99c6902c SN |
134 | struct s5pcsis_event { |
135 | u32 mask; | |
136 | const char * const name; | |
137 | unsigned int counter; | |
138 | }; | |
139 | ||
140 | static const struct s5pcsis_event s5pcsis_events[] = { | |
141 | /* Errors */ | |
142 | { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" }, | |
143 | { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" }, | |
144 | { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" }, | |
145 | { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" }, | |
146 | { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" }, | |
147 | { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" }, | |
148 | { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" }, | |
149 | /* Non-image data receive events */ | |
150 | { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" }, | |
151 | { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" }, | |
152 | { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" }, | |
153 | { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" }, | |
154 | }; | |
155 | #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events) | |
156 | ||
36fa8092 SN |
157 | struct csis_pktbuf { |
158 | u32 *data; | |
159 | unsigned int len; | |
160 | }; | |
161 | ||
b5f1220d SN |
162 | /** |
163 | * struct csis_state - the driver's internal state data structure | |
164 | * @lock: mutex serializing the subdev and power management operations, | |
165 | * protecting @format and @flags members | |
166 | * @pads: CSIS pads array | |
167 | * @sd: v4l2_subdev associated with CSIS device instance | |
ccbfd1d4 | 168 | * @index: the hardware instance index |
b5f1220d | 169 | * @pdev: CSIS platform device |
b5f1220d | 170 | * @regs: mmaped I/O registers memory |
99c6902c | 171 | * @supplies: CSIS regulator supplies |
b5f1220d SN |
172 | * @clock: CSIS clocks |
173 | * @irq: requested s5p-mipi-csis irq number | |
174 | * @flags: the state variable for power and streaming control | |
02399e35 SN |
175 | * @clock_frequency: device bus clock frequency |
176 | * @hs_settle: HS-RX settle time | |
177 | * @num_lanes: number of MIPI-CSI data lanes used | |
178 | * @max_num_lanes: maximum number of MIPI-CSI data lanes supported | |
179 | * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM | |
b5f1220d SN |
180 | * @csis_fmt: current CSIS pixel format |
181 | * @format: common media bus format for the source and sink pad | |
99c6902c | 182 | * @slock: spinlock protecting structure members below |
36fa8092 | 183 | * @pkt_buf: the frame embedded (non-image) data buffer |
99c6902c | 184 | * @events: MIPI-CSIS event (error) counters |
b5f1220d SN |
185 | */ |
186 | struct csis_state { | |
187 | struct mutex lock; | |
188 | struct media_pad pads[CSIS_PADS_NUM]; | |
189 | struct v4l2_subdev sd; | |
ccbfd1d4 | 190 | u8 index; |
b5f1220d | 191 | struct platform_device *pdev; |
b5f1220d | 192 | void __iomem *regs; |
438df3eb | 193 | struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES]; |
b5f1220d SN |
194 | struct clk *clock[NUM_CSIS_CLOCKS]; |
195 | int irq; | |
b5f1220d | 196 | u32 flags; |
02399e35 SN |
197 | |
198 | u32 clk_frequency; | |
199 | u32 hs_settle; | |
200 | u32 num_lanes; | |
201 | u32 max_num_lanes; | |
202 | u8 wclk_ext; | |
203 | ||
b5f1220d SN |
204 | const struct csis_pix_format *csis_fmt; |
205 | struct v4l2_mbus_framefmt format; | |
99c6902c | 206 | |
9d193b75 | 207 | spinlock_t slock; |
36fa8092 | 208 | struct csis_pktbuf pkt_buf; |
99c6902c | 209 | struct s5pcsis_event events[S5PCSIS_NUM_EVENTS]; |
b5f1220d SN |
210 | }; |
211 | ||
212 | /** | |
213 | * struct csis_pix_format - CSIS pixel format description | |
214 | * @pix_width_alignment: horizontal pixel alignment, width will be | |
215 | * multiple of 2^pix_width_alignment | |
216 | * @code: corresponding media bus code | |
217 | * @fmt_reg: S5PCSIS_CONFIG register value | |
20676a4c | 218 | * @data_alignment: MIPI-CSI data alignment in bits |
b5f1220d SN |
219 | */ |
220 | struct csis_pix_format { | |
221 | unsigned int pix_width_alignment; | |
222 | enum v4l2_mbus_pixelcode code; | |
223 | u32 fmt_reg; | |
20676a4c | 224 | u8 data_alignment; |
b5f1220d SN |
225 | }; |
226 | ||
227 | static const struct csis_pix_format s5pcsis_formats[] = { | |
228 | { | |
229 | .code = V4L2_MBUS_FMT_VYUY8_2X8, | |
230 | .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT, | |
20676a4c | 231 | .data_alignment = 32, |
b5f1220d SN |
232 | }, { |
233 | .code = V4L2_MBUS_FMT_JPEG_1X8, | |
234 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
20676a4c | 235 | .data_alignment = 32, |
14783d25 SN |
236 | }, { |
237 | .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
238 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
239 | .data_alignment = 32, | |
e26991b4 SN |
240 | }, { |
241 | .code = V4L2_MBUS_FMT_SGRBG8_1X8, | |
242 | .fmt_reg = S5PCSIS_CFG_FMT_RAW8, | |
243 | .data_alignment = 24, | |
244 | }, { | |
245 | .code = V4L2_MBUS_FMT_SGRBG10_1X10, | |
246 | .fmt_reg = S5PCSIS_CFG_FMT_RAW10, | |
247 | .data_alignment = 24, | |
248 | }, { | |
249 | .code = V4L2_MBUS_FMT_SGRBG12_1X12, | |
250 | .fmt_reg = S5PCSIS_CFG_FMT_RAW12, | |
251 | .data_alignment = 24, | |
14783d25 | 252 | } |
b5f1220d SN |
253 | }; |
254 | ||
255 | #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) | |
256 | #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r) | |
257 | ||
258 | static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev) | |
259 | { | |
260 | return container_of(sdev, struct csis_state, sd); | |
261 | } | |
262 | ||
263 | static const struct csis_pix_format *find_csis_format( | |
264 | struct v4l2_mbus_framefmt *mf) | |
265 | { | |
266 | int i; | |
267 | ||
268 | for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++) | |
269 | if (mf->code == s5pcsis_formats[i].code) | |
270 | return &s5pcsis_formats[i]; | |
271 | return NULL; | |
272 | } | |
273 | ||
274 | static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) | |
275 | { | |
276 | u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); | |
277 | ||
278 | val = on ? val | S5PCSIS_INTMSK_EN_ALL : | |
279 | val & ~S5PCSIS_INTMSK_EN_ALL; | |
280 | s5pcsis_write(state, S5PCSIS_INTMSK, val); | |
281 | } | |
282 | ||
283 | static void s5pcsis_reset(struct csis_state *state) | |
284 | { | |
285 | u32 val = s5pcsis_read(state, S5PCSIS_CTRL); | |
286 | ||
287 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); | |
288 | udelay(10); | |
289 | } | |
290 | ||
291 | static void s5pcsis_system_enable(struct csis_state *state, int on) | |
292 | { | |
cd65a645 | 293 | u32 val, mask; |
b5f1220d SN |
294 | |
295 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
296 | if (on) | |
297 | val |= S5PCSIS_CTRL_ENABLE; | |
298 | else | |
299 | val &= ~S5PCSIS_CTRL_ENABLE; | |
300 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
301 | ||
302 | val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
cd65a645 SN |
303 | val &= ~S5PCSIS_DPHYCTRL_ENABLE; |
304 | if (on) { | |
02399e35 | 305 | mask = (1 << (state->num_lanes + 1)) - 1; |
cd65a645 SN |
306 | val |= (mask & S5PCSIS_DPHYCTRL_ENABLE); |
307 | } | |
b5f1220d SN |
308 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); |
309 | } | |
310 | ||
311 | /* Called with the state.lock mutex held */ | |
312 | static void __s5pcsis_set_format(struct csis_state *state) | |
313 | { | |
314 | struct v4l2_mbus_framefmt *mf = &state->format; | |
315 | u32 val; | |
316 | ||
14783d25 | 317 | v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", |
b5f1220d SN |
318 | mf->code, mf->width, mf->height); |
319 | ||
320 | /* Color format */ | |
321 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
322 | val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; | |
323 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
324 | ||
325 | /* Pixel resolution */ | |
326 | val = (mf->width << 16) | mf->height; | |
327 | s5pcsis_write(state, S5PCSIS_RESOL, val); | |
328 | } | |
329 | ||
330 | static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) | |
331 | { | |
332 | u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
333 | ||
334 | val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); | |
335 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
336 | } | |
337 | ||
338 | static void s5pcsis_set_params(struct csis_state *state) | |
339 | { | |
b5f1220d SN |
340 | u32 val; |
341 | ||
342 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
02399e35 | 343 | val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); |
b5f1220d SN |
344 | s5pcsis_write(state, S5PCSIS_CONFIG, val); |
345 | ||
346 | __s5pcsis_set_format(state); | |
02399e35 | 347 | s5pcsis_set_hsync_settle(state, state->hs_settle); |
b5f1220d SN |
348 | |
349 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
20676a4c | 350 | if (state->csis_fmt->data_alignment == 32) |
b5f1220d SN |
351 | val |= S5PCSIS_CTRL_ALIGN_32BIT; |
352 | else /* 24-bits */ | |
353 | val &= ~S5PCSIS_CTRL_ALIGN_32BIT; | |
65214a86 | 354 | |
b5f1220d | 355 | val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; |
02399e35 | 356 | if (state->wclk_ext) |
65214a86 | 357 | val |= S5PCSIS_CTRL_WCLK_EXTCLK; |
b5f1220d SN |
358 | s5pcsis_write(state, S5PCSIS_CTRL, val); |
359 | ||
360 | /* Update the shadow register. */ | |
361 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
362 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); | |
363 | } | |
364 | ||
365 | static void s5pcsis_clk_put(struct csis_state *state) | |
366 | { | |
367 | int i; | |
368 | ||
bd7d8888 | 369 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { |
44e2b09c | 370 | if (IS_ERR(state->clock[i])) |
bd7d8888 SN |
371 | continue; |
372 | clk_unprepare(state->clock[i]); | |
373 | clk_put(state->clock[i]); | |
44e2b09c | 374 | state->clock[i] = ERR_PTR(-EINVAL); |
bd7d8888 | 375 | } |
b5f1220d SN |
376 | } |
377 | ||
378 | static int s5pcsis_clk_get(struct csis_state *state) | |
379 | { | |
380 | struct device *dev = &state->pdev->dev; | |
bd7d8888 | 381 | int i, ret; |
b5f1220d | 382 | |
44e2b09c SN |
383 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) |
384 | state->clock[i] = ERR_PTR(-EINVAL); | |
385 | ||
b5f1220d SN |
386 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { |
387 | state->clock[i] = clk_get(dev, csi_clock_name[i]); | |
44e2b09c SN |
388 | if (IS_ERR(state->clock[i])) { |
389 | ret = PTR_ERR(state->clock[i]); | |
bd7d8888 | 390 | goto err; |
44e2b09c | 391 | } |
bd7d8888 SN |
392 | ret = clk_prepare(state->clock[i]); |
393 | if (ret < 0) { | |
394 | clk_put(state->clock[i]); | |
44e2b09c | 395 | state->clock[i] = ERR_PTR(-EINVAL); |
bd7d8888 | 396 | goto err; |
b5f1220d SN |
397 | } |
398 | } | |
399 | return 0; | |
bd7d8888 SN |
400 | err: |
401 | s5pcsis_clk_put(state); | |
402 | dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]); | |
44e2b09c | 403 | return ret; |
b5f1220d SN |
404 | } |
405 | ||
a2fea0df SN |
406 | static void dump_regs(struct csis_state *state, const char *label) |
407 | { | |
408 | struct { | |
409 | u32 offset; | |
410 | const char * const name; | |
411 | } registers[] = { | |
412 | { 0x00, "CTRL" }, | |
413 | { 0x04, "DPHYCTRL" }, | |
414 | { 0x08, "CONFIG" }, | |
415 | { 0x0c, "DPHYSTS" }, | |
416 | { 0x10, "INTMSK" }, | |
417 | { 0x2c, "RESOL" }, | |
418 | { 0x38, "SDW_CONFIG" }, | |
419 | }; | |
420 | u32 i; | |
421 | ||
422 | v4l2_info(&state->sd, "--- %s ---\n", label); | |
423 | ||
424 | for (i = 0; i < ARRAY_SIZE(registers); i++) { | |
425 | u32 cfg = s5pcsis_read(state, registers[i].offset); | |
426 | v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg); | |
427 | } | |
428 | } | |
429 | ||
b5f1220d SN |
430 | static void s5pcsis_start_stream(struct csis_state *state) |
431 | { | |
432 | s5pcsis_reset(state); | |
433 | s5pcsis_set_params(state); | |
434 | s5pcsis_system_enable(state, true); | |
435 | s5pcsis_enable_interrupts(state, true); | |
436 | } | |
437 | ||
438 | static void s5pcsis_stop_stream(struct csis_state *state) | |
439 | { | |
440 | s5pcsis_enable_interrupts(state, false); | |
441 | s5pcsis_system_enable(state, false); | |
442 | } | |
443 | ||
99c6902c SN |
444 | static void s5pcsis_clear_counters(struct csis_state *state) |
445 | { | |
446 | unsigned long flags; | |
447 | int i; | |
448 | ||
449 | spin_lock_irqsave(&state->slock, flags); | |
450 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) | |
451 | state->events[i].counter = 0; | |
452 | spin_unlock_irqrestore(&state->slock, flags); | |
453 | } | |
454 | ||
455 | static void s5pcsis_log_counters(struct csis_state *state, bool non_errors) | |
456 | { | |
457 | int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4; | |
458 | unsigned long flags; | |
459 | ||
460 | spin_lock_irqsave(&state->slock, flags); | |
461 | ||
ef2c8326 SN |
462 | for (i--; i >= 0; i--) { |
463 | if (state->events[i].counter > 0 || debug) | |
99c6902c SN |
464 | v4l2_info(&state->sd, "%s events: %d\n", |
465 | state->events[i].name, | |
466 | state->events[i].counter); | |
ef2c8326 | 467 | } |
99c6902c SN |
468 | spin_unlock_irqrestore(&state->slock, flags); |
469 | } | |
470 | ||
471 | /* | |
472 | * V4L2 subdev operations | |
473 | */ | |
474 | static int s5pcsis_s_power(struct v4l2_subdev *sd, int on) | |
475 | { | |
476 | struct csis_state *state = sd_to_csis_state(sd); | |
477 | struct device *dev = &state->pdev->dev; | |
478 | ||
479 | if (on) | |
480 | return pm_runtime_get_sync(dev); | |
481 | ||
482 | return pm_runtime_put_sync(dev); | |
483 | } | |
484 | ||
b5f1220d SN |
485 | static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable) |
486 | { | |
487 | struct csis_state *state = sd_to_csis_state(sd); | |
488 | int ret = 0; | |
489 | ||
490 | v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", | |
491 | __func__, enable, state->flags); | |
492 | ||
493 | if (enable) { | |
99c6902c | 494 | s5pcsis_clear_counters(state); |
b5f1220d SN |
495 | ret = pm_runtime_get_sync(&state->pdev->dev); |
496 | if (ret && ret != 1) | |
497 | return ret; | |
498 | } | |
99c6902c | 499 | |
b5f1220d SN |
500 | mutex_lock(&state->lock); |
501 | if (enable) { | |
502 | if (state->flags & ST_SUSPENDED) { | |
503 | ret = -EBUSY; | |
504 | goto unlock; | |
505 | } | |
506 | s5pcsis_start_stream(state); | |
507 | state->flags |= ST_STREAMING; | |
508 | } else { | |
509 | s5pcsis_stop_stream(state); | |
510 | state->flags &= ~ST_STREAMING; | |
99c6902c SN |
511 | if (debug > 0) |
512 | s5pcsis_log_counters(state, true); | |
b5f1220d SN |
513 | } |
514 | unlock: | |
515 | mutex_unlock(&state->lock); | |
516 | if (!enable) | |
517 | pm_runtime_put(&state->pdev->dev); | |
518 | ||
519 | return ret == 1 ? 0 : ret; | |
520 | } | |
521 | ||
522 | static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd, | |
523 | struct v4l2_subdev_fh *fh, | |
524 | struct v4l2_subdev_mbus_code_enum *code) | |
525 | { | |
526 | if (code->index >= ARRAY_SIZE(s5pcsis_formats)) | |
527 | return -EINVAL; | |
528 | ||
529 | code->code = s5pcsis_formats[code->index].code; | |
530 | return 0; | |
531 | } | |
532 | ||
533 | static struct csis_pix_format const *s5pcsis_try_format( | |
534 | struct v4l2_mbus_framefmt *mf) | |
535 | { | |
536 | struct csis_pix_format const *csis_fmt; | |
537 | ||
538 | csis_fmt = find_csis_format(mf); | |
539 | if (csis_fmt == NULL) | |
540 | csis_fmt = &s5pcsis_formats[0]; | |
541 | ||
542 | mf->code = csis_fmt->code; | |
543 | v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH, | |
544 | csis_fmt->pix_width_alignment, | |
545 | &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1, | |
546 | 0); | |
547 | return csis_fmt; | |
548 | } | |
549 | ||
550 | static struct v4l2_mbus_framefmt *__s5pcsis_get_format( | |
551 | struct csis_state *state, struct v4l2_subdev_fh *fh, | |
552 | u32 pad, enum v4l2_subdev_format_whence which) | |
553 | { | |
554 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
555 | return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL; | |
556 | ||
557 | return &state->format; | |
558 | } | |
559 | ||
560 | static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
561 | struct v4l2_subdev_format *fmt) | |
562 | { | |
563 | struct csis_state *state = sd_to_csis_state(sd); | |
564 | struct csis_pix_format const *csis_fmt; | |
565 | struct v4l2_mbus_framefmt *mf; | |
566 | ||
567 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
568 | return -EINVAL; | |
569 | ||
570 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
571 | ||
572 | if (fmt->pad == CSIS_PAD_SOURCE) { | |
573 | if (mf) { | |
574 | mutex_lock(&state->lock); | |
575 | fmt->format = *mf; | |
576 | mutex_unlock(&state->lock); | |
577 | } | |
578 | return 0; | |
579 | } | |
580 | csis_fmt = s5pcsis_try_format(&fmt->format); | |
581 | if (mf) { | |
582 | mutex_lock(&state->lock); | |
583 | *mf = fmt->format; | |
584 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
585 | state->csis_fmt = csis_fmt; | |
586 | mutex_unlock(&state->lock); | |
587 | } | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
592 | struct v4l2_subdev_format *fmt) | |
593 | { | |
594 | struct csis_state *state = sd_to_csis_state(sd); | |
595 | struct v4l2_mbus_framefmt *mf; | |
596 | ||
597 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
598 | return -EINVAL; | |
599 | ||
600 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
601 | if (!mf) | |
602 | return -EINVAL; | |
603 | ||
604 | mutex_lock(&state->lock); | |
605 | fmt->format = *mf; | |
606 | mutex_unlock(&state->lock); | |
607 | return 0; | |
608 | } | |
609 | ||
36fa8092 SN |
610 | static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf, |
611 | unsigned int *size) | |
612 | { | |
613 | struct csis_state *state = sd_to_csis_state(sd); | |
614 | unsigned long flags; | |
615 | ||
616 | *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE); | |
617 | ||
618 | spin_lock_irqsave(&state->slock, flags); | |
619 | state->pkt_buf.data = buf; | |
620 | state->pkt_buf.len = *size; | |
621 | spin_unlock_irqrestore(&state->slock, flags); | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
99c6902c SN |
626 | static int s5pcsis_log_status(struct v4l2_subdev *sd) |
627 | { | |
628 | struct csis_state *state = sd_to_csis_state(sd); | |
629 | ||
a2fea0df | 630 | mutex_lock(&state->lock); |
99c6902c | 631 | s5pcsis_log_counters(state, true); |
a2fea0df SN |
632 | if (debug && (state->flags & ST_POWERED)) |
633 | dump_regs(state, __func__); | |
634 | mutex_unlock(&state->lock); | |
99c6902c SN |
635 | return 0; |
636 | } | |
637 | ||
6cf1056f SN |
638 | static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
639 | { | |
640 | struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0); | |
641 | ||
642 | format->colorspace = V4L2_COLORSPACE_JPEG; | |
643 | format->code = s5pcsis_formats[0].code; | |
644 | format->width = S5PCSIS_DEF_PIX_WIDTH; | |
645 | format->height = S5PCSIS_DEF_PIX_HEIGHT; | |
646 | format->field = V4L2_FIELD_NONE; | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = { | |
652 | .open = s5pcsis_open, | |
653 | }; | |
654 | ||
b5f1220d SN |
655 | static struct v4l2_subdev_core_ops s5pcsis_core_ops = { |
656 | .s_power = s5pcsis_s_power, | |
99c6902c | 657 | .log_status = s5pcsis_log_status, |
b5f1220d SN |
658 | }; |
659 | ||
660 | static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = { | |
661 | .enum_mbus_code = s5pcsis_enum_mbus_code, | |
662 | .get_fmt = s5pcsis_get_fmt, | |
663 | .set_fmt = s5pcsis_set_fmt, | |
664 | }; | |
665 | ||
666 | static struct v4l2_subdev_video_ops s5pcsis_video_ops = { | |
36fa8092 | 667 | .s_rx_buffer = s5pcsis_s_rx_buffer, |
b5f1220d SN |
668 | .s_stream = s5pcsis_s_stream, |
669 | }; | |
670 | ||
671 | static struct v4l2_subdev_ops s5pcsis_subdev_ops = { | |
672 | .core = &s5pcsis_core_ops, | |
673 | .pad = &s5pcsis_pad_ops, | |
674 | .video = &s5pcsis_video_ops, | |
675 | }; | |
676 | ||
677 | static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id) | |
678 | { | |
679 | struct csis_state *state = dev_id; | |
36fa8092 | 680 | struct csis_pktbuf *pktbuf = &state->pkt_buf; |
99c6902c SN |
681 | unsigned long flags; |
682 | u32 status; | |
683 | ||
684 | status = s5pcsis_read(state, S5PCSIS_INTSRC); | |
99c6902c SN |
685 | spin_lock_irqsave(&state->slock, flags); |
686 | ||
36fa8092 SN |
687 | if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) { |
688 | u32 offset; | |
689 | ||
690 | if (status & S5PCSIS_INTSRC_EVEN) | |
691 | offset = S5PCSIS_PKTDATA_EVEN; | |
692 | else | |
693 | offset = S5PCSIS_PKTDATA_ODD; | |
694 | ||
695 | memcpy(pktbuf->data, state->regs + offset, pktbuf->len); | |
696 | pktbuf->data = NULL; | |
697 | rmb(); | |
698 | } | |
699 | ||
99c6902c SN |
700 | /* Update the event/error counters */ |
701 | if ((status & S5PCSIS_INTSRC_ERRORS) || debug) { | |
702 | int i; | |
703 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) { | |
704 | if (!(status & state->events[i].mask)) | |
705 | continue; | |
706 | state->events[i].counter++; | |
707 | v4l2_dbg(2, debug, &state->sd, "%s: %d\n", | |
708 | state->events[i].name, | |
709 | state->events[i].counter); | |
710 | } | |
711 | v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); | |
712 | } | |
713 | spin_unlock_irqrestore(&state->slock, flags); | |
b5f1220d | 714 | |
99c6902c | 715 | s5pcsis_write(state, S5PCSIS_INTSRC, status); |
b5f1220d SN |
716 | return IRQ_HANDLED; |
717 | } | |
718 | ||
02399e35 SN |
719 | static int s5pcsis_get_platform_data(struct platform_device *pdev, |
720 | struct csis_state *state) | |
721 | { | |
722 | struct s5p_platform_mipi_csis *pdata = pdev->dev.platform_data; | |
723 | ||
724 | if (pdata == NULL) { | |
725 | dev_err(&pdev->dev, "Platform data not specified\n"); | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
729 | state->clk_frequency = pdata->clk_rate; | |
730 | state->num_lanes = pdata->lanes; | |
731 | state->hs_settle = pdata->hs_settle; | |
732 | state->index = max(0, pdev->id); | |
733 | state->max_num_lanes = state->index ? CSIS1_MAX_LANES : | |
734 | CSIS0_MAX_LANES; | |
735 | return 0; | |
736 | } | |
737 | ||
738 | #ifdef CONFIG_OF | |
739 | static int s5pcsis_parse_dt(struct platform_device *pdev, | |
740 | struct csis_state *state) | |
741 | { | |
742 | struct device_node *node = pdev->dev.of_node; | |
743 | struct v4l2_of_endpoint endpoint; | |
744 | ||
745 | if (of_property_read_u32(node, "clock-frequency", | |
746 | &state->clk_frequency)) | |
747 | state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; | |
748 | if (of_property_read_u32(node, "bus-width", | |
749 | &state->max_num_lanes)) | |
750 | return -EINVAL; | |
751 | ||
752 | node = v4l2_of_get_next_endpoint(node, NULL); | |
753 | if (!node) { | |
754 | dev_err(&pdev->dev, "No port node at %s\n", | |
755 | node->full_name); | |
756 | return -EINVAL; | |
757 | } | |
758 | /* Get port node and validate MIPI-CSI channel id. */ | |
759 | v4l2_of_parse_endpoint(node, &endpoint); | |
760 | ||
761 | state->index = endpoint.port - FIMC_INPUT_MIPI_CSI2_0; | |
762 | if (state->index < 0 || state->index >= CSIS_MAX_ENTITIES) | |
763 | return -ENXIO; | |
764 | ||
765 | /* Get MIPI CSI-2 bus configration from the endpoint node. */ | |
766 | of_property_read_u32(node, "samsung,csis-hs-settle", | |
767 | &state->hs_settle); | |
768 | state->wclk_ext = of_property_read_bool(node, | |
769 | "samsung,csis-wclk"); | |
770 | ||
771 | state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes; | |
772 | ||
773 | of_node_put(node); | |
774 | return 0; | |
775 | } | |
776 | #else | |
777 | #define s5pcsis_parse_dt(pdev, state) (-ENOSYS) | |
778 | #endif | |
779 | ||
4c62e976 | 780 | static int s5pcsis_probe(struct platform_device *pdev) |
b5f1220d | 781 | { |
02399e35 | 782 | struct device *dev = &pdev->dev; |
b5f1220d | 783 | struct resource *mem_res; |
b5f1220d SN |
784 | struct csis_state *state; |
785 | int ret = -ENOMEM; | |
438df3eb | 786 | int i; |
b5f1220d | 787 | |
02399e35 | 788 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); |
b5f1220d SN |
789 | if (!state) |
790 | return -ENOMEM; | |
791 | ||
792 | mutex_init(&state->lock); | |
99c6902c | 793 | spin_lock_init(&state->slock); |
b5f1220d SN |
794 | state->pdev = pdev; |
795 | ||
02399e35 SN |
796 | if (dev->of_node) |
797 | ret = s5pcsis_parse_dt(pdev, state); | |
798 | else | |
799 | ret = s5pcsis_get_platform_data(pdev, state); | |
800 | if (ret < 0) | |
801 | return ret; | |
b5f1220d | 802 | |
02399e35 SN |
803 | if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { |
804 | dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n", | |
805 | state->num_lanes, state->max_num_lanes); | |
a1212162 | 806 | return -EINVAL; |
b5f1220d SN |
807 | } |
808 | ||
809 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
02399e35 | 810 | state->regs = devm_ioremap_resource(dev, mem_res); |
f23999ec TR |
811 | if (IS_ERR(state->regs)) |
812 | return PTR_ERR(state->regs); | |
b5f1220d SN |
813 | |
814 | state->irq = platform_get_irq(pdev, 0); | |
815 | if (state->irq < 0) { | |
02399e35 | 816 | dev_err(dev, "Failed to get irq\n"); |
a1212162 | 817 | return state->irq; |
b5f1220d SN |
818 | } |
819 | ||
438df3eb SN |
820 | for (i = 0; i < CSIS_NUM_SUPPLIES; i++) |
821 | state->supplies[i].supply = csis_supply_name[i]; | |
822 | ||
02399e35 | 823 | ret = devm_regulator_bulk_get(dev, CSIS_NUM_SUPPLIES, |
438df3eb | 824 | state->supplies); |
a1212162 SN |
825 | if (ret) |
826 | return ret; | |
827 | ||
828 | ret = s5pcsis_clk_get(state); | |
44e2b09c SN |
829 | if (ret < 0) |
830 | return ret; | |
b5f1220d | 831 | |
02399e35 | 832 | if (state->clk_frequency) |
44e2b09c | 833 | ret = clk_set_rate(state->clock[CSIS_CLK_MUX], |
02399e35 | 834 | state->clk_frequency); |
a1212162 | 835 | else |
02399e35 | 836 | dev_WARN(dev, "No clock frequency specified!\n"); |
44e2b09c SN |
837 | if (ret < 0) |
838 | goto e_clkput; | |
839 | ||
840 | ret = clk_enable(state->clock[CSIS_CLK_MUX]); | |
841 | if (ret < 0) | |
842 | goto e_clkput; | |
a1212162 | 843 | |
02399e35 SN |
844 | ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler, |
845 | 0, dev_name(dev), state); | |
b5f1220d | 846 | if (ret) { |
02399e35 | 847 | dev_err(dev, "Interrupt request failed\n"); |
8cd5d42a | 848 | goto e_clkdis; |
b5f1220d SN |
849 | } |
850 | ||
851 | v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); | |
852 | state->sd.owner = THIS_MODULE; | |
02399e35 SN |
853 | snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d", |
854 | CSIS_SUBDEV_NAME, state->index); | |
6cf1056f | 855 | state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
b5f1220d SN |
856 | state->csis_fmt = &s5pcsis_formats[0]; |
857 | ||
6cf1056f SN |
858 | state->format.code = s5pcsis_formats[0].code; |
859 | state->format.width = S5PCSIS_DEF_PIX_WIDTH; | |
860 | state->format.height = S5PCSIS_DEF_PIX_HEIGHT; | |
861 | ||
b5f1220d SN |
862 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
863 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
864 | ret = media_entity_init(&state->sd.entity, | |
865 | CSIS_PADS_NUM, state->pads, 0); | |
866 | if (ret < 0) | |
8cd5d42a | 867 | goto e_clkdis; |
b5f1220d SN |
868 | |
869 | /* This allows to retrieve the platform device id by the host driver */ | |
870 | v4l2_set_subdevdata(&state->sd, pdev); | |
871 | ||
872 | /* .. and a pointer to the subdev. */ | |
873 | platform_set_drvdata(pdev, &state->sd); | |
99c6902c | 874 | memcpy(state->events, s5pcsis_events, sizeof(state->events)); |
02399e35 | 875 | pm_runtime_enable(dev); |
99c6902c | 876 | |
02399e35 SN |
877 | dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n", |
878 | state->num_lanes, state->hs_settle, state->wclk_ext, | |
879 | state->clk_frequency); | |
b5f1220d SN |
880 | return 0; |
881 | ||
8cd5d42a | 882 | e_clkdis: |
b5f1220d | 883 | clk_disable(state->clock[CSIS_CLK_MUX]); |
8cd5d42a | 884 | e_clkput: |
b5f1220d | 885 | s5pcsis_clk_put(state); |
b5f1220d SN |
886 | return ret; |
887 | } | |
888 | ||
d4d4e3c9 | 889 | static int s5pcsis_pm_suspend(struct device *dev, bool runtime) |
b5f1220d | 890 | { |
b5f1220d SN |
891 | struct platform_device *pdev = to_platform_device(dev); |
892 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
893 | struct csis_state *state = sd_to_csis_state(sd); | |
c68956c1 | 894 | int ret = 0; |
b5f1220d SN |
895 | |
896 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
897 | __func__, state->flags); | |
898 | ||
899 | mutex_lock(&state->lock); | |
900 | if (state->flags & ST_POWERED) { | |
901 | s5pcsis_stop_stream(state); | |
ccbfd1d4 | 902 | ret = s5p_csis_phy_enable(state->index, false); |
b5f1220d SN |
903 | if (ret) |
904 | goto unlock; | |
438df3eb SN |
905 | ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES, |
906 | state->supplies); | |
907 | if (ret) | |
908 | goto unlock; | |
b5f1220d SN |
909 | clk_disable(state->clock[CSIS_CLK_GATE]); |
910 | state->flags &= ~ST_POWERED; | |
d4d4e3c9 SN |
911 | if (!runtime) |
912 | state->flags |= ST_SUSPENDED; | |
b5f1220d | 913 | } |
b5f1220d SN |
914 | unlock: |
915 | mutex_unlock(&state->lock); | |
916 | return ret ? -EAGAIN : 0; | |
917 | } | |
918 | ||
d4d4e3c9 | 919 | static int s5pcsis_pm_resume(struct device *dev, bool runtime) |
b5f1220d | 920 | { |
b5f1220d SN |
921 | struct platform_device *pdev = to_platform_device(dev); |
922 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
923 | struct csis_state *state = sd_to_csis_state(sd); | |
924 | int ret = 0; | |
925 | ||
926 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
927 | __func__, state->flags); | |
928 | ||
929 | mutex_lock(&state->lock); | |
d4d4e3c9 | 930 | if (!runtime && !(state->flags & ST_SUSPENDED)) |
b5f1220d SN |
931 | goto unlock; |
932 | ||
933 | if (!(state->flags & ST_POWERED)) { | |
438df3eb SN |
934 | ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES, |
935 | state->supplies); | |
b5f1220d SN |
936 | if (ret) |
937 | goto unlock; | |
ccbfd1d4 | 938 | ret = s5p_csis_phy_enable(state->index, true); |
b5f1220d SN |
939 | if (!ret) { |
940 | state->flags |= ST_POWERED; | |
438df3eb SN |
941 | } else { |
942 | regulator_bulk_disable(CSIS_NUM_SUPPLIES, | |
943 | state->supplies); | |
b5f1220d SN |
944 | goto unlock; |
945 | } | |
946 | clk_enable(state->clock[CSIS_CLK_GATE]); | |
947 | } | |
948 | if (state->flags & ST_STREAMING) | |
949 | s5pcsis_start_stream(state); | |
950 | ||
951 | state->flags &= ~ST_SUSPENDED; | |
952 | unlock: | |
953 | mutex_unlock(&state->lock); | |
954 | return ret ? -EAGAIN : 0; | |
955 | } | |
956 | ||
957 | #ifdef CONFIG_PM_SLEEP | |
d4d4e3c9 | 958 | static int s5pcsis_suspend(struct device *dev) |
b5f1220d | 959 | { |
d4d4e3c9 | 960 | return s5pcsis_pm_suspend(dev, false); |
b5f1220d SN |
961 | } |
962 | ||
d4d4e3c9 | 963 | static int s5pcsis_resume(struct device *dev) |
b5f1220d | 964 | { |
d4d4e3c9 SN |
965 | return s5pcsis_pm_resume(dev, false); |
966 | } | |
967 | #endif | |
b5f1220d | 968 | |
d4d4e3c9 SN |
969 | #ifdef CONFIG_PM_RUNTIME |
970 | static int s5pcsis_runtime_suspend(struct device *dev) | |
971 | { | |
972 | return s5pcsis_pm_suspend(dev, true); | |
973 | } | |
b5f1220d | 974 | |
d4d4e3c9 SN |
975 | static int s5pcsis_runtime_resume(struct device *dev) |
976 | { | |
977 | return s5pcsis_pm_resume(dev, true); | |
b5f1220d SN |
978 | } |
979 | #endif | |
980 | ||
4c62e976 | 981 | static int s5pcsis_remove(struct platform_device *pdev) |
b5f1220d SN |
982 | { |
983 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
984 | struct csis_state *state = sd_to_csis_state(sd); | |
b5f1220d SN |
985 | |
986 | pm_runtime_disable(&pdev->dev); | |
68a6bb54 | 987 | s5pcsis_pm_suspend(&pdev->dev, false); |
b5f1220d SN |
988 | clk_disable(state->clock[CSIS_CLK_MUX]); |
989 | pm_runtime_set_suspended(&pdev->dev); | |
b5f1220d | 990 | s5pcsis_clk_put(state); |
b5f1220d SN |
991 | |
992 | media_entity_cleanup(&state->sd.entity); | |
b5f1220d SN |
993 | |
994 | return 0; | |
995 | } | |
996 | ||
997 | static const struct dev_pm_ops s5pcsis_pm_ops = { | |
d4d4e3c9 SN |
998 | SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume, |
999 | NULL) | |
1000 | SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume) | |
b5f1220d SN |
1001 | }; |
1002 | ||
02399e35 SN |
1003 | static const struct of_device_id s5pcsis_of_match[] = { |
1004 | { .compatible = "samsung,s5pv210-csis" }, | |
1005 | { .compatible = "samsung,exynos4210-csis" }, | |
1006 | { /* sentinel */ }, | |
1007 | }; | |
1008 | MODULE_DEVICE_TABLE(of, s5pcsis_of_match); | |
1009 | ||
b5f1220d SN |
1010 | static struct platform_driver s5pcsis_driver = { |
1011 | .probe = s5pcsis_probe, | |
4c62e976 | 1012 | .remove = s5pcsis_remove, |
b5f1220d | 1013 | .driver = { |
02399e35 SN |
1014 | .of_match_table = s5pcsis_of_match, |
1015 | .name = CSIS_DRIVER_NAME, | |
1016 | .owner = THIS_MODULE, | |
1017 | .pm = &s5pcsis_pm_ops, | |
b5f1220d SN |
1018 | }, |
1019 | }; | |
1020 | ||
ecd9acbf | 1021 | module_platform_driver(s5pcsis_driver); |
b5f1220d SN |
1022 | |
1023 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
ecd9acbf | 1024 | MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver"); |
b5f1220d | 1025 | MODULE_LICENSE("GPL"); |