[media] marvell-ccic: fill in colorspace
[deliverable/linux.git] / drivers / media / platform / marvell-ccic / mcam-core.c
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1/*
2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
4 *
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/fs.h>
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10#include <linux/mm.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
abfa3df3 14#include <linux/slab.h>
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15#include <linux/device.h>
16#include <linux/wait.h>
17#include <linux/list.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
abfa3df3 20#include <linux/vmalloc.h>
abfa3df3 21#include <linux/io.h>
05fed816 22#include <linux/clk.h>
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23#include <linux/videodev2.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-ioctl.h>
593403c5 26#include <media/v4l2-ctrls.h>
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27#include <media/ov7670.h>
28#include <media/videobuf2-vmalloc.h>
a9b36e85 29#include <media/videobuf2-dma-contig.h>
cbc4f3a2 30#include <media/videobuf2-dma-sg.h>
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31
32#include "mcam-core.h"
33
7498469f 34#ifdef MCAM_MODE_VMALLOC
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35/*
36 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
37 * we must have physically contiguous buffers to bring frames into.
38 * These parameters control how many buffers we use, whether we
39 * allocate them at load time (better chance of success, but nails down
40 * memory) or when somebody tries to use the camera (riskier), and,
41 * for load-time allocation, how big they should be.
42 *
43 * The controller can cycle through three buffers. We could use
44 * more by flipping pointers around, but it probably makes little
45 * sense.
46 */
47
90ab5ee9 48static bool alloc_bufs_at_read;
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49module_param(alloc_bufs_at_read, bool, 0444);
50MODULE_PARM_DESC(alloc_bufs_at_read,
51 "Non-zero value causes DMA buffers to be allocated when the "
52 "video capture device is read, rather than at module load "
53 "time. This saves memory, but decreases the chances of "
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54 "successfully getting those buffers. This parameter is "
55 "only used in the vmalloc buffer mode");
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56
57static int n_dma_bufs = 3;
58module_param(n_dma_bufs, uint, 0644);
59MODULE_PARM_DESC(n_dma_bufs,
60 "The number of DMA buffers to allocate. Can be either two "
61 "(saves memory, makes timing tighter) or three.");
62
63static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
64module_param(dma_buf_size, uint, 0444);
65MODULE_PARM_DESC(dma_buf_size,
66 "The size of the allocated DMA buffers. If actual operating "
67 "parameters require larger buffers, an attempt to reallocate "
68 "will be made.");
7498469f 69#else /* MCAM_MODE_VMALLOC */
a7459a9d 70static const bool alloc_bufs_at_read;
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71static const int n_dma_bufs = 3; /* Used by S/G_PARM */
72#endif /* MCAM_MODE_VMALLOC */
abfa3df3 73
90ab5ee9 74static bool flip;
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75module_param(flip, bool, 0444);
76MODULE_PARM_DESC(flip,
77 "If set, the sensor will be instructed to flip the image "
78 "vertically.");
79
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80static int buffer_mode = -1;
81module_param(buffer_mode, int, 0444);
82MODULE_PARM_DESC(buffer_mode,
83 "Set the buffer mode to be used; default is to go with what "
84 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
85 "DMA contiguous.");
86
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87/*
88 * Status flags. Always manipulated with bit operations.
89 */
90#define CF_BUF0_VALID 0 /* Buffers valid - first three */
91#define CF_BUF1_VALID 1
92#define CF_BUF2_VALID 2
93#define CF_DMA_ACTIVE 3 /* A frame is incoming */
94#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
a9b36e85 95#define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
cbc4f3a2 96#define CF_SG_RESTART 6 /* SG restart needed */
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97#define CF_FRAME_SOF0 7 /* Frame 0 started */
98#define CF_FRAME_SOF1 8
99#define CF_FRAME_SOF2 9
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100
101#define sensor_call(cam, o, f, args...) \
102 v4l2_subdev_call(cam->sensor, o, f, ##args)
103
104static struct mcam_format_struct {
105 __u8 *desc;
106 __u32 pixelformat;
107 int bpp; /* Bytes per pixel */
ad6ac452 108 bool planar;
27ffaeb0 109 u32 mbus_code;
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110} mcam_formats[] = {
111 {
112 .desc = "YUYV 4:2:2",
113 .pixelformat = V4L2_PIX_FMT_YUYV,
27ffaeb0 114 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
abfa3df3 115 .bpp = 2,
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116 .planar = false,
117 },
118 {
119 .desc = "UYVY 4:2:2",
120 .pixelformat = V4L2_PIX_FMT_UYVY,
27ffaeb0 121 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
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122 .bpp = 2,
123 .planar = false,
124 },
125 {
126 .desc = "YUV 4:2:2 PLANAR",
127 .pixelformat = V4L2_PIX_FMT_YUV422P,
27ffaeb0 128 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
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129 .bpp = 2,
130 .planar = true,
131 },
132 {
133 .desc = "YUV 4:2:0 PLANAR",
134 .pixelformat = V4L2_PIX_FMT_YUV420,
27ffaeb0 135 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
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136 .bpp = 2,
137 .planar = true,
138 },
139 {
140 .desc = "YVU 4:2:0 PLANAR",
141 .pixelformat = V4L2_PIX_FMT_YVU420,
27ffaeb0 142 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
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143 .bpp = 2,
144 .planar = true,
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145 },
146 {
147 .desc = "RGB 444",
148 .pixelformat = V4L2_PIX_FMT_RGB444,
27ffaeb0 149 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
abfa3df3 150 .bpp = 2,
ad6ac452 151 .planar = false,
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152 },
153 {
154 .desc = "RGB 565",
155 .pixelformat = V4L2_PIX_FMT_RGB565,
27ffaeb0 156 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
abfa3df3 157 .bpp = 2,
ad6ac452 158 .planar = false,
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159 },
160 {
161 .desc = "Raw RGB Bayer",
162 .pixelformat = V4L2_PIX_FMT_SBGGR8,
27ffaeb0 163 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
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164 .bpp = 1,
165 .planar = false,
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166 },
167};
168#define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
169
170static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
171{
172 unsigned i;
173
174 for (i = 0; i < N_MCAM_FMTS; i++)
175 if (mcam_formats[i].pixelformat == pixelformat)
176 return mcam_formats + i;
177 /* Not found? Then return the first format. */
178 return mcam_formats;
179}
180
181/*
d43dae75 182 * The default format we use until somebody says otherwise.
abfa3df3 183 */
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184static const struct v4l2_pix_format mcam_def_pix_format = {
185 .width = VGA_WIDTH,
186 .height = VGA_HEIGHT,
187 .pixelformat = V4L2_PIX_FMT_YUYV,
188 .field = V4L2_FIELD_NONE,
189 .bytesperline = VGA_WIDTH*2,
190 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
2e6e6095 191 .colorspace = V4L2_COLORSPACE_SRGB,
d43dae75 192};
abfa3df3 193
27ffaeb0 194static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
abfa3df3 195
abfa3df3 196
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197/*
198 * The two-word DMA descriptor format used by the Armada 610 and like. There
199 * Is a three-word format as well (set C1_DESC_3WORD) where the third
200 * word is a pointer to the next descriptor, but we don't use it. Two-word
201 * descriptors have to be contiguous in memory.
202 */
203struct mcam_dma_desc {
204 u32 dma_addr;
205 u32 segment_len;
206};
207
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208struct yuv_pointer_t {
209 dma_addr_t y;
210 dma_addr_t u;
211 dma_addr_t v;
212};
213
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214/*
215 * Our buffer type for working with videobuf2. Note that the vb2
216 * developers have decreed that struct vb2_buffer must be at the
217 * beginning of this structure.
218 */
219struct mcam_vb_buffer {
220 struct vb2_buffer vb_buf;
221 struct list_head queue;
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222 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
223 dma_addr_t dma_desc_pa; /* Descriptor physical address */
224 int dma_desc_nent; /* Number of mapped descriptors */
ad6ac452 225 struct yuv_pointer_t yuv_p;
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226};
227
228static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
229{
230 return container_of(vb, struct mcam_vb_buffer, vb_buf);
231}
232
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233/*
234 * Hand a completed buffer back to user space.
235 */
236static void mcam_buffer_done(struct mcam_camera *cam, int frame,
237 struct vb2_buffer *vbuf)
238{
239 vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
240 vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
241 vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
242 vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
243}
244
245
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246
247/*
67a8dbbc 248 * Debugging and related.
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249 */
250#define cam_err(cam, fmt, arg...) \
251 dev_err((cam)->dev, fmt, ##arg);
252#define cam_warn(cam, fmt, arg...) \
253 dev_warn((cam)->dev, fmt, ##arg);
254#define cam_dbg(cam, fmt, arg...) \
255 dev_dbg((cam)->dev, fmt, ##arg);
256
257
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258/*
259 * Flag manipulation helpers
260 */
261static void mcam_reset_buffers(struct mcam_camera *cam)
262{
263 int i;
264
265 cam->next_buf = -1;
0a0b3fb4 266 for (i = 0; i < cam->nbufs; i++) {
d43dae75 267 clear_bit(i, &cam->flags);
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268 clear_bit(CF_FRAME_SOF0 + i, &cam->flags);
269 }
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270}
271
272static inline int mcam_needs_config(struct mcam_camera *cam)
273{
274 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
275}
276
277static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
278{
279 if (needed)
280 set_bit(CF_CONFIG_NEEDED, &cam->flags);
281 else
282 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
283}
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284
285/* ------------------------------------------------------------------- */
286/*
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287 * Make the controller start grabbing images. Everything must
288 * be set up before doing this.
abfa3df3 289 */
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290static void mcam_ctlr_start(struct mcam_camera *cam)
291{
292 /* set_bit performs a read, so no other barrier should be
293 needed here */
294 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
295}
296
297static void mcam_ctlr_stop(struct mcam_camera *cam)
298{
299 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
300}
301
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302static void mcam_enable_mipi(struct mcam_camera *mcam)
303{
304 /* Using MIPI mode and enable MIPI */
305 cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n",
306 mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]);
307 mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
308 mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
309 mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
310
311 if (!mcam->mipi_enabled) {
312 if (mcam->lane > 4 || mcam->lane <= 0) {
313 cam_warn(mcam, "lane number error\n");
314 mcam->lane = 1; /* set the default value */
315 }
316 /*
317 * 0x41 actives 1 lane
318 * 0x43 actives 2 lanes
319 * 0x45 actives 3 lanes (never happen)
320 * 0x47 actives 4 lanes
321 */
322 mcam_reg_write(mcam, REG_CSI2_CTRL0,
323 CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane));
324 mcam_reg_write(mcam, REG_CLKCTRL,
325 (mcam->mclk_src << 29) | mcam->mclk_div);
326
327 mcam->mipi_enabled = true;
328 }
329}
330
331static void mcam_disable_mipi(struct mcam_camera *mcam)
332{
333 /* Using Parallel mode or disable MIPI */
334 mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
335 mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
336 mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
337 mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
338 mcam->mipi_enabled = false;
339}
340
d43dae75 341/* ------------------------------------------------------------------- */
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342
343#ifdef MCAM_MODE_VMALLOC
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344/*
345 * Code specific to the vmalloc buffer mode.
346 */
347
348/*
349 * Allocate in-kernel DMA buffers for vmalloc mode.
350 */
351static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
352{
353 int i;
354
355 mcam_set_config_needed(cam, 1);
356 if (loadtime)
357 cam->dma_buf_size = dma_buf_size;
358 else
359 cam->dma_buf_size = cam->pix_format.sizeimage;
360 if (n_dma_bufs > 3)
361 n_dma_bufs = 3;
362
363 cam->nbufs = 0;
364 for (i = 0; i < n_dma_bufs; i++) {
365 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
366 cam->dma_buf_size, cam->dma_handles + i,
367 GFP_KERNEL);
368 if (cam->dma_bufs[i] == NULL) {
369 cam_warn(cam, "Failed to allocate DMA buffer\n");
370 break;
371 }
372 (cam->nbufs)++;
373 }
374
375 switch (cam->nbufs) {
376 case 1:
377 dma_free_coherent(cam->dev, cam->dma_buf_size,
378 cam->dma_bufs[0], cam->dma_handles[0]);
379 cam->nbufs = 0;
380 case 0:
381 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
382 return -ENOMEM;
383
384 case 2:
385 if (n_dma_bufs > 2)
386 cam_warn(cam, "Will limp along with only 2 buffers\n");
387 break;
388 }
389 return 0;
390}
391
392static void mcam_free_dma_bufs(struct mcam_camera *cam)
393{
394 int i;
395
396 for (i = 0; i < cam->nbufs; i++) {
397 dma_free_coherent(cam->dev, cam->dma_buf_size,
398 cam->dma_bufs[i], cam->dma_handles[i]);
399 cam->dma_bufs[i] = NULL;
400 }
401 cam->nbufs = 0;
402}
403
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404
405/*
a9b36e85 406 * Set up DMA buffers when operating in vmalloc mode
abfa3df3 407 */
a9b36e85 408static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
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409{
410 /*
411 * Store the first two Y buffers (we aren't supporting
412 * planar formats for now, so no UV bufs). Then either
413 * set the third if it exists, or tell the controller
414 * to just use two.
415 */
416 mcam_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
417 mcam_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
418 if (cam->nbufs > 2) {
419 mcam_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
420 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
421 } else
422 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
7486af1a 423 if (cam->chip_id == MCAM_CAFE)
67a8dbbc 424 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
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425}
426
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427/*
428 * Copy data out to user space in the vmalloc case
429 */
430static void mcam_frame_tasklet(unsigned long data)
431{
432 struct mcam_camera *cam = (struct mcam_camera *) data;
433 int i;
434 unsigned long flags;
435 struct mcam_vb_buffer *buf;
436
437 spin_lock_irqsave(&cam->dev_lock, flags);
438 for (i = 0; i < cam->nbufs; i++) {
439 int bufno = cam->next_buf;
440
441 if (cam->state != S_STREAMING || bufno < 0)
442 break; /* I/O got stopped */
443 if (++(cam->next_buf) >= cam->nbufs)
444 cam->next_buf = 0;
445 if (!test_bit(bufno, &cam->flags))
446 continue;
447 if (list_empty(&cam->buffers)) {
f698957a 448 cam->frame_state.singles++;
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449 break; /* Leave it valid, hope for better later */
450 }
f698957a 451 cam->frame_state.delivered++;
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452 clear_bit(bufno, &cam->flags);
453 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
454 queue);
455 list_del_init(&buf->queue);
456 /*
457 * Drop the lock during the big copy. This *should* be safe...
458 */
459 spin_unlock_irqrestore(&cam->dev_lock, flags);
460 memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno],
461 cam->pix_format.sizeimage);
462 mcam_buffer_done(cam, bufno, &buf->vb_buf);
463 spin_lock_irqsave(&cam->dev_lock, flags);
464 }
465 spin_unlock_irqrestore(&cam->dev_lock, flags);
466}
467
468
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469/*
470 * Make sure our allocated buffers are up to the task.
471 */
472static int mcam_check_dma_buffers(struct mcam_camera *cam)
473{
474 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
475 mcam_free_dma_bufs(cam);
476 if (cam->nbufs == 0)
477 return mcam_alloc_dma_bufs(cam, 0);
478 return 0;
479}
480
481static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
482{
483 tasklet_schedule(&cam->s_tasklet);
484}
485
486#else /* MCAM_MODE_VMALLOC */
487
488static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
489{
490 return 0;
491}
492
493static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
494{
495 return;
496}
497
498static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
499{
500 return 0;
501}
502
503
504
505#endif /* MCAM_MODE_VMALLOC */
506
507
508#ifdef MCAM_MODE_DMA_CONTIG
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509/* ---------------------------------------------------------------------- */
510/*
511 * DMA-contiguous code.
512 */
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513
514static bool mcam_fmt_is_planar(__u32 pfmt)
515{
516 struct mcam_format_struct *f;
517
518 f = mcam_find_format(pfmt);
519 return f->planar;
520}
521
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522/*
523 * Set up a contiguous buffer for the given frame. Here also is where
524 * the underrun strategy is set: if there is no buffer available, reuse
525 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
526 * keep the interrupt handler from giving that buffer back to user
527 * space. In this way, we always have a buffer to DMA to and don't
528 * have to try to play games stopping and restarting the controller.
529 */
530static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
531{
532 struct mcam_vb_buffer *buf;
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533 struct v4l2_pix_format *fmt = &cam->pix_format;
534 dma_addr_t dma_handle;
535 u32 pixel_count = fmt->width * fmt->height;
536 struct vb2_buffer *vb;
537
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538 /*
539 * If there are no available buffers, go into single mode
540 */
541 if (list_empty(&cam->buffers)) {
542 buf = cam->vb_bufs[frame ^ 0x1];
a9b36e85 543 set_bit(CF_SINGLE_BUFFER, &cam->flags);
f698957a 544 cam->frame_state.singles++;
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545 } else {
546 /*
547 * OK, we have a buffer we can use.
548 */
549 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
550 queue);
551 list_del_init(&buf->queue);
552 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
a9b36e85 553 }
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554
555 cam->vb_bufs[frame] = buf;
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556 vb = &buf->vb_buf;
557
558 dma_handle = vb2_dma_contig_plane_dma_addr(vb, 0);
559 buf->yuv_p.y = dma_handle;
560
561 switch (cam->pix_format.pixelformat) {
562 case V4L2_PIX_FMT_YUV422P:
563 buf->yuv_p.u = buf->yuv_p.y + pixel_count;
564 buf->yuv_p.v = buf->yuv_p.u + pixel_count / 2;
565 break;
566 case V4L2_PIX_FMT_YUV420:
567 buf->yuv_p.u = buf->yuv_p.y + pixel_count;
568 buf->yuv_p.v = buf->yuv_p.u + pixel_count / 4;
569 break;
570 case V4L2_PIX_FMT_YVU420:
571 buf->yuv_p.v = buf->yuv_p.y + pixel_count;
572 buf->yuv_p.u = buf->yuv_p.v + pixel_count / 4;
573 break;
574 default:
575 break;
576 }
577
578 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR, buf->yuv_p.y);
579 if (mcam_fmt_is_planar(fmt->pixelformat)) {
580 mcam_reg_write(cam, frame == 0 ?
581 REG_U0BAR : REG_U1BAR, buf->yuv_p.u);
582 mcam_reg_write(cam, frame == 0 ?
583 REG_V0BAR : REG_V1BAR, buf->yuv_p.v);
584 }
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585}
586
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587/*
588 * Initial B_DMA_contig setup.
589 */
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590static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
591{
592 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
593 cam->nbufs = 2;
594 mcam_set_contig_buffer(cam, 0);
595 mcam_set_contig_buffer(cam, 1);
596}
597
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598/*
599 * Frame completion handling.
600 */
601static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
602{
603 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
604
605 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
f698957a 606 cam->frame_state.delivered++;
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607 mcam_buffer_done(cam, frame, &buf->vb_buf);
608 }
609 mcam_set_contig_buffer(cam, frame);
610}
611
7498469f 612#endif /* MCAM_MODE_DMA_CONTIG */
d43dae75 613
7498469f 614#ifdef MCAM_MODE_DMA_SG
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615/* ---------------------------------------------------------------------- */
616/*
617 * Scatter/gather-specific code.
618 */
a9b36e85 619
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620/*
621 * Set up the next buffer for S/G I/O; caller should be sure that
622 * the controller is stopped and a buffer is available.
623 */
624static void mcam_sg_next_buffer(struct mcam_camera *cam)
a9b36e85 625{
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626 struct mcam_vb_buffer *buf;
627
628 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
629 list_del_init(&buf->queue);
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630 /*
631 * Very Bad Not Good Things happen if you don't clear
632 * C1_DESC_ENA before making any descriptor changes.
633 */
634 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
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635 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
636 mcam_reg_write(cam, REG_DESC_LEN_Y,
637 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
638 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
639 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
121bbe25 640 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
cbc4f3a2 641 cam->vb_bufs[0] = buf;
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642}
643
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644/*
645 * Initial B_DMA_sg setup
646 */
647static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
648{
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649 /*
650 * The list-empty condition can hit us at resume time
651 * if the buffer list was empty when the system was suspended.
652 */
653 if (list_empty(&cam->buffers)) {
654 set_bit(CF_SG_RESTART, &cam->flags);
655 return;
656 }
657
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658 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
659 mcam_sg_next_buffer(cam);
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660 cam->nbufs = 3;
661}
662
d43dae75 663
cbc4f3a2 664/*
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665 * Frame completion with S/G is trickier. We can't muck with
666 * a descriptor chain on the fly, since the controller buffers it
667 * internally. So we have to actually stop and restart; Marvell
668 * says this is the way to do it.
669 *
670 * Of course, stopping is easier said than done; experience shows
671 * that the controller can start a frame *after* C0_ENABLE has been
672 * cleared. So when running in S/G mode, the controller is "stopped"
673 * on receipt of the start-of-frame interrupt. That means we can
674 * safely change the DMA descriptor array here and restart things
675 * (assuming there's another buffer waiting to go).
676 */
677static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
678{
679 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
680
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681 /*
682 * If we're no longer supposed to be streaming, don't do anything.
683 */
684 if (cam->state != S_STREAMING)
685 return;
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686 /*
687 * If we have another buffer available, put it in and
688 * restart the engine.
689 */
690 if (!list_empty(&cam->buffers)) {
691 mcam_sg_next_buffer(cam);
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692 mcam_ctlr_start(cam);
693 /*
694 * Otherwise set CF_SG_RESTART and the controller will
695 * be restarted once another buffer shows up.
696 */
697 } else {
698 set_bit(CF_SG_RESTART, &cam->flags);
f698957a 699 cam->frame_state.singles++;
bb0a896e 700 cam->vb_bufs[0] = NULL;
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701 }
702 /*
703 * Now we can give the completed frame back to user space.
704 */
f698957a 705 cam->frame_state.delivered++;
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706 mcam_buffer_done(cam, frame, &buf->vb_buf);
707}
708
709
710/*
711 * Scatter/gather mode requires stopping the controller between
712 * frames so we can put in a new DMA descriptor array. If no new
713 * buffer exists at frame completion, the controller is left stopped;
714 * this function is charged with gettig things going again.
715 */
716static void mcam_sg_restart(struct mcam_camera *cam)
717{
718 mcam_ctlr_dma_sg(cam);
719 mcam_ctlr_start(cam);
720 clear_bit(CF_SG_RESTART, &cam->flags);
721}
722
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723#else /* MCAM_MODE_DMA_SG */
724
725static inline void mcam_sg_restart(struct mcam_camera *cam)
726{
727 return;
728}
729
730#endif /* MCAM_MODE_DMA_SG */
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731
732/* ---------------------------------------------------------------------- */
733/*
734 * Buffer-mode-independent controller code.
735 */
736
737/*
738 * Image format setup
cbc4f3a2 739 */
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740static void mcam_ctlr_image(struct mcam_camera *cam)
741{
abfa3df3 742 struct v4l2_pix_format *fmt = &cam->pix_format;
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743 u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w;
744
745 cam_dbg(cam, "camera: bytesperline = %d; height = %d\n",
746 fmt->bytesperline, fmt->sizeimage / fmt->bytesperline);
747 imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK;
748 imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK;
749
750 switch (fmt->pixelformat) {
751 case V4L2_PIX_FMT_YUYV:
752 case V4L2_PIX_FMT_UYVY:
753 widthy = fmt->width * 2;
754 widthuv = 0;
755 break;
756 case V4L2_PIX_FMT_JPEG:
757 imgsz_h = (fmt->sizeimage / fmt->bytesperline) << IMGSZ_V_SHIFT;
758 widthy = fmt->bytesperline;
759 widthuv = 0;
760 break;
761 case V4L2_PIX_FMT_YUV422P:
762 case V4L2_PIX_FMT_YUV420:
763 case V4L2_PIX_FMT_YVU420:
764 widthy = fmt->width;
765 widthuv = fmt->width / 2;
766 break;
767 default:
768 widthy = fmt->bytesperline;
769 widthuv = 0;
770 }
771
772 mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy,
773 IMGP_YP_MASK | IMGP_UVP_MASK);
774 mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
775 mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
abfa3df3 776
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777 /*
778 * Tell the controller about the image format we are using.
779 */
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780 switch (fmt->pixelformat) {
781 case V4L2_PIX_FMT_YUV422P:
782 mcam_reg_write_mask(cam, REG_CTRL0,
783 C0_DF_YUV | C0_YUV_PLANAR | C0_YUVE_YVYU, C0_DF_MASK);
784 break;
785 case V4L2_PIX_FMT_YUV420:
786 case V4L2_PIX_FMT_YVU420:
787 mcam_reg_write_mask(cam, REG_CTRL0,
788 C0_DF_YUV | C0_YUV_420PL | C0_YUVE_YVYU, C0_DF_MASK);
789 break;
abfa3df3 790 case V4L2_PIX_FMT_YUYV:
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791 mcam_reg_write_mask(cam, REG_CTRL0,
792 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_UYVY, C0_DF_MASK);
793 break;
794 case V4L2_PIX_FMT_UYVY:
795 mcam_reg_write_mask(cam, REG_CTRL0,
796 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_YUYV, C0_DF_MASK);
797 break;
798 case V4L2_PIX_FMT_JPEG:
799 mcam_reg_write_mask(cam, REG_CTRL0,
800 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_YUYV, C0_DF_MASK);
801 break;
abfa3df3 802 case V4L2_PIX_FMT_RGB444:
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803 mcam_reg_write_mask(cam, REG_CTRL0,
804 C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XRGB, C0_DF_MASK);
abfa3df3 805 /* Alpha value? */
ad6ac452 806 break;
abfa3df3 807 case V4L2_PIX_FMT_RGB565:
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808 mcam_reg_write_mask(cam, REG_CTRL0,
809 C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK);
810 break;
abfa3df3 811 default:
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812 cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat);
813 break;
abfa3df3 814 }
ad6ac452 815
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816 /*
817 * Make sure it knows we want to use hsync/vsync.
818 */
ad6ac452 819 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK);
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820 /*
821 * This field controls the generation of EOF(DVP only)
822 */
823 if (cam->bus_type != V4L2_MBUS_CSI2)
824 mcam_reg_set_bit(cam, REG_CTRL0,
825 C0_EOF_VSYNC | C0_VEDGE_CTRL);
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826}
827
828
829/*
830 * Configure the controller for operation; caller holds the
831 * device mutex.
832 */
833static int mcam_ctlr_configure(struct mcam_camera *cam)
834{
835 unsigned long flags;
836
837 spin_lock_irqsave(&cam->dev_lock, flags);
bb0a896e 838 clear_bit(CF_SG_RESTART, &cam->flags);
7498469f 839 cam->dma_setup(cam);
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840 mcam_ctlr_image(cam);
841 mcam_set_config_needed(cam, 0);
842 spin_unlock_irqrestore(&cam->dev_lock, flags);
843 return 0;
844}
845
846static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
847{
848 /*
849 * Clear any pending interrupts, since we do not
850 * expect to have I/O active prior to enabling.
851 */
852 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
853 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
854}
855
856static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
857{
858 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
859}
860
abfa3df3 861
cbc4f3a2 862
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863static void mcam_ctlr_init(struct mcam_camera *cam)
864{
865 unsigned long flags;
866
867 spin_lock_irqsave(&cam->dev_lock, flags);
868 /*
869 * Make sure it's not powered down.
870 */
871 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
872 /*
873 * Turn off the enable bit. It sure should be off anyway,
874 * but it's good to be sure.
875 */
876 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
877 /*
878 * Clock the sensor appropriately. Controller clock should
879 * be 48MHz, sensor "typical" value is half that.
880 */
881 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
882 spin_unlock_irqrestore(&cam->dev_lock, flags);
883}
884
885
886/*
887 * Stop the controller, and don't return until we're really sure that no
888 * further DMA is going on.
889 */
890static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
891{
892 unsigned long flags;
893
894 /*
895 * Theory: stop the camera controller (whether it is operating
896 * or not). Delay briefly just in case we race with the SOF
897 * interrupt, then wait until no DMA is active.
898 */
899 spin_lock_irqsave(&cam->dev_lock, flags);
cbc4f3a2 900 clear_bit(CF_SG_RESTART, &cam->flags);
abfa3df3 901 mcam_ctlr_stop(cam);
cbc4f3a2 902 cam->state = S_IDLE;
abfa3df3 903 spin_unlock_irqrestore(&cam->dev_lock, flags);
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904 /*
905 * This is a brutally long sleep, but experience shows that
906 * it can take the controller a while to get the message that
907 * it needs to stop grabbing frames. In particular, we can
908 * sometimes (on mmp) get a frame at the end WITHOUT the
909 * start-of-frame indication.
910 */
911 msleep(150);
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912 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
913 cam_err(cam, "Timeout waiting for DMA to end\n");
914 /* This would be bad news - what now? */
915 spin_lock_irqsave(&cam->dev_lock, flags);
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916 mcam_ctlr_irq_disable(cam);
917 spin_unlock_irqrestore(&cam->dev_lock, flags);
918}
919
920/*
921 * Power up and down.
922 */
05fed816 923static int mcam_ctlr_power_up(struct mcam_camera *cam)
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924{
925 unsigned long flags;
05fed816 926 int ret;
abfa3df3
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927
928 spin_lock_irqsave(&cam->dev_lock, flags);
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929 ret = cam->plat_power_up(cam);
930 if (ret) {
931 spin_unlock_irqrestore(&cam->dev_lock, flags);
932 return ret;
933 }
67a8dbbc 934 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
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935 spin_unlock_irqrestore(&cam->dev_lock, flags);
936 msleep(5); /* Just to be sure */
05fed816 937 return 0;
abfa3df3
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938}
939
940static void mcam_ctlr_power_down(struct mcam_camera *cam)
941{
942 unsigned long flags;
943
944 spin_lock_irqsave(&cam->dev_lock, flags);
67a8dbbc
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945 /*
946 * School of hard knocks department: be sure we do any register
947 * twiddling on the controller *before* calling the platform
948 * power down routine.
949 */
abfa3df3 950 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
67a8dbbc 951 cam->plat_power_down(cam);
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952 spin_unlock_irqrestore(&cam->dev_lock, flags);
953}
954
955/* -------------------------------------------------------------------- */
956/*
957 * Communications with the sensor.
958 */
959
960static int __mcam_cam_reset(struct mcam_camera *cam)
961{
962 return sensor_call(cam, core, reset, 0);
963}
964
965/*
966 * We have found the sensor on the i2c. Let's try to have a
967 * conversation.
968 */
969static int mcam_cam_init(struct mcam_camera *cam)
970{
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971 int ret;
972
973 mutex_lock(&cam->s_mutex);
974 if (cam->state != S_NOTREADY)
975 cam_warn(cam, "Cam init with device in funky state %d",
976 cam->state);
977 ret = __mcam_cam_reset(cam);
7486af1a 978 /* Get/set parameters? */
d43dae75 979 cam->state = S_IDLE;
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980 mcam_ctlr_power_down(cam);
981 mutex_unlock(&cam->s_mutex);
982 return ret;
abfa3df3
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983}
984
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985/*
986 * Configure the sensor to match the parameters we have. Caller should
987 * hold s_mutex
988 */
989static int mcam_cam_set_flip(struct mcam_camera *cam)
abfa3df3 990{
d43dae75 991 struct v4l2_control ctrl;
abfa3df3 992
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993 memset(&ctrl, 0, sizeof(ctrl));
994 ctrl.id = V4L2_CID_VFLIP;
995 ctrl.value = flip;
996 return sensor_call(cam, core, s_ctrl, &ctrl);
abfa3df3
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997}
998
999
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1000static int mcam_cam_configure(struct mcam_camera *cam)
1001{
1002 struct v4l2_mbus_framefmt mbus_fmt;
1003 int ret;
abfa3df3 1004
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1005 v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code);
1006 ret = sensor_call(cam, core, init, 0);
1007 if (ret == 0)
1008 ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt);
1009 /*
1010 * OV7670 does weird things if flip is set *before* format...
1011 */
1012 ret += mcam_cam_set_flip(cam);
1013 return ret;
1014}
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1015
1016/*
1017 * Get everything ready, and start grabbing frames.
1018 */
a9b36e85 1019static int mcam_read_setup(struct mcam_camera *cam)
abfa3df3
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1020{
1021 int ret;
1022 unsigned long flags;
1023
1024 /*
1025 * Configuration. If we still don't have DMA buffers,
1026 * make one last, desperate attempt.
1027 */
a9b36e85
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1028 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
1029 mcam_alloc_dma_bufs(cam, 0))
1030 return -ENOMEM;
abfa3df3
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1031
1032 if (mcam_needs_config(cam)) {
1033 mcam_cam_configure(cam);
1034 ret = mcam_ctlr_configure(cam);
1035 if (ret)
1036 return ret;
1037 }
1038
1039 /*
1040 * Turn it loose.
1041 */
1042 spin_lock_irqsave(&cam->dev_lock, flags);
482d35c4 1043 clear_bit(CF_DMA_ACTIVE, &cam->flags);
abfa3df3 1044 mcam_reset_buffers(cam);
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1045 /*
1046 * Update CSI2_DPHY value
1047 */
1048 if (cam->calc_dphy)
1049 cam->calc_dphy(cam);
1050 cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
1051 cam->dphy[0], cam->dphy[1], cam->dphy[2]);
1052 if (cam->bus_type == V4L2_MBUS_CSI2)
1053 mcam_enable_mipi(cam);
1054 else
1055 mcam_disable_mipi(cam);
abfa3df3 1056 mcam_ctlr_irq_enable(cam);
a9b36e85 1057 cam->state = S_STREAMING;
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1058 if (!test_bit(CF_SG_RESTART, &cam->flags))
1059 mcam_ctlr_start(cam);
abfa3df3
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1060 spin_unlock_irqrestore(&cam->dev_lock, flags);
1061 return 0;
1062}
1063
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1064/* ----------------------------------------------------------------------- */
1065/*
1066 * Videobuf2 interface code.
1067 */
abfa3df3 1068
fc714e70
GL
1069static int mcam_vb_queue_setup(struct vb2_queue *vq,
1070 const struct v4l2_format *fmt, unsigned int *nbufs,
035aa147 1071 unsigned int *num_planes, unsigned int sizes[],
b5210fd2 1072 void *alloc_ctxs[])
abfa3df3 1073{
b5210fd2 1074 struct mcam_camera *cam = vb2_get_drv_priv(vq);
cbc4f3a2 1075 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
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1076
1077 sizes[0] = cam->pix_format.sizeimage;
1078 *num_planes = 1; /* Someday we have to support planar formats... */
cbc4f3a2
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1079 if (*nbufs < minbufs)
1080 *nbufs = minbufs;
a9b36e85
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1081 if (cam->buffer_mode == B_DMA_contig)
1082 alloc_ctxs[0] = cam->vb_alloc_ctx;
0c3a14c1
HV
1083 else if (cam->buffer_mode == B_DMA_sg)
1084 alloc_ctxs[0] = cam->vb_alloc_ctx_sg;
b5210fd2
JC
1085 return 0;
1086}
1087
cbc4f3a2 1088
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1089static void mcam_vb_buf_queue(struct vb2_buffer *vb)
1090{
1091 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1092 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1093 unsigned long flags;
a9b36e85 1094 int start;
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1095
1096 spin_lock_irqsave(&cam->dev_lock, flags);
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1097 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
1098 list_add(&mvb->queue, &cam->buffers);
49df19eb 1099 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
cbc4f3a2 1100 mcam_sg_restart(cam);
b5210fd2 1101 spin_unlock_irqrestore(&cam->dev_lock, flags);
a9b36e85
JC
1102 if (start)
1103 mcam_read_setup(cam);
b5210fd2
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1104}
1105
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1106/*
1107 * These need to be called with the mutex held from vb2
1108 */
bd323e28 1109static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
b5210fd2
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1110{
1111 struct mcam_camera *cam = vb2_get_drv_priv(vq);
0a0b3fb4 1112 unsigned int frame;
abfa3df3 1113
bd323e28
MS
1114 if (cam->state != S_IDLE) {
1115 INIT_LIST_HEAD(&cam->buffers);
a9b36e85 1116 return -EINVAL;
bd323e28 1117 }
a9b36e85
JC
1118 cam->sequence = 0;
1119 /*
1120 * Videobuf2 sneakily hoards all the buffers and won't
1121 * give them to us until *after* streaming starts. But
1122 * we can't actually start streaming until we have a
1123 * destination. So go into a wait state and hope they
1124 * give us buffers soon.
1125 */
1126 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
1127 cam->state = S_BUFWAIT;
1128 return 0;
abfa3df3 1129 }
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1130
1131 /*
1132 * Ensure clear the left over frame flags
1133 * before every really start streaming
1134 */
1135 for (frame = 0; frame < cam->nbufs; frame++)
1136 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1137
a9b36e85 1138 return mcam_read_setup(cam);
b5210fd2
JC
1139}
1140
e37559b2 1141static void mcam_vb_stop_streaming(struct vb2_queue *vq)
b5210fd2
JC
1142{
1143 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1144 unsigned long flags;
1145
a9b36e85
JC
1146 if (cam->state == S_BUFWAIT) {
1147 /* They never gave us buffers */
1148 cam->state = S_IDLE;
e37559b2 1149 return;
a9b36e85 1150 }
b5210fd2 1151 if (cam->state != S_STREAMING)
e37559b2 1152 return;
b5210fd2 1153 mcam_ctlr_stop_dma(cam);
7c269f45
LY
1154 /*
1155 * Reset the CCIC PHY after stopping streaming,
1156 * otherwise, the CCIC may be unstable.
1157 */
1158 if (cam->ctlr_reset)
1159 cam->ctlr_reset(cam);
abfa3df3 1160 /*
b5210fd2
JC
1161 * VB2 reclaims the buffers, so we need to forget
1162 * about them.
abfa3df3 1163 */
b5210fd2
JC
1164 spin_lock_irqsave(&cam->dev_lock, flags);
1165 INIT_LIST_HEAD(&cam->buffers);
1166 spin_unlock_irqrestore(&cam->dev_lock, flags);
abfa3df3
JC
1167}
1168
1169
b5210fd2
JC
1170static const struct vb2_ops mcam_vb2_ops = {
1171 .queue_setup = mcam_vb_queue_setup,
b5210fd2
JC
1172 .buf_queue = mcam_vb_buf_queue,
1173 .start_streaming = mcam_vb_start_streaming,
1174 .stop_streaming = mcam_vb_stop_streaming,
519694f9
PL
1175 .wait_prepare = vb2_ops_wait_prepare,
1176 .wait_finish = vb2_ops_wait_finish,
b5210fd2 1177};
abfa3df3 1178
7498469f
JC
1179
1180#ifdef MCAM_MODE_DMA_SG
cbc4f3a2 1181/*
d43dae75
JC
1182 * Scatter/gather mode uses all of the above functions plus a
1183 * few extras to deal with DMA mapping.
cbc4f3a2 1184 */
d43dae75
JC
1185static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1186{
1187 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1188 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1189 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1190
1191 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1192 ndesc * sizeof(struct mcam_dma_desc),
1193 &mvb->dma_desc_pa, GFP_KERNEL);
1194 if (mvb->dma_desc == NULL) {
1195 cam_err(cam, "Unable to get DMA descriptor array\n");
1196 return -ENOMEM;
1197 }
1198 return 0;
1199}
1200
1201static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1202{
1203 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
22301247 1204 struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0);
d43dae75
JC
1205 struct mcam_dma_desc *desc = mvb->dma_desc;
1206 struct scatterlist *sg;
1207 int i;
1208
d790b7ed 1209 for_each_sg(sg_table->sgl, sg, sg_table->nents, i) {
d43dae75
JC
1210 desc->dma_addr = sg_dma_address(sg);
1211 desc->segment_len = sg_dma_len(sg);
1212 desc++;
1213 }
1214 return 0;
1215}
1216
d43dae75
JC
1217static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1218{
1219 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1220 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1221 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1222
1223 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1224 mvb->dma_desc, mvb->dma_desc_pa);
1225}
1226
1227
cbc4f3a2
JC
1228static const struct vb2_ops mcam_vb2_sg_ops = {
1229 .queue_setup = mcam_vb_queue_setup,
1230 .buf_init = mcam_vb_sg_buf_init,
1231 .buf_prepare = mcam_vb_sg_buf_prepare,
1232 .buf_queue = mcam_vb_buf_queue,
cbc4f3a2
JC
1233 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1234 .start_streaming = mcam_vb_start_streaming,
1235 .stop_streaming = mcam_vb_stop_streaming,
519694f9
PL
1236 .wait_prepare = vb2_ops_wait_prepare,
1237 .wait_finish = vb2_ops_wait_finish,
cbc4f3a2
JC
1238};
1239
7498469f
JC
1240#endif /* MCAM_MODE_DMA_SG */
1241
b5210fd2
JC
1242static int mcam_setup_vb2(struct mcam_camera *cam)
1243{
1244 struct vb2_queue *vq = &cam->vb_queue;
abfa3df3 1245
b5210fd2
JC
1246 memset(vq, 0, sizeof(*vq));
1247 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
b5210fd2 1248 vq->drv_priv = cam;
519694f9 1249 vq->lock = &cam->s_mutex;
17d3675a 1250 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
cbc4f3a2
JC
1251 INIT_LIST_HEAD(&cam->buffers);
1252 switch (cam->buffer_mode) {
1253 case B_DMA_contig:
7498469f 1254#ifdef MCAM_MODE_DMA_CONTIG
cbc4f3a2 1255 vq->ops = &mcam_vb2_ops;
a9b36e85 1256 vq->mem_ops = &vb2_dma_contig_memops;
ad6ac452 1257 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
cbc4f3a2 1258 vq->io_modes = VB2_MMAP | VB2_USERPTR;
7498469f
JC
1259 cam->dma_setup = mcam_ctlr_dma_contig;
1260 cam->frame_complete = mcam_dma_contig_done;
0c3a14c1
HV
1261 cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
1262 if (IS_ERR(cam->vb_alloc_ctx))
1263 return PTR_ERR(cam->vb_alloc_ctx);
7498469f 1264#endif
cbc4f3a2
JC
1265 break;
1266 case B_DMA_sg:
7498469f 1267#ifdef MCAM_MODE_DMA_SG
cbc4f3a2
JC
1268 vq->ops = &mcam_vb2_sg_ops;
1269 vq->mem_ops = &vb2_dma_sg_memops;
ad6ac452 1270 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
cbc4f3a2 1271 vq->io_modes = VB2_MMAP | VB2_USERPTR;
7498469f
JC
1272 cam->dma_setup = mcam_ctlr_dma_sg;
1273 cam->frame_complete = mcam_dma_sg_done;
0c3a14c1
HV
1274 cam->vb_alloc_ctx_sg = vb2_dma_sg_init_ctx(cam->dev);
1275 if (IS_ERR(cam->vb_alloc_ctx_sg))
1276 return PTR_ERR(cam->vb_alloc_ctx_sg);
7498469f 1277#endif
cbc4f3a2
JC
1278 break;
1279 case B_vmalloc:
7498469f
JC
1280#ifdef MCAM_MODE_VMALLOC
1281 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1282 (unsigned long) cam);
cbc4f3a2 1283 vq->ops = &mcam_vb2_ops;
a9b36e85 1284 vq->mem_ops = &vb2_vmalloc_memops;
cbc4f3a2
JC
1285 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1286 vq->io_modes = VB2_MMAP;
7498469f
JC
1287 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1288 cam->frame_complete = mcam_vmalloc_done;
1289#endif
cbc4f3a2
JC
1290 break;
1291 }
b5210fd2
JC
1292 return vb2_queue_init(vq);
1293}
1294
1295static void mcam_cleanup_vb2(struct mcam_camera *cam)
1296{
1297 vb2_queue_release(&cam->vb_queue);
7498469f 1298#ifdef MCAM_MODE_DMA_CONTIG
a9b36e85
JC
1299 if (cam->buffer_mode == B_DMA_contig)
1300 vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx);
7498469f 1301#endif
0c3a14c1
HV
1302#ifdef MCAM_MODE_DMA_SG
1303 if (cam->buffer_mode == B_DMA_sg)
1304 vb2_dma_sg_cleanup_ctx(cam->vb_alloc_ctx_sg);
1305#endif
b5210fd2
JC
1306}
1307
abfa3df3 1308
d43dae75 1309/* ---------------------------------------------------------------------- */
abfa3df3 1310/*
d43dae75 1311 * The long list of V4L2 ioctl() operations.
abfa3df3
JC
1312 */
1313
abfa3df3
JC
1314static int mcam_vidioc_streamon(struct file *filp, void *priv,
1315 enum v4l2_buf_type type)
1316{
1317 struct mcam_camera *cam = filp->private_data;
b5210fd2 1318 int ret;
abfa3df3 1319
abfa3df3 1320 mutex_lock(&cam->s_mutex);
b5210fd2 1321 ret = vb2_streamon(&cam->vb_queue, type);
abfa3df3 1322 mutex_unlock(&cam->s_mutex);
abfa3df3
JC
1323 return ret;
1324}
1325
1326
1327static int mcam_vidioc_streamoff(struct file *filp, void *priv,
1328 enum v4l2_buf_type type)
1329{
1330 struct mcam_camera *cam = filp->private_data;
b5210fd2 1331 int ret;
abfa3df3 1332
abfa3df3 1333 mutex_lock(&cam->s_mutex);
b5210fd2 1334 ret = vb2_streamoff(&cam->vb_queue, type);
abfa3df3 1335 mutex_unlock(&cam->s_mutex);
abfa3df3
JC
1336 return ret;
1337}
1338
1339
abfa3df3
JC
1340static int mcam_vidioc_reqbufs(struct file *filp, void *priv,
1341 struct v4l2_requestbuffers *req)
1342{
1343 struct mcam_camera *cam = filp->private_data;
b5210fd2 1344 int ret;
abfa3df3 1345
abfa3df3 1346 mutex_lock(&cam->s_mutex);
b5210fd2 1347 ret = vb2_reqbufs(&cam->vb_queue, req);
abfa3df3
JC
1348 mutex_unlock(&cam->s_mutex);
1349 return ret;
1350}
1351
1352
1353static int mcam_vidioc_querybuf(struct file *filp, void *priv,
1354 struct v4l2_buffer *buf)
1355{
1356 struct mcam_camera *cam = filp->private_data;
b5210fd2 1357 int ret;
abfa3df3
JC
1358
1359 mutex_lock(&cam->s_mutex);
d43dae75 1360 ret = vb2_querybuf(&cam->vb_queue, buf);
abfa3df3 1361 mutex_unlock(&cam->s_mutex);
d43dae75 1362 return ret;
abfa3df3
JC
1363}
1364
d43dae75
JC
1365static int mcam_vidioc_qbuf(struct file *filp, void *priv,
1366 struct v4l2_buffer *buf)
1367{
1368 struct mcam_camera *cam = filp->private_data;
1369 int ret;
abfa3df3 1370
d43dae75
JC
1371 mutex_lock(&cam->s_mutex);
1372 ret = vb2_qbuf(&cam->vb_queue, buf);
1373 mutex_unlock(&cam->s_mutex);
1374 return ret;
1375}
abfa3df3 1376
d43dae75
JC
1377static int mcam_vidioc_dqbuf(struct file *filp, void *priv,
1378 struct v4l2_buffer *buf)
abfa3df3
JC
1379{
1380 struct mcam_camera *cam = filp->private_data;
b5210fd2 1381 int ret;
abfa3df3 1382
b5210fd2 1383 mutex_lock(&cam->s_mutex);
d43dae75 1384 ret = vb2_dqbuf(&cam->vb_queue, buf, filp->f_flags & O_NONBLOCK);
b5210fd2
JC
1385 mutex_unlock(&cam->s_mutex);
1386 return ret;
abfa3df3
JC
1387}
1388
abfa3df3
JC
1389static int mcam_vidioc_querycap(struct file *file, void *priv,
1390 struct v4l2_capability *cap)
1391{
b7b68393
HV
1392 struct mcam_camera *cam = priv;
1393
abfa3df3
JC
1394 strcpy(cap->driver, "marvell_ccic");
1395 strcpy(cap->card, "marvell_ccic");
b7b68393 1396 strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info));
a020c747 1397 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
abfa3df3 1398 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
a020c747 1399 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
abfa3df3
JC
1400 return 0;
1401}
1402
1403
abfa3df3
JC
1404static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1405 void *priv, struct v4l2_fmtdesc *fmt)
1406{
1407 if (fmt->index >= N_MCAM_FMTS)
1408 return -EINVAL;
1409 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1410 sizeof(fmt->description));
1411 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1412 return 0;
1413}
1414
1415static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1416 struct v4l2_format *fmt)
1417{
1418 struct mcam_camera *cam = priv;
1419 struct mcam_format_struct *f;
1420 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1421 struct v4l2_mbus_framefmt mbus_fmt;
1422 int ret;
1423
1424 f = mcam_find_format(pix->pixelformat);
1425 pix->pixelformat = f->pixelformat;
1426 v4l2_fill_mbus_format(&mbus_fmt, pix, f->mbus_code);
1427 mutex_lock(&cam->s_mutex);
1428 ret = sensor_call(cam, video, try_mbus_fmt, &mbus_fmt);
1429 mutex_unlock(&cam->s_mutex);
1430 v4l2_fill_pix_format(pix, &mbus_fmt);
ad6ac452
LY
1431 switch (f->pixelformat) {
1432 case V4L2_PIX_FMT_YUV420:
1433 case V4L2_PIX_FMT_YVU420:
1434 pix->bytesperline = pix->width * 3 / 2;
1435 break;
1436 default:
1437 pix->bytesperline = pix->width * f->bpp;
1438 break;
1439 }
abfa3df3 1440 pix->sizeimage = pix->height * pix->bytesperline;
2e6e6095 1441 pix->colorspace = V4L2_COLORSPACE_SRGB;
abfa3df3
JC
1442 return ret;
1443}
1444
1445static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1446 struct v4l2_format *fmt)
1447{
1448 struct mcam_camera *cam = priv;
1449 struct mcam_format_struct *f;
1450 int ret;
1451
1452 /*
1453 * Can't do anything if the device is not idle
1454 * Also can't if there are streaming buffers in place.
1455 */
b5210fd2 1456 if (cam->state != S_IDLE || cam->vb_queue.num_buffers > 0)
abfa3df3
JC
1457 return -EBUSY;
1458
1459 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1460
1461 /*
1462 * See if the formatting works in principle.
1463 */
1464 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1465 if (ret)
1466 return ret;
1467 /*
1468 * Now we start to change things for real, so let's do it
1469 * under lock.
1470 */
1471 mutex_lock(&cam->s_mutex);
1472 cam->pix_format = fmt->fmt.pix;
1473 cam->mbus_code = f->mbus_code;
1474
1475 /*
1476 * Make sure we have appropriate DMA buffers.
1477 */
a9b36e85 1478 if (cam->buffer_mode == B_vmalloc) {
7498469f
JC
1479 ret = mcam_check_dma_buffers(cam);
1480 if (ret)
1481 goto out;
abfa3df3 1482 }
a9b36e85 1483 mcam_set_config_needed(cam, 1);
abfa3df3
JC
1484out:
1485 mutex_unlock(&cam->s_mutex);
1486 return ret;
1487}
1488
1489/*
1490 * Return our stored notion of how the camera is/should be configured.
1491 * The V4l2 spec wants us to be smarter, and actually get this from
1492 * the camera (and not mess with it at open time). Someday.
1493 */
1494static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1495 struct v4l2_format *f)
1496{
1497 struct mcam_camera *cam = priv;
1498
1499 f->fmt.pix = cam->pix_format;
1500 return 0;
1501}
1502
1503/*
1504 * We only have one input - the sensor - so minimize the nonsense here.
1505 */
1506static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1507 struct v4l2_input *input)
1508{
1509 if (input->index != 0)
1510 return -EINVAL;
1511
1512 input->type = V4L2_INPUT_TYPE_CAMERA;
abfa3df3
JC
1513 strcpy(input->name, "Camera");
1514 return 0;
1515}
1516
1517static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1518{
1519 *i = 0;
1520 return 0;
1521}
1522
1523static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1524{
1525 if (i != 0)
1526 return -EINVAL;
1527 return 0;
1528}
1529
abfa3df3
JC
1530/*
1531 * G/S_PARM. Most of this is done by the sensor, but we are
1532 * the level which controls the number of read buffers.
1533 */
1534static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1535 struct v4l2_streamparm *parms)
1536{
1537 struct mcam_camera *cam = priv;
1538 int ret;
1539
1540 mutex_lock(&cam->s_mutex);
1541 ret = sensor_call(cam, video, g_parm, parms);
1542 mutex_unlock(&cam->s_mutex);
1543 parms->parm.capture.readbuffers = n_dma_bufs;
1544 return ret;
1545}
1546
1547static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1548 struct v4l2_streamparm *parms)
1549{
1550 struct mcam_camera *cam = priv;
1551 int ret;
1552
1553 mutex_lock(&cam->s_mutex);
1554 ret = sensor_call(cam, video, s_parm, parms);
1555 mutex_unlock(&cam->s_mutex);
1556 parms->parm.capture.readbuffers = n_dma_bufs;
1557 return ret;
1558}
1559
abfa3df3
JC
1560static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1561 struct v4l2_frmsizeenum *sizes)
1562{
1563 struct mcam_camera *cam = priv;
17bef885
HV
1564 struct mcam_format_struct *f;
1565 struct v4l2_subdev_frame_size_enum fse = {
1566 .index = sizes->index,
1567 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1568 };
abfa3df3
JC
1569 int ret;
1570
17bef885
HV
1571 f = mcam_find_format(sizes->pixel_format);
1572 if (f->pixelformat != sizes->pixel_format)
1573 return -EINVAL;
1574 fse.code = f->mbus_code;
abfa3df3 1575 mutex_lock(&cam->s_mutex);
17bef885 1576 ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse);
abfa3df3 1577 mutex_unlock(&cam->s_mutex);
17bef885
HV
1578 if (ret)
1579 return ret;
1580 if (fse.min_width == fse.max_width &&
1581 fse.min_height == fse.max_height) {
1582 sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1583 sizes->discrete.width = fse.min_width;
1584 sizes->discrete.height = fse.min_height;
1585 return 0;
1586 }
1587 sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1588 sizes->stepwise.min_width = fse.min_width;
1589 sizes->stepwise.max_width = fse.max_width;
1590 sizes->stepwise.min_height = fse.min_height;
1591 sizes->stepwise.max_height = fse.max_height;
1592 sizes->stepwise.step_width = 1;
1593 sizes->stepwise.step_height = 1;
1594 return 0;
abfa3df3
JC
1595}
1596
1597static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1598 struct v4l2_frmivalenum *interval)
1599{
1600 struct mcam_camera *cam = priv;
17bef885
HV
1601 struct mcam_format_struct *f;
1602 struct v4l2_subdev_frame_interval_enum fie = {
1603 .index = interval->index,
1604 .width = interval->width,
1605 .height = interval->height,
1606 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1607 };
abfa3df3
JC
1608 int ret;
1609
17bef885
HV
1610 f = mcam_find_format(interval->pixel_format);
1611 if (f->pixelformat != interval->pixel_format)
1612 return -EINVAL;
1613 fie.code = f->mbus_code;
abfa3df3 1614 mutex_lock(&cam->s_mutex);
17bef885 1615 ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie);
abfa3df3 1616 mutex_unlock(&cam->s_mutex);
17bef885
HV
1617 if (ret)
1618 return ret;
1619 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1620 interval->discrete = fie.interval;
1621 return 0;
abfa3df3
JC
1622}
1623
1624#ifdef CONFIG_VIDEO_ADV_DEBUG
1625static int mcam_vidioc_g_register(struct file *file, void *priv,
1626 struct v4l2_dbg_register *reg)
1627{
1628 struct mcam_camera *cam = priv;
1629
4e032f3f
HV
1630 if (reg->reg > cam->regs_size - 4)
1631 return -EINVAL;
7486af1a
HV
1632 reg->val = mcam_reg_read(cam, reg->reg);
1633 reg->size = 4;
1634 return 0;
abfa3df3
JC
1635}
1636
1637static int mcam_vidioc_s_register(struct file *file, void *priv,
977ba3b1 1638 const struct v4l2_dbg_register *reg)
abfa3df3
JC
1639{
1640 struct mcam_camera *cam = priv;
1641
4e032f3f
HV
1642 if (reg->reg > cam->regs_size - 4)
1643 return -EINVAL;
7486af1a
HV
1644 mcam_reg_write(cam, reg->reg, reg->val);
1645 return 0;
abfa3df3
JC
1646}
1647#endif
1648
abfa3df3
JC
1649static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1650 .vidioc_querycap = mcam_vidioc_querycap,
1651 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1652 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1653 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1654 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1655 .vidioc_enum_input = mcam_vidioc_enum_input,
1656 .vidioc_g_input = mcam_vidioc_g_input,
1657 .vidioc_s_input = mcam_vidioc_s_input,
abfa3df3
JC
1658 .vidioc_reqbufs = mcam_vidioc_reqbufs,
1659 .vidioc_querybuf = mcam_vidioc_querybuf,
1660 .vidioc_qbuf = mcam_vidioc_qbuf,
1661 .vidioc_dqbuf = mcam_vidioc_dqbuf,
1662 .vidioc_streamon = mcam_vidioc_streamon,
1663 .vidioc_streamoff = mcam_vidioc_streamoff,
abfa3df3
JC
1664 .vidioc_g_parm = mcam_vidioc_g_parm,
1665 .vidioc_s_parm = mcam_vidioc_s_parm,
1666 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1667 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
abfa3df3
JC
1668#ifdef CONFIG_VIDEO_ADV_DEBUG
1669 .vidioc_g_register = mcam_vidioc_g_register,
1670 .vidioc_s_register = mcam_vidioc_s_register,
1671#endif
1672};
1673
abfa3df3
JC
1674/* ---------------------------------------------------------------------- */
1675/*
d43dae75 1676 * Our various file operations.
abfa3df3 1677 */
d43dae75
JC
1678static int mcam_v4l_open(struct file *filp)
1679{
1680 struct mcam_camera *cam = video_drvdata(filp);
1681 int ret = 0;
abfa3df3 1682
d43dae75 1683 filp->private_data = cam;
abfa3df3 1684
f698957a
LY
1685 cam->frame_state.frames = 0;
1686 cam->frame_state.singles = 0;
1687 cam->frame_state.delivered = 0;
d43dae75
JC
1688 mutex_lock(&cam->s_mutex);
1689 if (cam->users == 0) {
1690 ret = mcam_setup_vb2(cam);
1691 if (ret)
1692 goto out;
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LY
1693 ret = mcam_ctlr_power_up(cam);
1694 if (ret)
1695 goto out;
d43dae75
JC
1696 __mcam_cam_reset(cam);
1697 mcam_set_config_needed(cam, 1);
1698 }
1699 (cam->users)++;
1700out:
1701 mutex_unlock(&cam->s_mutex);
1702 return ret;
a9b36e85 1703}
abfa3df3 1704
abfa3df3 1705
d43dae75
JC
1706static int mcam_v4l_release(struct file *filp)
1707{
1708 struct mcam_camera *cam = filp->private_data;
b5210fd2 1709
f698957a
LY
1710 cam_dbg(cam, "Release, %d frames, %d singles, %d delivered\n",
1711 cam->frame_state.frames, cam->frame_state.singles,
1712 cam->frame_state.delivered);
d43dae75
JC
1713 mutex_lock(&cam->s_mutex);
1714 (cam->users)--;
d43dae75 1715 if (cam->users == 0) {
0770d07f 1716 mcam_ctlr_stop_dma(cam);
d43dae75 1717 mcam_cleanup_vb2(cam);
05fed816 1718 mcam_disable_mipi(cam);
d43dae75
JC
1719 mcam_ctlr_power_down(cam);
1720 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1721 mcam_free_dma_bufs(cam);
1722 }
05fed816 1723
d43dae75
JC
1724 mutex_unlock(&cam->s_mutex);
1725 return 0;
abfa3df3
JC
1726}
1727
d43dae75
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1728static ssize_t mcam_v4l_read(struct file *filp,
1729 char __user *buffer, size_t len, loff_t *pos)
a9b36e85 1730{
d43dae75
JC
1731 struct mcam_camera *cam = filp->private_data;
1732 int ret;
a9b36e85 1733
d43dae75
JC
1734 mutex_lock(&cam->s_mutex);
1735 ret = vb2_read(&cam->vb_queue, buffer, len, pos,
1736 filp->f_flags & O_NONBLOCK);
1737 mutex_unlock(&cam->s_mutex);
1738 return ret;
a9b36e85 1739}
abfa3df3 1740
d43dae75
JC
1741
1742
1743static unsigned int mcam_v4l_poll(struct file *filp,
1744 struct poll_table_struct *pt)
cbc4f3a2 1745{
d43dae75
JC
1746 struct mcam_camera *cam = filp->private_data;
1747 int ret;
cbc4f3a2 1748
d43dae75
JC
1749 mutex_lock(&cam->s_mutex);
1750 ret = vb2_poll(&cam->vb_queue, filp, pt);
1751 mutex_unlock(&cam->s_mutex);
1752 return ret;
1753}
1754
1755
1756static int mcam_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
1757{
1758 struct mcam_camera *cam = filp->private_data;
1759 int ret;
1760
1761 mutex_lock(&cam->s_mutex);
1762 ret = vb2_mmap(&cam->vb_queue, vma);
1763 mutex_unlock(&cam->s_mutex);
1764 return ret;
cbc4f3a2
JC
1765}
1766
1767
abfa3df3 1768
d43dae75
JC
1769static const struct v4l2_file_operations mcam_v4l_fops = {
1770 .owner = THIS_MODULE,
1771 .open = mcam_v4l_open,
1772 .release = mcam_v4l_release,
1773 .read = mcam_v4l_read,
1774 .poll = mcam_v4l_poll,
1775 .mmap = mcam_v4l_mmap,
1776 .unlocked_ioctl = video_ioctl2,
1777};
1778
1779
1780/*
1781 * This template device holds all of those v4l2 methods; we
1782 * clone it for specific real devices.
1783 */
1784static struct video_device mcam_v4l_template = {
1785 .name = "mcam",
1786 .tvnorms = V4L2_STD_NTSC_M,
d43dae75
JC
1787
1788 .fops = &mcam_v4l_fops,
1789 .ioctl_ops = &mcam_v4l_ioctl_ops,
1790 .release = video_device_release_empty,
1791};
1792
1793/* ---------------------------------------------------------------------- */
1794/*
1795 * Interrupt handler stuff
1796 */
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JC
1797static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1798{
1799 /*
1800 * Basic frame housekeeping.
1801 */
abfa3df3
JC
1802 set_bit(frame, &cam->flags);
1803 clear_bit(CF_DMA_ACTIVE, &cam->flags);
a9b36e85 1804 cam->next_buf = frame;
abfa3df3 1805 cam->buf_seq[frame] = ++(cam->sequence);
f698957a 1806 cam->frame_state.frames++;
abfa3df3 1807 /*
cbc4f3a2 1808 * "This should never happen"
abfa3df3 1809 */
cbc4f3a2
JC
1810 if (cam->state != S_STREAMING)
1811 return;
1812 /*
1813 * Process the frame and set up the next one.
1814 */
7498469f 1815 cam->frame_complete(cam, frame);
abfa3df3
JC
1816}
1817
1818
d43dae75
JC
1819/*
1820 * The interrupt handler; this needs to be called from the
1821 * platform irq handler with the lock held.
1822 */
abfa3df3
JC
1823int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1824{
1825 unsigned int frame, handled = 0;
1826
1827 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1828 /*
1829 * Handle any frame completions. There really should
1830 * not be more than one of these, or we have fallen
1831 * far behind.
cbc4f3a2
JC
1832 *
1833 * When running in S/G mode, the frame number lacks any
1834 * real meaning - there's only one descriptor array - but
1835 * the controller still picks a different one to signal
1836 * each time.
abfa3df3
JC
1837 */
1838 for (frame = 0; frame < cam->nbufs; frame++)
0a0b3fb4
LY
1839 if (irqs & (IRQ_EOF0 << frame) &&
1840 test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) {
abfa3df3
JC
1841 mcam_frame_complete(cam, frame);
1842 handled = 1;
0a0b3fb4 1843 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
f2354dd1
JC
1844 if (cam->buffer_mode == B_DMA_sg)
1845 break;
abfa3df3
JC
1846 }
1847 /*
1848 * If a frame starts, note that we have DMA active. This
1849 * code assumes that we won't get multiple frame interrupts
1850 * at once; may want to rethink that.
1851 */
0a0b3fb4
LY
1852 for (frame = 0; frame < cam->nbufs; frame++) {
1853 if (irqs & (IRQ_SOF0 << frame)) {
1854 set_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1855 handled = IRQ_HANDLED;
1856 }
1857 }
1858
1859 if (handled == IRQ_HANDLED) {
abfa3df3 1860 set_bit(CF_DMA_ACTIVE, &cam->flags);
cbc4f3a2
JC
1861 if (cam->buffer_mode == B_DMA_sg)
1862 mcam_ctlr_stop(cam);
abfa3df3
JC
1863 }
1864 return handled;
1865}
1866
d43dae75 1867/* ---------------------------------------------------------------------- */
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JC
1868/*
1869 * Registration and such.
1870 */
abfa3df3 1871static struct ov7670_config sensor_cfg = {
abfa3df3
JC
1872 /*
1873 * Exclude QCIF mode, because it only captures a tiny portion
1874 * of the sensor FOV
1875 */
1876 .min_width = 320,
1877 .min_height = 240,
1878};
1879
1880
1881int mccic_register(struct mcam_camera *cam)
1882{
1883 struct i2c_board_info ov7670_info = {
1884 .type = "ov7670",
1c68f889 1885 .addr = 0x42 >> 1,
abfa3df3
JC
1886 .platform_data = &sensor_cfg,
1887 };
1888 int ret;
1889
7498469f
JC
1890 /*
1891 * Validate the requested buffer mode.
1892 */
1893 if (buffer_mode >= 0)
1894 cam->buffer_mode = buffer_mode;
1895 if (cam->buffer_mode == B_DMA_sg &&
7486af1a 1896 cam->chip_id == MCAM_CAFE) {
7498469f
JC
1897 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1898 "attempting vmalloc mode instead\n");
1899 cam->buffer_mode = B_vmalloc;
1900 }
1901 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1902 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1903 cam->buffer_mode);
1904 return -EINVAL;
1905 }
abfa3df3
JC
1906 /*
1907 * Register with V4L
1908 */
1909 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1910 if (ret)
1911 return ret;
1912
1913 mutex_init(&cam->s_mutex);
1914 cam->state = S_NOTREADY;
1915 mcam_set_config_needed(cam, 1);
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JC
1916 cam->pix_format = mcam_def_pix_format;
1917 cam->mbus_code = mcam_def_mbus_code;
b5210fd2 1918 INIT_LIST_HEAD(&cam->buffers);
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JC
1919 mcam_ctlr_init(cam);
1920
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JC
1921 /*
1922 * Try to find the sensor.
1923 */
2164b5af
JC
1924 sensor_cfg.clock_speed = cam->clock_speed;
1925 sensor_cfg.use_smbus = cam->use_smbus;
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JC
1926 cam->sensor_addr = ov7670_info.addr;
1927 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
595a93a4 1928 cam->i2c_adapter, &ov7670_info, NULL);
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JC
1929 if (cam->sensor == NULL) {
1930 ret = -ENODEV;
1931 goto out_unregister;
1932 }
1933
1934 ret = mcam_cam_init(cam);
1935 if (ret)
1936 goto out_unregister;
1937 /*
1938 * Get the v4l2 setup done.
1939 */
593403c5
JM
1940 ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1941 if (ret)
1942 goto out_unregister;
1943 cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1944
abfa3df3
JC
1945 mutex_lock(&cam->s_mutex);
1946 cam->vdev = mcam_v4l_template;
abfa3df3 1947 cam->vdev.v4l2_dev = &cam->v4l2_dev;
593403c5 1948 video_set_drvdata(&cam->vdev, cam);
abfa3df3
JC
1949 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1950 if (ret)
1951 goto out;
abfa3df3
JC
1952
1953 /*
1954 * If so requested, try to get our DMA buffers now.
1955 */
a9b36e85 1956 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
abfa3df3
JC
1957 if (mcam_alloc_dma_bufs(cam, 1))
1958 cam_warn(cam, "Unable to alloc DMA buffers at load"
1959 " will try again later.");
1960 }
1961
1962out:
593403c5 1963 v4l2_ctrl_handler_free(&cam->ctrl_handler);
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JC
1964 mutex_unlock(&cam->s_mutex);
1965 return ret;
1966out_unregister:
1967 v4l2_device_unregister(&cam->v4l2_dev);
1968 return ret;
1969}
1970
1971
1972void mccic_shutdown(struct mcam_camera *cam)
1973{
67a8dbbc
JC
1974 /*
1975 * If we have no users (and we really, really should have no
1976 * users) the device will already be powered down. Trying to
1977 * take it down again will wedge the machine, which is frowned
1978 * upon.
1979 */
1980 if (cam->users > 0) {
abfa3df3 1981 cam_warn(cam, "Removing a device with users!\n");
67a8dbbc
JC
1982 mcam_ctlr_power_down(cam);
1983 }
b5210fd2 1984 vb2_queue_release(&cam->vb_queue);
a9b36e85
JC
1985 if (cam->buffer_mode == B_vmalloc)
1986 mcam_free_dma_bufs(cam);
abfa3df3 1987 video_unregister_device(&cam->vdev);
593403c5 1988 v4l2_ctrl_handler_free(&cam->ctrl_handler);
abfa3df3
JC
1989 v4l2_device_unregister(&cam->v4l2_dev);
1990}
1991
1992/*
1993 * Power management
1994 */
1995#ifdef CONFIG_PM
1996
1997void mccic_suspend(struct mcam_camera *cam)
1998{
bb0a896e
JC
1999 mutex_lock(&cam->s_mutex);
2000 if (cam->users > 0) {
2001 enum mcam_state cstate = cam->state;
abfa3df3 2002
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JC
2003 mcam_ctlr_stop_dma(cam);
2004 mcam_ctlr_power_down(cam);
2005 cam->state = cstate;
2006 }
2007 mutex_unlock(&cam->s_mutex);
abfa3df3
JC
2008}
2009
2010int mccic_resume(struct mcam_camera *cam)
2011{
2012 int ret = 0;
2013
2014 mutex_lock(&cam->s_mutex);
2015 if (cam->users > 0) {
05fed816
LY
2016 ret = mcam_ctlr_power_up(cam);
2017 if (ret) {
2018 mutex_unlock(&cam->s_mutex);
2019 return ret;
2020 }
abfa3df3
JC
2021 __mcam_cam_reset(cam);
2022 } else {
2023 mcam_ctlr_power_down(cam);
2024 }
2025 mutex_unlock(&cam->s_mutex);
2026
2027 set_bit(CF_CONFIG_NEEDED, &cam->flags);
bb0a896e
JC
2028 if (cam->state == S_STREAMING) {
2029 /*
2030 * If there was a buffer in the DMA engine at suspend
2031 * time, put it back on the queue or we'll forget about it.
2032 */
2033 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
2034 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
a9b36e85 2035 ret = mcam_read_setup(cam);
bb0a896e 2036 }
abfa3df3
JC
2037 return ret;
2038}
2039#endif /* CONFIG_PM */
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