Commit | Line | Data |
---|---|---|
4f67130a GL |
1 | /* |
2 | * V4L2 Driver for i.MX3x camera host | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
4f67130a GL |
14 | #include <linux/videodev2.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/interrupt.h> | |
f39c1ab3 | 19 | #include <linux/sched.h> |
4f67130a GL |
20 | |
21 | #include <media/v4l2-common.h> | |
22 | #include <media/v4l2-dev.h> | |
379fa5d3 | 23 | #include <media/videobuf2-dma-contig.h> |
4f67130a | 24 | #include <media/soc_camera.h> |
760697be | 25 | #include <media/soc_mediabus.h> |
4f67130a GL |
26 | |
27 | #include <mach/ipu.h> | |
28 | #include <mach/mx3_camera.h> | |
a8de6635 | 29 | #include <mach/dma.h> |
4f67130a GL |
30 | |
31 | #define MX3_CAM_DRV_NAME "mx3-camera" | |
32 | ||
33 | /* CMOS Sensor Interface Registers */ | |
34 | #define CSI_REG_START 0x60 | |
35 | ||
36 | #define CSI_SENS_CONF (0x60 - CSI_REG_START) | |
37 | #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START) | |
38 | #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START) | |
39 | #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START) | |
40 | #define CSI_TST_CTRL (0x70 - CSI_REG_START) | |
41 | #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START) | |
42 | #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START) | |
43 | #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START) | |
44 | #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START) | |
45 | #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START) | |
46 | ||
47 | #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 | |
48 | #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 | |
49 | #define CSI_SENS_CONF_DATA_POL_SHIFT 2 | |
50 | #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 | |
51 | #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 | |
52 | #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7 | |
53 | #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 | |
54 | #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10 | |
55 | #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 | |
56 | #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 | |
57 | ||
58 | #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
59 | #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
60 | #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
61 | ||
62 | #define MAX_VIDEO_MEM 16 | |
63 | ||
64 | struct mx3_camera_buffer { | |
65 | /* common v4l buffer stuff -- must be first */ | |
379fa5d3 | 66 | struct vb2_buffer vb; |
379fa5d3 | 67 | struct list_head queue; |
4f67130a GL |
68 | |
69 | /* One descriptot per scatterlist (per frame) */ | |
70 | struct dma_async_tx_descriptor *txd; | |
71 | ||
72 | /* We have to "build" a scatterlist ourselves - one element per frame */ | |
73 | struct scatterlist sg; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct mx3_camera_dev - i.MX3x camera (CSI) object | |
78 | * @dev: camera device, to which the coherent buffer is attached | |
79 | * @icd: currently attached camera sensor | |
80 | * @clk: pointer to clock | |
81 | * @base: remapped register base address | |
82 | * @pdata: platform data | |
83 | * @platform_flags: platform flags | |
84 | * @mclk: master clock frequency in Hz | |
85 | * @capture: list of capture videobuffers | |
86 | * @lock: protects video buffer lists | |
87 | * @active: active video buffer | |
88 | * @idmac_channel: array of pointers to IPU DMAC DMA channels | |
89 | * @soc_host: embedded soc_host object | |
90 | */ | |
91 | struct mx3_camera_dev { | |
4f67130a GL |
92 | /* |
93 | * i.MX3x is only supposed to handle one camera on its Camera Sensor | |
94 | * Interface. If anyone ever builds hardware to enable more than one | |
95 | * camera _simultaneously_, they will have to modify this driver too | |
96 | */ | |
97 | struct soc_camera_device *icd; | |
98 | struct clk *clk; | |
99 | ||
100 | void __iomem *base; | |
101 | ||
102 | struct mx3_camera_pdata *pdata; | |
103 | ||
104 | unsigned long platform_flags; | |
105 | unsigned long mclk; | |
579cea03 | 106 | u16 width_flags; /* max 15 bits */ |
4f67130a GL |
107 | |
108 | struct list_head capture; | |
109 | spinlock_t lock; /* Protects video buffer lists */ | |
110 | struct mx3_camera_buffer *active; | |
07f92448 | 111 | size_t buf_total; |
379fa5d3 GL |
112 | struct vb2_alloc_ctx *alloc_ctx; |
113 | enum v4l2_field field; | |
114 | int sequence; | |
4f67130a GL |
115 | |
116 | /* IDMAC / dmaengine interface */ | |
117 | struct idmac_channel *idmac_channel[1]; /* We need one channel */ | |
118 | ||
119 | struct soc_camera_host soc_host; | |
120 | }; | |
121 | ||
122 | struct dma_chan_request { | |
123 | struct mx3_camera_dev *mx3_cam; | |
124 | enum ipu_channel id; | |
125 | }; | |
126 | ||
4f67130a GL |
127 | static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg) |
128 | { | |
129 | return __raw_readl(mx3->base + reg); | |
130 | } | |
131 | ||
132 | static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg) | |
133 | { | |
134 | __raw_writel(value, mx3->base + reg); | |
135 | } | |
136 | ||
379fa5d3 GL |
137 | static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb) |
138 | { | |
139 | return container_of(vb, struct mx3_camera_buffer, vb); | |
140 | } | |
141 | ||
4f67130a GL |
142 | /* Called from the IPU IDMAC ISR */ |
143 | static void mx3_cam_dma_done(void *arg) | |
144 | { | |
145 | struct idmac_tx_desc *desc = to_tx_desc(arg); | |
146 | struct dma_chan *chan = desc->txd.chan; | |
147 | struct idmac_channel *ichannel = to_idmac_chan(chan); | |
148 | struct mx3_camera_dev *mx3_cam = ichannel->client; | |
4f67130a GL |
149 | |
150 | dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", | |
151 | desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0); | |
152 | ||
153 | spin_lock(&mx3_cam->lock); | |
154 | if (mx3_cam->active) { | |
379fa5d3 GL |
155 | struct vb2_buffer *vb = &mx3_cam->active->vb; |
156 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); | |
157 | ||
158 | list_del_init(&buf->queue); | |
159 | do_gettimeofday(&vb->v4l2_buf.timestamp); | |
160 | vb->v4l2_buf.field = mx3_cam->field; | |
161 | vb->v4l2_buf.sequence = mx3_cam->sequence++; | |
162 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
4f67130a GL |
163 | } |
164 | ||
165 | if (list_empty(&mx3_cam->capture)) { | |
166 | mx3_cam->active = NULL; | |
167 | spin_unlock(&mx3_cam->lock); | |
168 | ||
169 | /* | |
170 | * stop capture - without further buffers IPU_CHA_BUF0_RDY will | |
171 | * not get updated | |
172 | */ | |
173 | return; | |
174 | } | |
175 | ||
176 | mx3_cam->active = list_entry(mx3_cam->capture.next, | |
379fa5d3 | 177 | struct mx3_camera_buffer, queue); |
4f67130a GL |
178 | spin_unlock(&mx3_cam->lock); |
179 | } | |
180 | ||
4f67130a GL |
181 | /* |
182 | * Videobuf operations | |
183 | */ | |
184 | ||
185 | /* | |
186 | * Calculate the __buffer__ (not data) size and number of buffers. | |
4f67130a | 187 | */ |
379fa5d3 | 188 | static int mx3_videobuf_setup(struct vb2_queue *vq, |
fc714e70 | 189 | const struct v4l2_format *fmt, |
379fa5d3 | 190 | unsigned int *count, unsigned int *num_planes, |
035aa147 | 191 | unsigned int sizes[], void *alloc_ctxs[]) |
4f67130a | 192 | { |
379fa5d3 | 193 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
7dfff953 | 194 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 195 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a GL |
196 | |
197 | if (!mx3_cam->idmac_channel[0]) | |
198 | return -EINVAL; | |
199 | ||
07f92448 GL |
200 | if (fmt) { |
201 | const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd, | |
202 | fmt->fmt.pix.pixelformat); | |
bed8d803 LP |
203 | unsigned int bytes_per_line; |
204 | int ret; | |
2b61d46e | 205 | |
07f92448 GL |
206 | if (!xlate) |
207 | return -EINVAL; | |
2b61d46e | 208 | |
bed8d803 LP |
209 | ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width, |
210 | xlate->host_fmt); | |
211 | if (ret < 0) | |
212 | return ret; | |
2b61d46e | 213 | |
bed8d803 LP |
214 | bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret); |
215 | ||
216 | ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line, | |
217 | fmt->fmt.pix.height); | |
218 | if (ret < 0) | |
219 | return ret; | |
220 | ||
221 | sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret); | |
07f92448 GL |
222 | } else { |
223 | /* Called from VIDIOC_REQBUFS or in compatibility mode */ | |
2b61d46e | 224 | sizes[0] = icd->sizeimage; |
07f92448 | 225 | } |
4f67130a | 226 | |
07f92448 | 227 | alloc_ctxs[0] = mx3_cam->alloc_ctx; |
4f67130a | 228 | |
07f92448 GL |
229 | if (!vq->num_buffers) |
230 | mx3_cam->sequence = 0; | |
4f67130a | 231 | |
07f92448 GL |
232 | if (!*count) |
233 | *count = 2; | |
4f67130a | 234 | |
07f92448 GL |
235 | /* If *num_planes != 0, we have already verified *count. */ |
236 | if (!*num_planes && | |
237 | sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024) | |
238 | *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) / | |
239 | sizes[0]; | |
4f67130a | 240 | |
07f92448 | 241 | *num_planes = 1; |
4f67130a | 242 | |
379fa5d3 | 243 | return 0; |
4f67130a GL |
244 | } |
245 | ||
246 | static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc) | |
247 | { | |
248 | /* Add more formats as need arises and test possibilities appear... */ | |
249 | switch (fourcc) { | |
4f67130a GL |
250 | case V4L2_PIX_FMT_RGB24: |
251 | return IPU_PIX_FMT_RGB24; | |
a48be1d6 AP |
252 | case V4L2_PIX_FMT_UYVY: |
253 | case V4L2_PIX_FMT_RGB565: | |
4f67130a GL |
254 | default: |
255 | return IPU_PIX_FMT_GENERIC; | |
256 | } | |
257 | } | |
258 | ||
379fa5d3 | 259 | static void mx3_videobuf_queue(struct vb2_buffer *vb) |
4f67130a | 260 | { |
379fa5d3 | 261 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 262 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 263 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 | 264 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 GL |
265 | struct scatterlist *sg = &buf->sg; |
266 | struct dma_async_tx_descriptor *txd; | |
267 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
4f67130a | 268 | struct idmac_video_param *video = &ichan->params.video; |
07f92448 | 269 | const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt; |
379fa5d3 | 270 | unsigned long flags; |
07f92448 GL |
271 | dma_cookie_t cookie; |
272 | size_t new_size; | |
273 | ||
2b61d46e | 274 | new_size = icd->sizeimage; |
07f92448 GL |
275 | |
276 | if (vb2_plane_size(vb, 0) < new_size) { | |
277 | dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n", | |
278 | vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size); | |
279 | goto error; | |
280 | } | |
281 | ||
c72f429f | 282 | if (!buf->txd) { |
07f92448 GL |
283 | sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0); |
284 | sg_dma_len(sg) = new_size; | |
285 | ||
16052827 | 286 | txd = dmaengine_prep_slave_sg( |
e0d23ef2 | 287 | &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM, |
07f92448 GL |
288 | DMA_PREP_INTERRUPT); |
289 | if (!txd) | |
290 | goto error; | |
291 | ||
292 | txd->callback_param = txd; | |
293 | txd->callback = mx3_cam_dma_done; | |
294 | ||
07f92448 GL |
295 | buf->txd = txd; |
296 | } else { | |
297 | txd = buf->txd; | |
298 | } | |
299 | ||
300 | vb2_set_plane_payload(vb, 0, new_size); | |
4f67130a GL |
301 | |
302 | /* This is the configuration of one sg-element */ | |
07f92448 | 303 | video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc); |
a48be1d6 AP |
304 | |
305 | if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) { | |
306 | /* | |
07f92448 GL |
307 | * If the IPU DMA channel is configured to transfer generic |
308 | * 8-bit data, we have to set up the geometry parameters | |
309 | * correctly, according to the current pixel format. The DMA | |
310 | * horizontal parameters in this case are expressed in bytes, | |
311 | * not in pixels. | |
a48be1d6 | 312 | */ |
1c0f95ee | 313 | video->out_width = icd->bytesperline; |
a48be1d6 | 314 | video->out_height = icd->user_height; |
1c0f95ee | 315 | video->out_stride = icd->bytesperline; |
a48be1d6 AP |
316 | } else { |
317 | /* | |
318 | * For IPU known formats the pixel unit will be managed | |
319 | * successfully by the IPU code | |
320 | */ | |
321 | video->out_width = icd->user_width; | |
322 | video->out_height = icd->user_height; | |
323 | video->out_stride = icd->user_width; | |
324 | } | |
4f67130a GL |
325 | |
326 | #ifdef DEBUG | |
327 | /* helps to see what DMA actually has written */ | |
379fa5d3 GL |
328 | if (vb2_plane_vaddr(vb, 0)) |
329 | memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0)); | |
4f67130a GL |
330 | #endif |
331 | ||
379fa5d3 GL |
332 | spin_lock_irqsave(&mx3_cam->lock, flags); |
333 | list_add_tail(&buf->queue, &mx3_cam->capture); | |
4f67130a | 334 | |
379fa5d3 | 335 | if (!mx3_cam->active) |
4f67130a | 336 | mx3_cam->active = buf; |
4f67130a | 337 | |
2dd54a54 | 338 | spin_unlock_irq(&mx3_cam->lock); |
4f67130a GL |
339 | |
340 | cookie = txd->tx_submit(txd); | |
7dfff953 | 341 | dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n", |
0166b743 | 342 | cookie, sg_dma_address(&buf->sg)); |
2dd54a54 | 343 | |
4f67130a GL |
344 | if (cookie >= 0) |
345 | return; | |
346 | ||
379fa5d3 | 347 | spin_lock_irq(&mx3_cam->lock); |
4f67130a | 348 | |
379fa5d3 GL |
349 | /* Submit error */ |
350 | list_del_init(&buf->queue); | |
4f67130a GL |
351 | |
352 | if (mx3_cam->active == buf) | |
353 | mx3_cam->active = NULL; | |
379fa5d3 GL |
354 | |
355 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
07f92448 | 356 | error: |
379fa5d3 | 357 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); |
4f67130a GL |
358 | } |
359 | ||
379fa5d3 | 360 | static void mx3_videobuf_release(struct vb2_buffer *vb) |
4f67130a | 361 | { |
379fa5d3 | 362 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 363 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 364 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 GL |
365 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
366 | struct dma_async_tx_descriptor *txd = buf->txd; | |
4f67130a GL |
367 | unsigned long flags; |
368 | ||
7dfff953 | 369 | dev_dbg(icd->parent, |
379fa5d3 | 370 | "Release%s DMA 0x%08x, queue %sempty\n", |
4f67130a | 371 | mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), |
379fa5d3 GL |
372 | list_empty(&buf->queue) ? "" : "not "); |
373 | ||
4f67130a | 374 | spin_lock_irqsave(&mx3_cam->lock, flags); |
4f67130a | 375 | |
379fa5d3 GL |
376 | if (mx3_cam->active == buf) |
377 | mx3_cam->active = NULL; | |
378 | ||
379 | /* Doesn't hurt also if the list is empty */ | |
380 | list_del_init(&buf->queue); | |
379fa5d3 GL |
381 | |
382 | if (txd) { | |
383 | buf->txd = NULL; | |
384 | if (mx3_cam->idmac_channel[0]) | |
385 | async_tx_ack(txd); | |
4f67130a | 386 | } |
379fa5d3 | 387 | |
4f67130a | 388 | spin_unlock_irqrestore(&mx3_cam->lock, flags); |
07f92448 GL |
389 | |
390 | mx3_cam->buf_total -= vb2_plane_size(vb, 0); | |
4f67130a GL |
391 | } |
392 | ||
379fa5d3 GL |
393 | static int mx3_videobuf_init(struct vb2_buffer *vb) |
394 | { | |
07f92448 GL |
395 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
396 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
397 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 | 398 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 | 399 | |
c72f429f AG |
400 | if (!buf->txd) { |
401 | /* This is for locking debugging only */ | |
402 | INIT_LIST_HEAD(&buf->queue); | |
403 | sg_init_table(&buf->sg, 1); | |
379fa5d3 | 404 | |
c72f429f AG |
405 | mx3_cam->buf_total += vb2_plane_size(vb, 0); |
406 | } | |
379fa5d3 GL |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
08a31b96 GL |
411 | static int mx3_stop_streaming(struct vb2_queue *q) |
412 | { | |
413 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
7dfff953 | 414 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
08a31b96 GL |
415 | struct mx3_camera_dev *mx3_cam = ici->priv; |
416 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
08a31b96 GL |
417 | struct mx3_camera_buffer *buf, *tmp; |
418 | unsigned long flags; | |
419 | ||
420 | if (ichan) { | |
07f92448 GL |
421 | struct dma_chan *chan = &ichan->dma_chan; |
422 | chan->device->device_control(chan, DMA_PAUSE, 0); | |
08a31b96 GL |
423 | } |
424 | ||
425 | spin_lock_irqsave(&mx3_cam->lock, flags); | |
426 | ||
427 | mx3_cam->active = NULL; | |
428 | ||
429 | list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) { | |
08a31b96 | 430 | list_del_init(&buf->queue); |
07f92448 | 431 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); |
08a31b96 GL |
432 | } |
433 | ||
434 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
379fa5d3 GL |
439 | static struct vb2_ops mx3_videobuf_ops = { |
440 | .queue_setup = mx3_videobuf_setup, | |
379fa5d3 GL |
441 | .buf_queue = mx3_videobuf_queue, |
442 | .buf_cleanup = mx3_videobuf_release, | |
443 | .buf_init = mx3_videobuf_init, | |
444 | .wait_prepare = soc_camera_unlock, | |
445 | .wait_finish = soc_camera_lock, | |
08a31b96 | 446 | .stop_streaming = mx3_stop_streaming, |
4f67130a GL |
447 | }; |
448 | ||
379fa5d3 | 449 | static int mx3_camera_init_videobuf(struct vb2_queue *q, |
4f67130a GL |
450 | struct soc_camera_device *icd) |
451 | { | |
379fa5d3 GL |
452 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
453 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
454 | q->drv_priv = icd; | |
455 | q->ops = &mx3_videobuf_ops; | |
456 | q->mem_ops = &vb2_dma_contig_memops; | |
457 | q->buf_struct_size = sizeof(struct mx3_camera_buffer); | |
458 | ||
459 | return vb2_queue_init(q); | |
4f67130a GL |
460 | } |
461 | ||
462 | /* First part of ipu_csi_init_interface() */ | |
463 | static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam, | |
464 | struct soc_camera_device *icd) | |
465 | { | |
466 | u32 conf; | |
467 | long rate; | |
468 | ||
469 | /* Set default size: ipu_csi_set_window_size() */ | |
470 | csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE); | |
471 | /* ...and position to 0:0: ipu_csi_set_window_pos() */ | |
472 | conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
473 | csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL); | |
474 | ||
475 | /* We use only gated clock synchronisation mode so far */ | |
476 | conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT; | |
477 | ||
478 | /* Set generic data, platform-biggest bus-width */ | |
479 | conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
480 | ||
481 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
482 | conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
483 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
484 | conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
485 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
486 | conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
487 | else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/ | |
488 | conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
489 | ||
490 | if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC) | |
491 | conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; | |
492 | if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC) | |
493 | conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT; | |
494 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
495 | conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
496 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
497 | conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
498 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
499 | conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
500 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
501 | conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
502 | ||
503 | /* ipu_csi_init_interface() */ | |
504 | csi_reg_write(mx3_cam, conf, CSI_SENS_CONF); | |
505 | ||
fdf7748b | 506 | clk_prepare_enable(mx3_cam->clk); |
4f67130a | 507 | rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); |
7dfff953 | 508 | dev_dbg(icd->parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate); |
4f67130a GL |
509 | if (rate) |
510 | clk_set_rate(mx3_cam->clk, rate); | |
511 | } | |
512 | ||
513 | /* Called with .video_lock held */ | |
514 | static int mx3_camera_add_device(struct soc_camera_device *icd) | |
515 | { | |
7dfff953 | 516 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 517 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a | 518 | |
979ea1dd GL |
519 | if (mx3_cam->icd) |
520 | return -EBUSY; | |
4f67130a GL |
521 | |
522 | mx3_camera_activate(mx3_cam, icd); | |
4f67130a | 523 | |
07f92448 | 524 | mx3_cam->buf_total = 0; |
4f67130a GL |
525 | mx3_cam->icd = icd; |
526 | ||
7dfff953 | 527 | dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n", |
40e2e092 GL |
528 | icd->devnum); |
529 | ||
530 | return 0; | |
4f67130a GL |
531 | } |
532 | ||
533 | /* Called with .video_lock held */ | |
534 | static void mx3_camera_remove_device(struct soc_camera_device *icd) | |
535 | { | |
7dfff953 | 536 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a GL |
537 | struct mx3_camera_dev *mx3_cam = ici->priv; |
538 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
539 | ||
540 | BUG_ON(icd != mx3_cam->icd); | |
541 | ||
542 | if (*ichan) { | |
543 | dma_release_channel(&(*ichan)->dma_chan); | |
544 | *ichan = NULL; | |
545 | } | |
546 | ||
fdf7748b | 547 | clk_disable_unprepare(mx3_cam->clk); |
4f67130a GL |
548 | |
549 | mx3_cam->icd = NULL; | |
550 | ||
7dfff953 | 551 | dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n", |
4f67130a GL |
552 | icd->devnum); |
553 | } | |
554 | ||
4f67130a GL |
555 | static int test_platform_param(struct mx3_camera_dev *mx3_cam, |
556 | unsigned char buswidth, unsigned long *flags) | |
557 | { | |
579cea03 GL |
558 | /* |
559 | * If requested data width is supported by the platform, use it or any | |
560 | * possible lower value - i.MX31 is smart enough to shift bits | |
561 | */ | |
562 | if (buswidth > fls(mx3_cam->width_flags)) | |
563 | return -EINVAL; | |
564 | ||
4f67130a GL |
565 | /* |
566 | * Platform specified synchronization and pixel clock polarities are | |
567 | * only a recommendation and are only used during probing. MX3x | |
568 | * camera interface only works in master mode, i.e., uses HSYNC and | |
569 | * VSYNC signals from the sensor | |
570 | */ | |
579cea03 GL |
571 | *flags = V4L2_MBUS_MASTER | |
572 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
573 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
574 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
575 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
576 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
577 | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
578 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
579 | V4L2_MBUS_DATA_ACTIVE_LOW; | |
4f67130a GL |
580 | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static int mx3_camera_try_bus_param(struct soc_camera_device *icd, | |
585 | const unsigned int depth) | |
586 | { | |
579cea03 | 587 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 588 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 589 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 GL |
590 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
591 | unsigned long bus_flags, common_flags; | |
4f67130a GL |
592 | int ret = test_platform_param(mx3_cam, depth, &bus_flags); |
593 | ||
7dfff953 | 594 | dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret); |
4f67130a GL |
595 | |
596 | if (ret < 0) | |
597 | return ret; | |
598 | ||
579cea03 GL |
599 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
600 | if (!ret) { | |
601 | common_flags = soc_mbus_config_compatible(&cfg, | |
602 | bus_flags); | |
603 | if (!common_flags) { | |
604 | dev_warn(icd->parent, | |
605 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
606 | cfg.flags, bus_flags); | |
607 | return -EINVAL; | |
608 | } | |
609 | } else if (ret != -ENOIOCTLCMD) { | |
610 | return ret; | |
611 | } | |
4f67130a | 612 | |
579cea03 | 613 | return 0; |
4f67130a GL |
614 | } |
615 | ||
616 | static bool chan_filter(struct dma_chan *chan, void *arg) | |
617 | { | |
618 | struct dma_chan_request *rq = arg; | |
619 | struct mx3_camera_pdata *pdata; | |
620 | ||
a8de6635 SH |
621 | if (!imx_dma_is_ipu(chan)) |
622 | return false; | |
623 | ||
4f67130a GL |
624 | if (!rq) |
625 | return false; | |
626 | ||
979ea1dd | 627 | pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data; |
4f67130a GL |
628 | |
629 | return rq->id == chan->chan_id && | |
630 | pdata->dma_dev == chan->device->dev; | |
631 | } | |
632 | ||
760697be | 633 | static const struct soc_mbus_pixelfmt mx3_camera_formats[] = { |
4f67130a | 634 | { |
760697be GL |
635 | .fourcc = V4L2_PIX_FMT_SBGGR8, |
636 | .name = "Bayer BGGR (sRGB) 8 bit", | |
637 | .bits_per_sample = 8, | |
638 | .packing = SOC_MBUS_PACKING_NONE, | |
639 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 640 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a | 641 | }, { |
760697be GL |
642 | .fourcc = V4L2_PIX_FMT_GREY, |
643 | .name = "Monochrome 8 bit", | |
644 | .bits_per_sample = 8, | |
645 | .packing = SOC_MBUS_PACKING_NONE, | |
646 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 647 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a GL |
648 | }, |
649 | }; | |
650 | ||
760697be GL |
651 | /* This will be corrected as we get more formats */ |
652 | static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
4f67130a | 653 | { |
760697be GL |
654 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
655 | (fmt->bits_per_sample == 8 && | |
656 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
657 | (fmt->bits_per_sample > 8 && | |
658 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
4f67130a GL |
659 | } |
660 | ||
3805f201 | 661 | static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
4f67130a GL |
662 | struct soc_camera_format_xlate *xlate) |
663 | { | |
760697be | 664 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 665 | struct device *dev = icd->parent; |
760697be GL |
666 | int formats = 0, ret; |
667 | enum v4l2_mbus_pixelcode code; | |
668 | const struct soc_mbus_pixelfmt *fmt; | |
4f67130a | 669 | |
760697be GL |
670 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
671 | if (ret < 0) | |
672 | /* No more formats */ | |
673 | return 0; | |
4f67130a | 674 | |
760697be GL |
675 | fmt = soc_mbus_get_fmtdesc(code); |
676 | if (!fmt) { | |
7dfff953 | 677 | dev_warn(icd->parent, |
d2dcad49 | 678 | "Unsupported format code #%u: %d\n", idx, code); |
4f67130a | 679 | return 0; |
760697be | 680 | } |
4f67130a | 681 | |
760697be GL |
682 | /* This also checks support for the requested bits-per-sample */ |
683 | ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample); | |
4f67130a GL |
684 | if (ret < 0) |
685 | return 0; | |
686 | ||
760697be GL |
687 | switch (code) { |
688 | case V4L2_MBUS_FMT_SBGGR10_1X10: | |
4f67130a GL |
689 | formats++; |
690 | if (xlate) { | |
760697be GL |
691 | xlate->host_fmt = &mx3_camera_formats[0]; |
692 | xlate->code = code; | |
4f67130a | 693 | xlate++; |
760697be GL |
694 | dev_dbg(dev, "Providing format %s using code %d\n", |
695 | mx3_camera_formats[0].name, code); | |
4f67130a | 696 | } |
760697be GL |
697 | break; |
698 | case V4L2_MBUS_FMT_Y10_1X10: | |
4f67130a GL |
699 | formats++; |
700 | if (xlate) { | |
760697be GL |
701 | xlate->host_fmt = &mx3_camera_formats[1]; |
702 | xlate->code = code; | |
4f67130a | 703 | xlate++; |
760697be GL |
704 | dev_dbg(dev, "Providing format %s using code %d\n", |
705 | mx3_camera_formats[1].name, code); | |
4f67130a | 706 | } |
760697be | 707 | break; |
4f67130a | 708 | default: |
760697be GL |
709 | if (!mx3_camera_packing_supported(fmt)) |
710 | return 0; | |
711 | } | |
712 | ||
713 | /* Generic pass-through */ | |
714 | formats++; | |
715 | if (xlate) { | |
716 | xlate->host_fmt = fmt; | |
717 | xlate->code = code; | |
a48be1d6 AP |
718 | dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n", |
719 | (fmt->fourcc >> (0*8)) & 0xFF, | |
720 | (fmt->fourcc >> (1*8)) & 0xFF, | |
721 | (fmt->fourcc >> (2*8)) & 0xFF, | |
722 | (fmt->fourcc >> (3*8)) & 0xFF); | |
760697be | 723 | xlate++; |
4f67130a GL |
724 | } |
725 | ||
726 | return formats; | |
727 | } | |
728 | ||
09e231b3 | 729 | static void configure_geometry(struct mx3_camera_dev *mx3_cam, |
a48be1d6 | 730 | unsigned int width, unsigned int height, |
d2dcad49 | 731 | const struct soc_mbus_pixelfmt *fmt) |
4f67130a | 732 | { |
4f67130a | 733 | u32 ctrl, width_field, height_field; |
a48be1d6 AP |
734 | |
735 | if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) { | |
736 | /* | |
737 | * As the CSI will be configured to output BAYER, here | |
738 | * the width parameter count the number of samples to | |
739 | * capture to complete the whole image width. | |
740 | */ | |
cc552b62 GL |
741 | unsigned int num, den; |
742 | int ret = soc_mbus_samples_per_pixel(fmt, &num, &den); | |
743 | BUG_ON(ret < 0); | |
744 | width = width * num / den; | |
a48be1d6 | 745 | } |
4f67130a GL |
746 | |
747 | /* Setup frame size - this cannot be changed on-the-fly... */ | |
6a6c8786 GL |
748 | width_field = width - 1; |
749 | height_field = height - 1; | |
4f67130a GL |
750 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); |
751 | ||
752 | csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); | |
753 | csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2); | |
754 | ||
755 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE); | |
756 | ||
757 | /* ...and position */ | |
758 | ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
759 | /* Sensor does the cropping */ | |
760 | csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); | |
09e231b3 GL |
761 | } |
762 | ||
763 | static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) | |
764 | { | |
765 | dma_cap_mask_t mask; | |
766 | struct dma_chan *chan; | |
767 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
768 | /* We have to use IDMAC_IC_7 for Bayer / generic data */ | |
769 | struct dma_chan_request rq = {.mx3_cam = mx3_cam, | |
770 | .id = IDMAC_IC_7}; | |
771 | ||
09e231b3 GL |
772 | dma_cap_zero(mask); |
773 | dma_cap_set(DMA_SLAVE, mask); | |
774 | dma_cap_set(DMA_PRIVATE, mask); | |
775 | chan = dma_request_channel(mask, chan_filter, &rq); | |
776 | if (!chan) | |
777 | return -EBUSY; | |
778 | ||
779 | *ichan = to_idmac_chan(chan); | |
780 | (*ichan)->client = mx3_cam; | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
6a6c8786 GL |
785 | /* |
786 | * FIXME: learn to use stride != width, then we can keep stride properly aligned | |
787 | * and support arbitrary (even) widths. | |
788 | */ | |
e26b3144 | 789 | static inline void stride_align(__u32 *width) |
6a6c8786 | 790 | { |
d2dcad49 GL |
791 | if (ALIGN(*width, 8) < 4096) |
792 | *width = ALIGN(*width, 8); | |
6a6c8786 GL |
793 | else |
794 | *width = *width & ~7; | |
795 | } | |
796 | ||
797 | /* | |
798 | * As long as we don't implement host-side cropping and scaling, we can use | |
799 | * default g_crop and cropcap from soc_camera.c | |
800 | */ | |
09e231b3 | 801 | static int mx3_camera_set_crop(struct soc_camera_device *icd, |
08590b96 | 802 | struct v4l2_crop *a) |
09e231b3 | 803 | { |
08590b96 | 804 | struct v4l2_rect *rect = &a->c; |
7dfff953 | 805 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 806 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 807 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
760697be | 808 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 809 | int ret; |
09e231b3 | 810 | |
6a6c8786 GL |
811 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); |
812 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
813 | ||
814 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
815 | if (ret < 0) | |
816 | return ret; | |
817 | ||
d2dcad49 | 818 | /* The capture device might have changed its output sizes */ |
760697be | 819 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
820 | if (ret < 0) |
821 | return ret; | |
822 | ||
d2dcad49 GL |
823 | if (mf.code != icd->current_fmt->code) |
824 | return -EINVAL; | |
825 | ||
760697be | 826 | if (mf.width & 7) { |
6a6c8786 | 827 | /* Ouch! We can only handle 8-byte aligned width... */ |
760697be GL |
828 | stride_align(&mf.width); |
829 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
09e231b3 GL |
830 | if (ret < 0) |
831 | return ret; | |
832 | } | |
833 | ||
379fa5d3 | 834 | if (mf.width != icd->user_width || mf.height != icd->user_height) |
d2dcad49 GL |
835 | configure_geometry(mx3_cam, mf.width, mf.height, |
836 | icd->current_fmt->host_fmt); | |
6a6c8786 | 837 | |
7dfff953 | 838 | dev_dbg(icd->parent, "Sensor cropped %dx%d\n", |
760697be | 839 | mf.width, mf.height); |
6a6c8786 | 840 | |
760697be GL |
841 | icd->user_width = mf.width; |
842 | icd->user_height = mf.height; | |
6a6c8786 GL |
843 | |
844 | return ret; | |
09e231b3 GL |
845 | } |
846 | ||
847 | static int mx3_camera_set_fmt(struct soc_camera_device *icd, | |
848 | struct v4l2_format *f) | |
849 | { | |
7dfff953 | 850 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 851 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 852 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
853 | const struct soc_camera_format_xlate *xlate; |
854 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 855 | struct v4l2_mbus_framefmt mf; |
09e231b3 GL |
856 | int ret; |
857 | ||
858 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
859 | if (!xlate) { | |
7dfff953 | 860 | dev_warn(icd->parent, "Format %x not found\n", |
0166b743 | 861 | pix->pixelformat); |
09e231b3 GL |
862 | return -EINVAL; |
863 | } | |
864 | ||
6a6c8786 | 865 | stride_align(&pix->width); |
7dfff953 | 866 | dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height); |
6a6c8786 | 867 | |
09e231b3 GL |
868 | /* |
869 | * Might have to perform a complete interface initialisation like in | |
870 | * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider | |
871 | * mxc_v4l2_s_fmt() | |
872 | */ | |
873 | ||
d2dcad49 | 874 | configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt); |
4f67130a | 875 | |
760697be GL |
876 | mf.width = pix->width; |
877 | mf.height = pix->height; | |
878 | mf.field = pix->field; | |
879 | mf.colorspace = pix->colorspace; | |
880 | mf.code = xlate->code; | |
881 | ||
882 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
883 | if (ret < 0) | |
884 | return ret; | |
885 | ||
886 | if (mf.code != xlate->code) | |
887 | return -EINVAL; | |
888 | ||
379fa5d3 GL |
889 | if (!mx3_cam->idmac_channel[0]) { |
890 | ret = acquire_dma_channel(mx3_cam); | |
891 | if (ret < 0) | |
892 | return ret; | |
893 | } | |
894 | ||
760697be GL |
895 | pix->width = mf.width; |
896 | pix->height = mf.height; | |
897 | pix->field = mf.field; | |
379fa5d3 | 898 | mx3_cam->field = mf.field; |
760697be GL |
899 | pix->colorspace = mf.colorspace; |
900 | icd->current_fmt = xlate; | |
4f67130a | 901 | |
7dfff953 | 902 | dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height); |
6a6c8786 | 903 | |
4f67130a GL |
904 | return ret; |
905 | } | |
906 | ||
907 | static int mx3_camera_try_fmt(struct soc_camera_device *icd, | |
908 | struct v4l2_format *f) | |
909 | { | |
c9c1f1c0 | 910 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
4f67130a GL |
911 | const struct soc_camera_format_xlate *xlate; |
912 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 913 | struct v4l2_mbus_framefmt mf; |
4f67130a | 914 | __u32 pixfmt = pix->pixelformat; |
4f67130a GL |
915 | int ret; |
916 | ||
917 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
918 | if (pixfmt && !xlate) { | |
7dfff953 | 919 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
4f67130a GL |
920 | return -EINVAL; |
921 | } | |
922 | ||
923 | /* limit to MX3 hardware capabilities */ | |
924 | if (pix->height > 4096) | |
925 | pix->height = 4096; | |
926 | if (pix->width > 4096) | |
927 | pix->width = 4096; | |
928 | ||
4f67130a | 929 | /* limit to sensor capabilities */ |
760697be GL |
930 | mf.width = pix->width; |
931 | mf.height = pix->height; | |
932 | mf.field = pix->field; | |
933 | mf.colorspace = pix->colorspace; | |
934 | mf.code = xlate->code; | |
4f67130a | 935 | |
760697be GL |
936 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
937 | if (ret < 0) | |
938 | return ret; | |
4f67130a | 939 | |
760697be GL |
940 | pix->width = mf.width; |
941 | pix->height = mf.height; | |
942 | pix->colorspace = mf.colorspace; | |
943 | ||
944 | switch (mf.field) { | |
945 | case V4L2_FIELD_ANY: | |
4f67130a | 946 | pix->field = V4L2_FIELD_NONE; |
760697be GL |
947 | break; |
948 | case V4L2_FIELD_NONE: | |
949 | break; | |
950 | default: | |
7dfff953 | 951 | dev_err(icd->parent, "Field type %d unsupported.\n", |
760697be GL |
952 | mf.field); |
953 | ret = -EINVAL; | |
4f67130a GL |
954 | } |
955 | ||
956 | return ret; | |
957 | } | |
958 | ||
57bee29d | 959 | static int mx3_camera_reqbufs(struct soc_camera_device *icd, |
4f67130a GL |
960 | struct v4l2_requestbuffers *p) |
961 | { | |
962 | return 0; | |
963 | } | |
964 | ||
965 | static unsigned int mx3_camera_poll(struct file *file, poll_table *pt) | |
966 | { | |
57bee29d | 967 | struct soc_camera_device *icd = file->private_data; |
4f67130a | 968 | |
379fa5d3 | 969 | return vb2_poll(&icd->vb2_vidq, file, pt); |
4f67130a GL |
970 | } |
971 | ||
972 | static int mx3_camera_querycap(struct soc_camera_host *ici, | |
973 | struct v4l2_capability *cap) | |
974 | { | |
975 | /* cap->name is set by the firendly caller:-> */ | |
976 | strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card)); | |
4f67130a GL |
977 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
8843d119 | 982 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd) |
4f67130a | 983 | { |
579cea03 | 984 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 985 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 986 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 | 987 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 988 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
579cea03 | 989 | unsigned long bus_flags, common_flags; |
4f67130a | 990 | u32 dw, sens_conf; |
760697be GL |
991 | const struct soc_mbus_pixelfmt *fmt; |
992 | int buswidth; | |
993 | int ret; | |
4f67130a | 994 | const struct soc_camera_format_xlate *xlate; |
7dfff953 | 995 | struct device *dev = icd->parent; |
4f67130a | 996 | |
760697be GL |
997 | fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code); |
998 | if (!fmt) | |
999 | return -EINVAL; | |
1000 | ||
4f67130a GL |
1001 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1002 | if (!xlate) { | |
0166b743 | 1003 | dev_warn(dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
1004 | return -EINVAL; |
1005 | } | |
1006 | ||
579cea03 GL |
1007 | buswidth = fmt->bits_per_sample; |
1008 | ret = test_platform_param(mx3_cam, buswidth, &bus_flags); | |
1009 | ||
760697be | 1010 | dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret); |
4f67130a GL |
1011 | |
1012 | if (ret < 0) | |
1013 | return ret; | |
1014 | ||
579cea03 GL |
1015 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1016 | if (!ret) { | |
1017 | common_flags = soc_mbus_config_compatible(&cfg, | |
1018 | bus_flags); | |
1019 | if (!common_flags) { | |
1020 | dev_warn(icd->parent, | |
1021 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1022 | cfg.flags, bus_flags); | |
1023 | return -EINVAL; | |
1024 | } | |
1025 | } else if (ret != -ENOIOCTLCMD) { | |
1026 | return ret; | |
1027 | } else { | |
1028 | common_flags = bus_flags; | |
4f67130a GL |
1029 | } |
1030 | ||
579cea03 GL |
1031 | dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n", |
1032 | cfg.flags, bus_flags, common_flags); | |
1033 | ||
4f67130a | 1034 | /* Make choices, based on platform preferences */ |
579cea03 GL |
1035 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1036 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
4f67130a | 1037 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) |
579cea03 | 1038 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
4f67130a | 1039 | else |
579cea03 | 1040 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
4f67130a GL |
1041 | } |
1042 | ||
579cea03 GL |
1043 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1044 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
4f67130a | 1045 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) |
579cea03 | 1046 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
4f67130a | 1047 | else |
579cea03 | 1048 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
4f67130a GL |
1049 | } |
1050 | ||
579cea03 GL |
1051 | if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) && |
1052 | (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) { | |
4f67130a | 1053 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) |
579cea03 | 1054 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH; |
4f67130a | 1055 | else |
579cea03 | 1056 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW; |
4f67130a GL |
1057 | } |
1058 | ||
579cea03 GL |
1059 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1060 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
4f67130a | 1061 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) |
579cea03 | 1062 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
4f67130a | 1063 | else |
579cea03 | 1064 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
4f67130a GL |
1065 | } |
1066 | ||
579cea03 GL |
1067 | cfg.flags = common_flags; |
1068 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1069 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1070 | dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n", | |
40e2e092 | 1071 | common_flags, ret); |
4f67130a | 1072 | return ret; |
40e2e092 | 1073 | } |
4f67130a GL |
1074 | |
1075 | /* | |
1076 | * So far only gated clock mode is supported. Add a line | |
1077 | * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) | | |
1078 | * below and select the required mode when supporting other | |
1079 | * synchronisation protocols. | |
1080 | */ | |
1081 | sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) & | |
1082 | ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) | | |
1083 | (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) | | |
1084 | (1 << CSI_SENS_CONF_DATA_POL_SHIFT) | | |
1085 | (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) | | |
1086 | (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) | | |
1087 | (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT)); | |
1088 | ||
1089 | /* TODO: Support RGB and YUV formats */ | |
1090 | ||
1091 | /* This has been set in mx3_camera_activate(), but we clear it above */ | |
1092 | sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
1093 | ||
579cea03 | 1094 | if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
4f67130a | 1095 | sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; |
579cea03 | 1096 | if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
4f67130a | 1097 | sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; |
579cea03 | 1098 | if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
4f67130a | 1099 | sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; |
579cea03 | 1100 | if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW) |
4f67130a GL |
1101 | sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; |
1102 | ||
1103 | /* Just do what we're asked to do */ | |
760697be | 1104 | switch (xlate->host_fmt->bits_per_sample) { |
4f67130a GL |
1105 | case 4: |
1106 | dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1107 | break; | |
1108 | case 8: | |
1109 | dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1110 | break; | |
1111 | case 10: | |
1112 | dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1113 | break; | |
1114 | default: | |
1115 | /* | |
1116 | * Actually it can only be 15 now, default is just to silence | |
1117 | * compiler warnings | |
1118 | */ | |
1119 | case 15: | |
1120 | dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1121 | } | |
1122 | ||
1123 | csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); | |
1124 | ||
0166b743 | 1125 | dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw); |
4f67130a GL |
1126 | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static struct soc_camera_host_ops mx3_soc_camera_host_ops = { | |
1131 | .owner = THIS_MODULE, | |
1132 | .add = mx3_camera_add_device, | |
1133 | .remove = mx3_camera_remove_device, | |
09e231b3 | 1134 | .set_crop = mx3_camera_set_crop, |
4f67130a GL |
1135 | .set_fmt = mx3_camera_set_fmt, |
1136 | .try_fmt = mx3_camera_try_fmt, | |
1137 | .get_formats = mx3_camera_get_formats, | |
379fa5d3 | 1138 | .init_videobuf2 = mx3_camera_init_videobuf, |
4f67130a GL |
1139 | .reqbufs = mx3_camera_reqbufs, |
1140 | .poll = mx3_camera_poll, | |
1141 | .querycap = mx3_camera_querycap, | |
1142 | .set_bus_param = mx3_camera_set_bus_param, | |
1143 | }; | |
1144 | ||
e36bc31f | 1145 | static int __devinit mx3_camera_probe(struct platform_device *pdev) |
4f67130a GL |
1146 | { |
1147 | struct mx3_camera_dev *mx3_cam; | |
1148 | struct resource *res; | |
1149 | void __iomem *base; | |
1150 | int err = 0; | |
1151 | struct soc_camera_host *soc_host; | |
1152 | ||
1153 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1154 | if (!res) { | |
1155 | err = -ENODEV; | |
1156 | goto egetres; | |
1157 | } | |
1158 | ||
101b25b5 | 1159 | mx3_cam = vzalloc(sizeof(*mx3_cam)); |
4f67130a GL |
1160 | if (!mx3_cam) { |
1161 | dev_err(&pdev->dev, "Could not allocate mx3 camera object\n"); | |
1162 | err = -ENOMEM; | |
1163 | goto ealloc; | |
1164 | } | |
4f67130a | 1165 | |
b71df97a | 1166 | mx3_cam->clk = clk_get(&pdev->dev, NULL); |
4f67130a GL |
1167 | if (IS_ERR(mx3_cam->clk)) { |
1168 | err = PTR_ERR(mx3_cam->clk); | |
1169 | goto eclkget; | |
1170 | } | |
1171 | ||
4f67130a GL |
1172 | mx3_cam->pdata = pdev->dev.platform_data; |
1173 | mx3_cam->platform_flags = mx3_cam->pdata->flags; | |
1174 | if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 | | |
1175 | MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 | | |
1176 | MX3_CAMERA_DATAWIDTH_15))) { | |
5d28d525 GL |
1177 | /* |
1178 | * Platform hasn't set available data widths. This is bad. | |
1179 | * Warn and use a default. | |
1180 | */ | |
4f67130a GL |
1181 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1182 | "data widths, using default 8 bit\n"); | |
1183 | mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8; | |
1184 | } | |
579cea03 GL |
1185 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4) |
1186 | mx3_cam->width_flags = 1 << 3; | |
1187 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
1188 | mx3_cam->width_flags |= 1 << 7; | |
1189 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
1190 | mx3_cam->width_flags |= 1 << 9; | |
1191 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
1192 | mx3_cam->width_flags |= 1 << 14; | |
4f67130a GL |
1193 | |
1194 | mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000; | |
1195 | if (!mx3_cam->mclk) { | |
1196 | dev_warn(&pdev->dev, | |
1197 | "mclk_10khz == 0! Please, fix your platform data. " | |
1198 | "Using default 20MHz\n"); | |
1199 | mx3_cam->mclk = 20000000; | |
1200 | } | |
1201 | ||
1202 | /* list of video-buffers */ | |
1203 | INIT_LIST_HEAD(&mx3_cam->capture); | |
1204 | spin_lock_init(&mx3_cam->lock); | |
1205 | ||
40e2e092 | 1206 | base = ioremap(res->start, resource_size(res)); |
4f67130a | 1207 | if (!base) { |
40e2e092 | 1208 | pr_err("Couldn't map %x@%x\n", resource_size(res), res->start); |
4f67130a GL |
1209 | err = -ENOMEM; |
1210 | goto eioremap; | |
1211 | } | |
1212 | ||
1213 | mx3_cam->base = base; | |
4f67130a GL |
1214 | |
1215 | soc_host = &mx3_cam->soc_host; | |
1216 | soc_host->drv_name = MX3_CAM_DRV_NAME; | |
1217 | soc_host->ops = &mx3_soc_camera_host_ops; | |
1218 | soc_host->priv = mx3_cam; | |
979ea1dd | 1219 | soc_host->v4l2_dev.dev = &pdev->dev; |
4f67130a | 1220 | soc_host->nr = pdev->id; |
eff505fa | 1221 | |
379fa5d3 GL |
1222 | mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
1223 | if (IS_ERR(mx3_cam->alloc_ctx)) { | |
1224 | err = PTR_ERR(mx3_cam->alloc_ctx); | |
1225 | goto eallocctx; | |
1226 | } | |
1227 | ||
4f67130a GL |
1228 | err = soc_camera_host_register(soc_host); |
1229 | if (err) | |
1230 | goto ecamhostreg; | |
1231 | ||
1232 | /* IDMAC interface */ | |
1233 | dmaengine_get(); | |
1234 | ||
1235 | return 0; | |
1236 | ||
1237 | ecamhostreg: | |
379fa5d3 GL |
1238 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1239 | eallocctx: | |
4f67130a GL |
1240 | iounmap(base); |
1241 | eioremap: | |
1242 | clk_put(mx3_cam->clk); | |
1243 | eclkget: | |
1244 | vfree(mx3_cam); | |
1245 | ealloc: | |
1246 | egetres: | |
1247 | return err; | |
1248 | } | |
1249 | ||
1250 | static int __devexit mx3_camera_remove(struct platform_device *pdev) | |
1251 | { | |
eff505fa GL |
1252 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1253 | struct mx3_camera_dev *mx3_cam = container_of(soc_host, | |
1254 | struct mx3_camera_dev, soc_host); | |
4f67130a GL |
1255 | |
1256 | clk_put(mx3_cam->clk); | |
1257 | ||
eff505fa | 1258 | soc_camera_host_unregister(soc_host); |
4f67130a GL |
1259 | |
1260 | iounmap(mx3_cam->base); | |
1261 | ||
1262 | /* | |
1263 | * The channel has either not been allocated, | |
1264 | * or should have been released | |
1265 | */ | |
1266 | if (WARN_ON(mx3_cam->idmac_channel[0])) | |
1267 | dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan); | |
1268 | ||
379fa5d3 GL |
1269 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1270 | ||
4f67130a GL |
1271 | vfree(mx3_cam); |
1272 | ||
1273 | dmaengine_put(); | |
1274 | ||
4f67130a GL |
1275 | return 0; |
1276 | } | |
1277 | ||
1278 | static struct platform_driver mx3_camera_driver = { | |
1279 | .driver = { | |
1280 | .name = MX3_CAM_DRV_NAME, | |
1281 | }, | |
1282 | .probe = mx3_camera_probe, | |
e36bc31f | 1283 | .remove = __devexit_p(mx3_camera_remove), |
4f67130a GL |
1284 | }; |
1285 | ||
1d6629b1 | 1286 | module_platform_driver(mx3_camera_driver); |
4f67130a GL |
1287 | |
1288 | MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); | |
1289 | MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>"); | |
1290 | MODULE_LICENSE("GPL v2"); | |
64dc3c1a | 1291 | MODULE_VERSION("0.2.3"); |
40e2e092 | 1292 | MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME); |