projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] omap3isp: ccdc: Simplify ccdc_lsc_is_configured()
[deliverable/linux.git] / drivers / media / platform / omap3isp / ispccdc.c
CommitLineData
de1135d4
LP		 1/*
2 * ispccdc.c
3 *
4 * TI OMAP3 ISP - CCDC module
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
de1135d4
LP		 15 */
16
17#include <linux/module.h>
18#include <linux/uaccess.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mm.h>
23#include <linux/sched.h>
e74d83aa 24#include <linux/slab.h>
de1135d4
LP		 25#include <media/v4l2-event.h>
26
27#include "isp.h"
28#include "ispreg.h"
29#include "ispccdc.h"
30
a64909b8
LP		 31#define CCDC_MIN_WIDTH 32
32#define CCDC_MIN_HEIGHT 32
33
de1135d4
LP		 34static struct v4l2_mbus_framefmt *
35__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
36 unsigned int pad, enum v4l2_subdev_format_whence which);
37
38static const unsigned int ccdc_fmts[] = {
39 V4L2_MBUS_FMT_Y8_1X8,
5782f97b
MJ		 40 V4L2_MBUS_FMT_Y10_1X10,
41 V4L2_MBUS_FMT_Y12_1X12,
42 V4L2_MBUS_FMT_SGRBG8_1X8,
43 V4L2_MBUS_FMT_SRGGB8_1X8,
44 V4L2_MBUS_FMT_SBGGR8_1X8,
45 V4L2_MBUS_FMT_SGBRG8_1X8,
de1135d4
LP		 46 V4L2_MBUS_FMT_SGRBG10_1X10,
47 V4L2_MBUS_FMT_SRGGB10_1X10,
48 V4L2_MBUS_FMT_SBGGR10_1X10,
49 V4L2_MBUS_FMT_SGBRG10_1X10,
50 V4L2_MBUS_FMT_SGRBG12_1X12,
51 V4L2_MBUS_FMT_SRGGB12_1X12,
52 V4L2_MBUS_FMT_SBGGR12_1X12,
53 V4L2_MBUS_FMT_SGBRG12_1X12,
c51364ca
LP		 54 V4L2_MBUS_FMT_YUYV8_2X8,
55 V4L2_MBUS_FMT_UYVY8_2X8,
de1135d4
LP		 56};
57
58/*
59 * ccdc_print_status - Print current CCDC Module register values.
60 * @ccdc: Pointer to ISP CCDC device.
61 *
62 * Also prints other debug information stored in the CCDC module.
63 */
64#define CCDC_PRINT_REGISTER(isp, name)\
65 dev_dbg(isp->dev, "###CCDC " #name "=0x%08x\n", \
66 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_##name))
67
68static void ccdc_print_status(struct isp_ccdc_device *ccdc)
69{
70 struct isp_device *isp = to_isp_device(ccdc);
71
72 dev_dbg(isp->dev, "-------------CCDC Register dump-------------\n");
73
74 CCDC_PRINT_REGISTER(isp, PCR);
75 CCDC_PRINT_REGISTER(isp, SYN_MODE);
76 CCDC_PRINT_REGISTER(isp, HD_VD_WID);
77 CCDC_PRINT_REGISTER(isp, PIX_LINES);
78 CCDC_PRINT_REGISTER(isp, HORZ_INFO);
79 CCDC_PRINT_REGISTER(isp, VERT_START);
80 CCDC_PRINT_REGISTER(isp, VERT_LINES);
81 CCDC_PRINT_REGISTER(isp, CULLING);
82 CCDC_PRINT_REGISTER(isp, HSIZE_OFF);
83 CCDC_PRINT_REGISTER(isp, SDOFST);
84 CCDC_PRINT_REGISTER(isp, SDR_ADDR);
85 CCDC_PRINT_REGISTER(isp, CLAMP);
86 CCDC_PRINT_REGISTER(isp, DCSUB);
87 CCDC_PRINT_REGISTER(isp, COLPTN);
88 CCDC_PRINT_REGISTER(isp, BLKCMP);
89 CCDC_PRINT_REGISTER(isp, FPC);
90 CCDC_PRINT_REGISTER(isp, FPC_ADDR);
91 CCDC_PRINT_REGISTER(isp, VDINT);
92 CCDC_PRINT_REGISTER(isp, ALAW);
93 CCDC_PRINT_REGISTER(isp, REC656IF);
94 CCDC_PRINT_REGISTER(isp, CFG);
95 CCDC_PRINT_REGISTER(isp, FMTCFG);
96 CCDC_PRINT_REGISTER(isp, FMT_HORZ);
97 CCDC_PRINT_REGISTER(isp, FMT_VERT);
98 CCDC_PRINT_REGISTER(isp, PRGEVEN0);
99 CCDC_PRINT_REGISTER(isp, PRGEVEN1);
100 CCDC_PRINT_REGISTER(isp, PRGODD0);
101 CCDC_PRINT_REGISTER(isp, PRGODD1);
102 CCDC_PRINT_REGISTER(isp, VP_OUT);
103 CCDC_PRINT_REGISTER(isp, LSC_CONFIG);
104 CCDC_PRINT_REGISTER(isp, LSC_INITIAL);
105 CCDC_PRINT_REGISTER(isp, LSC_TABLE_BASE);
106 CCDC_PRINT_REGISTER(isp, LSC_TABLE_OFFSET);
107
108 dev_dbg(isp->dev, "--------------------------------------------\n");
109}
110
111/*
112 * omap3isp_ccdc_busy - Get busy state of the CCDC.
113 * @ccdc: Pointer to ISP CCDC device.
114 */
115int omap3isp_ccdc_busy(struct isp_ccdc_device *ccdc)
116{
117 struct isp_device *isp = to_isp_device(ccdc);
118
119 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
120 ISPCCDC_PCR_BUSY;
121}
122
123/* -----------------------------------------------------------------------------
124 * Lens Shading Compensation
125 */
126
127/*
128 * ccdc_lsc_validate_config - Check that LSC configuration is valid.
129 * @ccdc: Pointer to ISP CCDC device.
130 * @lsc_cfg: the LSC configuration to check.
131 *
132 * Returns 0 if the LSC configuration is valid, or -EINVAL if invalid.
133 */
134static int ccdc_lsc_validate_config(struct isp_ccdc_device *ccdc,
135 struct omap3isp_ccdc_lsc_config *lsc_cfg)
136{
137 struct isp_device *isp = to_isp_device(ccdc);
138 struct v4l2_mbus_framefmt *format;
139 unsigned int paxel_width, paxel_height;
140 unsigned int paxel_shift_x, paxel_shift_y;
141 unsigned int min_width, min_height, min_size;
142 unsigned int input_width, input_height;
143
144 paxel_shift_x = lsc_cfg->gain_mode_m;
145 paxel_shift_y = lsc_cfg->gain_mode_n;
146
147 if ((paxel_shift_x < 2) || (paxel_shift_x > 6) ||
148 (paxel_shift_y < 2) || (paxel_shift_y > 6)) {
149 dev_dbg(isp->dev, "CCDC: LSC: Invalid paxel size\n");
150 return -EINVAL;
151 }
152
153 if (lsc_cfg->offset & 3) {
154 dev_dbg(isp->dev, "CCDC: LSC: Offset must be a multiple of "
155 "4\n");
156 return -EINVAL;
157 }
158
159 if ((lsc_cfg->initial_x & 1) || (lsc_cfg->initial_y & 1)) {
160 dev_dbg(isp->dev, "CCDC: LSC: initial_x and y must be even\n");
161 return -EINVAL;
162 }
163
164 format = __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
165 V4L2_SUBDEV_FORMAT_ACTIVE);
166 input_width = format->width;
167 input_height = format->height;
168
169 /* Calculate minimum bytesize for validation */
170 paxel_width = 1 << paxel_shift_x;
171 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1)
172 >> paxel_shift_x) + 1;
173
174 paxel_height = 1 << paxel_shift_y;
175 min_height = ((input_height + lsc_cfg->initial_y + paxel_height - 1)
176 >> paxel_shift_y) + 1;
177
178 min_size = 4 * min_width * min_height;
179 if (min_size > lsc_cfg->size) {
180 dev_dbg(isp->dev, "CCDC: LSC: too small table\n");
181 return -EINVAL;
182 }
183 if (lsc_cfg->offset < (min_width * 4)) {
184 dev_dbg(isp->dev, "CCDC: LSC: Offset is too small\n");
185 return -EINVAL;
186 }
187 if ((lsc_cfg->size / lsc_cfg->offset) < min_height) {
188 dev_dbg(isp->dev, "CCDC: LSC: Wrong size/offset combination\n");
189 return -EINVAL;
190 }
191 return 0;
192}
193
194/*
195 * ccdc_lsc_program_table - Program Lens Shading Compensation table address.
196 * @ccdc: Pointer to ISP CCDC device.
197 */
d33186d0
LP		 198static void ccdc_lsc_program_table(struct isp_ccdc_device *ccdc,
199 dma_addr_t addr)
de1135d4
LP		 200{
201 isp_reg_writel(to_isp_device(ccdc), addr,
202 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
203}
204
205/*
206 * ccdc_lsc_setup_regs - Configures the lens shading compensation module
207 * @ccdc: Pointer to ISP CCDC device.
208 */
209static void ccdc_lsc_setup_regs(struct isp_ccdc_device *ccdc,
210 struct omap3isp_ccdc_lsc_config *cfg)
211{
212 struct isp_device *isp = to_isp_device(ccdc);
213 int reg;
214
215 isp_reg_writel(isp, cfg->offset, OMAP3_ISP_IOMEM_CCDC,
216 ISPCCDC_LSC_TABLE_OFFSET);
217
218 reg = 0;
219 reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
220 reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
221 reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
222 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
223
224 reg = 0;
225 reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
226 reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
227 reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
228 reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
229 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC,
230 ISPCCDC_LSC_INITIAL);
231}
232
233static int ccdc_lsc_wait_prefetch(struct isp_ccdc_device *ccdc)
234{
235 struct isp_device *isp = to_isp_device(ccdc);
236 unsigned int wait;
237
238 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
239 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
240
241 /* timeout 1 ms */
242 for (wait = 0; wait < 1000; wait++) {
243 if (isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS) &
244 IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ) {
245 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
246 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
247 return 0;
248 }
249
250 rmb();
251 udelay(1);
252 }
253
254 return -ETIMEDOUT;
255}
256
257/*
258 * __ccdc_lsc_enable - Enables/Disables the Lens Shading Compensation module.
259 * @ccdc: Pointer to ISP CCDC device.
260 * @enable: 0 Disables LSC, 1 Enables LSC.
261 */
262static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable)
263{
264 struct isp_device *isp = to_isp_device(ccdc);
265 const struct v4l2_mbus_framefmt *format =
266 __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
267 V4L2_SUBDEV_FORMAT_ACTIVE);
268
269 if ((format->code != V4L2_MBUS_FMT_SGRBG10_1X10) &&
270 (format->code != V4L2_MBUS_FMT_SRGGB10_1X10) &&
271 (format->code != V4L2_MBUS_FMT_SBGGR10_1X10) &&
272 (format->code != V4L2_MBUS_FMT_SGBRG10_1X10))
273 return -EINVAL;
274
275 if (enable)
276 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_LSC_READ);
277
278 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
279 ISPCCDC_LSC_ENABLE, enable ? ISPCCDC_LSC_ENABLE : 0);
280
281 if (enable) {
282 if (ccdc_lsc_wait_prefetch(ccdc) < 0) {
283 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC,
284 ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE);
285 ccdc->lsc.state = LSC_STATE_STOPPED;
25aeb418 286 dev_warn(to_device(ccdc), "LSC prefetch timeout\n");
de1135d4
LP		 287 return -ETIMEDOUT;
288 }
289 ccdc->lsc.state = LSC_STATE_RUNNING;
290 } else {
291 ccdc->lsc.state = LSC_STATE_STOPPING;
292 }
293
294 return 0;
295}
296
297static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
298{
299 struct isp_device *isp = to_isp_device(ccdc);
300
301 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG) &
302 ISPCCDC_LSC_BUSY;
303}
304
305/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
306 * @ccdc: Pointer to ISP CCDC device
307 * @req: New configuration request
308 *
309 * context: in_interrupt()
310 */
311static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
312 struct ispccdc_lsc_config_req *req)
313{
314 if (!req->enable)
315 return -EINVAL;
316
317 if (ccdc_lsc_validate_config(ccdc, &req->config) < 0) {
318 dev_dbg(to_device(ccdc), "Discard LSC configuration\n");
319 return -EINVAL;
320 }
321
322 if (ccdc_lsc_busy(ccdc))
323 return -EBUSY;
324
325 ccdc_lsc_setup_regs(ccdc, &req->config);
d33186d0 326 ccdc_lsc_program_table(ccdc, req->table.dma);
de1135d4
LP		 327 return 0;
328}
329
330/*
331 * ccdc_lsc_error_handler - Handle LSC prefetch error scenario.
332 * @ccdc: Pointer to ISP CCDC device.
333 *
334 * Disables LSC, and defers enablement to shadow registers update time.
335 */
336static void ccdc_lsc_error_handler(struct isp_ccdc_device *ccdc)
337{
338 struct isp_device *isp = to_isp_device(ccdc);
339 /*
340 * From OMAP3 TRM: When this event is pending, the module
341 * goes into transparent mode (output =input). Normal
342 * operation can be resumed at the start of the next frame
343 * after:
344 * 1) Clearing this event
345 * 2) Disabling the LSC module
346 * 3) Enabling it
347 */
348 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
349 ISPCCDC_LSC_ENABLE);
350 ccdc->lsc.state = LSC_STATE_STOPPED;
351}
352
353static void ccdc_lsc_free_request(struct isp_ccdc_device *ccdc,
354 struct ispccdc_lsc_config_req *req)
355{
356 struct isp_device *isp = to_isp_device(ccdc);
357
358 if (req == NULL)
359 return;
360
d33186d0
LP		 361 if (req->table.addr) {
362 sg_free_table(&req->table.sgt);
363 dma_free_coherent(isp->dev, req->config.size, req->table.addr,
364 req->table.dma);
365 }
366
de1135d4
LP		 367 kfree(req);
368}
369
370static void ccdc_lsc_free_queue(struct isp_ccdc_device *ccdc,
371 struct list_head *queue)
372{
373 struct ispccdc_lsc_config_req *req, *n;
374 unsigned long flags;
375
376 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
377 list_for_each_entry_safe(req, n, queue, list) {
378 list_del(&req->list);
379 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
380 ccdc_lsc_free_request(ccdc, req);
381 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
382 }
383 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
384}
385
386static void ccdc_lsc_free_table_work(struct work_struct *work)
387{
388 struct isp_ccdc_device *ccdc;
389 struct ispccdc_lsc *lsc;
390
391 lsc = container_of(work, struct ispccdc_lsc, table_work);
392 ccdc = container_of(lsc, struct isp_ccdc_device, lsc);
393
394 ccdc_lsc_free_queue(ccdc, &lsc->free_queue);
395}
396
397/*
398 * ccdc_lsc_config - Configure the LSC module from a userspace request
399 *
400 * Store the request LSC configuration in the LSC engine request pointer. The
401 * configuration will be applied to the hardware when the CCDC will be enabled,
402 * or at the next LSC interrupt if the CCDC is already running.
403 */
404static int ccdc_lsc_config(struct isp_ccdc_device *ccdc,
405 struct omap3isp_ccdc_update_config *config)
406{
407 struct isp_device *isp = to_isp_device(ccdc);
408 struct ispccdc_lsc_config_req *req;
409 unsigned long flags;
de1135d4
LP		 410 u16 update;
411 int ret;
412
413 update = config->update &
414 (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC);
415 if (!update)
416 return 0;
417
418 if (update != (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC)) {
419 dev_dbg(to_device(ccdc), "%s: Both LSC configuration and table "
420 "need to be supplied\n", __func__);
421 return -EINVAL;
422 }
423
424 req = kzalloc(sizeof(*req), GFP_KERNEL);
425 if (req == NULL)
426 return -ENOMEM;
427
428 if (config->flag & OMAP3ISP_CCDC_CONFIG_LSC) {
429 if (copy_from_user(&req->config, config->lsc_cfg,
430 sizeof(req->config))) {
431 ret = -EFAULT;
432 goto done;
433 }
434
435 req->enable = 1;
436
d33186d0
LP		 437 req->table.addr = dma_alloc_coherent(isp->dev, req->config.size,
438 &req->table.dma,
439 GFP_KERNEL);
440 if (req->table.addr == NULL) {
de1135d4
LP		 441 ret = -ENOMEM;
442 goto done;
443 }
444
d33186d0
LP		 445 ret = dma_get_sgtable(isp->dev, &req->table.sgt,
446 req->table.addr, req->table.dma,
447 req->config.size);
448 if (ret < 0)
de1135d4 449 goto done;
de1135d4 450
d33186d0
LP		 451 dma_sync_sg_for_cpu(isp->dev, req->table.sgt.sgl,
452 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4 453
d33186d0
LP		 454 if (copy_from_user(req->table.addr, config->lsc,
455 req->config.size)) {
de1135d4
LP		 456 ret = -EFAULT;
457 goto done;
458 }
459
d33186d0
LP		 460 dma_sync_sg_for_device(isp->dev, req->table.sgt.sgl,
461 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4
LP		 462 }
463
464 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
465 if (ccdc->lsc.request) {
466 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
467 schedule_work(&ccdc->lsc.table_work);
468 }
469 ccdc->lsc.request = req;
470 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
471
472 ret = 0;
473
474done:
475 if (ret < 0)
476 ccdc_lsc_free_request(ccdc, req);
477
478 return ret;
479}
480
481static inline int ccdc_lsc_is_configured(struct isp_ccdc_device *ccdc)
482{
483 unsigned long flags;
1c748174 484 int ret;
de1135d4
LP		 485
486 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1c748174 487 ret = ccdc->lsc.active != NULL;
de1135d4 488 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1c748174
LP		 489
490 return ret;
de1135d4
LP		 491}
492
493static int ccdc_lsc_enable(struct isp_ccdc_device *ccdc)
494{
495 struct ispccdc_lsc *lsc = &ccdc->lsc;
496
497 if (lsc->state != LSC_STATE_STOPPED)
498 return -EINVAL;
499
500 if (lsc->active) {
501 list_add_tail(&lsc->active->list, &lsc->free_queue);
502 lsc->active = NULL;
503 }
504
505 if (__ccdc_lsc_configure(ccdc, lsc->request) < 0) {
506 omap3isp_sbl_disable(to_isp_device(ccdc),
507 OMAP3_ISP_SBL_CCDC_LSC_READ);
508 list_add_tail(&lsc->request->list, &lsc->free_queue);
509 lsc->request = NULL;
510 goto done;
511 }
512
513 lsc->active = lsc->request;
514 lsc->request = NULL;
515 __ccdc_lsc_enable(ccdc, 1);
516
517done:
518 if (!list_empty(&lsc->free_queue))
519 schedule_work(&lsc->table_work);
520
521 return 0;
522}
523
524/* -----------------------------------------------------------------------------
525 * Parameters configuration
526 */
527
528/*
529 * ccdc_configure_clamp - Configure optical-black or digital clamping
530 * @ccdc: Pointer to ISP CCDC device.
531 *
532 * The CCDC performs either optical-black or digital clamp. Configure and enable
533 * the selected clamp method.
534 */
535static void ccdc_configure_clamp(struct isp_ccdc_device *ccdc)
536{
537 struct isp_device *isp = to_isp_device(ccdc);
538 u32 clamp;
539
540 if (ccdc->obclamp) {
541 clamp = ccdc->clamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
542 clamp |= ccdc->clamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
543 clamp |= ccdc->clamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
544 clamp |= ccdc->clamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
545 isp_reg_writel(isp, clamp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP);
546 } else {
547 isp_reg_writel(isp, ccdc->clamp.dcsubval,
548 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB);
549 }
550
551 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
552 ISPCCDC_CLAMP_CLAMPEN,
553 ccdc->obclamp ? ISPCCDC_CLAMP_CLAMPEN : 0);
554}
555
556/*
557 * ccdc_configure_fpc - Configure Faulty Pixel Correction
558 * @ccdc: Pointer to ISP CCDC device.
559 */
560static void ccdc_configure_fpc(struct isp_ccdc_device *ccdc)
561{
562 struct isp_device *isp = to_isp_device(ccdc);
563
564 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, ISPCCDC_FPC_FPCEN);
565
566 if (!ccdc->fpc_en)
567 return;
568
c60e153d 569 isp_reg_writel(isp, ccdc->fpc.dma, OMAP3_ISP_IOMEM_CCDC,
de1135d4
LP		 570 ISPCCDC_FPC_ADDR);
571 /* The FPNUM field must be set before enabling FPC. */
572 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
573 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
574 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT) |
575 ISPCCDC_FPC_FPCEN, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
576}
577
578/*
579 * ccdc_configure_black_comp - Configure Black Level Compensation.
580 * @ccdc: Pointer to ISP CCDC device.
581 */
582static void ccdc_configure_black_comp(struct isp_ccdc_device *ccdc)
583{
584 struct isp_device *isp = to_isp_device(ccdc);
585 u32 blcomp;
586
587 blcomp = ccdc->blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
588 blcomp |= ccdc->blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
589 blcomp |= ccdc->blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
590 blcomp |= ccdc->blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
591
592 isp_reg_writel(isp, blcomp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
593}
594
595/*
596 * ccdc_configure_lpf - Configure Low-Pass Filter (LPF).
597 * @ccdc: Pointer to ISP CCDC device.
598 */
599static void ccdc_configure_lpf(struct isp_ccdc_device *ccdc)
600{
601 struct isp_device *isp = to_isp_device(ccdc);
602
603 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
604 ISPCCDC_SYN_MODE_LPF,
605 ccdc->lpf ? ISPCCDC_SYN_MODE_LPF : 0);
606}
607
608/*
609 * ccdc_configure_alaw - Configure A-law compression.
610 * @ccdc: Pointer to ISP CCDC device.
611 */
612static void ccdc_configure_alaw(struct isp_ccdc_device *ccdc)
613{
614 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 615 const struct isp_format_info *info;
de1135d4
LP		 616 u32 alaw = 0;
617
73ea57eb
LP		 618 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
619
620 switch (info->width) {
de1135d4
LP		 621 case 8:
622 return;
623
624 case 10:
625 alaw = ISPCCDC_ALAW_GWDI_9_0;
626 break;
627 case 11:
628 alaw = ISPCCDC_ALAW_GWDI_10_1;
629 break;
630 case 12:
631 alaw = ISPCCDC_ALAW_GWDI_11_2;
632 break;
633 case 13:
634 alaw = ISPCCDC_ALAW_GWDI_12_3;
635 break;
636 }
637
638 if (ccdc->alaw)
639 alaw |= ISPCCDC_ALAW_CCDTBL;
640
641 isp_reg_writel(isp, alaw, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
642}
643
644/*
645 * ccdc_config_imgattr - Configure sensor image specific attributes.
646 * @ccdc: Pointer to ISP CCDC device.
647 * @colptn: Color pattern of the sensor.
648 */
649static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn)
650{
651 struct isp_device *isp = to_isp_device(ccdc);
652
653 isp_reg_writel(isp, colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
654}
655
656/*
657 * ccdc_config - Set CCDC configuration from userspace
658 * @ccdc: Pointer to ISP CCDC device.
872aba51 659 * @ccdc_struct: Structure containing CCDC configuration sent from userspace.
de1135d4
LP		 660 *
661 * Returns 0 if successful, -EINVAL if the pointer to the configuration
662 * structure is null, or the copy_from_user function fails to copy user space
663 * memory to kernel space memory.
664 */
665static int ccdc_config(struct isp_ccdc_device *ccdc,
666 struct omap3isp_ccdc_update_config *ccdc_struct)
667{
668 struct isp_device *isp = to_isp_device(ccdc);
669 unsigned long flags;
670
671 spin_lock_irqsave(&ccdc->lock, flags);
672 ccdc->shadow_update = 1;
673 spin_unlock_irqrestore(&ccdc->lock, flags);
674
675 if (OMAP3ISP_CCDC_ALAW & ccdc_struct->update) {
676 ccdc->alaw = !!(OMAP3ISP_CCDC_ALAW & ccdc_struct->flag);
677 ccdc->update |= OMAP3ISP_CCDC_ALAW;
678 }
679
680 if (OMAP3ISP_CCDC_LPF & ccdc_struct->update) {
681 ccdc->lpf = !!(OMAP3ISP_CCDC_LPF & ccdc_struct->flag);
682 ccdc->update |= OMAP3ISP_CCDC_LPF;
683 }
684
685 if (OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->update) {
686 if (copy_from_user(&ccdc->clamp, ccdc_struct->bclamp,
687 sizeof(ccdc->clamp))) {
688 ccdc->shadow_update = 0;
689 return -EFAULT;
690 }
691
692 ccdc->obclamp = !!(OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->flag);
693 ccdc->update |= OMAP3ISP_CCDC_BLCLAMP;
694 }
695
696 if (OMAP3ISP_CCDC_BCOMP & ccdc_struct->update) {
697 if (copy_from_user(&ccdc->blcomp, ccdc_struct->blcomp,
698 sizeof(ccdc->blcomp))) {
699 ccdc->shadow_update = 0;
700 return -EFAULT;
701 }
702
703 ccdc->update |= OMAP3ISP_CCDC_BCOMP;
704 }
705
706 ccdc->shadow_update = 0;
707
708 if (OMAP3ISP_CCDC_FPC & ccdc_struct->update) {
c60e153d
LP		 709 struct omap3isp_ccdc_fpc fpc;
710 struct ispccdc_fpc fpc_old = { .addr = NULL, };
711 struct ispccdc_fpc fpc_new;
de1135d4
LP		 712 u32 size;
713
714 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
715 return -EBUSY;
716
717 ccdc->fpc_en = !!(OMAP3ISP_CCDC_FPC & ccdc_struct->flag);
718
719 if (ccdc->fpc_en) {
c60e153d 720 if (copy_from_user(&fpc, ccdc_struct->fpc, sizeof(fpc)))
de1135d4
LP		 721 return -EFAULT;
722
c60e153d
LP		 723 size = fpc.fpnum * 4;
724
de1135d4 725 /*
c60e153d
LP		 726 * The table address must be 64-bytes aligned, which is
727 * guaranteed by dma_alloc_coherent().
de1135d4 728 */
c60e153d
LP		 729 fpc_new.fpnum = fpc.fpnum;
730 fpc_new.addr = dma_alloc_coherent(isp->dev, size,
731 &fpc_new.dma,
732 GFP_KERNEL);
733 if (fpc_new.addr == NULL)
de1135d4
LP		 734 return -ENOMEM;
735
c60e153d
LP		 736 if (copy_from_user(fpc_new.addr,
737 (__force void __user *)fpc.fpcaddr,
738 size)) {
739 dma_free_coherent(isp->dev, size, fpc_new.addr,
740 fpc_new.dma);
de1135d4
LP		 741 return -EFAULT;
742 }
743
c60e153d
LP		 744 fpc_old = ccdc->fpc;
745 ccdc->fpc = fpc_new;
de1135d4
LP		 746 }
747
748 ccdc_configure_fpc(ccdc);
c60e153d
LP		 749
750 if (fpc_old.addr != NULL)
751 dma_free_coherent(isp->dev, fpc_old.fpnum * 4,
752 fpc_old.addr, fpc_old.dma);
de1135d4
LP		 753 }
754
755 return ccdc_lsc_config(ccdc, ccdc_struct);
756}
757
758static void ccdc_apply_controls(struct isp_ccdc_device *ccdc)
759{
760 if (ccdc->update & OMAP3ISP_CCDC_ALAW) {
761 ccdc_configure_alaw(ccdc);
762 ccdc->update &= ~OMAP3ISP_CCDC_ALAW;
763 }
764
765 if (ccdc->update & OMAP3ISP_CCDC_LPF) {
766 ccdc_configure_lpf(ccdc);
767 ccdc->update &= ~OMAP3ISP_CCDC_LPF;
768 }
769
770 if (ccdc->update & OMAP3ISP_CCDC_BLCLAMP) {
771 ccdc_configure_clamp(ccdc);
772 ccdc->update &= ~OMAP3ISP_CCDC_BLCLAMP;
773 }
774
775 if (ccdc->update & OMAP3ISP_CCDC_BCOMP) {
776 ccdc_configure_black_comp(ccdc);
777 ccdc->update &= ~OMAP3ISP_CCDC_BCOMP;
778 }
779}
780
781/*
782 * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers
872aba51 783 * @isp: Pointer to ISP device
de1135d4
LP		 784 */
785void omap3isp_ccdc_restore_context(struct isp_device *isp)
786{
787 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
788
789 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
790
791 ccdc->update = OMAP3ISP_CCDC_ALAW | OMAP3ISP_CCDC_LPF
792 | OMAP3ISP_CCDC_BLCLAMP | OMAP3ISP_CCDC_BCOMP;
793 ccdc_apply_controls(ccdc);
794 ccdc_configure_fpc(ccdc);
795}
796
797/* -----------------------------------------------------------------------------
798 * Format- and pipeline-related configuration helpers
799 */
800
801/*
802 * ccdc_config_vp - Configure the Video Port.
803 * @ccdc: Pointer to ISP CCDC device.
804 */
805static void ccdc_config_vp(struct isp_ccdc_device *ccdc)
806{
807 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
808 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 809 const struct isp_format_info *info;
aec2de0e 810 struct v4l2_mbus_framefmt *format;
de1135d4
LP		 811 unsigned long l3_ick = pipe->l3_ick;
812 unsigned int max_div = isp->revision == ISP_REVISION_15_0 ? 64 : 8;
813 unsigned int div = 0;
aec2de0e
LP		 814 u32 fmtcfg = ISPCCDC_FMTCFG_VPEN;
815
816 format = &ccdc->formats[CCDC_PAD_SOURCE_VP];
817
818 if (!format->code) {
819 /* Disable the video port when the input format isn't supported.
820 * This is indicated by a pixel code set to 0.
821 */
822 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
823 return;
824 }
825
826 isp_reg_writel(isp, (0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
827 (format->width << ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
828 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ);
829 isp_reg_writel(isp, (0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
830 ((format->height + 1) << ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
831 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT);
de1135d4 832
aec2de0e
LP		 833 isp_reg_writel(isp, (format->width << ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
834 (format->height << ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
835 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
de1135d4 836
73ea57eb
LP		 837 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
838
839 switch (info->width) {
de1135d4
LP		 840 case 8:
841 case 10:
aec2de0e 842 fmtcfg |= ISPCCDC_FMTCFG_VPIN_9_0;
de1135d4
LP		 843 break;
844 case 11:
aec2de0e 845 fmtcfg |= ISPCCDC_FMTCFG_VPIN_10_1;
de1135d4
LP		 846 break;
847 case 12:
aec2de0e 848 fmtcfg |= ISPCCDC_FMTCFG_VPIN_11_2;
de1135d4
LP		 849 break;
850 case 13:
aec2de0e 851 fmtcfg |= ISPCCDC_FMTCFG_VPIN_12_3;
de1135d4 852 break;
13eaaa7f 853 }
de1135d4
LP		 854
855 if (pipe->input)
856 div = DIV_ROUND_UP(l3_ick, pipe->max_rate);
c6c01f97
SA		 857 else if (pipe->external_rate)
858 div = l3_ick / pipe->external_rate;
de1135d4
LP		 859
860 div = clamp(div, 2U, max_div);
aec2de0e 861 fmtcfg |= (div - 2) << ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT;
de1135d4 862
aec2de0e 863 isp_reg_writel(isp, fmtcfg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
de1135d4
LP		 864}
865
866/*
867 * ccdc_config_outlineoffset - Configure memory saving output line offset
868 * @ccdc: Pointer to ISP CCDC device.
bcb4e0ef
LP		 869 * @bpl: Number of bytes per line when stored in memory.
870 * @field: Field order when storing interlaced formats in memory.
de1135d4 871 *
bcb4e0ef
LP		 872 * Configure the offsets for the line output control:
873 *
874 * - The horizontal line offset is defined as the number of bytes between the
875 * start of two consecutive lines in memory. Set it to the given bytes per
876 * line value.
877 *
878 * - The field offset value is defined as the number of lines to offset the
879 * start of the field identified by FID = 1. Set it to one.
880 *
881 * - The line offset values are defined as the number of lines (as defined by
882 * the horizontal line offset) between the start of two consecutive lines for
883 * all combinations of odd/even lines in odd/even fields. When interleaving
884 * fields set them all to two lines, and to one line otherwise.
de1135d4
LP		 885 */
886static void ccdc_config_outlineoffset(struct isp_ccdc_device *ccdc,
bcb4e0ef
LP		 887 unsigned int bpl,
888 enum v4l2_field field)
de1135d4
LP		 889{
890 struct isp_device *isp = to_isp_device(ccdc);
bcb4e0ef 891 u32 sdofst = 0;
de1135d4 892
bcb4e0ef
LP		 893 isp_reg_writel(isp, bpl & 0xffff, OMAP3_ISP_IOMEM_CCDC,
894 ISPCCDC_HSIZE_OFF);
de1135d4 895
bcb4e0ef
LP		 896 switch (field) {
897 case V4L2_FIELD_INTERLACED_TB:
898 case V4L2_FIELD_INTERLACED_BT:
899 /* When interleaving fields in memory offset field one by one
900 * line and set the line offset to two lines.
901 */
902 sdofst |= (1 << ISPCCDC_SDOFST_LOFST0_SHIFT)
903 | (1 << ISPCCDC_SDOFST_LOFST1_SHIFT)
904 | (1 << ISPCCDC_SDOFST_LOFST2_SHIFT)
905 | (1 << ISPCCDC_SDOFST_LOFST3_SHIFT);
de1135d4 906 break;
bcb4e0ef 907
de1135d4 908 default:
bcb4e0ef 909 /* In all other cases set the line offsets to one line. */
de1135d4
LP		 910 break;
911 }
bcb4e0ef
LP		 912
913 isp_reg_writel(isp, sdofst, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST);
de1135d4
LP		 914}
915
916/*
917 * ccdc_set_outaddr - Set memory address to save output image
918 * @ccdc: Pointer to ISP CCDC device.
919 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
920 *
921 * Sets the memory address where the output will be saved.
922 */
923static void ccdc_set_outaddr(struct isp_ccdc_device *ccdc, u32 addr)
924{
925 struct isp_device *isp = to_isp_device(ccdc);
926
927 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
928}
929
930/*
931 * omap3isp_ccdc_max_rate - Calculate maximum input data rate based on the input
932 * @ccdc: Pointer to ISP CCDC device.
933 * @max_rate: Maximum calculated data rate.
934 *
935 * Returns in *max_rate less value between calculated and passed
936 */
937void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
938 unsigned int *max_rate)
939{
940 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
941 unsigned int rate;
942
943 if (pipe == NULL)
944 return;
945
946 /*
947 * TRM says that for parallel sensors the maximum data rate
948 * should be 90% form L3/2 clock, otherwise just L3/2.
949 */
950 if (ccdc->input == CCDC_INPUT_PARALLEL)
951 rate = pipe->l3_ick / 2 * 9 / 10;
952 else
953 rate = pipe->l3_ick / 2;
954
955 *max_rate = min(*max_rate, rate);
956}
957
958/*
959 * ccdc_config_sync_if - Set CCDC sync interface configuration
960 * @ccdc: Pointer to ISP CCDC device.
73ea57eb
LP		 961 * @pdata: Parallel interface platform data (may be NULL)
962 * @data_size: Data size
de1135d4
LP		 963 */
964static void ccdc_config_sync_if(struct isp_ccdc_device *ccdc,
73ea57eb
LP		 965 struct isp_parallel_platform_data *pdata,
966 unsigned int data_size)
de1135d4
LP		 967{
968 struct isp_device *isp = to_isp_device(ccdc);
c51364ca 969 const struct v4l2_mbus_framefmt *format;
cf7a3d91 970 u32 syn_mode = ISPCCDC_SYN_MODE_VDHDEN;
de1135d4 971
c51364ca
LP		 972 format = &ccdc->formats[CCDC_PAD_SINK];
973
974 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
975 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
9de7af4d
LP		 976 /* According to the OMAP3 TRM the input mode only affects SYNC
977 * mode, enabling BT.656 mode should take precedence. However,
978 * in practice setting the input mode to YCbCr data on 8 bits
979 * seems to be required in BT.656 mode. In SYNC mode set it to
980 * YCbCr on 16 bits as the bridge is enabled in that case.
c51364ca 981 */
9de7af4d
LP		 982 if (ccdc->bt656)
983 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
984 else
985 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
c51364ca
LP		 986 }
987
73ea57eb 988 switch (data_size) {
de1135d4
LP		 989 case 8:
990 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
991 break;
992 case 10:
993 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
994 break;
995 case 11:
996 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
997 break;
998 case 12:
999 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
1000 break;
13eaaa7f 1001 }
de1135d4 1002
73ea57eb 1003 if (pdata && pdata->data_pol)
de1135d4 1004 syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
de1135d4 1005
73ea57eb 1006 if (pdata && pdata->hs_pol)
de1135d4 1007 syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
de1135d4 1008
9de7af4d
LP		 1009 /* The polarity of the vertical sync signal output by the BT.656
1010 * decoder is not documented and seems to be active low.
1011 */
1012 if ((pdata && pdata->vs_pol) || ccdc->bt656)
de1135d4 1013 syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
de1135d4 1014
9a36d8ed
LP		 1015 if (pdata && pdata->fld_pol)
1016 syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
1017
de1135d4 1018 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
c51364ca
LP		 1019
1020 /* The CCDC_CFG.Y8POS bit is used in YCbCr8 input mode only. The
1021 * hardware seems to ignore it in all other input modes.
1022 */
1023 if (format->code == V4L2_MBUS_FMT_UYVY8_2X8)
1024 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1025 ISPCCDC_CFG_Y8POS);
1026 else
1027 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1028 ISPCCDC_CFG_Y8POS);
1029
9de7af4d
LP		 1030 /* Enable or disable BT.656 mode, including error correction for the
1031 * synchronization codes.
1032 */
1033 if (ccdc->bt656)
1034 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1035 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1036 else
1037 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1038 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1039
de1135d4
LP		 1040}
1041
1042/* CCDC formats descriptions */
1043static const u32 ccdc_sgrbg_pattern =
1044 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1045 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1046 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1047 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1048 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1049 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1050 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1051 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1052 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1053 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1054 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1055 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1056 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1057 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1058 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1059 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1060
1061static const u32 ccdc_srggb_pattern =
1062 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1063 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1064 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1065 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1066 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1067 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1068 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1069 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1070 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1071 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1072 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1073 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1074 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1075 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1076 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1077 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1078
1079static const u32 ccdc_sbggr_pattern =
1080 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1081 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1082 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1083 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1084 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1085 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1086 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1087 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1088 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1089 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1090 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1091 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1092 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1093 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1094 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1095 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1096
1097static const u32 ccdc_sgbrg_pattern =
1098 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1099 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1100 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1101 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1102 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1103 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1104 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1105 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1106 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1107 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1108 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1109 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1110 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1111 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1112 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1113 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1114
1115static void ccdc_configure(struct isp_ccdc_device *ccdc)
1116{
1117 struct isp_device *isp = to_isp_device(ccdc);
1118 struct isp_parallel_platform_data *pdata = NULL;
1119 struct v4l2_subdev *sensor;
1120 struct v4l2_mbus_framefmt *format;
a64909b8 1121 const struct v4l2_rect *crop;
c09af044
MJ		 1122 const struct isp_format_info *fmt_info;
1123 struct v4l2_subdev_format fmt_src;
1124 unsigned int depth_out;
1125 unsigned int depth_in = 0;
de1135d4
LP		 1126 struct media_pad *pad;
1127 unsigned long flags;
c51364ca 1128 unsigned int bridge;
c09af044 1129 unsigned int shift;
9de7af4d
LP		 1130 unsigned int nph;
1131 unsigned int sph;
de1135d4
LP		 1132 u32 syn_mode;
1133 u32 ccdc_pattern;
1134
9de7af4d 1135 ccdc->bt656 = false;
93d7badf 1136 ccdc->fields = 0;
9de7af4d 1137
1bddf1b3 1138 pad = media_entity_remote_pad(&ccdc->pads[CCDC_PAD_SINK]);
c09af044 1139 sensor = media_entity_to_v4l2_subdev(pad->entity);
9de7af4d
LP		 1140 if (ccdc->input == CCDC_INPUT_PARALLEL) {
1141 struct v4l2_mbus_config cfg;
1142 int ret;
1143
1144 ret = v4l2_subdev_call(sensor, video, g_mbus_config, &cfg);
1145 if (!ret)
1146 ccdc->bt656 = cfg.type == V4L2_MBUS_BT656;
1147
de1135d4
LP		 1148 pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
1149 ->bus.parallel;
9de7af4d 1150 }
c09af044 1151
2e8f0172
LP		 1152 /* CCDC_PAD_SINK */
1153 format = &ccdc->formats[CCDC_PAD_SINK];
1154
c51364ca 1155 /* Compute the lane shifter shift value and enable the bridge when the
9de7af4d 1156 * input format is a non-BT.656 YUV variant.
c51364ca 1157 */
c09af044
MJ		 1158 fmt_src.pad = pad->index;
1159 fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1160 if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
1161 fmt_info = omap3isp_video_format_info(fmt_src.format.code);
1697e49a 1162 depth_in = fmt_info->width;
de1135d4
LP		 1163 }
1164
2e8f0172 1165 fmt_info = omap3isp_video_format_info(format->code);
1697e49a 1166 depth_out = fmt_info->width;
c09af044 1167 shift = depth_in - depth_out;
de1135d4 1168
9de7af4d
LP		 1169 if (ccdc->bt656)
1170 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
1171 else if (fmt_info->code == V4L2_MBUS_FMT_YUYV8_2X8)
c51364ca
LP		 1172 bridge = ISPCTRL_PAR_BRIDGE_LENDIAN;
1173 else if (fmt_info->code == V4L2_MBUS_FMT_UYVY8_2X8)
1174 bridge = ISPCTRL_PAR_BRIDGE_BENDIAN;
1175 else
1176 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
de1135d4 1177
c51364ca
LP		 1178 omap3isp_configure_bridge(isp, ccdc->input, pdata, shift, bridge);
1179
9a36d8ed 1180 /* Configure the sync interface. */
c51364ca 1181 ccdc_config_sync_if(ccdc, pdata, depth_out);
de1135d4
LP		 1182
1183 syn_mode = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1184
1185 /* Use the raw, unprocessed data when writing to memory. The H3A and
1186 * histogram modules are still fed with lens shading corrected data.
1187 */
1188 syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
1189
1190 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1191 syn_mode |= ISPCCDC_SYN_MODE_WEN;
1192 else
1193 syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
1194
1195 if (ccdc->output & CCDC_OUTPUT_RESIZER)
1196 syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
1197 else
1198 syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
1199
de1135d4
LP		 1200 /* Mosaic filter */
1201 switch (format->code) {
1202 case V4L2_MBUS_FMT_SRGGB10_1X10:
1203 case V4L2_MBUS_FMT_SRGGB12_1X12:
1204 ccdc_pattern = ccdc_srggb_pattern;
1205 break;
1206 case V4L2_MBUS_FMT_SBGGR10_1X10:
1207 case V4L2_MBUS_FMT_SBGGR12_1X12:
1208 ccdc_pattern = ccdc_sbggr_pattern;
1209 break;
1210 case V4L2_MBUS_FMT_SGBRG10_1X10:
1211 case V4L2_MBUS_FMT_SGBRG12_1X12:
1212 ccdc_pattern = ccdc_sgbrg_pattern;
1213 break;
1214 default:
1215 /* Use GRBG */
1216 ccdc_pattern = ccdc_sgrbg_pattern;
1217 break;
1218 }
1219 ccdc_config_imgattr(ccdc, ccdc_pattern);
1220
1221 /* Generate VD0 on the last line of the image and VD1 on the
1222 * 2/3 height line.
1223 */
1224 isp_reg_writel(isp, ((format->height - 2) << ISPCCDC_VDINT_0_SHIFT) |
1225 ((format->height * 2 / 3) << ISPCCDC_VDINT_1_SHIFT),
1226 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT);
1227
1228 /* CCDC_PAD_SOURCE_OF */
c51364ca 1229 format = &ccdc->formats[CCDC_PAD_SOURCE_OF];
a64909b8 1230 crop = &ccdc->crop;
de1135d4 1231
9de7af4d
LP		 1232 /* The horizontal coordinates are expressed in pixel clock cycles. We
1233 * need two cycles per pixel in BT.656 mode, and one cycle per pixel in
1234 * SYNC mode regardless of the format as the bridge is enabled for YUV
1235 * formats in that case.
1236 */
1237 if (ccdc->bt656) {
1238 sph = crop->left * 2;
1239 nph = crop->width * 2 - 1;
1240 } else {
1241 sph = crop->left;
1242 nph = crop->width - 1;
1243 }
1244
1245 isp_reg_writel(isp, (sph << ISPCCDC_HORZ_INFO_SPH_SHIFT) |
1246 (nph << ISPCCDC_HORZ_INFO_NPH_SHIFT),
de1135d4 1247 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO);
9de7af4d
LP		 1248 isp_reg_writel(isp, (crop->top << ISPCCDC_VERT_START_SLV0_SHIFT) |
1249 (crop->top << ISPCCDC_VERT_START_SLV1_SHIFT),
de1135d4 1250 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START);
a64909b8 1251 isp_reg_writel(isp, (crop->height - 1)
de1135d4
LP		 1252 << ISPCCDC_VERT_LINES_NLV_SHIFT,
1253 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES);
1254
bcb4e0ef
LP		 1255 ccdc_config_outlineoffset(ccdc, ccdc->video_out.bpl_value,
1256 format->field);
1257
1258 /* When interleaving fields enable processing of the field input signal.
1259 * This will cause the line output control module to apply the field
1260 * offset to field 1.
1261 */
1262 if (ccdc->formats[CCDC_PAD_SINK].field == V4L2_FIELD_ALTERNATE &&
1263 (format->field == V4L2_FIELD_INTERLACED_TB ||
1264 format->field == V4L2_FIELD_INTERLACED_BT))
1265 syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
de1135d4 1266
c51364ca
LP		 1267 /* The CCDC outputs data in UYVY order by default. Swap bytes to get
1268 * YUYV.
1269 */
1270 if (format->code == V4L2_MBUS_FMT_YUYV8_1X16)
1271 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1272 ISPCCDC_CFG_BSWD);
1273 else
1274 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1275 ISPCCDC_CFG_BSWD);
1276
9de7af4d
LP		 1277 /* Use PACK8 mode for 1byte per pixel formats. Check for BT.656 mode
1278 * explicitly as the driver reports 1X16 instead of 2X8 at the OF pad
1279 * for simplicity.
1280 */
1281 if (omap3isp_video_format_info(format->code)->width <= 8 || ccdc->bt656)
c51364ca
LP		 1282 syn_mode |= ISPCCDC_SYN_MODE_PACK8;
1283 else
1284 syn_mode &= ~ISPCCDC_SYN_MODE_PACK8;
1285
1286 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1287
de1135d4 1288 /* CCDC_PAD_SOURCE_VP */
aec2de0e 1289 ccdc_config_vp(ccdc);
de1135d4 1290
c51364ca 1291 /* Lens shading correction. */
de1135d4
LP		 1292 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1293 if (ccdc->lsc.request == NULL)
1294 goto unlock;
1295
1296 WARN_ON(ccdc->lsc.active);
1297
1298 /* Get last good LSC configuration. If it is not supported for
1299 * the current active resolution discard it.
1300 */
1301 if (ccdc->lsc.active == NULL &&
1302 __ccdc_lsc_configure(ccdc, ccdc->lsc.request) == 0) {
1303 ccdc->lsc.active = ccdc->lsc.request;
1304 } else {
1305 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
1306 schedule_work(&ccdc->lsc.table_work);
1307 }
1308
1309 ccdc->lsc.request = NULL;
1310
1311unlock:
1312 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1313
1314 ccdc_apply_controls(ccdc);
1315}
1316
1317static void __ccdc_enable(struct isp_ccdc_device *ccdc, int enable)
1318{
1319 struct isp_device *isp = to_isp_device(ccdc);
1320
1321 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR,
1322 ISPCCDC_PCR_EN, enable ? ISPCCDC_PCR_EN : 0);
1323}
1324
1325static int ccdc_disable(struct isp_ccdc_device *ccdc)
1326{
1327 unsigned long flags;
1328 int ret = 0;
1329
1330 spin_lock_irqsave(&ccdc->lock, flags);
1331 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1332 ccdc->stopping = CCDC_STOP_REQUEST;
1333 spin_unlock_irqrestore(&ccdc->lock, flags);
1334
1335 ret = wait_event_timeout(ccdc->wait,
1336 ccdc->stopping == CCDC_STOP_FINISHED,
1337 msecs_to_jiffies(2000));
1338 if (ret == 0) {
1339 ret = -ETIMEDOUT;
1340 dev_warn(to_device(ccdc), "CCDC stop timeout!\n");
1341 }
1342
1343 omap3isp_sbl_disable(to_isp_device(ccdc), OMAP3_ISP_SBL_CCDC_LSC_READ);
1344
1345 mutex_lock(&ccdc->ioctl_lock);
1346 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
1347 ccdc->lsc.request = ccdc->lsc.active;
1348 ccdc->lsc.active = NULL;
1349 cancel_work_sync(&ccdc->lsc.table_work);
1350 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
1351 mutex_unlock(&ccdc->ioctl_lock);
1352
1353 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
1354
1355 return ret > 0 ? 0 : ret;
1356}
1357
1358static void ccdc_enable(struct isp_ccdc_device *ccdc)
1359{
1360 if (ccdc_lsc_is_configured(ccdc))
1361 __ccdc_lsc_enable(ccdc, 1);
1362 __ccdc_enable(ccdc, 1);
1363}
1364
1365/* -----------------------------------------------------------------------------
1366 * Interrupt handling
1367 */
1368
1369/*
1370 * ccdc_sbl_busy - Poll idle state of CCDC and related SBL memory write bits
1371 * @ccdc: Pointer to ISP CCDC device.
1372 *
1373 * Returns zero if the CCDC is idle and the image has been written to
1374 * memory, too.
1375 */
1376static int ccdc_sbl_busy(struct isp_ccdc_device *ccdc)
1377{
1378 struct isp_device *isp = to_isp_device(ccdc);
1379
1380 return omap3isp_ccdc_busy(ccdc)
1381 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
1382 ISPSBL_CCDC_WR_0_DATA_READY)
1383 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
1384 ISPSBL_CCDC_WR_0_DATA_READY)
1385 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
1386 ISPSBL_CCDC_WR_0_DATA_READY)
1387 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
1388 ISPSBL_CCDC_WR_0_DATA_READY);
1389}
1390
1391/*
1392 * ccdc_sbl_wait_idle - Wait until the CCDC and related SBL are idle
1393 * @ccdc: Pointer to ISP CCDC device.
1394 * @max_wait: Max retry count in us for wait for idle/busy transition.
1395 */
1396static int ccdc_sbl_wait_idle(struct isp_ccdc_device *ccdc,
1397 unsigned int max_wait)
1398{
1399 unsigned int wait = 0;
1400
1401 if (max_wait == 0)
1402 max_wait = 10000; /* 10 ms */
1403
1404 for (wait = 0; wait <= max_wait; wait++) {
1405 if (!ccdc_sbl_busy(ccdc))
1406 return 0;
1407
1408 rmb();
1409 udelay(1);
1410 }
1411
1412 return -EBUSY;
1413}
1414
8815392a 1415/* ccdc_handle_stopping - Handle CCDC and/or LSC stopping sequence
de1135d4
LP		 1416 * @ccdc: Pointer to ISP CCDC device.
1417 * @event: Pointing which event trigger handler
1418 *
2d4e9d1d 1419 * Return 1 when the event and stopping request combination is satisfied,
de1135d4
LP		 1420 * zero otherwise.
1421 */
8815392a 1422static int ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
de1135d4
LP		 1423{
1424 int rval = 0;
1425
1426 switch ((ccdc->stopping & 3) | event) {
1427 case CCDC_STOP_REQUEST | CCDC_EVENT_VD1:
1428 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1429 __ccdc_lsc_enable(ccdc, 0);
1430 __ccdc_enable(ccdc, 0);
1431 ccdc->stopping = CCDC_STOP_EXECUTED;
1432 return 1;
1433
1434 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD0:
1435 ccdc->stopping |= CCDC_STOP_CCDC_FINISHED;
1436 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1437 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1438 rval = 1;
1439 break;
1440
1441 case CCDC_STOP_EXECUTED | CCDC_EVENT_LSC_DONE:
1442 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1443 rval = 1;
1444 break;
1445
1446 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD1:
1447 return 1;
1448 }
1449
1450 if (ccdc->stopping == CCDC_STOP_FINISHED) {
1451 wake_up(&ccdc->wait);
1452 rval = 1;
1453 }
1454
1455 return rval;
1456}
1457
1458static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
1459{
bd0f2e6d 1460 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
63ae37ea 1461 struct video_device *vdev = ccdc->subdev.devnode;
de1135d4
LP		 1462 struct v4l2_event event;
1463
b43883d6
LP		 1464 /* Frame number propagation */
1465 atomic_inc(&pipe->frame_number);
1466
de1135d4 1467 memset(&event, 0, sizeof(event));
69d232ae
SA		 1468 event.type = V4L2_EVENT_FRAME_SYNC;
1469 event.u.frame_sync.frame_sequence = atomic_read(&pipe->frame_number);
de1135d4
LP		 1470
1471 v4l2_event_queue(vdev, &event);
1472}
1473
1474/*
1475 * ccdc_lsc_isr - Handle LSC events
1476 * @ccdc: Pointer to ISP CCDC device.
1477 * @events: LSC events
1478 */
1479static void ccdc_lsc_isr(struct isp_ccdc_device *ccdc, u32 events)
1480{
1481 unsigned long flags;
1482
1483 if (events & IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ) {
875e2e3e
LP		 1484 struct isp_pipeline *pipe =
1485 to_isp_pipeline(&ccdc->subdev.entity);
1486
de1135d4 1487 ccdc_lsc_error_handler(ccdc);
875e2e3e 1488 pipe->error = true;
de1135d4
LP		 1489 dev_dbg(to_device(ccdc), "lsc prefetch error\n");
1490 }
1491
1492 if (!(events & IRQ0STATUS_CCDC_LSC_DONE_IRQ))
1493 return;
1494
1495 /* LSC_DONE interrupt occur, there are two cases
1496 * 1. stopping for reconfiguration
1497 * 2. stopping because of STREAM OFF command
1498 */
1499 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1500
1501 if (ccdc->lsc.state == LSC_STATE_STOPPING)
1502 ccdc->lsc.state = LSC_STATE_STOPPED;
1503
8815392a 1504 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_LSC_DONE))
de1135d4
LP		 1505 goto done;
1506
1507 if (ccdc->lsc.state != LSC_STATE_RECONFIG)
1508 goto done;
1509
1510 /* LSC is in STOPPING state, change to the new state */
1511 ccdc->lsc.state = LSC_STATE_STOPPED;
1512
1513 /* This is an exception. Start of frame and LSC_DONE interrupt
1514 * have been received on the same time. Skip this event and wait
1515 * for better times.
1516 */
1517 if (events & IRQ0STATUS_HS_VS_IRQ)
1518 goto done;
1519
1520 /* The LSC engine is stopped at this point. Enable it if there's a
1521 * pending request.
1522 */
1523 if (ccdc->lsc.request == NULL)
1524 goto done;
1525
1526 ccdc_lsc_enable(ccdc);
1527
1528done:
1529 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1530}
1531
93d7badf
LP		 1532/*
1533 * Check whether the CCDC has captured all fields necessary to complete the
1534 * buffer.
1535 */
1536static bool ccdc_has_all_fields(struct isp_ccdc_device *ccdc)
1537{
1538 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1539 struct isp_device *isp = to_isp_device(ccdc);
1540 enum v4l2_field of_field = ccdc->formats[CCDC_PAD_SOURCE_OF].field;
1541 enum v4l2_field field;
1542
1543 /* When the input is progressive fields don't matter. */
1544 if (of_field == V4L2_FIELD_NONE)
1545 return true;
1546
1547 /* Read the current field identifier. */
1548 field = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE)
1549 & ISPCCDC_SYN_MODE_FLDSTAT
1550 ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
1551
1552 /* When capturing fields in alternate order just store the current field
1553 * identifier in the pipeline.
1554 */
1555 if (of_field == V4L2_FIELD_ALTERNATE) {
1556 pipe->field = field;
1557 return true;
1558 }
1559
1560 /* The format is interlaced. Make sure we've captured both fields. */
1561 ccdc->fields |= field == V4L2_FIELD_BOTTOM
1562 ? CCDC_FIELD_BOTTOM : CCDC_FIELD_TOP;
1563
1564 if (ccdc->fields != CCDC_FIELD_BOTH)
1565 return false;
1566
1567 /* Verify that the field just captured corresponds to the last field
1568 * needed based on the desired field order.
1569 */
1570 if ((of_field == V4L2_FIELD_INTERLACED_TB && field == V4L2_FIELD_TOP) ||
1571 (of_field == V4L2_FIELD_INTERLACED_BT && field == V4L2_FIELD_BOTTOM))
1572 return false;
1573
1574 /* The buffer can be completed, reset the fields for the next buffer. */
1575 ccdc->fields = 0;
1576
1577 return true;
1578}
1579
de1135d4
LP		 1580static int ccdc_isr_buffer(struct isp_ccdc_device *ccdc)
1581{
1582 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1583 struct isp_device *isp = to_isp_device(ccdc);
1584 struct isp_buffer *buffer;
de1135d4
LP		 1585
1586 /* The CCDC generates VD0 interrupts even when disabled (the datasheet
1587 * doesn't explicitly state if that's supposed to happen or not, so it
1588 * can be considered as a hardware bug or as a feature, but we have to
1589 * deal with it anyway). Disabling the CCDC when no buffer is available
1590 * would thus not be enough, we need to handle the situation explicitly.
1591 */
1592 if (list_empty(&ccdc->video_out.dmaqueue))
0a7b1a01 1593 return 0;
de1135d4
LP		 1594
1595 /* We're in continuous mode, and memory writes were disabled due to a
1596 * buffer underrun. Reenable them now that we have a buffer. The buffer
1597 * address has been set in ccdc_video_queue.
1598 */
1599 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && ccdc->underrun) {
de1135d4 1600 ccdc->underrun = 0;
0a7b1a01 1601 return 1;
de1135d4
LP		 1602 }
1603
bcb4e0ef 1604 /* Wait for the CCDC to become idle. */
de1135d4
LP		 1605 if (ccdc_sbl_wait_idle(ccdc, 1000)) {
1606 dev_info(isp->dev, "CCDC won't become idle!\n");
9554b7db
LP		 1607 isp->crashed |= 1U << ccdc->subdev.entity.id;
1608 omap3isp_pipeline_cancel_stream(pipe);
0a7b1a01 1609 return 0;
de1135d4
LP		 1610 }
1611
93d7badf
LP		 1612 if (!ccdc_has_all_fields(ccdc))
1613 return 1;
bcb4e0ef 1614
875e2e3e 1615 buffer = omap3isp_video_buffer_next(&ccdc->video_out);
0a7b1a01 1616 if (buffer != NULL)
21d8582d 1617 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4
LP		 1618
1619 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1620
1621 if (ccdc->state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1622 isp_pipeline_ready(pipe))
1623 omap3isp_pipeline_set_stream(pipe,
1624 ISP_PIPELINE_STREAM_SINGLESHOT);
1625
0a7b1a01 1626 return buffer != NULL;
de1135d4
LP		 1627}
1628
1629/*
1630 * ccdc_vd0_isr - Handle VD0 event
1631 * @ccdc: Pointer to ISP CCDC device.
1632 *
1633 * Executes LSC deferred enablement before next frame starts.
1634 */
1635static void ccdc_vd0_isr(struct isp_ccdc_device *ccdc)
1636{
1637 unsigned long flags;
1638 int restart = 0;
1639
1640 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1641 restart = ccdc_isr_buffer(ccdc);
1642
1643 spin_lock_irqsave(&ccdc->lock, flags);
8815392a 1644 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_VD0)) {
de1135d4
LP		 1645 spin_unlock_irqrestore(&ccdc->lock, flags);
1646 return;
1647 }
1648
1649 if (!ccdc->shadow_update)
1650 ccdc_apply_controls(ccdc);
1651 spin_unlock_irqrestore(&ccdc->lock, flags);
1652
1653 if (restart)
1654 ccdc_enable(ccdc);
1655}
1656
1657/*
1658 * ccdc_vd1_isr - Handle VD1 event
1659 * @ccdc: Pointer to ISP CCDC device.
1660 */
1661static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)
1662{
1663 unsigned long flags;
1664
9de7af4d
LP		 1665 /* In BT.656 mode the CCDC doesn't generate an HS/VS interrupt. We thus
1666 * need to increment the frame counter here.
1667 */
1668 if (ccdc->bt656) {
1669 struct isp_pipeline *pipe =
1670 to_isp_pipeline(&ccdc->subdev.entity);
1671
1672 atomic_inc(&pipe->frame_number);
1673 }
1674
de1135d4
LP		 1675 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1676
1677 /*
1678 * Depending on the CCDC pipeline state, CCDC stopping should be
1679 * handled differently. In SINGLESHOT we emulate an internal CCDC
1680 * stopping because the CCDC hw works only in continuous mode.
1681 * When CONTINUOUS pipeline state is used and the CCDC writes it's
1682 * data to memory the CCDC and LSC are stopped immediately but
1683 * without change the CCDC stopping state machine. The CCDC
1684 * stopping state machine should be used only when user request
1685 * for stopping is received (SINGLESHOT is an exeption).
1686 */
1687 switch (ccdc->state) {
1688 case ISP_PIPELINE_STREAM_SINGLESHOT:
1689 ccdc->stopping = CCDC_STOP_REQUEST;
1690 break;
1691
1692 case ISP_PIPELINE_STREAM_CONTINUOUS:
1693 if (ccdc->output & CCDC_OUTPUT_MEMORY) {
1694 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1695 __ccdc_lsc_enable(ccdc, 0);
1696 __ccdc_enable(ccdc, 0);
1697 }
1698 break;
1699
1700 case ISP_PIPELINE_STREAM_STOPPED:
1701 break;
1702 }
1703
8815392a 1704 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))
de1135d4
LP		 1705 goto done;
1706
1707 if (ccdc->lsc.request == NULL)
1708 goto done;
1709
1710 /*
1711 * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ
1712 * do the appropriate changes in registers
1713 */
1714 if (ccdc->lsc.state == LSC_STATE_RUNNING) {
1715 __ccdc_lsc_enable(ccdc, 0);
1716 ccdc->lsc.state = LSC_STATE_RECONFIG;
1717 goto done;
1718 }
1719
1720 /* LSC has been in STOPPED state, enable it */
1721 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1722 ccdc_lsc_enable(ccdc);
1723
1724done:
1725 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1726}
1727
1728/*
1729 * omap3isp_ccdc_isr - Configure CCDC during interframe time.
1730 * @ccdc: Pointer to ISP CCDC device.
1731 * @events: CCDC events
1732 */
1733int omap3isp_ccdc_isr(struct isp_ccdc_device *ccdc, u32 events)
1734{
1735 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED)
1736 return 0;
1737
1738 if (events & IRQ0STATUS_CCDC_VD1_IRQ)
1739 ccdc_vd1_isr(ccdc);
1740
1741 ccdc_lsc_isr(ccdc, events);
1742
1743 if (events & IRQ0STATUS_CCDC_VD0_IRQ)
1744 ccdc_vd0_isr(ccdc);
1745
1746 if (events & IRQ0STATUS_HS_VS_IRQ)
1747 ccdc_hs_vs_isr(ccdc);
1748
1749 return 0;
1750}
1751
1752/* -----------------------------------------------------------------------------
1753 * ISP video operations
1754 */
1755
1756static int ccdc_video_queue(struct isp_video *video, struct isp_buffer *buffer)
1757{
1758 struct isp_ccdc_device *ccdc = &video->isp->isp_ccdc;
1759
1760 if (!(ccdc->output & CCDC_OUTPUT_MEMORY))
1761 return -ENODEV;
1762
21d8582d 1763 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4 1764
2d4e9d1d 1765 /* We now have a buffer queued on the output, restart the pipeline
de1135d4
LP		 1766 * on the next CCDC interrupt if running in continuous mode (or when
1767 * starting the stream).
1768 */
1769 ccdc->underrun = 1;
1770
1771 return 0;
1772}
1773
1774static const struct isp_video_operations ccdc_video_ops = {
1775 .queue = ccdc_video_queue,
1776};
1777
1778/* -----------------------------------------------------------------------------
1779 * V4L2 subdev operations
1780 */
1781
1782/*
1783 * ccdc_ioctl - CCDC module private ioctl's
1784 * @sd: ISP CCDC V4L2 subdevice
1785 * @cmd: ioctl command
1786 * @arg: ioctl argument
1787 *
1788 * Return 0 on success or a negative error code otherwise.
1789 */
1790static long ccdc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1791{
1792 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1793 int ret;
1794
1795 switch (cmd) {
1796 case VIDIOC_OMAP3ISP_CCDC_CFG:
1797 mutex_lock(&ccdc->ioctl_lock);
1798 ret = ccdc_config(ccdc, arg);
1799 mutex_unlock(&ccdc->ioctl_lock);
1800 break;
1801
1802 default:
1803 return -ENOIOCTLCMD;
1804 }
1805
1806 return ret;
1807}
1808
1809static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1810 struct v4l2_event_subscription *sub)
de1135d4 1811{
69d232ae
SA		 1812 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1813 return -EINVAL;
1814
1815 /* line number is zero at frame start */
1816 if (sub->id != 0)
de1135d4
LP		 1817 return -EINVAL;
1818
c53c2549 1819 return v4l2_event_subscribe(fh, sub, OMAP3ISP_CCDC_NEVENTS, NULL);
de1135d4
LP		 1820}
1821
1822static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1823 struct v4l2_event_subscription *sub)
de1135d4
LP		 1824{
1825 return v4l2_event_unsubscribe(fh, sub);
1826}
1827
1828/*
1829 * ccdc_set_stream - Enable/Disable streaming on the CCDC module
1830 * @sd: ISP CCDC V4L2 subdevice
1831 * @enable: Enable/disable stream
1832 *
1833 * When writing to memory, the CCDC hardware can't be enabled without a memory
1834 * buffer to write to. As the s_stream operation is called in response to a
1835 * STREAMON call without any buffer queued yet, just update the enabled field
1836 * and return immediately. The CCDC will be enabled in ccdc_isr_buffer().
1837 *
1838 * When not writing to memory enable the CCDC immediately.
1839 */
1840static int ccdc_set_stream(struct v4l2_subdev *sd, int enable)
1841{
1842 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1843 struct isp_device *isp = to_isp_device(ccdc);
1844 int ret = 0;
1845
1846 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED) {
1847 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1848 return 0;
1849
1850 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_CCDC);
1851 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1852 ISPCCDC_CFG_VDLC);
1853
1854 ccdc_configure(ccdc);
1855
de1135d4
LP		 1856 ccdc_print_status(ccdc);
1857 }
1858
1859 switch (enable) {
1860 case ISP_PIPELINE_STREAM_CONTINUOUS:
1861 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1862 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1863
1864 if (ccdc->underrun || !(ccdc->output & CCDC_OUTPUT_MEMORY))
1865 ccdc_enable(ccdc);
1866
1867 ccdc->underrun = 0;
1868 break;
1869
1870 case ISP_PIPELINE_STREAM_SINGLESHOT:
1871 if (ccdc->output & CCDC_OUTPUT_MEMORY &&
1872 ccdc->state != ISP_PIPELINE_STREAM_SINGLESHOT)
1873 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1874
1875 ccdc_enable(ccdc);
1876 break;
1877
1878 case ISP_PIPELINE_STREAM_STOPPED:
1879 ret = ccdc_disable(ccdc);
1880 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1881 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1882 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_CCDC);
1883 ccdc->underrun = 0;
1884 break;
1885 }
1886
1887 ccdc->state = enable;
1888 return ret;
1889}
1890
1891static struct v4l2_mbus_framefmt *
1892__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1893 unsigned int pad, enum v4l2_subdev_format_whence which)
1894{
1895 if (which == V4L2_SUBDEV_FORMAT_TRY)
1896 return v4l2_subdev_get_try_format(fh, pad);
1897 else
1898 return &ccdc->formats[pad];
1899}
1900
a64909b8
LP		 1901static struct v4l2_rect *
1902__ccdc_get_crop(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1903 enum v4l2_subdev_format_whence which)
1904{
1905 if (which == V4L2_SUBDEV_FORMAT_TRY)
1906 return v4l2_subdev_get_try_crop(fh, CCDC_PAD_SOURCE_OF);
1907 else
1908 return &ccdc->crop;
1909}
1910
de1135d4
LP		 1911/*
1912 * ccdc_try_format - Try video format on a pad
1913 * @ccdc: ISP CCDC device
1914 * @fh : V4L2 subdev file handle
1915 * @pad: Pad number
1916 * @fmt: Format
1917 */
1918static void
1919ccdc_try_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1920 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
1921 enum v4l2_subdev_format_whence which)
1922{
de1135d4 1923 const struct isp_format_info *info;
c51364ca 1924 enum v4l2_mbus_pixelcode pixelcode;
de1135d4
LP		 1925 unsigned int width = fmt->width;
1926 unsigned int height = fmt->height;
a64909b8 1927 struct v4l2_rect *crop;
bcb4e0ef 1928 enum v4l2_field field;
de1135d4
LP		 1929 unsigned int i;
1930
1931 switch (pad) {
1932 case CCDC_PAD_SINK:
de1135d4
LP		 1933 for (i = 0; i < ARRAY_SIZE(ccdc_fmts); i++) {
1934 if (fmt->code == ccdc_fmts[i])
1935 break;
1936 }
1937
1938 /* If not found, use SGRBG10 as default */
1939 if (i >= ARRAY_SIZE(ccdc_fmts))
1940 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1941
1942 /* Clamp the input size. */
1943 fmt->width = clamp_t(u32, width, 32, 4096);
1944 fmt->height = clamp_t(u32, height, 32, 4096);
9a36d8ed
LP		 1945
1946 /* Default to progressive field order. */
1947 if (fmt->field == V4L2_FIELD_ANY)
1948 fmt->field = V4L2_FIELD_NONE;
1949
de1135d4
LP		 1950 break;
1951
1952 case CCDC_PAD_SOURCE_OF:
c51364ca 1953 pixelcode = fmt->code;
bcb4e0ef 1954 field = fmt->field;
c51364ca
LP		 1955 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
1956
9de7af4d
LP		 1957 /* In SYNC mode the bridge converts YUV formats from 2X8 to
1958 * 1X16. In BT.656 no such conversion occurs. As we don't know
1959 * at this point whether the source will use SYNC or BT.656 mode
1960 * let's pretend the conversion always occurs. The CCDC will be
1961 * configured to pack bytes in BT.656, hiding the inaccuracy.
1962 * In all cases bytes can be swapped.
c51364ca
LP		 1963 */
1964 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1965 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1966 /* Use the user requested format if YUV. */
1967 if (pixelcode == V4L2_MBUS_FMT_YUYV8_2X8 ||
1968 pixelcode == V4L2_MBUS_FMT_UYVY8_2X8 ||
1969 pixelcode == V4L2_MBUS_FMT_YUYV8_1X16 ||
1970 pixelcode == V4L2_MBUS_FMT_UYVY8_1X16)
1971 fmt->code = pixelcode;
1972
1973 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8)
1974 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1975 else if (fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1976 fmt->code = V4L2_MBUS_FMT_UYVY8_1X16;
1977 }
de1135d4 1978
a64909b8
LP		 1979 /* Hardcode the output size to the crop rectangle size. */
1980 crop = __ccdc_get_crop(ccdc, fh, which);
1981 fmt->width = crop->width;
1982 fmt->height = crop->height;
bcb4e0ef
LP		 1983
1984 /* When input format is interlaced with alternating fields the
1985 * CCDC can interleave the fields.
1986 */
1987 if (fmt->field == V4L2_FIELD_ALTERNATE &&
1988 (field == V4L2_FIELD_INTERLACED_TB ||
1989 field == V4L2_FIELD_INTERLACED_BT)) {
1990 fmt->field = field;
1991 fmt->height *= 2;
1992 }
1993
de1135d4
LP		 1994 break;
1995
1996 case CCDC_PAD_SOURCE_VP:
c51364ca 1997 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
de1135d4
LP		 1998
1999 /* The video port interface truncates the data to 10 bits. */
2000 info = omap3isp_video_format_info(fmt->code);
2001 fmt->code = info->truncated;
2002
c51364ca
LP		 2003 /* YUV formats are not supported by the video port. */
2004 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
2005 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
2006 fmt->code = 0;
2007
de1135d4
LP		 2008 /* The number of lines that can be clocked out from the video
2009 * port output must be at least one line less than the number
2010 * of input lines.
2011 */
2012 fmt->width = clamp_t(u32, width, 32, fmt->width);
2013 fmt->height = clamp_t(u32, height, 32, fmt->height - 1);
2014 break;
2015 }
2016
2017 /* Data is written to memory unpacked, each 10-bit or 12-bit pixel is
2018 * stored on 2 bytes.
2019 */
2020 fmt->colorspace = V4L2_COLORSPACE_SRGB;
de1135d4
LP		 2021}
2022
a64909b8
LP		 2023/*
2024 * ccdc_try_crop - Validate a crop rectangle
2025 * @ccdc: ISP CCDC device
2026 * @sink: format on the sink pad
2027 * @crop: crop rectangle to be validated
2028 */
2029static void ccdc_try_crop(struct isp_ccdc_device *ccdc,
2030 const struct v4l2_mbus_framefmt *sink,
2031 struct v4l2_rect *crop)
2032{
2033 const struct isp_format_info *info;
2034 unsigned int max_width;
2035
2036 /* For Bayer formats, restrict left/top and width/height to even values
2037 * to keep the Bayer pattern.
2038 */
2039 info = omap3isp_video_format_info(sink->code);
2040 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2041 crop->left &= ~1;
2042 crop->top &= ~1;
2043 }
2044
2045 crop->left = clamp_t(u32, crop->left, 0, sink->width - CCDC_MIN_WIDTH);
2046 crop->top = clamp_t(u32, crop->top, 0, sink->height - CCDC_MIN_HEIGHT);
2047
2048 /* The data formatter truncates the number of horizontal output pixels
2049 * to a multiple of 16. To avoid clipping data, allow callers to request
2050 * an output size bigger than the input size up to the nearest multiple
2051 * of 16.
2052 */
2053 max_width = (sink->width - crop->left + 15) & ~15;
2054 crop->width = clamp_t(u32, crop->width, CCDC_MIN_WIDTH, max_width)
2055 & ~15;
2056 crop->height = clamp_t(u32, crop->height, CCDC_MIN_HEIGHT,
2057 sink->height - crop->top);
2058
2059 /* Odd width/height values don't make sense for Bayer formats. */
2060 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2061 crop->width &= ~1;
2062 crop->height &= ~1;
2063 }
2064}
2065
de1135d4
LP		 2066/*
2067 * ccdc_enum_mbus_code - Handle pixel format enumeration
2068 * @sd : pointer to v4l2 subdev structure
2069 * @fh : V4L2 subdev file handle
2070 * @code : pointer to v4l2_subdev_mbus_code_enum structure
2071 * return -EINVAL or zero on success
2072 */
2073static int ccdc_enum_mbus_code(struct v4l2_subdev *sd,
2074 struct v4l2_subdev_fh *fh,
2075 struct v4l2_subdev_mbus_code_enum *code)
2076{
2077 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2078 struct v4l2_mbus_framefmt *format;
2079
2080 switch (code->pad) {
2081 case CCDC_PAD_SINK:
2082 if (code->index >= ARRAY_SIZE(ccdc_fmts))
2083 return -EINVAL;
2084
2085 code->code = ccdc_fmts[code->index];
2086 break;
2087
2088 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 2089 format = __ccdc_get_format(ccdc, fh, code->pad,
2090 V4L2_SUBDEV_FORMAT_TRY);
2091
2092 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
2093 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
2094 /* In YUV mode the CCDC can swap bytes. */
2095 if (code->index == 0)
2096 code->code = V4L2_MBUS_FMT_YUYV8_1X16;
2097 else if (code->index == 1)
2098 code->code = V4L2_MBUS_FMT_UYVY8_1X16;
2099 else
2100 return -EINVAL;
2101 } else {
2102 /* In raw mode, no configurable format confversion is
2103 * available.
2104 */
2105 if (code->index == 0)
2106 code->code = format->code;
2107 else
2108 return -EINVAL;
2109 }
2110 break;
2111
de1135d4 2112 case CCDC_PAD_SOURCE_VP:
c51364ca
LP		 2113 /* The CCDC supports no configurable format conversion
2114 * compatible with the video port. Enumerate a single output
2115 * format code.
2116 */
de1135d4
LP		 2117 if (code->index != 0)
2118 return -EINVAL;
2119
c51364ca 2120 format = __ccdc_get_format(ccdc, fh, code->pad,
de1135d4
LP		 2121 V4L2_SUBDEV_FORMAT_TRY);
2122
c51364ca
LP		 2123 /* A pixel code equal to 0 means that the video port doesn't
2124 * support the input format. Don't enumerate any pixel code.
2125 */
2126 if (format->code == 0)
2127 return -EINVAL;
2128
de1135d4
LP		 2129 code->code = format->code;
2130 break;
2131
2132 default:
2133 return -EINVAL;
2134 }
2135
2136 return 0;
2137}
2138
2139static int ccdc_enum_frame_size(struct v4l2_subdev *sd,
2140 struct v4l2_subdev_fh *fh,
2141 struct v4l2_subdev_frame_size_enum *fse)
2142{
2143 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2144 struct v4l2_mbus_framefmt format;
2145
2146 if (fse->index != 0)
2147 return -EINVAL;
2148
2149 format.code = fse->code;
2150 format.width = 1;
2151 format.height = 1;
2152 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2153 fse->min_width = format.width;
2154 fse->min_height = format.height;
2155
2156 if (format.code != fse->code)
2157 return -EINVAL;
2158
2159 format.code = fse->code;
2160 format.width = -1;
2161 format.height = -1;
2162 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2163 fse->max_width = format.width;
2164 fse->max_height = format.height;
2165
2166 return 0;
2167}
2168
a64909b8
LP		 2169/*
2170 * ccdc_get_selection - Retrieve a selection rectangle on a pad
2171 * @sd: ISP CCDC V4L2 subdevice
2172 * @fh: V4L2 subdev file handle
2173 * @sel: Selection rectangle
2174 *
2175 * The only supported rectangles are the crop rectangles on the output formatter
2176 * source pad.
2177 *
2178 * Return 0 on success or a negative error code otherwise.
2179 */
2180static int ccdc_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2181 struct v4l2_subdev_selection *sel)
2182{
2183 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2184 struct v4l2_mbus_framefmt *format;
2185
2186 if (sel->pad != CCDC_PAD_SOURCE_OF)
2187 return -EINVAL;
2188
2189 switch (sel->target) {
5689b288 2190 case V4L2_SEL_TGT_CROP_BOUNDS:
a64909b8
LP		 2191 sel->r.left = 0;
2192 sel->r.top = 0;
2193 sel->r.width = INT_MAX;
2194 sel->r.height = INT_MAX;
2195
2196 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2197 ccdc_try_crop(ccdc, format, &sel->r);
2198 break;
2199
5689b288 2200 case V4L2_SEL_TGT_CROP:
a64909b8
LP		 2201 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2202 break;
2203
2204 default:
2205 return -EINVAL;
2206 }
2207
2208 return 0;
2209}
2210
2211/*
2212 * ccdc_set_selection - Set a selection rectangle on a pad
2213 * @sd: ISP CCDC V4L2 subdevice
2214 * @fh: V4L2 subdev file handle
2215 * @sel: Selection rectangle
2216 *
2217 * The only supported rectangle is the actual crop rectangle on the output
2218 * formatter source pad.
2219 *
2220 * Return 0 on success or a negative error code otherwise.
2221 */
2222static int ccdc_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2223 struct v4l2_subdev_selection *sel)
2224{
2225 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2226 struct v4l2_mbus_framefmt *format;
2227
5689b288 2228 if (sel->target != V4L2_SEL_TGT_CROP ||
a64909b8
LP		 2229 sel->pad != CCDC_PAD_SOURCE_OF)
2230 return -EINVAL;
2231
2232 /* The crop rectangle can't be changed while streaming. */
2233 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
2234 return -EBUSY;
2235
2236 /* Modifying the crop rectangle always changes the format on the source
2237 * pad. If the KEEP_CONFIG flag is set, just return the current crop
2238 * rectangle.
2239 */
563df3d0 2240 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
a64909b8
LP		 2241 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2242 return 0;
2243 }
2244
2245 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2246 ccdc_try_crop(ccdc, format, &sel->r);
2247 *__ccdc_get_crop(ccdc, fh, sel->which) = sel->r;
2248
2249 /* Update the source format. */
2250 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF, sel->which);
2251 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format, sel->which);
2252
2253 return 0;
2254}
2255
de1135d4
LP		 2256/*
2257 * ccdc_get_format - Retrieve the video format on a pad
2258 * @sd : ISP CCDC V4L2 subdevice
2259 * @fh : V4L2 subdev file handle
2260 * @fmt: Format
2261 *
2262 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2263 * to the format type.
2264 */
2265static int ccdc_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2266 struct v4l2_subdev_format *fmt)
2267{
2268 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2269 struct v4l2_mbus_framefmt *format;
2270
2271 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2272 if (format == NULL)
2273 return -EINVAL;
2274
2275 fmt->format = *format;
2276 return 0;
2277}
2278
2279/*
2280 * ccdc_set_format - Set the video format on a pad
2281 * @sd : ISP CCDC V4L2 subdevice
2282 * @fh : V4L2 subdev file handle
2283 * @fmt: Format
2284 *
2285 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2286 * to the format type.
2287 */
2288static int ccdc_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2289 struct v4l2_subdev_format *fmt)
2290{
2291 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2292 struct v4l2_mbus_framefmt *format;
a64909b8 2293 struct v4l2_rect *crop;
de1135d4
LP		 2294
2295 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2296 if (format == NULL)
2297 return -EINVAL;
2298
2299 ccdc_try_format(ccdc, fh, fmt->pad, &fmt->format, fmt->which);
2300 *format = fmt->format;
2301
2302 /* Propagate the format from sink to source */
2303 if (fmt->pad == CCDC_PAD_SINK) {
a64909b8
LP		 2304 /* Reset the crop rectangle. */
2305 crop = __ccdc_get_crop(ccdc, fh, fmt->which);
2306 crop->left = 0;
2307 crop->top = 0;
2308 crop->width = fmt->format.width;
2309 crop->height = fmt->format.height;
2310
2311 ccdc_try_crop(ccdc, &fmt->format, crop);
2312
2313 /* Update the source formats. */
de1135d4
LP		 2314 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF,
2315 fmt->which);
2316 *format = fmt->format;
2317 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format,
2318 fmt->which);
2319
2320 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_VP,
2321 fmt->which);
2322 *format = fmt->format;
2323 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_VP, format,
2324 fmt->which);
2325 }
2326
2327 return 0;
2328}
2329
a6d7a62d
SA		 2330/*
2331 * Decide whether desired output pixel code can be obtained with
2332 * the lane shifter by shifting the input pixel code.
2333 * @in: input pixelcode to shifter
2334 * @out: output pixelcode from shifter
2335 * @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
2336 *
2337 * return true if the combination is possible
2338 * return false otherwise
2339 */
2340static bool ccdc_is_shiftable(enum v4l2_mbus_pixelcode in,
2341 enum v4l2_mbus_pixelcode out,
2342 unsigned int additional_shift)
2343{
2344 const struct isp_format_info *in_info, *out_info;
2345
2346 if (in == out)
2347 return true;
2348
2349 in_info = omap3isp_video_format_info(in);
2350 out_info = omap3isp_video_format_info(out);
2351
2352 if ((in_info->flavor == 0) || (out_info->flavor == 0))
2353 return false;
2354
2355 if (in_info->flavor != out_info->flavor)
2356 return false;
2357
1697e49a 2358 return in_info->width - out_info->width + additional_shift <= 6;
a6d7a62d
SA		 2359}
2360
2361static int ccdc_link_validate(struct v4l2_subdev *sd,
2362 struct media_link *link,
2363 struct v4l2_subdev_format *source_fmt,
2364 struct v4l2_subdev_format *sink_fmt)
2365{
2366 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2367 unsigned long parallel_shift;
2368
2369 /* Check if the two ends match */
2370 if (source_fmt->format.width != sink_fmt->format.width ||
2371 source_fmt->format.height != sink_fmt->format.height)
2372 return -EPIPE;
2373
2374 /* We've got a parallel sensor here. */
2375 if (ccdc->input == CCDC_INPUT_PARALLEL) {
2376 struct isp_parallel_platform_data *pdata =
2377 &((struct isp_v4l2_subdevs_group *)
2378 media_entity_to_v4l2_subdev(link->source->entity)
2379 ->host_priv)->bus.parallel;
2380 parallel_shift = pdata->data_lane_shift * 2;
2381 } else {
2382 parallel_shift = 0;
2383 }
2384
2385 /* Lane shifter may be used to drop bits on CCDC sink pad */
2386 if (!ccdc_is_shiftable(source_fmt->format.code,
2387 sink_fmt->format.code, parallel_shift))
2388 return -EPIPE;
2389
2390 return 0;
2391}
2392
de1135d4
LP		 2393/*
2394 * ccdc_init_formats - Initialize formats on all pads
2395 * @sd: ISP CCDC V4L2 subdevice
2396 * @fh: V4L2 subdev file handle
2397 *
2398 * Initialize all pad formats with default values. If fh is not NULL, try
2399 * formats are initialized on the file handle. Otherwise active formats are
2400 * initialized on the device.
2401 */
2402static int ccdc_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2403{
2404 struct v4l2_subdev_format format;
2405
2406 memset(&format, 0, sizeof(format));
2407 format.pad = CCDC_PAD_SINK;
2408 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
2409 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
2410 format.format.width = 4096;
2411 format.format.height = 4096;
2412 ccdc_set_format(sd, fh, &format);
2413
2414 return 0;
2415}
2416
2417/* V4L2 subdev core operations */
2418static const struct v4l2_subdev_core_ops ccdc_v4l2_core_ops = {
2419 .ioctl = ccdc_ioctl,
2420 .subscribe_event = ccdc_subscribe_event,
2421 .unsubscribe_event = ccdc_unsubscribe_event,
2422};
2423
2424/* V4L2 subdev video operations */
2425static const struct v4l2_subdev_video_ops ccdc_v4l2_video_ops = {
2426 .s_stream = ccdc_set_stream,
2427};
2428
2429/* V4L2 subdev pad operations */
2430static const struct v4l2_subdev_pad_ops ccdc_v4l2_pad_ops = {
2431 .enum_mbus_code = ccdc_enum_mbus_code,
2432 .enum_frame_size = ccdc_enum_frame_size,
2433 .get_fmt = ccdc_get_format,
2434 .set_fmt = ccdc_set_format,
a64909b8
LP		 2435 .get_selection = ccdc_get_selection,
2436 .set_selection = ccdc_set_selection,
a6d7a62d 2437 .link_validate = ccdc_link_validate,
de1135d4
LP		 2438};
2439
2440/* V4L2 subdev operations */
2441static const struct v4l2_subdev_ops ccdc_v4l2_ops = {
2442 .core = &ccdc_v4l2_core_ops,
2443 .video = &ccdc_v4l2_video_ops,
2444 .pad = &ccdc_v4l2_pad_ops,
2445};
2446
2447/* V4L2 subdev internal operations */
2448static const struct v4l2_subdev_internal_ops ccdc_v4l2_internal_ops = {
2449 .open = ccdc_init_formats,
2450};
2451
2452/* -----------------------------------------------------------------------------
2453 * Media entity operations
2454 */
2455
2456/*
2457 * ccdc_link_setup - Setup CCDC connections
2458 * @entity: CCDC media entity
2459 * @local: Pad at the local end of the link
2460 * @remote: Pad at the remote end of the link
2461 * @flags: Link flags
2462 *
2463 * return -EINVAL or zero on success
2464 */
2465static int ccdc_link_setup(struct media_entity *entity,
2466 const struct media_pad *local,
2467 const struct media_pad *remote, u32 flags)
2468{
2469 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2470 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2471 struct isp_device *isp = to_isp_device(ccdc);
2472
2473 switch (local->index | media_entity_type(remote->entity)) {
2474 case CCDC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2475 /* Read from the sensor (parallel interface), CCP2, CSI2a or
2476 * CSI2c.
2477 */
2478 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
2479 ccdc->input = CCDC_INPUT_NONE;
2480 break;
2481 }
2482
2483 if (ccdc->input != CCDC_INPUT_NONE)
2484 return -EBUSY;
2485
2486 if (remote->entity == &isp->isp_ccp2.subdev.entity)
2487 ccdc->input = CCDC_INPUT_CCP2B;
2488 else if (remote->entity == &isp->isp_csi2a.subdev.entity)
2489 ccdc->input = CCDC_INPUT_CSI2A;
2490 else if (remote->entity == &isp->isp_csi2c.subdev.entity)
2491 ccdc->input = CCDC_INPUT_CSI2C;
2492 else
2493 ccdc->input = CCDC_INPUT_PARALLEL;
2494
2495 break;
2496
2497 /*
2498 * The ISP core doesn't support pipelines with multiple video outputs.
2499 * Revisit this when it will be implemented, and return -EBUSY for now.
2500 */
2501
2502 case CCDC_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
2503 /* Write to preview engine, histogram and H3A. When none of
2504 * those links are active, the video port can be disabled.
2505 */
2506 if (flags & MEDIA_LNK_FL_ENABLED) {
2507 if (ccdc->output & ~CCDC_OUTPUT_PREVIEW)
2508 return -EBUSY;
2509 ccdc->output |= CCDC_OUTPUT_PREVIEW;
2510 } else {
2511 ccdc->output &= ~CCDC_OUTPUT_PREVIEW;
2512 }
2513 break;
2514
2515 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_DEVNODE:
2516 /* Write to memory */
2517 if (flags & MEDIA_LNK_FL_ENABLED) {
2518 if (ccdc->output & ~CCDC_OUTPUT_MEMORY)
2519 return -EBUSY;
2520 ccdc->output |= CCDC_OUTPUT_MEMORY;
2521 } else {
2522 ccdc->output &= ~CCDC_OUTPUT_MEMORY;
2523 }
2524 break;
2525
2526 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_V4L2_SUBDEV:
2527 /* Write to resizer */
2528 if (flags & MEDIA_LNK_FL_ENABLED) {
2529 if (ccdc->output & ~CCDC_OUTPUT_RESIZER)
2530 return -EBUSY;
2531 ccdc->output |= CCDC_OUTPUT_RESIZER;
2532 } else {
2533 ccdc->output &= ~CCDC_OUTPUT_RESIZER;
2534 }
2535 break;
2536
2537 default:
2538 return -EINVAL;
2539 }
2540
2541 return 0;
2542}
2543
2544/* media operations */
2545static const struct media_entity_operations ccdc_media_ops = {
2546 .link_setup = ccdc_link_setup,
a6d7a62d 2547 .link_validate = v4l2_subdev_link_validate,
de1135d4
LP		 2548};
2549
39099d09
LP		 2550void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc)
2551{
2552 v4l2_device_unregister_subdev(&ccdc->subdev);
2553 omap3isp_video_unregister(&ccdc->video_out);
2554}
2555
2556int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
2557 struct v4l2_device *vdev)
2558{
2559 int ret;
2560
2561 /* Register the subdev and video node. */
2562 ret = v4l2_device_register_subdev(vdev, &ccdc->subdev);
2563 if (ret < 0)
2564 goto error;
2565
2566 ret = omap3isp_video_register(&ccdc->video_out, vdev);
2567 if (ret < 0)
2568 goto error;
2569
2570 return 0;
2571
2572error:
2573 omap3isp_ccdc_unregister_entities(ccdc);
2574 return ret;
2575}
2576
2577/* -----------------------------------------------------------------------------
2578 * ISP CCDC initialisation and cleanup
2579 */
2580
de1135d4
LP		 2581/*
2582 * ccdc_init_entities - Initialize V4L2 subdev and media entity
2583 * @ccdc: ISP CCDC module
2584 *
2585 * Return 0 on success and a negative error code on failure.
2586 */
2587static int ccdc_init_entities(struct isp_ccdc_device *ccdc)
2588{
2589 struct v4l2_subdev *sd = &ccdc->subdev;
2590 struct media_pad *pads = ccdc->pads;
2591 struct media_entity *me = &sd->entity;
2592 int ret;
2593
2594 ccdc->input = CCDC_INPUT_NONE;
2595
2596 v4l2_subdev_init(sd, &ccdc_v4l2_ops);
2597 sd->internal_ops = &ccdc_v4l2_internal_ops;
2598 strlcpy(sd->name, "OMAP3 ISP CCDC", sizeof(sd->name));
2599 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2600 v4l2_set_subdevdata(sd, ccdc);
2601 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
de1135d4 2602
8dad936a
SA		 2603 pads[CCDC_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2604 | MEDIA_PAD_FL_MUST_CONNECT;
de1135d4
LP		 2605 pads[CCDC_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
2606 pads[CCDC_PAD_SOURCE_OF].flags = MEDIA_PAD_FL_SOURCE;
2607
2608 me->ops = &ccdc_media_ops;
2609 ret = media_entity_init(me, CCDC_PADS_NUM, pads, 0);
2610 if (ret < 0)
2611 return ret;
2612
2613 ccdc_init_formats(sd, NULL);
2614
2615 ccdc->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2616 ccdc->video_out.ops = &ccdc_video_ops;
2617 ccdc->video_out.isp = to_isp_device(ccdc);
2618 ccdc->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
2619 ccdc->video_out.bpl_alignment = 32;
2620
2621 ret = omap3isp_video_init(&ccdc->video_out, "CCDC");
2622 if (ret < 0)
9b6390bd 2623 goto error_video;
de1135d4
LP		 2624
2625 /* Connect the CCDC subdev to the video node. */
2626 ret = media_entity_create_link(&ccdc->subdev.entity, CCDC_PAD_SOURCE_OF,
2627 &ccdc->video_out.video.entity, 0, 0);
2628 if (ret < 0)
9b6390bd 2629 goto error_link;
de1135d4
LP		 2630
2631 return 0;
9b6390bd
LP		 2632
2633error_link:
2634 omap3isp_video_cleanup(&ccdc->video_out);
2635error_video:
2636 media_entity_cleanup(me);
2637 return ret;
de1135d4
LP		 2638}
2639
de1135d4
LP		 2640/*
2641 * omap3isp_ccdc_init - CCDC module initialization.
872aba51 2642 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2643 *
2644 * TODO: Get the initialisation values from platform data.
2645 *
2646 * Return 0 on success or a negative error code otherwise.
2647 */
2648int omap3isp_ccdc_init(struct isp_device *isp)
2649{
2650 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
9b6390bd 2651 int ret;
de1135d4
LP		 2652
2653 spin_lock_init(&ccdc->lock);
2654 init_waitqueue_head(&ccdc->wait);
2655 mutex_init(&ccdc->ioctl_lock);
2656
2657 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
2658
2659 INIT_WORK(&ccdc->lsc.table_work, ccdc_lsc_free_table_work);
2660 ccdc->lsc.state = LSC_STATE_STOPPED;
2661 INIT_LIST_HEAD(&ccdc->lsc.free_queue);
2662 spin_lock_init(&ccdc->lsc.req_lock);
2663
de1135d4
LP		 2664 ccdc->clamp.oblen = 0;
2665 ccdc->clamp.dcsubval = 0;
2666
de1135d4
LP		 2667 ccdc->update = OMAP3ISP_CCDC_BLCLAMP;
2668 ccdc_apply_controls(ccdc);
2669
9b6390bd
LP		 2670 ret = ccdc_init_entities(ccdc);
2671 if (ret < 0) {
2672 mutex_destroy(&ccdc->ioctl_lock);
2673 return ret;
2674 }
2675
2676 return 0;
de1135d4
LP		 2677}
2678
2679/*
2680 * omap3isp_ccdc_cleanup - CCDC module cleanup.
872aba51 2681 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2682 */
2683void omap3isp_ccdc_cleanup(struct isp_device *isp)
2684{
2685 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
2686
63b4ca23
LP		 2687 omap3isp_video_cleanup(&ccdc->video_out);
2688 media_entity_cleanup(&ccdc->subdev.entity);
2689
de1135d4
LP		 2690 /* Free LSC requests. As the CCDC is stopped there's no active request,
2691 * so only the pending request and the free queue need to be handled.
2692 */
2693 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
2694 cancel_work_sync(&ccdc->lsc.table_work);
2695 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
2696
c60e153d
LP		 2697 if (ccdc->fpc.addr != NULL)
2698 dma_free_coherent(isp->dev, ccdc->fpc.fpnum * 4, ccdc->fpc.addr,
2699 ccdc->fpc.dma);
ed33ac8e
LP		 2700
2701 mutex_destroy(&ccdc->ioctl_lock);
de1135d4 2702}
Linux kernel - Deliverables
This page took 0.34386 seconds and 5 git commands to generate.