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[media] platform: Make use of media_bus_format enum
[deliverable/linux.git] / drivers / media / platform / omap3isp / ispccdc.c
CommitLineData
de1135d4
LP		 1/*
2 * ispccdc.c
3 *
4 * TI OMAP3 ISP - CCDC module
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
de1135d4
LP		 15 */
16
17#include <linux/module.h>
18#include <linux/uaccess.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mm.h>
23#include <linux/sched.h>
e74d83aa 24#include <linux/slab.h>
de1135d4
LP		 25#include <media/v4l2-event.h>
26
27#include "isp.h"
28#include "ispreg.h"
29#include "ispccdc.h"
30
a64909b8
LP		 31#define CCDC_MIN_WIDTH 32
32#define CCDC_MIN_HEIGHT 32
33
de1135d4
LP		 34static struct v4l2_mbus_framefmt *
35__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
36 unsigned int pad, enum v4l2_subdev_format_whence which);
37
38static const unsigned int ccdc_fmts[] = {
27ffaeb0
BB		 39 MEDIA_BUS_FMT_Y8_1X8,
40 MEDIA_BUS_FMT_Y10_1X10,
41 MEDIA_BUS_FMT_Y12_1X12,
42 MEDIA_BUS_FMT_SGRBG8_1X8,
43 MEDIA_BUS_FMT_SRGGB8_1X8,
44 MEDIA_BUS_FMT_SBGGR8_1X8,
45 MEDIA_BUS_FMT_SGBRG8_1X8,
46 MEDIA_BUS_FMT_SGRBG10_1X10,
47 MEDIA_BUS_FMT_SRGGB10_1X10,
48 MEDIA_BUS_FMT_SBGGR10_1X10,
49 MEDIA_BUS_FMT_SGBRG10_1X10,
50 MEDIA_BUS_FMT_SGRBG12_1X12,
51 MEDIA_BUS_FMT_SRGGB12_1X12,
52 MEDIA_BUS_FMT_SBGGR12_1X12,
53 MEDIA_BUS_FMT_SGBRG12_1X12,
54 MEDIA_BUS_FMT_YUYV8_2X8,
55 MEDIA_BUS_FMT_UYVY8_2X8,
de1135d4
LP		 56};
57
58/*
59 * ccdc_print_status - Print current CCDC Module register values.
60 * @ccdc: Pointer to ISP CCDC device.
61 *
62 * Also prints other debug information stored in the CCDC module.
63 */
64#define CCDC_PRINT_REGISTER(isp, name)\
65 dev_dbg(isp->dev, "###CCDC " #name "=0x%08x\n", \
66 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_##name))
67
68static void ccdc_print_status(struct isp_ccdc_device *ccdc)
69{
70 struct isp_device *isp = to_isp_device(ccdc);
71
72 dev_dbg(isp->dev, "-------------CCDC Register dump-------------\n");
73
74 CCDC_PRINT_REGISTER(isp, PCR);
75 CCDC_PRINT_REGISTER(isp, SYN_MODE);
76 CCDC_PRINT_REGISTER(isp, HD_VD_WID);
77 CCDC_PRINT_REGISTER(isp, PIX_LINES);
78 CCDC_PRINT_REGISTER(isp, HORZ_INFO);
79 CCDC_PRINT_REGISTER(isp, VERT_START);
80 CCDC_PRINT_REGISTER(isp, VERT_LINES);
81 CCDC_PRINT_REGISTER(isp, CULLING);
82 CCDC_PRINT_REGISTER(isp, HSIZE_OFF);
83 CCDC_PRINT_REGISTER(isp, SDOFST);
84 CCDC_PRINT_REGISTER(isp, SDR_ADDR);
85 CCDC_PRINT_REGISTER(isp, CLAMP);
86 CCDC_PRINT_REGISTER(isp, DCSUB);
87 CCDC_PRINT_REGISTER(isp, COLPTN);
88 CCDC_PRINT_REGISTER(isp, BLKCMP);
89 CCDC_PRINT_REGISTER(isp, FPC);
90 CCDC_PRINT_REGISTER(isp, FPC_ADDR);
91 CCDC_PRINT_REGISTER(isp, VDINT);
92 CCDC_PRINT_REGISTER(isp, ALAW);
93 CCDC_PRINT_REGISTER(isp, REC656IF);
94 CCDC_PRINT_REGISTER(isp, CFG);
95 CCDC_PRINT_REGISTER(isp, FMTCFG);
96 CCDC_PRINT_REGISTER(isp, FMT_HORZ);
97 CCDC_PRINT_REGISTER(isp, FMT_VERT);
98 CCDC_PRINT_REGISTER(isp, PRGEVEN0);
99 CCDC_PRINT_REGISTER(isp, PRGEVEN1);
100 CCDC_PRINT_REGISTER(isp, PRGODD0);
101 CCDC_PRINT_REGISTER(isp, PRGODD1);
102 CCDC_PRINT_REGISTER(isp, VP_OUT);
103 CCDC_PRINT_REGISTER(isp, LSC_CONFIG);
104 CCDC_PRINT_REGISTER(isp, LSC_INITIAL);
105 CCDC_PRINT_REGISTER(isp, LSC_TABLE_BASE);
106 CCDC_PRINT_REGISTER(isp, LSC_TABLE_OFFSET);
107
108 dev_dbg(isp->dev, "--------------------------------------------\n");
109}
110
111/*
112 * omap3isp_ccdc_busy - Get busy state of the CCDC.
113 * @ccdc: Pointer to ISP CCDC device.
114 */
115int omap3isp_ccdc_busy(struct isp_ccdc_device *ccdc)
116{
117 struct isp_device *isp = to_isp_device(ccdc);
118
119 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
120 ISPCCDC_PCR_BUSY;
121}
122
123/* -----------------------------------------------------------------------------
124 * Lens Shading Compensation
125 */
126
127/*
128 * ccdc_lsc_validate_config - Check that LSC configuration is valid.
129 * @ccdc: Pointer to ISP CCDC device.
130 * @lsc_cfg: the LSC configuration to check.
131 *
132 * Returns 0 if the LSC configuration is valid, or -EINVAL if invalid.
133 */
134static int ccdc_lsc_validate_config(struct isp_ccdc_device *ccdc,
135 struct omap3isp_ccdc_lsc_config *lsc_cfg)
136{
137 struct isp_device *isp = to_isp_device(ccdc);
138 struct v4l2_mbus_framefmt *format;
139 unsigned int paxel_width, paxel_height;
140 unsigned int paxel_shift_x, paxel_shift_y;
141 unsigned int min_width, min_height, min_size;
142 unsigned int input_width, input_height;
143
144 paxel_shift_x = lsc_cfg->gain_mode_m;
145 paxel_shift_y = lsc_cfg->gain_mode_n;
146
147 if ((paxel_shift_x < 2) || (paxel_shift_x > 6) ||
148 (paxel_shift_y < 2) || (paxel_shift_y > 6)) {
149 dev_dbg(isp->dev, "CCDC: LSC: Invalid paxel size\n");
150 return -EINVAL;
151 }
152
153 if (lsc_cfg->offset & 3) {
154 dev_dbg(isp->dev, "CCDC: LSC: Offset must be a multiple of "
155 "4\n");
156 return -EINVAL;
157 }
158
159 if ((lsc_cfg->initial_x & 1) || (lsc_cfg->initial_y & 1)) {
160 dev_dbg(isp->dev, "CCDC: LSC: initial_x and y must be even\n");
161 return -EINVAL;
162 }
163
164 format = __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
165 V4L2_SUBDEV_FORMAT_ACTIVE);
166 input_width = format->width;
167 input_height = format->height;
168
169 /* Calculate minimum bytesize for validation */
170 paxel_width = 1 << paxel_shift_x;
171 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1)
172 >> paxel_shift_x) + 1;
173
174 paxel_height = 1 << paxel_shift_y;
175 min_height = ((input_height + lsc_cfg->initial_y + paxel_height - 1)
176 >> paxel_shift_y) + 1;
177
178 min_size = 4 * min_width * min_height;
179 if (min_size > lsc_cfg->size) {
180 dev_dbg(isp->dev, "CCDC: LSC: too small table\n");
181 return -EINVAL;
182 }
183 if (lsc_cfg->offset < (min_width * 4)) {
184 dev_dbg(isp->dev, "CCDC: LSC: Offset is too small\n");
185 return -EINVAL;
186 }
187 if ((lsc_cfg->size / lsc_cfg->offset) < min_height) {
188 dev_dbg(isp->dev, "CCDC: LSC: Wrong size/offset combination\n");
189 return -EINVAL;
190 }
191 return 0;
192}
193
194/*
195 * ccdc_lsc_program_table - Program Lens Shading Compensation table address.
196 * @ccdc: Pointer to ISP CCDC device.
197 */
d33186d0
LP		 198static void ccdc_lsc_program_table(struct isp_ccdc_device *ccdc,
199 dma_addr_t addr)
de1135d4
LP		 200{
201 isp_reg_writel(to_isp_device(ccdc), addr,
202 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
203}
204
205/*
206 * ccdc_lsc_setup_regs - Configures the lens shading compensation module
207 * @ccdc: Pointer to ISP CCDC device.
208 */
209static void ccdc_lsc_setup_regs(struct isp_ccdc_device *ccdc,
210 struct omap3isp_ccdc_lsc_config *cfg)
211{
212 struct isp_device *isp = to_isp_device(ccdc);
213 int reg;
214
215 isp_reg_writel(isp, cfg->offset, OMAP3_ISP_IOMEM_CCDC,
216 ISPCCDC_LSC_TABLE_OFFSET);
217
218 reg = 0;
219 reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
220 reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
221 reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
222 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
223
224 reg = 0;
225 reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
226 reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
227 reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
228 reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
229 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC,
230 ISPCCDC_LSC_INITIAL);
231}
232
233static int ccdc_lsc_wait_prefetch(struct isp_ccdc_device *ccdc)
234{
235 struct isp_device *isp = to_isp_device(ccdc);
236 unsigned int wait;
237
238 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
239 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
240
241 /* timeout 1 ms */
242 for (wait = 0; wait < 1000; wait++) {
243 if (isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS) &
244 IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ) {
245 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
246 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
247 return 0;
248 }
249
250 rmb();
251 udelay(1);
252 }
253
254 return -ETIMEDOUT;
255}
256
257/*
258 * __ccdc_lsc_enable - Enables/Disables the Lens Shading Compensation module.
259 * @ccdc: Pointer to ISP CCDC device.
260 * @enable: 0 Disables LSC, 1 Enables LSC.
261 */
262static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable)
263{
264 struct isp_device *isp = to_isp_device(ccdc);
265 const struct v4l2_mbus_framefmt *format =
266 __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
267 V4L2_SUBDEV_FORMAT_ACTIVE);
268
27ffaeb0
BB		 269 if ((format->code != MEDIA_BUS_FMT_SGRBG10_1X10) &&
270 (format->code != MEDIA_BUS_FMT_SRGGB10_1X10) &&
271 (format->code != MEDIA_BUS_FMT_SBGGR10_1X10) &&
272 (format->code != MEDIA_BUS_FMT_SGBRG10_1X10))
de1135d4
LP		 273 return -EINVAL;
274
275 if (enable)
276 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_LSC_READ);
277
278 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
279 ISPCCDC_LSC_ENABLE, enable ? ISPCCDC_LSC_ENABLE : 0);
280
281 if (enable) {
282 if (ccdc_lsc_wait_prefetch(ccdc) < 0) {
283 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC,
284 ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE);
285 ccdc->lsc.state = LSC_STATE_STOPPED;
25aeb418 286 dev_warn(to_device(ccdc), "LSC prefetch timeout\n");
de1135d4
LP		 287 return -ETIMEDOUT;
288 }
289 ccdc->lsc.state = LSC_STATE_RUNNING;
290 } else {
291 ccdc->lsc.state = LSC_STATE_STOPPING;
292 }
293
294 return 0;
295}
296
297static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
298{
299 struct isp_device *isp = to_isp_device(ccdc);
300
301 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG) &
302 ISPCCDC_LSC_BUSY;
303}
304
305/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
306 * @ccdc: Pointer to ISP CCDC device
307 * @req: New configuration request
308 *
309 * context: in_interrupt()
310 */
311static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
312 struct ispccdc_lsc_config_req *req)
313{
314 if (!req->enable)
315 return -EINVAL;
316
317 if (ccdc_lsc_validate_config(ccdc, &req->config) < 0) {
318 dev_dbg(to_device(ccdc), "Discard LSC configuration\n");
319 return -EINVAL;
320 }
321
322 if (ccdc_lsc_busy(ccdc))
323 return -EBUSY;
324
325 ccdc_lsc_setup_regs(ccdc, &req->config);
d33186d0 326 ccdc_lsc_program_table(ccdc, req->table.dma);
de1135d4
LP		 327 return 0;
328}
329
330/*
331 * ccdc_lsc_error_handler - Handle LSC prefetch error scenario.
332 * @ccdc: Pointer to ISP CCDC device.
333 *
334 * Disables LSC, and defers enablement to shadow registers update time.
335 */
336static void ccdc_lsc_error_handler(struct isp_ccdc_device *ccdc)
337{
338 struct isp_device *isp = to_isp_device(ccdc);
339 /*
340 * From OMAP3 TRM: When this event is pending, the module
341 * goes into transparent mode (output =input). Normal
342 * operation can be resumed at the start of the next frame
343 * after:
344 * 1) Clearing this event
345 * 2) Disabling the LSC module
346 * 3) Enabling it
347 */
348 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
349 ISPCCDC_LSC_ENABLE);
350 ccdc->lsc.state = LSC_STATE_STOPPED;
351}
352
353static void ccdc_lsc_free_request(struct isp_ccdc_device *ccdc,
354 struct ispccdc_lsc_config_req *req)
355{
356 struct isp_device *isp = to_isp_device(ccdc);
357
358 if (req == NULL)
359 return;
360
d33186d0
LP		 361 if (req->table.addr) {
362 sg_free_table(&req->table.sgt);
363 dma_free_coherent(isp->dev, req->config.size, req->table.addr,
364 req->table.dma);
365 }
366
de1135d4
LP		 367 kfree(req);
368}
369
370static void ccdc_lsc_free_queue(struct isp_ccdc_device *ccdc,
371 struct list_head *queue)
372{
373 struct ispccdc_lsc_config_req *req, *n;
374 unsigned long flags;
375
376 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
377 list_for_each_entry_safe(req, n, queue, list) {
378 list_del(&req->list);
379 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
380 ccdc_lsc_free_request(ccdc, req);
381 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
382 }
383 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
384}
385
386static void ccdc_lsc_free_table_work(struct work_struct *work)
387{
388 struct isp_ccdc_device *ccdc;
389 struct ispccdc_lsc *lsc;
390
391 lsc = container_of(work, struct ispccdc_lsc, table_work);
392 ccdc = container_of(lsc, struct isp_ccdc_device, lsc);
393
394 ccdc_lsc_free_queue(ccdc, &lsc->free_queue);
395}
396
397/*
398 * ccdc_lsc_config - Configure the LSC module from a userspace request
399 *
400 * Store the request LSC configuration in the LSC engine request pointer. The
401 * configuration will be applied to the hardware when the CCDC will be enabled,
402 * or at the next LSC interrupt if the CCDC is already running.
403 */
404static int ccdc_lsc_config(struct isp_ccdc_device *ccdc,
405 struct omap3isp_ccdc_update_config *config)
406{
407 struct isp_device *isp = to_isp_device(ccdc);
408 struct ispccdc_lsc_config_req *req;
409 unsigned long flags;
de1135d4
LP		 410 u16 update;
411 int ret;
412
413 update = config->update &
414 (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC);
415 if (!update)
416 return 0;
417
418 if (update != (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC)) {
419 dev_dbg(to_device(ccdc), "%s: Both LSC configuration and table "
420 "need to be supplied\n", __func__);
421 return -EINVAL;
422 }
423
424 req = kzalloc(sizeof(*req), GFP_KERNEL);
425 if (req == NULL)
426 return -ENOMEM;
427
428 if (config->flag & OMAP3ISP_CCDC_CONFIG_LSC) {
429 if (copy_from_user(&req->config, config->lsc_cfg,
430 sizeof(req->config))) {
431 ret = -EFAULT;
432 goto done;
433 }
434
435 req->enable = 1;
436
d33186d0
LP		 437 req->table.addr = dma_alloc_coherent(isp->dev, req->config.size,
438 &req->table.dma,
439 GFP_KERNEL);
440 if (req->table.addr == NULL) {
de1135d4
LP		 441 ret = -ENOMEM;
442 goto done;
443 }
444
d33186d0
LP		 445 ret = dma_get_sgtable(isp->dev, &req->table.sgt,
446 req->table.addr, req->table.dma,
447 req->config.size);
448 if (ret < 0)
de1135d4 449 goto done;
de1135d4 450
d33186d0
LP		 451 dma_sync_sg_for_cpu(isp->dev, req->table.sgt.sgl,
452 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4 453
d33186d0
LP		 454 if (copy_from_user(req->table.addr, config->lsc,
455 req->config.size)) {
de1135d4
LP		 456 ret = -EFAULT;
457 goto done;
458 }
459
d33186d0
LP		 460 dma_sync_sg_for_device(isp->dev, req->table.sgt.sgl,
461 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4
LP		 462 }
463
464 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
465 if (ccdc->lsc.request) {
466 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
467 schedule_work(&ccdc->lsc.table_work);
468 }
469 ccdc->lsc.request = req;
470 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
471
472 ret = 0;
473
474done:
475 if (ret < 0)
476 ccdc_lsc_free_request(ccdc, req);
477
478 return ret;
479}
480
481static inline int ccdc_lsc_is_configured(struct isp_ccdc_device *ccdc)
482{
483 unsigned long flags;
1c748174 484 int ret;
de1135d4
LP		 485
486 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1c748174 487 ret = ccdc->lsc.active != NULL;
de1135d4 488 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1c748174
LP		 489
490 return ret;
de1135d4
LP		 491}
492
493static int ccdc_lsc_enable(struct isp_ccdc_device *ccdc)
494{
495 struct ispccdc_lsc *lsc = &ccdc->lsc;
496
497 if (lsc->state != LSC_STATE_STOPPED)
498 return -EINVAL;
499
500 if (lsc->active) {
501 list_add_tail(&lsc->active->list, &lsc->free_queue);
502 lsc->active = NULL;
503 }
504
505 if (__ccdc_lsc_configure(ccdc, lsc->request) < 0) {
506 omap3isp_sbl_disable(to_isp_device(ccdc),
507 OMAP3_ISP_SBL_CCDC_LSC_READ);
508 list_add_tail(&lsc->request->list, &lsc->free_queue);
509 lsc->request = NULL;
510 goto done;
511 }
512
513 lsc->active = lsc->request;
514 lsc->request = NULL;
515 __ccdc_lsc_enable(ccdc, 1);
516
517done:
518 if (!list_empty(&lsc->free_queue))
519 schedule_work(&lsc->table_work);
520
521 return 0;
522}
523
524/* -----------------------------------------------------------------------------
525 * Parameters configuration
526 */
527
528/*
529 * ccdc_configure_clamp - Configure optical-black or digital clamping
530 * @ccdc: Pointer to ISP CCDC device.
531 *
532 * The CCDC performs either optical-black or digital clamp. Configure and enable
533 * the selected clamp method.
534 */
535static void ccdc_configure_clamp(struct isp_ccdc_device *ccdc)
536{
537 struct isp_device *isp = to_isp_device(ccdc);
538 u32 clamp;
539
540 if (ccdc->obclamp) {
541 clamp = ccdc->clamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
542 clamp |= ccdc->clamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
543 clamp |= ccdc->clamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
544 clamp |= ccdc->clamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
545 isp_reg_writel(isp, clamp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP);
546 } else {
547 isp_reg_writel(isp, ccdc->clamp.dcsubval,
548 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB);
549 }
550
551 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
552 ISPCCDC_CLAMP_CLAMPEN,
553 ccdc->obclamp ? ISPCCDC_CLAMP_CLAMPEN : 0);
554}
555
556/*
557 * ccdc_configure_fpc - Configure Faulty Pixel Correction
558 * @ccdc: Pointer to ISP CCDC device.
559 */
560static void ccdc_configure_fpc(struct isp_ccdc_device *ccdc)
561{
562 struct isp_device *isp = to_isp_device(ccdc);
563
564 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, ISPCCDC_FPC_FPCEN);
565
566 if (!ccdc->fpc_en)
567 return;
568
c60e153d 569 isp_reg_writel(isp, ccdc->fpc.dma, OMAP3_ISP_IOMEM_CCDC,
de1135d4
LP		 570 ISPCCDC_FPC_ADDR);
571 /* The FPNUM field must be set before enabling FPC. */
572 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
573 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
574 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT) |
575 ISPCCDC_FPC_FPCEN, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
576}
577
578/*
579 * ccdc_configure_black_comp - Configure Black Level Compensation.
580 * @ccdc: Pointer to ISP CCDC device.
581 */
582static void ccdc_configure_black_comp(struct isp_ccdc_device *ccdc)
583{
584 struct isp_device *isp = to_isp_device(ccdc);
585 u32 blcomp;
586
587 blcomp = ccdc->blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
588 blcomp |= ccdc->blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
589 blcomp |= ccdc->blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
590 blcomp |= ccdc->blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
591
592 isp_reg_writel(isp, blcomp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
593}
594
595/*
596 * ccdc_configure_lpf - Configure Low-Pass Filter (LPF).
597 * @ccdc: Pointer to ISP CCDC device.
598 */
599static void ccdc_configure_lpf(struct isp_ccdc_device *ccdc)
600{
601 struct isp_device *isp = to_isp_device(ccdc);
602
603 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
604 ISPCCDC_SYN_MODE_LPF,
605 ccdc->lpf ? ISPCCDC_SYN_MODE_LPF : 0);
606}
607
608/*
609 * ccdc_configure_alaw - Configure A-law compression.
610 * @ccdc: Pointer to ISP CCDC device.
611 */
612static void ccdc_configure_alaw(struct isp_ccdc_device *ccdc)
613{
614 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 615 const struct isp_format_info *info;
de1135d4
LP		 616 u32 alaw = 0;
617
73ea57eb
LP		 618 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
619
620 switch (info->width) {
de1135d4
LP		 621 case 8:
622 return;
623
624 case 10:
625 alaw = ISPCCDC_ALAW_GWDI_9_0;
626 break;
627 case 11:
628 alaw = ISPCCDC_ALAW_GWDI_10_1;
629 break;
630 case 12:
631 alaw = ISPCCDC_ALAW_GWDI_11_2;
632 break;
633 case 13:
634 alaw = ISPCCDC_ALAW_GWDI_12_3;
635 break;
636 }
637
638 if (ccdc->alaw)
639 alaw |= ISPCCDC_ALAW_CCDTBL;
640
641 isp_reg_writel(isp, alaw, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
642}
643
644/*
645 * ccdc_config_imgattr - Configure sensor image specific attributes.
646 * @ccdc: Pointer to ISP CCDC device.
647 * @colptn: Color pattern of the sensor.
648 */
649static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn)
650{
651 struct isp_device *isp = to_isp_device(ccdc);
652
653 isp_reg_writel(isp, colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
654}
655
656/*
657 * ccdc_config - Set CCDC configuration from userspace
658 * @ccdc: Pointer to ISP CCDC device.
872aba51 659 * @ccdc_struct: Structure containing CCDC configuration sent from userspace.
de1135d4
LP		 660 *
661 * Returns 0 if successful, -EINVAL if the pointer to the configuration
662 * structure is null, or the copy_from_user function fails to copy user space
663 * memory to kernel space memory.
664 */
665static int ccdc_config(struct isp_ccdc_device *ccdc,
666 struct omap3isp_ccdc_update_config *ccdc_struct)
667{
668 struct isp_device *isp = to_isp_device(ccdc);
669 unsigned long flags;
670
671 spin_lock_irqsave(&ccdc->lock, flags);
672 ccdc->shadow_update = 1;
673 spin_unlock_irqrestore(&ccdc->lock, flags);
674
675 if (OMAP3ISP_CCDC_ALAW & ccdc_struct->update) {
676 ccdc->alaw = !!(OMAP3ISP_CCDC_ALAW & ccdc_struct->flag);
677 ccdc->update |= OMAP3ISP_CCDC_ALAW;
678 }
679
680 if (OMAP3ISP_CCDC_LPF & ccdc_struct->update) {
681 ccdc->lpf = !!(OMAP3ISP_CCDC_LPF & ccdc_struct->flag);
682 ccdc->update |= OMAP3ISP_CCDC_LPF;
683 }
684
685 if (OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->update) {
686 if (copy_from_user(&ccdc->clamp, ccdc_struct->bclamp,
687 sizeof(ccdc->clamp))) {
688 ccdc->shadow_update = 0;
689 return -EFAULT;
690 }
691
692 ccdc->obclamp = !!(OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->flag);
693 ccdc->update |= OMAP3ISP_CCDC_BLCLAMP;
694 }
695
696 if (OMAP3ISP_CCDC_BCOMP & ccdc_struct->update) {
697 if (copy_from_user(&ccdc->blcomp, ccdc_struct->blcomp,
698 sizeof(ccdc->blcomp))) {
699 ccdc->shadow_update = 0;
700 return -EFAULT;
701 }
702
703 ccdc->update |= OMAP3ISP_CCDC_BCOMP;
704 }
705
706 ccdc->shadow_update = 0;
707
708 if (OMAP3ISP_CCDC_FPC & ccdc_struct->update) {
c60e153d
LP		 709 struct omap3isp_ccdc_fpc fpc;
710 struct ispccdc_fpc fpc_old = { .addr = NULL, };
711 struct ispccdc_fpc fpc_new;
de1135d4
LP		 712 u32 size;
713
714 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
715 return -EBUSY;
716
717 ccdc->fpc_en = !!(OMAP3ISP_CCDC_FPC & ccdc_struct->flag);
718
719 if (ccdc->fpc_en) {
c60e153d 720 if (copy_from_user(&fpc, ccdc_struct->fpc, sizeof(fpc)))
de1135d4
LP		 721 return -EFAULT;
722
c60e153d
LP		 723 size = fpc.fpnum * 4;
724
de1135d4 725 /*
c60e153d
LP		 726 * The table address must be 64-bytes aligned, which is
727 * guaranteed by dma_alloc_coherent().
de1135d4 728 */
c60e153d
LP		 729 fpc_new.fpnum = fpc.fpnum;
730 fpc_new.addr = dma_alloc_coherent(isp->dev, size,
731 &fpc_new.dma,
732 GFP_KERNEL);
733 if (fpc_new.addr == NULL)
de1135d4
LP		 734 return -ENOMEM;
735
c60e153d
LP		 736 if (copy_from_user(fpc_new.addr,
737 (__force void __user *)fpc.fpcaddr,
738 size)) {
739 dma_free_coherent(isp->dev, size, fpc_new.addr,
740 fpc_new.dma);
de1135d4
LP		 741 return -EFAULT;
742 }
743
c60e153d
LP		 744 fpc_old = ccdc->fpc;
745 ccdc->fpc = fpc_new;
de1135d4
LP		 746 }
747
748 ccdc_configure_fpc(ccdc);
c60e153d
LP		 749
750 if (fpc_old.addr != NULL)
751 dma_free_coherent(isp->dev, fpc_old.fpnum * 4,
752 fpc_old.addr, fpc_old.dma);
de1135d4
LP		 753 }
754
755 return ccdc_lsc_config(ccdc, ccdc_struct);
756}
757
758static void ccdc_apply_controls(struct isp_ccdc_device *ccdc)
759{
760 if (ccdc->update & OMAP3ISP_CCDC_ALAW) {
761 ccdc_configure_alaw(ccdc);
762 ccdc->update &= ~OMAP3ISP_CCDC_ALAW;
763 }
764
765 if (ccdc->update & OMAP3ISP_CCDC_LPF) {
766 ccdc_configure_lpf(ccdc);
767 ccdc->update &= ~OMAP3ISP_CCDC_LPF;
768 }
769
770 if (ccdc->update & OMAP3ISP_CCDC_BLCLAMP) {
771 ccdc_configure_clamp(ccdc);
772 ccdc->update &= ~OMAP3ISP_CCDC_BLCLAMP;
773 }
774
775 if (ccdc->update & OMAP3ISP_CCDC_BCOMP) {
776 ccdc_configure_black_comp(ccdc);
777 ccdc->update &= ~OMAP3ISP_CCDC_BCOMP;
778 }
779}
780
781/*
782 * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers
872aba51 783 * @isp: Pointer to ISP device
de1135d4
LP		 784 */
785void omap3isp_ccdc_restore_context(struct isp_device *isp)
786{
787 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
788
789 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
790
791 ccdc->update = OMAP3ISP_CCDC_ALAW | OMAP3ISP_CCDC_LPF
792 | OMAP3ISP_CCDC_BLCLAMP | OMAP3ISP_CCDC_BCOMP;
793 ccdc_apply_controls(ccdc);
794 ccdc_configure_fpc(ccdc);
795}
796
797/* -----------------------------------------------------------------------------
798 * Format- and pipeline-related configuration helpers
799 */
800
801/*
802 * ccdc_config_vp - Configure the Video Port.
803 * @ccdc: Pointer to ISP CCDC device.
804 */
805static void ccdc_config_vp(struct isp_ccdc_device *ccdc)
806{
807 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
808 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 809 const struct isp_format_info *info;
aec2de0e 810 struct v4l2_mbus_framefmt *format;
de1135d4
LP		 811 unsigned long l3_ick = pipe->l3_ick;
812 unsigned int max_div = isp->revision == ISP_REVISION_15_0 ? 64 : 8;
813 unsigned int div = 0;
aec2de0e
LP		 814 u32 fmtcfg = ISPCCDC_FMTCFG_VPEN;
815
816 format = &ccdc->formats[CCDC_PAD_SOURCE_VP];
817
818 if (!format->code) {
819 /* Disable the video port when the input format isn't supported.
820 * This is indicated by a pixel code set to 0.
821 */
822 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
823 return;
824 }
825
826 isp_reg_writel(isp, (0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
827 (format->width << ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
828 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ);
829 isp_reg_writel(isp, (0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
830 ((format->height + 1) << ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
831 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT);
de1135d4 832
aec2de0e
LP		 833 isp_reg_writel(isp, (format->width << ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
834 (format->height << ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
835 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
de1135d4 836
73ea57eb
LP		 837 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
838
839 switch (info->width) {
de1135d4
LP		 840 case 8:
841 case 10:
aec2de0e 842 fmtcfg |= ISPCCDC_FMTCFG_VPIN_9_0;
de1135d4
LP		 843 break;
844 case 11:
aec2de0e 845 fmtcfg |= ISPCCDC_FMTCFG_VPIN_10_1;
de1135d4
LP		 846 break;
847 case 12:
aec2de0e 848 fmtcfg |= ISPCCDC_FMTCFG_VPIN_11_2;
de1135d4
LP		 849 break;
850 case 13:
aec2de0e 851 fmtcfg |= ISPCCDC_FMTCFG_VPIN_12_3;
de1135d4 852 break;
13eaaa7f 853 }
de1135d4
LP		 854
855 if (pipe->input)
856 div = DIV_ROUND_UP(l3_ick, pipe->max_rate);
c6c01f97
SA		 857 else if (pipe->external_rate)
858 div = l3_ick / pipe->external_rate;
de1135d4
LP		 859
860 div = clamp(div, 2U, max_div);
aec2de0e 861 fmtcfg |= (div - 2) << ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT;
de1135d4 862
aec2de0e 863 isp_reg_writel(isp, fmtcfg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
de1135d4
LP		 864}
865
866/*
867 * ccdc_config_outlineoffset - Configure memory saving output line offset
868 * @ccdc: Pointer to ISP CCDC device.
bcb4e0ef
LP		 869 * @bpl: Number of bytes per line when stored in memory.
870 * @field: Field order when storing interlaced formats in memory.
de1135d4 871 *
bcb4e0ef
LP		 872 * Configure the offsets for the line output control:
873 *
874 * - The horizontal line offset is defined as the number of bytes between the
875 * start of two consecutive lines in memory. Set it to the given bytes per
876 * line value.
877 *
878 * - The field offset value is defined as the number of lines to offset the
879 * start of the field identified by FID = 1. Set it to one.
880 *
881 * - The line offset values are defined as the number of lines (as defined by
882 * the horizontal line offset) between the start of two consecutive lines for
883 * all combinations of odd/even lines in odd/even fields. When interleaving
884 * fields set them all to two lines, and to one line otherwise.
de1135d4
LP		 885 */
886static void ccdc_config_outlineoffset(struct isp_ccdc_device *ccdc,
bcb4e0ef
LP		 887 unsigned int bpl,
888 enum v4l2_field field)
de1135d4
LP		 889{
890 struct isp_device *isp = to_isp_device(ccdc);
bcb4e0ef 891 u32 sdofst = 0;
de1135d4 892
bcb4e0ef
LP		 893 isp_reg_writel(isp, bpl & 0xffff, OMAP3_ISP_IOMEM_CCDC,
894 ISPCCDC_HSIZE_OFF);
de1135d4 895
bcb4e0ef
LP		 896 switch (field) {
897 case V4L2_FIELD_INTERLACED_TB:
898 case V4L2_FIELD_INTERLACED_BT:
899 /* When interleaving fields in memory offset field one by one
900 * line and set the line offset to two lines.
901 */
902 sdofst |= (1 << ISPCCDC_SDOFST_LOFST0_SHIFT)
903 | (1 << ISPCCDC_SDOFST_LOFST1_SHIFT)
904 | (1 << ISPCCDC_SDOFST_LOFST2_SHIFT)
905 | (1 << ISPCCDC_SDOFST_LOFST3_SHIFT);
de1135d4 906 break;
bcb4e0ef 907
de1135d4 908 default:
bcb4e0ef 909 /* In all other cases set the line offsets to one line. */
de1135d4
LP		 910 break;
911 }
bcb4e0ef
LP		 912
913 isp_reg_writel(isp, sdofst, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST);
de1135d4
LP		 914}
915
916/*
917 * ccdc_set_outaddr - Set memory address to save output image
918 * @ccdc: Pointer to ISP CCDC device.
919 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
920 *
921 * Sets the memory address where the output will be saved.
922 */
923static void ccdc_set_outaddr(struct isp_ccdc_device *ccdc, u32 addr)
924{
925 struct isp_device *isp = to_isp_device(ccdc);
926
927 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
928}
929
930/*
931 * omap3isp_ccdc_max_rate - Calculate maximum input data rate based on the input
932 * @ccdc: Pointer to ISP CCDC device.
933 * @max_rate: Maximum calculated data rate.
934 *
935 * Returns in *max_rate less value between calculated and passed
936 */
937void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
938 unsigned int *max_rate)
939{
940 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
941 unsigned int rate;
942
943 if (pipe == NULL)
944 return;
945
946 /*
947 * TRM says that for parallel sensors the maximum data rate
948 * should be 90% form L3/2 clock, otherwise just L3/2.
949 */
950 if (ccdc->input == CCDC_INPUT_PARALLEL)
951 rate = pipe->l3_ick / 2 * 9 / 10;
952 else
953 rate = pipe->l3_ick / 2;
954
955 *max_rate = min(*max_rate, rate);
956}
957
958/*
959 * ccdc_config_sync_if - Set CCDC sync interface configuration
960 * @ccdc: Pointer to ISP CCDC device.
73ea57eb
LP		 961 * @pdata: Parallel interface platform data (may be NULL)
962 * @data_size: Data size
de1135d4
LP		 963 */
964static void ccdc_config_sync_if(struct isp_ccdc_device *ccdc,
73ea57eb
LP		 965 struct isp_parallel_platform_data *pdata,
966 unsigned int data_size)
de1135d4
LP		 967{
968 struct isp_device *isp = to_isp_device(ccdc);
c51364ca 969 const struct v4l2_mbus_framefmt *format;
cf7a3d91 970 u32 syn_mode = ISPCCDC_SYN_MODE_VDHDEN;
de1135d4 971
c51364ca
LP		 972 format = &ccdc->formats[CCDC_PAD_SINK];
973
27ffaeb0
BB		 974 if (format->code == MEDIA_BUS_FMT_YUYV8_2X8 ||
975 format->code == MEDIA_BUS_FMT_UYVY8_2X8) {
9de7af4d
LP		 976 /* According to the OMAP3 TRM the input mode only affects SYNC
977 * mode, enabling BT.656 mode should take precedence. However,
978 * in practice setting the input mode to YCbCr data on 8 bits
979 * seems to be required in BT.656 mode. In SYNC mode set it to
980 * YCbCr on 16 bits as the bridge is enabled in that case.
c51364ca 981 */
9de7af4d
LP		 982 if (ccdc->bt656)
983 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
984 else
985 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
c51364ca
LP		 986 }
987
73ea57eb 988 switch (data_size) {
de1135d4
LP		 989 case 8:
990 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
991 break;
992 case 10:
993 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
994 break;
995 case 11:
996 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
997 break;
998 case 12:
999 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
1000 break;
13eaaa7f 1001 }
de1135d4 1002
73ea57eb 1003 if (pdata && pdata->data_pol)
de1135d4 1004 syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
de1135d4 1005
73ea57eb 1006 if (pdata && pdata->hs_pol)
de1135d4 1007 syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
de1135d4 1008
9de7af4d
LP		 1009 /* The polarity of the vertical sync signal output by the BT.656
1010 * decoder is not documented and seems to be active low.
1011 */
1012 if ((pdata && pdata->vs_pol) || ccdc->bt656)
de1135d4 1013 syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
de1135d4 1014
9a36d8ed
LP		 1015 if (pdata && pdata->fld_pol)
1016 syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
1017
de1135d4 1018 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
c51364ca
LP		 1019
1020 /* The CCDC_CFG.Y8POS bit is used in YCbCr8 input mode only. The
1021 * hardware seems to ignore it in all other input modes.
1022 */
27ffaeb0 1023 if (format->code == MEDIA_BUS_FMT_UYVY8_2X8)
c51364ca
LP		 1024 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1025 ISPCCDC_CFG_Y8POS);
1026 else
1027 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1028 ISPCCDC_CFG_Y8POS);
1029
9de7af4d
LP		 1030 /* Enable or disable BT.656 mode, including error correction for the
1031 * synchronization codes.
1032 */
1033 if (ccdc->bt656)
1034 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1035 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1036 else
1037 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1038 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1039
de1135d4
LP		 1040}
1041
1042/* CCDC formats descriptions */
1043static const u32 ccdc_sgrbg_pattern =
1044 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1045 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1046 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1047 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1048 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1049 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1050 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1051 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1052 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1053 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1054 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1055 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1056 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1057 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1058 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1059 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1060
1061static const u32 ccdc_srggb_pattern =
1062 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1063 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1064 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1065 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1066 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1067 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1068 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1069 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1070 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1071 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1072 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1073 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1074 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1075 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1076 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1077 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1078
1079static const u32 ccdc_sbggr_pattern =
1080 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1081 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1082 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1083 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1084 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1085 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1086 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1087 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1088 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1089 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1090 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1091 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1092 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1093 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1094 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1095 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1096
1097static const u32 ccdc_sgbrg_pattern =
1098 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1099 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1100 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1101 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1102 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1103 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1104 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1105 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1106 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1107 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1108 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1109 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1110 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1111 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1112 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1113 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1114
1115static void ccdc_configure(struct isp_ccdc_device *ccdc)
1116{
1117 struct isp_device *isp = to_isp_device(ccdc);
1118 struct isp_parallel_platform_data *pdata = NULL;
1119 struct v4l2_subdev *sensor;
1120 struct v4l2_mbus_framefmt *format;
a64909b8 1121 const struct v4l2_rect *crop;
c09af044
MJ		 1122 const struct isp_format_info *fmt_info;
1123 struct v4l2_subdev_format fmt_src;
1124 unsigned int depth_out;
1125 unsigned int depth_in = 0;
de1135d4
LP		 1126 struct media_pad *pad;
1127 unsigned long flags;
c51364ca 1128 unsigned int bridge;
c09af044 1129 unsigned int shift;
9de7af4d
LP		 1130 unsigned int nph;
1131 unsigned int sph;
de1135d4
LP		 1132 u32 syn_mode;
1133 u32 ccdc_pattern;
1134
9de7af4d 1135 ccdc->bt656 = false;
93d7badf 1136 ccdc->fields = 0;
9de7af4d 1137
1bddf1b3 1138 pad = media_entity_remote_pad(&ccdc->pads[CCDC_PAD_SINK]);
c09af044 1139 sensor = media_entity_to_v4l2_subdev(pad->entity);
9de7af4d
LP		 1140 if (ccdc->input == CCDC_INPUT_PARALLEL) {
1141 struct v4l2_mbus_config cfg;
1142 int ret;
1143
1144 ret = v4l2_subdev_call(sensor, video, g_mbus_config, &cfg);
1145 if (!ret)
1146 ccdc->bt656 = cfg.type == V4L2_MBUS_BT656;
1147
de1135d4
LP		 1148 pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
1149 ->bus.parallel;
9de7af4d 1150 }
c09af044 1151
2e8f0172
LP		 1152 /* CCDC_PAD_SINK */
1153 format = &ccdc->formats[CCDC_PAD_SINK];
1154
c51364ca 1155 /* Compute the lane shifter shift value and enable the bridge when the
9de7af4d 1156 * input format is a non-BT.656 YUV variant.
c51364ca 1157 */
c09af044
MJ		 1158 fmt_src.pad = pad->index;
1159 fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1160 if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
1161 fmt_info = omap3isp_video_format_info(fmt_src.format.code);
1697e49a 1162 depth_in = fmt_info->width;
de1135d4
LP		 1163 }
1164
2e8f0172 1165 fmt_info = omap3isp_video_format_info(format->code);
1697e49a 1166 depth_out = fmt_info->width;
c09af044 1167 shift = depth_in - depth_out;
de1135d4 1168
9de7af4d
LP		 1169 if (ccdc->bt656)
1170 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
27ffaeb0 1171 else if (fmt_info->code == MEDIA_BUS_FMT_YUYV8_2X8)
c51364ca 1172 bridge = ISPCTRL_PAR_BRIDGE_LENDIAN;
27ffaeb0 1173 else if (fmt_info->code == MEDIA_BUS_FMT_UYVY8_2X8)
c51364ca
LP		 1174 bridge = ISPCTRL_PAR_BRIDGE_BENDIAN;
1175 else
1176 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
de1135d4 1177
c51364ca
LP		 1178 omap3isp_configure_bridge(isp, ccdc->input, pdata, shift, bridge);
1179
9a36d8ed 1180 /* Configure the sync interface. */
c51364ca 1181 ccdc_config_sync_if(ccdc, pdata, depth_out);
de1135d4
LP		 1182
1183 syn_mode = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1184
1185 /* Use the raw, unprocessed data when writing to memory. The H3A and
1186 * histogram modules are still fed with lens shading corrected data.
1187 */
1188 syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
1189
1190 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1191 syn_mode |= ISPCCDC_SYN_MODE_WEN;
1192 else
1193 syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
1194
1195 if (ccdc->output & CCDC_OUTPUT_RESIZER)
1196 syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
1197 else
1198 syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
1199
de1135d4
LP		 1200 /* Mosaic filter */
1201 switch (format->code) {
27ffaeb0
BB		 1202 case MEDIA_BUS_FMT_SRGGB10_1X10:
1203 case MEDIA_BUS_FMT_SRGGB12_1X12:
de1135d4
LP		 1204 ccdc_pattern = ccdc_srggb_pattern;
1205 break;
27ffaeb0
BB		 1206 case MEDIA_BUS_FMT_SBGGR10_1X10:
1207 case MEDIA_BUS_FMT_SBGGR12_1X12:
de1135d4
LP		 1208 ccdc_pattern = ccdc_sbggr_pattern;
1209 break;
27ffaeb0
BB		 1210 case MEDIA_BUS_FMT_SGBRG10_1X10:
1211 case MEDIA_BUS_FMT_SGBRG12_1X12:
de1135d4
LP		 1212 ccdc_pattern = ccdc_sgbrg_pattern;
1213 break;
1214 default:
1215 /* Use GRBG */
1216 ccdc_pattern = ccdc_sgrbg_pattern;
1217 break;
1218 }
1219 ccdc_config_imgattr(ccdc, ccdc_pattern);
1220
1221 /* Generate VD0 on the last line of the image and VD1 on the
1222 * 2/3 height line.
1223 */
1224 isp_reg_writel(isp, ((format->height - 2) << ISPCCDC_VDINT_0_SHIFT) |
1225 ((format->height * 2 / 3) << ISPCCDC_VDINT_1_SHIFT),
1226 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT);
1227
1228 /* CCDC_PAD_SOURCE_OF */
c51364ca 1229 format = &ccdc->formats[CCDC_PAD_SOURCE_OF];
a64909b8 1230 crop = &ccdc->crop;
de1135d4 1231
9de7af4d
LP		 1232 /* The horizontal coordinates are expressed in pixel clock cycles. We
1233 * need two cycles per pixel in BT.656 mode, and one cycle per pixel in
1234 * SYNC mode regardless of the format as the bridge is enabled for YUV
1235 * formats in that case.
1236 */
1237 if (ccdc->bt656) {
1238 sph = crop->left * 2;
1239 nph = crop->width * 2 - 1;
1240 } else {
1241 sph = crop->left;
1242 nph = crop->width - 1;
1243 }
1244
1245 isp_reg_writel(isp, (sph << ISPCCDC_HORZ_INFO_SPH_SHIFT) |
1246 (nph << ISPCCDC_HORZ_INFO_NPH_SHIFT),
de1135d4 1247 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO);
9de7af4d
LP		 1248 isp_reg_writel(isp, (crop->top << ISPCCDC_VERT_START_SLV0_SHIFT) |
1249 (crop->top << ISPCCDC_VERT_START_SLV1_SHIFT),
de1135d4 1250 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START);
a64909b8 1251 isp_reg_writel(isp, (crop->height - 1)
de1135d4
LP		 1252 << ISPCCDC_VERT_LINES_NLV_SHIFT,
1253 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES);
1254
bcb4e0ef
LP		 1255 ccdc_config_outlineoffset(ccdc, ccdc->video_out.bpl_value,
1256 format->field);
1257
1258 /* When interleaving fields enable processing of the field input signal.
1259 * This will cause the line output control module to apply the field
1260 * offset to field 1.
1261 */
1262 if (ccdc->formats[CCDC_PAD_SINK].field == V4L2_FIELD_ALTERNATE &&
1263 (format->field == V4L2_FIELD_INTERLACED_TB ||
1264 format->field == V4L2_FIELD_INTERLACED_BT))
1265 syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
de1135d4 1266
c51364ca
LP		 1267 /* The CCDC outputs data in UYVY order by default. Swap bytes to get
1268 * YUYV.
1269 */
27ffaeb0 1270 if (format->code == MEDIA_BUS_FMT_YUYV8_1X16)
c51364ca
LP		 1271 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1272 ISPCCDC_CFG_BSWD);
1273 else
1274 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1275 ISPCCDC_CFG_BSWD);
1276
9de7af4d
LP		 1277 /* Use PACK8 mode for 1byte per pixel formats. Check for BT.656 mode
1278 * explicitly as the driver reports 1X16 instead of 2X8 at the OF pad
1279 * for simplicity.
1280 */
1281 if (omap3isp_video_format_info(format->code)->width <= 8 || ccdc->bt656)
c51364ca
LP		 1282 syn_mode |= ISPCCDC_SYN_MODE_PACK8;
1283 else
1284 syn_mode &= ~ISPCCDC_SYN_MODE_PACK8;
1285
1286 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1287
de1135d4 1288 /* CCDC_PAD_SOURCE_VP */
aec2de0e 1289 ccdc_config_vp(ccdc);
de1135d4 1290
c51364ca 1291 /* Lens shading correction. */
de1135d4
LP		 1292 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1293 if (ccdc->lsc.request == NULL)
1294 goto unlock;
1295
1296 WARN_ON(ccdc->lsc.active);
1297
1298 /* Get last good LSC configuration. If it is not supported for
1299 * the current active resolution discard it.
1300 */
1301 if (ccdc->lsc.active == NULL &&
1302 __ccdc_lsc_configure(ccdc, ccdc->lsc.request) == 0) {
1303 ccdc->lsc.active = ccdc->lsc.request;
1304 } else {
1305 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
1306 schedule_work(&ccdc->lsc.table_work);
1307 }
1308
1309 ccdc->lsc.request = NULL;
1310
1311unlock:
1312 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1313
1314 ccdc_apply_controls(ccdc);
1315}
1316
1317static void __ccdc_enable(struct isp_ccdc_device *ccdc, int enable)
1318{
1319 struct isp_device *isp = to_isp_device(ccdc);
1320
1321 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR,
1322 ISPCCDC_PCR_EN, enable ? ISPCCDC_PCR_EN : 0);
0b3fcd57
LP		 1323
1324 ccdc->running = enable;
de1135d4
LP		 1325}
1326
1327static int ccdc_disable(struct isp_ccdc_device *ccdc)
1328{
1329 unsigned long flags;
1330 int ret = 0;
1331
1332 spin_lock_irqsave(&ccdc->lock, flags);
1333 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1334 ccdc->stopping = CCDC_STOP_REQUEST;
0b3fcd57
LP		 1335 if (!ccdc->running)
1336 ccdc->stopping = CCDC_STOP_FINISHED;
de1135d4
LP		 1337 spin_unlock_irqrestore(&ccdc->lock, flags);
1338
1339 ret = wait_event_timeout(ccdc->wait,
1340 ccdc->stopping == CCDC_STOP_FINISHED,
1341 msecs_to_jiffies(2000));
1342 if (ret == 0) {
1343 ret = -ETIMEDOUT;
1344 dev_warn(to_device(ccdc), "CCDC stop timeout!\n");
1345 }
1346
1347 omap3isp_sbl_disable(to_isp_device(ccdc), OMAP3_ISP_SBL_CCDC_LSC_READ);
1348
1349 mutex_lock(&ccdc->ioctl_lock);
1350 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
1351 ccdc->lsc.request = ccdc->lsc.active;
1352 ccdc->lsc.active = NULL;
1353 cancel_work_sync(&ccdc->lsc.table_work);
1354 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
1355 mutex_unlock(&ccdc->ioctl_lock);
1356
1357 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
1358
1359 return ret > 0 ? 0 : ret;
1360}
1361
1362static void ccdc_enable(struct isp_ccdc_device *ccdc)
1363{
1364 if (ccdc_lsc_is_configured(ccdc))
1365 __ccdc_lsc_enable(ccdc, 1);
1366 __ccdc_enable(ccdc, 1);
1367}
1368
1369/* -----------------------------------------------------------------------------
1370 * Interrupt handling
1371 */
1372
1373/*
1374 * ccdc_sbl_busy - Poll idle state of CCDC and related SBL memory write bits
1375 * @ccdc: Pointer to ISP CCDC device.
1376 *
1377 * Returns zero if the CCDC is idle and the image has been written to
1378 * memory, too.
1379 */
1380static int ccdc_sbl_busy(struct isp_ccdc_device *ccdc)
1381{
1382 struct isp_device *isp = to_isp_device(ccdc);
1383
1384 return omap3isp_ccdc_busy(ccdc)
1385 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
1386 ISPSBL_CCDC_WR_0_DATA_READY)
1387 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
1388 ISPSBL_CCDC_WR_0_DATA_READY)
1389 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
1390 ISPSBL_CCDC_WR_0_DATA_READY)
1391 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
1392 ISPSBL_CCDC_WR_0_DATA_READY);
1393}
1394
1395/*
1396 * ccdc_sbl_wait_idle - Wait until the CCDC and related SBL are idle
1397 * @ccdc: Pointer to ISP CCDC device.
1398 * @max_wait: Max retry count in us for wait for idle/busy transition.
1399 */
1400static int ccdc_sbl_wait_idle(struct isp_ccdc_device *ccdc,
1401 unsigned int max_wait)
1402{
1403 unsigned int wait = 0;
1404
1405 if (max_wait == 0)
1406 max_wait = 10000; /* 10 ms */
1407
1408 for (wait = 0; wait <= max_wait; wait++) {
1409 if (!ccdc_sbl_busy(ccdc))
1410 return 0;
1411
1412 rmb();
1413 udelay(1);
1414 }
1415
1416 return -EBUSY;
1417}
1418
8815392a 1419/* ccdc_handle_stopping - Handle CCDC and/or LSC stopping sequence
de1135d4
LP		 1420 * @ccdc: Pointer to ISP CCDC device.
1421 * @event: Pointing which event trigger handler
1422 *
2d4e9d1d 1423 * Return 1 when the event and stopping request combination is satisfied,
de1135d4
LP		 1424 * zero otherwise.
1425 */
8815392a 1426static int ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
de1135d4
LP		 1427{
1428 int rval = 0;
1429
1430 switch ((ccdc->stopping & 3) | event) {
1431 case CCDC_STOP_REQUEST | CCDC_EVENT_VD1:
1432 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1433 __ccdc_lsc_enable(ccdc, 0);
1434 __ccdc_enable(ccdc, 0);
1435 ccdc->stopping = CCDC_STOP_EXECUTED;
1436 return 1;
1437
1438 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD0:
1439 ccdc->stopping |= CCDC_STOP_CCDC_FINISHED;
1440 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1441 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1442 rval = 1;
1443 break;
1444
1445 case CCDC_STOP_EXECUTED | CCDC_EVENT_LSC_DONE:
1446 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1447 rval = 1;
1448 break;
1449
1450 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD1:
1451 return 1;
1452 }
1453
1454 if (ccdc->stopping == CCDC_STOP_FINISHED) {
1455 wake_up(&ccdc->wait);
1456 rval = 1;
1457 }
1458
1459 return rval;
1460}
1461
1462static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
1463{
bd0f2e6d 1464 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
63ae37ea 1465 struct video_device *vdev = ccdc->subdev.devnode;
de1135d4
LP		 1466 struct v4l2_event event;
1467
b43883d6
LP		 1468 /* Frame number propagation */
1469 atomic_inc(&pipe->frame_number);
1470
de1135d4 1471 memset(&event, 0, sizeof(event));
69d232ae
SA		 1472 event.type = V4L2_EVENT_FRAME_SYNC;
1473 event.u.frame_sync.frame_sequence = atomic_read(&pipe->frame_number);
de1135d4
LP		 1474
1475 v4l2_event_queue(vdev, &event);
1476}
1477
1478/*
1479 * ccdc_lsc_isr - Handle LSC events
1480 * @ccdc: Pointer to ISP CCDC device.
1481 * @events: LSC events
1482 */
1483static void ccdc_lsc_isr(struct isp_ccdc_device *ccdc, u32 events)
1484{
1485 unsigned long flags;
1486
1487 if (events & IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ) {
875e2e3e
LP		 1488 struct isp_pipeline *pipe =
1489 to_isp_pipeline(&ccdc->subdev.entity);
1490
de1135d4 1491 ccdc_lsc_error_handler(ccdc);
875e2e3e 1492 pipe->error = true;
de1135d4
LP		 1493 dev_dbg(to_device(ccdc), "lsc prefetch error\n");
1494 }
1495
1496 if (!(events & IRQ0STATUS_CCDC_LSC_DONE_IRQ))
1497 return;
1498
1499 /* LSC_DONE interrupt occur, there are two cases
1500 * 1. stopping for reconfiguration
1501 * 2. stopping because of STREAM OFF command
1502 */
1503 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1504
1505 if (ccdc->lsc.state == LSC_STATE_STOPPING)
1506 ccdc->lsc.state = LSC_STATE_STOPPED;
1507
8815392a 1508 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_LSC_DONE))
de1135d4
LP		 1509 goto done;
1510
1511 if (ccdc->lsc.state != LSC_STATE_RECONFIG)
1512 goto done;
1513
1514 /* LSC is in STOPPING state, change to the new state */
1515 ccdc->lsc.state = LSC_STATE_STOPPED;
1516
1517 /* This is an exception. Start of frame and LSC_DONE interrupt
1518 * have been received on the same time. Skip this event and wait
1519 * for better times.
1520 */
1521 if (events & IRQ0STATUS_HS_VS_IRQ)
1522 goto done;
1523
1524 /* The LSC engine is stopped at this point. Enable it if there's a
1525 * pending request.
1526 */
1527 if (ccdc->lsc.request == NULL)
1528 goto done;
1529
1530 ccdc_lsc_enable(ccdc);
1531
1532done:
1533 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1534}
1535
93d7badf
LP		 1536/*
1537 * Check whether the CCDC has captured all fields necessary to complete the
1538 * buffer.
1539 */
1540static bool ccdc_has_all_fields(struct isp_ccdc_device *ccdc)
1541{
1542 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1543 struct isp_device *isp = to_isp_device(ccdc);
1544 enum v4l2_field of_field = ccdc->formats[CCDC_PAD_SOURCE_OF].field;
1545 enum v4l2_field field;
1546
1547 /* When the input is progressive fields don't matter. */
1548 if (of_field == V4L2_FIELD_NONE)
1549 return true;
1550
1551 /* Read the current field identifier. */
1552 field = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE)
1553 & ISPCCDC_SYN_MODE_FLDSTAT
1554 ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
1555
1556 /* When capturing fields in alternate order just store the current field
1557 * identifier in the pipeline.
1558 */
1559 if (of_field == V4L2_FIELD_ALTERNATE) {
1560 pipe->field = field;
1561 return true;
1562 }
1563
1564 /* The format is interlaced. Make sure we've captured both fields. */
1565 ccdc->fields |= field == V4L2_FIELD_BOTTOM
1566 ? CCDC_FIELD_BOTTOM : CCDC_FIELD_TOP;
1567
1568 if (ccdc->fields != CCDC_FIELD_BOTH)
1569 return false;
1570
1571 /* Verify that the field just captured corresponds to the last field
1572 * needed based on the desired field order.
1573 */
1574 if ((of_field == V4L2_FIELD_INTERLACED_TB && field == V4L2_FIELD_TOP) ||
1575 (of_field == V4L2_FIELD_INTERLACED_BT && field == V4L2_FIELD_BOTTOM))
1576 return false;
1577
1578 /* The buffer can be completed, reset the fields for the next buffer. */
1579 ccdc->fields = 0;
1580
1581 return true;
1582}
1583
de1135d4
LP		 1584static int ccdc_isr_buffer(struct isp_ccdc_device *ccdc)
1585{
1586 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1587 struct isp_device *isp = to_isp_device(ccdc);
1588 struct isp_buffer *buffer;
de1135d4
LP		 1589
1590 /* The CCDC generates VD0 interrupts even when disabled (the datasheet
1591 * doesn't explicitly state if that's supposed to happen or not, so it
1592 * can be considered as a hardware bug or as a feature, but we have to
1593 * deal with it anyway). Disabling the CCDC when no buffer is available
1594 * would thus not be enough, we need to handle the situation explicitly.
1595 */
1596 if (list_empty(&ccdc->video_out.dmaqueue))
0a7b1a01 1597 return 0;
de1135d4
LP		 1598
1599 /* We're in continuous mode, and memory writes were disabled due to a
1600 * buffer underrun. Reenable them now that we have a buffer. The buffer
1601 * address has been set in ccdc_video_queue.
1602 */
1603 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && ccdc->underrun) {
de1135d4 1604 ccdc->underrun = 0;
0a7b1a01 1605 return 1;
de1135d4
LP		 1606 }
1607
bcb4e0ef 1608 /* Wait for the CCDC to become idle. */
de1135d4
LP		 1609 if (ccdc_sbl_wait_idle(ccdc, 1000)) {
1610 dev_info(isp->dev, "CCDC won't become idle!\n");
9554b7db
LP		 1611 isp->crashed |= 1U << ccdc->subdev.entity.id;
1612 omap3isp_pipeline_cancel_stream(pipe);
0a7b1a01 1613 return 0;
de1135d4
LP		 1614 }
1615
93d7badf
LP		 1616 if (!ccdc_has_all_fields(ccdc))
1617 return 1;
bcb4e0ef 1618
875e2e3e 1619 buffer = omap3isp_video_buffer_next(&ccdc->video_out);
0a7b1a01 1620 if (buffer != NULL)
21d8582d 1621 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4
LP		 1622
1623 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1624
1625 if (ccdc->state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1626 isp_pipeline_ready(pipe))
1627 omap3isp_pipeline_set_stream(pipe,
1628 ISP_PIPELINE_STREAM_SINGLESHOT);
1629
0a7b1a01 1630 return buffer != NULL;
de1135d4
LP		 1631}
1632
1633/*
1634 * ccdc_vd0_isr - Handle VD0 event
1635 * @ccdc: Pointer to ISP CCDC device.
1636 *
1637 * Executes LSC deferred enablement before next frame starts.
1638 */
1639static void ccdc_vd0_isr(struct isp_ccdc_device *ccdc)
1640{
1641 unsigned long flags;
1642 int restart = 0;
1643
fd93c10a
LP		 1644 /* In BT.656 mode the CCDC doesn't generate an HS/VS interrupt. We thus
1645 * need to increment the frame counter here.
1646 */
1647 if (ccdc->bt656) {
1648 struct isp_pipeline *pipe =
1649 to_isp_pipeline(&ccdc->subdev.entity);
1650
1651 atomic_inc(&pipe->frame_number);
1652 }
1653
93456527
LP		 1654 /* Emulate a VD1 interrupt for BT.656 mode, as we can't stop the CCDC in
1655 * the VD1 interrupt handler in that mode without risking a CCDC stall
1656 * if a short frame is received.
1657 */
1658 if (ccdc->bt656) {
1659 spin_lock_irqsave(&ccdc->lock, flags);
1660 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS &&
1661 ccdc->output & CCDC_OUTPUT_MEMORY) {
1662 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1663 __ccdc_lsc_enable(ccdc, 0);
1664 __ccdc_enable(ccdc, 0);
1665 }
1666 ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1);
1667 spin_unlock_irqrestore(&ccdc->lock, flags);
1668 }
1669
de1135d4
LP		 1670 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1671 restart = ccdc_isr_buffer(ccdc);
1672
1673 spin_lock_irqsave(&ccdc->lock, flags);
93456527 1674
8815392a 1675 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_VD0)) {
de1135d4
LP		 1676 spin_unlock_irqrestore(&ccdc->lock, flags);
1677 return;
1678 }
1679
1680 if (!ccdc->shadow_update)
1681 ccdc_apply_controls(ccdc);
1682 spin_unlock_irqrestore(&ccdc->lock, flags);
1683
1684 if (restart)
1685 ccdc_enable(ccdc);
1686}
1687
1688/*
1689 * ccdc_vd1_isr - Handle VD1 event
1690 * @ccdc: Pointer to ISP CCDC device.
1691 */
1692static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)
1693{
1694 unsigned long flags;
1695
93456527
LP		 1696 /* In BT.656 mode the synchronization signals are generated by the CCDC
1697 * from the embedded sync codes. The VD0 and VD1 interrupts are thus
1698 * only triggered when the CCDC is enabled, unlike external sync mode
1699 * where the line counter runs even when the CCDC is stopped. We can't
1700 * disable the CCDC at VD1 time, as no VD0 interrupt would be generated
1701 * for a short frame, which would result in the CCDC being stopped and
1702 * no VD interrupt generated anymore. The CCDC is stopped from the VD0
1703 * interrupt handler instead for BT.656.
1704 */
1705 if (ccdc->bt656)
1706 return;
1707
de1135d4
LP		 1708 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1709
1710 /*
1711 * Depending on the CCDC pipeline state, CCDC stopping should be
1712 * handled differently. In SINGLESHOT we emulate an internal CCDC
1713 * stopping because the CCDC hw works only in continuous mode.
1714 * When CONTINUOUS pipeline state is used and the CCDC writes it's
1715 * data to memory the CCDC and LSC are stopped immediately but
1716 * without change the CCDC stopping state machine. The CCDC
1717 * stopping state machine should be used only when user request
1718 * for stopping is received (SINGLESHOT is an exeption).
1719 */
1720 switch (ccdc->state) {
1721 case ISP_PIPELINE_STREAM_SINGLESHOT:
1722 ccdc->stopping = CCDC_STOP_REQUEST;
1723 break;
1724
1725 case ISP_PIPELINE_STREAM_CONTINUOUS:
1726 if (ccdc->output & CCDC_OUTPUT_MEMORY) {
1727 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1728 __ccdc_lsc_enable(ccdc, 0);
1729 __ccdc_enable(ccdc, 0);
1730 }
1731 break;
1732
1733 case ISP_PIPELINE_STREAM_STOPPED:
1734 break;
1735 }
1736
8815392a 1737 if (ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))
de1135d4
LP		 1738 goto done;
1739
1740 if (ccdc->lsc.request == NULL)
1741 goto done;
1742
1743 /*
1744 * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ
1745 * do the appropriate changes in registers
1746 */
1747 if (ccdc->lsc.state == LSC_STATE_RUNNING) {
1748 __ccdc_lsc_enable(ccdc, 0);
1749 ccdc->lsc.state = LSC_STATE_RECONFIG;
1750 goto done;
1751 }
1752
1753 /* LSC has been in STOPPED state, enable it */
1754 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1755 ccdc_lsc_enable(ccdc);
1756
1757done:
1758 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1759}
1760
1761/*
1762 * omap3isp_ccdc_isr - Configure CCDC during interframe time.
1763 * @ccdc: Pointer to ISP CCDC device.
1764 * @events: CCDC events
1765 */
1766int omap3isp_ccdc_isr(struct isp_ccdc_device *ccdc, u32 events)
1767{
1768 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED)
1769 return 0;
1770
1771 if (events & IRQ0STATUS_CCDC_VD1_IRQ)
1772 ccdc_vd1_isr(ccdc);
1773
1774 ccdc_lsc_isr(ccdc, events);
1775
1776 if (events & IRQ0STATUS_CCDC_VD0_IRQ)
1777 ccdc_vd0_isr(ccdc);
1778
1779 if (events & IRQ0STATUS_HS_VS_IRQ)
1780 ccdc_hs_vs_isr(ccdc);
1781
1782 return 0;
1783}
1784
1785/* -----------------------------------------------------------------------------
1786 * ISP video operations
1787 */
1788
1789static int ccdc_video_queue(struct isp_video *video, struct isp_buffer *buffer)
1790{
1791 struct isp_ccdc_device *ccdc = &video->isp->isp_ccdc;
ca84ea49
LP		 1792 unsigned long flags;
1793 bool restart = false;
de1135d4
LP		 1794
1795 if (!(ccdc->output & CCDC_OUTPUT_MEMORY))
1796 return -ENODEV;
1797
21d8582d 1798 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4 1799
2d4e9d1d 1800 /* We now have a buffer queued on the output, restart the pipeline
de1135d4 1801 * on the next CCDC interrupt if running in continuous mode (or when
ca84ea49
LP		 1802 * starting the stream) in external sync mode, or immediately in BT.656
1803 * sync mode as no CCDC interrupt is generated when the CCDC is stopped
1804 * in that case.
de1135d4 1805 */
ca84ea49
LP		 1806 spin_lock_irqsave(&ccdc->lock, flags);
1807 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && !ccdc->running &&
1808 ccdc->bt656)
11b4c175 1809 restart = true;
ca84ea49
LP		 1810 else
1811 ccdc->underrun = 1;
1812 spin_unlock_irqrestore(&ccdc->lock, flags);
1813
1814 if (restart)
1815 ccdc_enable(ccdc);
de1135d4
LP		 1816
1817 return 0;
1818}
1819
1820static const struct isp_video_operations ccdc_video_ops = {
1821 .queue = ccdc_video_queue,
1822};
1823
1824/* -----------------------------------------------------------------------------
1825 * V4L2 subdev operations
1826 */
1827
1828/*
1829 * ccdc_ioctl - CCDC module private ioctl's
1830 * @sd: ISP CCDC V4L2 subdevice
1831 * @cmd: ioctl command
1832 * @arg: ioctl argument
1833 *
1834 * Return 0 on success or a negative error code otherwise.
1835 */
1836static long ccdc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1837{
1838 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1839 int ret;
1840
1841 switch (cmd) {
1842 case VIDIOC_OMAP3ISP_CCDC_CFG:
1843 mutex_lock(&ccdc->ioctl_lock);
1844 ret = ccdc_config(ccdc, arg);
1845 mutex_unlock(&ccdc->ioctl_lock);
1846 break;
1847
1848 default:
1849 return -ENOIOCTLCMD;
1850 }
1851
1852 return ret;
1853}
1854
1855static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1856 struct v4l2_event_subscription *sub)
de1135d4 1857{
69d232ae
SA		 1858 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1859 return -EINVAL;
1860
1861 /* line number is zero at frame start */
1862 if (sub->id != 0)
de1135d4
LP		 1863 return -EINVAL;
1864
c53c2549 1865 return v4l2_event_subscribe(fh, sub, OMAP3ISP_CCDC_NEVENTS, NULL);
de1135d4
LP		 1866}
1867
1868static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1869 struct v4l2_event_subscription *sub)
de1135d4
LP		 1870{
1871 return v4l2_event_unsubscribe(fh, sub);
1872}
1873
1874/*
1875 * ccdc_set_stream - Enable/Disable streaming on the CCDC module
1876 * @sd: ISP CCDC V4L2 subdevice
1877 * @enable: Enable/disable stream
1878 *
1879 * When writing to memory, the CCDC hardware can't be enabled without a memory
1880 * buffer to write to. As the s_stream operation is called in response to a
1881 * STREAMON call without any buffer queued yet, just update the enabled field
1882 * and return immediately. The CCDC will be enabled in ccdc_isr_buffer().
1883 *
1884 * When not writing to memory enable the CCDC immediately.
1885 */
1886static int ccdc_set_stream(struct v4l2_subdev *sd, int enable)
1887{
1888 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1889 struct isp_device *isp = to_isp_device(ccdc);
1890 int ret = 0;
1891
1892 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED) {
1893 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1894 return 0;
1895
1896 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_CCDC);
1897 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1898 ISPCCDC_CFG_VDLC);
1899
1900 ccdc_configure(ccdc);
1901
de1135d4
LP		 1902 ccdc_print_status(ccdc);
1903 }
1904
1905 switch (enable) {
1906 case ISP_PIPELINE_STREAM_CONTINUOUS:
1907 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1908 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1909
1910 if (ccdc->underrun || !(ccdc->output & CCDC_OUTPUT_MEMORY))
1911 ccdc_enable(ccdc);
1912
1913 ccdc->underrun = 0;
1914 break;
1915
1916 case ISP_PIPELINE_STREAM_SINGLESHOT:
1917 if (ccdc->output & CCDC_OUTPUT_MEMORY &&
1918 ccdc->state != ISP_PIPELINE_STREAM_SINGLESHOT)
1919 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1920
1921 ccdc_enable(ccdc);
1922 break;
1923
1924 case ISP_PIPELINE_STREAM_STOPPED:
1925 ret = ccdc_disable(ccdc);
1926 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1927 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1928 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_CCDC);
1929 ccdc->underrun = 0;
1930 break;
1931 }
1932
1933 ccdc->state = enable;
1934 return ret;
1935}
1936
1937static struct v4l2_mbus_framefmt *
1938__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1939 unsigned int pad, enum v4l2_subdev_format_whence which)
1940{
1941 if (which == V4L2_SUBDEV_FORMAT_TRY)
1942 return v4l2_subdev_get_try_format(fh, pad);
1943 else
1944 return &ccdc->formats[pad];
1945}
1946
a64909b8
LP		 1947static struct v4l2_rect *
1948__ccdc_get_crop(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1949 enum v4l2_subdev_format_whence which)
1950{
1951 if (which == V4L2_SUBDEV_FORMAT_TRY)
1952 return v4l2_subdev_get_try_crop(fh, CCDC_PAD_SOURCE_OF);
1953 else
1954 return &ccdc->crop;
1955}
1956
de1135d4
LP		 1957/*
1958 * ccdc_try_format - Try video format on a pad
1959 * @ccdc: ISP CCDC device
1960 * @fh : V4L2 subdev file handle
1961 * @pad: Pad number
1962 * @fmt: Format
1963 */
1964static void
1965ccdc_try_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1966 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
1967 enum v4l2_subdev_format_whence which)
1968{
de1135d4 1969 const struct isp_format_info *info;
27ffaeb0 1970 u32 pixelcode;
de1135d4
LP		 1971 unsigned int width = fmt->width;
1972 unsigned int height = fmt->height;
a64909b8 1973 struct v4l2_rect *crop;
bcb4e0ef 1974 enum v4l2_field field;
de1135d4
LP		 1975 unsigned int i;
1976
1977 switch (pad) {
1978 case CCDC_PAD_SINK:
de1135d4
LP		 1979 for (i = 0; i < ARRAY_SIZE(ccdc_fmts); i++) {
1980 if (fmt->code == ccdc_fmts[i])
1981 break;
1982 }
1983
1984 /* If not found, use SGRBG10 as default */
1985 if (i >= ARRAY_SIZE(ccdc_fmts))
27ffaeb0 1986 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
de1135d4
LP		 1987
1988 /* Clamp the input size. */
1989 fmt->width = clamp_t(u32, width, 32, 4096);
1990 fmt->height = clamp_t(u32, height, 32, 4096);
9a36d8ed
LP		 1991
1992 /* Default to progressive field order. */
1993 if (fmt->field == V4L2_FIELD_ANY)
1994 fmt->field = V4L2_FIELD_NONE;
1995
de1135d4
LP		 1996 break;
1997
1998 case CCDC_PAD_SOURCE_OF:
c51364ca 1999 pixelcode = fmt->code;
bcb4e0ef 2000 field = fmt->field;
c51364ca
LP		 2001 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
2002
9de7af4d
LP		 2003 /* In SYNC mode the bridge converts YUV formats from 2X8 to
2004 * 1X16. In BT.656 no such conversion occurs. As we don't know
2005 * at this point whether the source will use SYNC or BT.656 mode
2006 * let's pretend the conversion always occurs. The CCDC will be
2007 * configured to pack bytes in BT.656, hiding the inaccuracy.
2008 * In all cases bytes can be swapped.
c51364ca 2009 */
27ffaeb0
BB		 2010 if (fmt->code == MEDIA_BUS_FMT_YUYV8_2X8 ||
2011 fmt->code == MEDIA_BUS_FMT_UYVY8_2X8) {
c51364ca 2012 /* Use the user requested format if YUV. */
27ffaeb0
BB		 2013 if (pixelcode == MEDIA_BUS_FMT_YUYV8_2X8 ||
2014 pixelcode == MEDIA_BUS_FMT_UYVY8_2X8 ||
2015 pixelcode == MEDIA_BUS_FMT_YUYV8_1X16 ||
2016 pixelcode == MEDIA_BUS_FMT_UYVY8_1X16)
c51364ca
LP		 2017 fmt->code = pixelcode;
2018
27ffaeb0
BB		 2019 if (fmt->code == MEDIA_BUS_FMT_YUYV8_2X8)
2020 fmt->code = MEDIA_BUS_FMT_YUYV8_1X16;
2021 else if (fmt->code == MEDIA_BUS_FMT_UYVY8_2X8)
2022 fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
c51364ca 2023 }
de1135d4 2024
a64909b8
LP		 2025 /* Hardcode the output size to the crop rectangle size. */
2026 crop = __ccdc_get_crop(ccdc, fh, which);
2027 fmt->width = crop->width;
2028 fmt->height = crop->height;
bcb4e0ef
LP		 2029
2030 /* When input format is interlaced with alternating fields the
2031 * CCDC can interleave the fields.
2032 */
2033 if (fmt->field == V4L2_FIELD_ALTERNATE &&
2034 (field == V4L2_FIELD_INTERLACED_TB ||
2035 field == V4L2_FIELD_INTERLACED_BT)) {
2036 fmt->field = field;
2037 fmt->height *= 2;
2038 }
2039
de1135d4
LP		 2040 break;
2041
2042 case CCDC_PAD_SOURCE_VP:
c51364ca 2043 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
de1135d4
LP		 2044
2045 /* The video port interface truncates the data to 10 bits. */
2046 info = omap3isp_video_format_info(fmt->code);
2047 fmt->code = info->truncated;
2048
c51364ca 2049 /* YUV formats are not supported by the video port. */
27ffaeb0
BB		 2050 if (fmt->code == MEDIA_BUS_FMT_YUYV8_2X8 ||
2051 fmt->code == MEDIA_BUS_FMT_UYVY8_2X8)
c51364ca
LP		 2052 fmt->code = 0;
2053
de1135d4
LP		 2054 /* The number of lines that can be clocked out from the video
2055 * port output must be at least one line less than the number
2056 * of input lines.
2057 */
2058 fmt->width = clamp_t(u32, width, 32, fmt->width);
2059 fmt->height = clamp_t(u32, height, 32, fmt->height - 1);
2060 break;
2061 }
2062
2063 /* Data is written to memory unpacked, each 10-bit or 12-bit pixel is
2064 * stored on 2 bytes.
2065 */
2066 fmt->colorspace = V4L2_COLORSPACE_SRGB;
de1135d4
LP		 2067}
2068
a64909b8
LP		 2069/*
2070 * ccdc_try_crop - Validate a crop rectangle
2071 * @ccdc: ISP CCDC device
2072 * @sink: format on the sink pad
2073 * @crop: crop rectangle to be validated
2074 */
2075static void ccdc_try_crop(struct isp_ccdc_device *ccdc,
2076 const struct v4l2_mbus_framefmt *sink,
2077 struct v4l2_rect *crop)
2078{
2079 const struct isp_format_info *info;
2080 unsigned int max_width;
2081
2082 /* For Bayer formats, restrict left/top and width/height to even values
2083 * to keep the Bayer pattern.
2084 */
2085 info = omap3isp_video_format_info(sink->code);
27ffaeb0 2086 if (info->flavor != MEDIA_BUS_FMT_Y8_1X8) {
a64909b8
LP		 2087 crop->left &= ~1;
2088 crop->top &= ~1;
2089 }
2090
2091 crop->left = clamp_t(u32, crop->left, 0, sink->width - CCDC_MIN_WIDTH);
2092 crop->top = clamp_t(u32, crop->top, 0, sink->height - CCDC_MIN_HEIGHT);
2093
2094 /* The data formatter truncates the number of horizontal output pixels
2095 * to a multiple of 16. To avoid clipping data, allow callers to request
2096 * an output size bigger than the input size up to the nearest multiple
2097 * of 16.
2098 */
2099 max_width = (sink->width - crop->left + 15) & ~15;
2100 crop->width = clamp_t(u32, crop->width, CCDC_MIN_WIDTH, max_width)
2101 & ~15;
2102 crop->height = clamp_t(u32, crop->height, CCDC_MIN_HEIGHT,
2103 sink->height - crop->top);
2104
2105 /* Odd width/height values don't make sense for Bayer formats. */
27ffaeb0 2106 if (info->flavor != MEDIA_BUS_FMT_Y8_1X8) {
a64909b8
LP		 2107 crop->width &= ~1;
2108 crop->height &= ~1;
2109 }
2110}
2111
de1135d4
LP		 2112/*
2113 * ccdc_enum_mbus_code - Handle pixel format enumeration
2114 * @sd : pointer to v4l2 subdev structure
2115 * @fh : V4L2 subdev file handle
2116 * @code : pointer to v4l2_subdev_mbus_code_enum structure
2117 * return -EINVAL or zero on success
2118 */
2119static int ccdc_enum_mbus_code(struct v4l2_subdev *sd,
2120 struct v4l2_subdev_fh *fh,
2121 struct v4l2_subdev_mbus_code_enum *code)
2122{
2123 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2124 struct v4l2_mbus_framefmt *format;
2125
2126 switch (code->pad) {
2127 case CCDC_PAD_SINK:
2128 if (code->index >= ARRAY_SIZE(ccdc_fmts))
2129 return -EINVAL;
2130
2131 code->code = ccdc_fmts[code->index];
2132 break;
2133
2134 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 2135 format = __ccdc_get_format(ccdc, fh, code->pad,
2136 V4L2_SUBDEV_FORMAT_TRY);
2137
27ffaeb0
BB		 2138 if (format->code == MEDIA_BUS_FMT_YUYV8_2X8 ||
2139 format->code == MEDIA_BUS_FMT_UYVY8_2X8) {
c51364ca
LP		 2140 /* In YUV mode the CCDC can swap bytes. */
2141 if (code->index == 0)
27ffaeb0 2142 code->code = MEDIA_BUS_FMT_YUYV8_1X16;
c51364ca 2143 else if (code->index == 1)
27ffaeb0 2144 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
c51364ca
LP		 2145 else
2146 return -EINVAL;
2147 } else {
2148 /* In raw mode, no configurable format confversion is
2149 * available.
2150 */
2151 if (code->index == 0)
2152 code->code = format->code;
2153 else
2154 return -EINVAL;
2155 }
2156 break;
2157
de1135d4 2158 case CCDC_PAD_SOURCE_VP:
c51364ca
LP		 2159 /* The CCDC supports no configurable format conversion
2160 * compatible with the video port. Enumerate a single output
2161 * format code.
2162 */
de1135d4
LP		 2163 if (code->index != 0)
2164 return -EINVAL;
2165
c51364ca 2166 format = __ccdc_get_format(ccdc, fh, code->pad,
de1135d4
LP		 2167 V4L2_SUBDEV_FORMAT_TRY);
2168
c51364ca
LP		 2169 /* A pixel code equal to 0 means that the video port doesn't
2170 * support the input format. Don't enumerate any pixel code.
2171 */
2172 if (format->code == 0)
2173 return -EINVAL;
2174
de1135d4
LP		 2175 code->code = format->code;
2176 break;
2177
2178 default:
2179 return -EINVAL;
2180 }
2181
2182 return 0;
2183}
2184
2185static int ccdc_enum_frame_size(struct v4l2_subdev *sd,
2186 struct v4l2_subdev_fh *fh,
2187 struct v4l2_subdev_frame_size_enum *fse)
2188{
2189 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2190 struct v4l2_mbus_framefmt format;
2191
2192 if (fse->index != 0)
2193 return -EINVAL;
2194
2195 format.code = fse->code;
2196 format.width = 1;
2197 format.height = 1;
2198 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2199 fse->min_width = format.width;
2200 fse->min_height = format.height;
2201
2202 if (format.code != fse->code)
2203 return -EINVAL;
2204
2205 format.code = fse->code;
2206 format.width = -1;
2207 format.height = -1;
2208 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2209 fse->max_width = format.width;
2210 fse->max_height = format.height;
2211
2212 return 0;
2213}
2214
a64909b8
LP		 2215/*
2216 * ccdc_get_selection - Retrieve a selection rectangle on a pad
2217 * @sd: ISP CCDC V4L2 subdevice
2218 * @fh: V4L2 subdev file handle
2219 * @sel: Selection rectangle
2220 *
2221 * The only supported rectangles are the crop rectangles on the output formatter
2222 * source pad.
2223 *
2224 * Return 0 on success or a negative error code otherwise.
2225 */
2226static int ccdc_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2227 struct v4l2_subdev_selection *sel)
2228{
2229 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2230 struct v4l2_mbus_framefmt *format;
2231
2232 if (sel->pad != CCDC_PAD_SOURCE_OF)
2233 return -EINVAL;
2234
2235 switch (sel->target) {
5689b288 2236 case V4L2_SEL_TGT_CROP_BOUNDS:
a64909b8
LP		 2237 sel->r.left = 0;
2238 sel->r.top = 0;
2239 sel->r.width = INT_MAX;
2240 sel->r.height = INT_MAX;
2241
2242 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2243 ccdc_try_crop(ccdc, format, &sel->r);
2244 break;
2245
5689b288 2246 case V4L2_SEL_TGT_CROP:
a64909b8
LP		 2247 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2248 break;
2249
2250 default:
2251 return -EINVAL;
2252 }
2253
2254 return 0;
2255}
2256
2257/*
2258 * ccdc_set_selection - Set a selection rectangle on a pad
2259 * @sd: ISP CCDC V4L2 subdevice
2260 * @fh: V4L2 subdev file handle
2261 * @sel: Selection rectangle
2262 *
2263 * The only supported rectangle is the actual crop rectangle on the output
2264 * formatter source pad.
2265 *
2266 * Return 0 on success or a negative error code otherwise.
2267 */
2268static int ccdc_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2269 struct v4l2_subdev_selection *sel)
2270{
2271 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2272 struct v4l2_mbus_framefmt *format;
2273
5689b288 2274 if (sel->target != V4L2_SEL_TGT_CROP ||
a64909b8
LP		 2275 sel->pad != CCDC_PAD_SOURCE_OF)
2276 return -EINVAL;
2277
2278 /* The crop rectangle can't be changed while streaming. */
2279 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
2280 return -EBUSY;
2281
2282 /* Modifying the crop rectangle always changes the format on the source
2283 * pad. If the KEEP_CONFIG flag is set, just return the current crop
2284 * rectangle.
2285 */
563df3d0 2286 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
a64909b8
LP		 2287 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2288 return 0;
2289 }
2290
2291 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2292 ccdc_try_crop(ccdc, format, &sel->r);
2293 *__ccdc_get_crop(ccdc, fh, sel->which) = sel->r;
2294
2295 /* Update the source format. */
2296 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF, sel->which);
2297 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format, sel->which);
2298
2299 return 0;
2300}
2301
de1135d4
LP		 2302/*
2303 * ccdc_get_format - Retrieve the video format on a pad
2304 * @sd : ISP CCDC V4L2 subdevice
2305 * @fh : V4L2 subdev file handle
2306 * @fmt: Format
2307 *
2308 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2309 * to the format type.
2310 */
2311static int ccdc_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2312 struct v4l2_subdev_format *fmt)
2313{
2314 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2315 struct v4l2_mbus_framefmt *format;
2316
2317 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2318 if (format == NULL)
2319 return -EINVAL;
2320
2321 fmt->format = *format;
2322 return 0;
2323}
2324
2325/*
2326 * ccdc_set_format - Set the video format on a pad
2327 * @sd : ISP CCDC V4L2 subdevice
2328 * @fh : V4L2 subdev file handle
2329 * @fmt: Format
2330 *
2331 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2332 * to the format type.
2333 */
2334static int ccdc_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2335 struct v4l2_subdev_format *fmt)
2336{
2337 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2338 struct v4l2_mbus_framefmt *format;
a64909b8 2339 struct v4l2_rect *crop;
de1135d4
LP		 2340
2341 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2342 if (format == NULL)
2343 return -EINVAL;
2344
2345 ccdc_try_format(ccdc, fh, fmt->pad, &fmt->format, fmt->which);
2346 *format = fmt->format;
2347
2348 /* Propagate the format from sink to source */
2349 if (fmt->pad == CCDC_PAD_SINK) {
a64909b8
LP		 2350 /* Reset the crop rectangle. */
2351 crop = __ccdc_get_crop(ccdc, fh, fmt->which);
2352 crop->left = 0;
2353 crop->top = 0;
2354 crop->width = fmt->format.width;
2355 crop->height = fmt->format.height;
2356
2357 ccdc_try_crop(ccdc, &fmt->format, crop);
2358
2359 /* Update the source formats. */
de1135d4
LP		 2360 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF,
2361 fmt->which);
2362 *format = fmt->format;
2363 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format,
2364 fmt->which);
2365
2366 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_VP,
2367 fmt->which);
2368 *format = fmt->format;
2369 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_VP, format,
2370 fmt->which);
2371 }
2372
2373 return 0;
2374}
2375
a6d7a62d
SA		 2376/*
2377 * Decide whether desired output pixel code can be obtained with
2378 * the lane shifter by shifting the input pixel code.
2379 * @in: input pixelcode to shifter
2380 * @out: output pixelcode from shifter
2381 * @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
2382 *
2383 * return true if the combination is possible
2384 * return false otherwise
2385 */
27ffaeb0 2386static bool ccdc_is_shiftable(u32 in, u32 out, unsigned int additional_shift)
a6d7a62d
SA		 2387{
2388 const struct isp_format_info *in_info, *out_info;
2389
2390 if (in == out)
2391 return true;
2392
2393 in_info = omap3isp_video_format_info(in);
2394 out_info = omap3isp_video_format_info(out);
2395
2396 if ((in_info->flavor == 0) || (out_info->flavor == 0))
2397 return false;
2398
2399 if (in_info->flavor != out_info->flavor)
2400 return false;
2401
1697e49a 2402 return in_info->width - out_info->width + additional_shift <= 6;
a6d7a62d
SA		 2403}
2404
2405static int ccdc_link_validate(struct v4l2_subdev *sd,
2406 struct media_link *link,
2407 struct v4l2_subdev_format *source_fmt,
2408 struct v4l2_subdev_format *sink_fmt)
2409{
2410 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2411 unsigned long parallel_shift;
2412
2413 /* Check if the two ends match */
2414 if (source_fmt->format.width != sink_fmt->format.width ||
2415 source_fmt->format.height != sink_fmt->format.height)
2416 return -EPIPE;
2417
2418 /* We've got a parallel sensor here. */
2419 if (ccdc->input == CCDC_INPUT_PARALLEL) {
2420 struct isp_parallel_platform_data *pdata =
2421 &((struct isp_v4l2_subdevs_group *)
2422 media_entity_to_v4l2_subdev(link->source->entity)
2423 ->host_priv)->bus.parallel;
2424 parallel_shift = pdata->data_lane_shift * 2;
2425 } else {
2426 parallel_shift = 0;
2427 }
2428
2429 /* Lane shifter may be used to drop bits on CCDC sink pad */
2430 if (!ccdc_is_shiftable(source_fmt->format.code,
2431 sink_fmt->format.code, parallel_shift))
2432 return -EPIPE;
2433
2434 return 0;
2435}
2436
de1135d4
LP		 2437/*
2438 * ccdc_init_formats - Initialize formats on all pads
2439 * @sd: ISP CCDC V4L2 subdevice
2440 * @fh: V4L2 subdev file handle
2441 *
2442 * Initialize all pad formats with default values. If fh is not NULL, try
2443 * formats are initialized on the file handle. Otherwise active formats are
2444 * initialized on the device.
2445 */
2446static int ccdc_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2447{
2448 struct v4l2_subdev_format format;
2449
2450 memset(&format, 0, sizeof(format));
2451 format.pad = CCDC_PAD_SINK;
2452 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
27ffaeb0 2453 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
de1135d4
LP		 2454 format.format.width = 4096;
2455 format.format.height = 4096;
2456 ccdc_set_format(sd, fh, &format);
2457
2458 return 0;
2459}
2460
2461/* V4L2 subdev core operations */
2462static const struct v4l2_subdev_core_ops ccdc_v4l2_core_ops = {
2463 .ioctl = ccdc_ioctl,
2464 .subscribe_event = ccdc_subscribe_event,
2465 .unsubscribe_event = ccdc_unsubscribe_event,
2466};
2467
2468/* V4L2 subdev video operations */
2469static const struct v4l2_subdev_video_ops ccdc_v4l2_video_ops = {
2470 .s_stream = ccdc_set_stream,
2471};
2472
2473/* V4L2 subdev pad operations */
2474static const struct v4l2_subdev_pad_ops ccdc_v4l2_pad_ops = {
2475 .enum_mbus_code = ccdc_enum_mbus_code,
2476 .enum_frame_size = ccdc_enum_frame_size,
2477 .get_fmt = ccdc_get_format,
2478 .set_fmt = ccdc_set_format,
a64909b8
LP		 2479 .get_selection = ccdc_get_selection,
2480 .set_selection = ccdc_set_selection,
a6d7a62d 2481 .link_validate = ccdc_link_validate,
de1135d4
LP		 2482};
2483
2484/* V4L2 subdev operations */
2485static const struct v4l2_subdev_ops ccdc_v4l2_ops = {
2486 .core = &ccdc_v4l2_core_ops,
2487 .video = &ccdc_v4l2_video_ops,
2488 .pad = &ccdc_v4l2_pad_ops,
2489};
2490
2491/* V4L2 subdev internal operations */
2492static const struct v4l2_subdev_internal_ops ccdc_v4l2_internal_ops = {
2493 .open = ccdc_init_formats,
2494};
2495
2496/* -----------------------------------------------------------------------------
2497 * Media entity operations
2498 */
2499
2500/*
2501 * ccdc_link_setup - Setup CCDC connections
2502 * @entity: CCDC media entity
2503 * @local: Pad at the local end of the link
2504 * @remote: Pad at the remote end of the link
2505 * @flags: Link flags
2506 *
2507 * return -EINVAL or zero on success
2508 */
2509static int ccdc_link_setup(struct media_entity *entity,
2510 const struct media_pad *local,
2511 const struct media_pad *remote, u32 flags)
2512{
2513 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2514 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2515 struct isp_device *isp = to_isp_device(ccdc);
2516
2517 switch (local->index | media_entity_type(remote->entity)) {
2518 case CCDC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2519 /* Read from the sensor (parallel interface), CCP2, CSI2a or
2520 * CSI2c.
2521 */
2522 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
2523 ccdc->input = CCDC_INPUT_NONE;
2524 break;
2525 }
2526
2527 if (ccdc->input != CCDC_INPUT_NONE)
2528 return -EBUSY;
2529
2530 if (remote->entity == &isp->isp_ccp2.subdev.entity)
2531 ccdc->input = CCDC_INPUT_CCP2B;
2532 else if (remote->entity == &isp->isp_csi2a.subdev.entity)
2533 ccdc->input = CCDC_INPUT_CSI2A;
2534 else if (remote->entity == &isp->isp_csi2c.subdev.entity)
2535 ccdc->input = CCDC_INPUT_CSI2C;
2536 else
2537 ccdc->input = CCDC_INPUT_PARALLEL;
2538
2539 break;
2540
2541 /*
2542 * The ISP core doesn't support pipelines with multiple video outputs.
2543 * Revisit this when it will be implemented, and return -EBUSY for now.
2544 */
2545
2546 case CCDC_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
2547 /* Write to preview engine, histogram and H3A. When none of
2548 * those links are active, the video port can be disabled.
2549 */
2550 if (flags & MEDIA_LNK_FL_ENABLED) {
2551 if (ccdc->output & ~CCDC_OUTPUT_PREVIEW)
2552 return -EBUSY;
2553 ccdc->output |= CCDC_OUTPUT_PREVIEW;
2554 } else {
2555 ccdc->output &= ~CCDC_OUTPUT_PREVIEW;
2556 }
2557 break;
2558
2559 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_DEVNODE:
2560 /* Write to memory */
2561 if (flags & MEDIA_LNK_FL_ENABLED) {
2562 if (ccdc->output & ~CCDC_OUTPUT_MEMORY)
2563 return -EBUSY;
2564 ccdc->output |= CCDC_OUTPUT_MEMORY;
2565 } else {
2566 ccdc->output &= ~CCDC_OUTPUT_MEMORY;
2567 }
2568 break;
2569
2570 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_V4L2_SUBDEV:
2571 /* Write to resizer */
2572 if (flags & MEDIA_LNK_FL_ENABLED) {
2573 if (ccdc->output & ~CCDC_OUTPUT_RESIZER)
2574 return -EBUSY;
2575 ccdc->output |= CCDC_OUTPUT_RESIZER;
2576 } else {
2577 ccdc->output &= ~CCDC_OUTPUT_RESIZER;
2578 }
2579 break;
2580
2581 default:
2582 return -EINVAL;
2583 }
2584
2585 return 0;
2586}
2587
2588/* media operations */
2589static const struct media_entity_operations ccdc_media_ops = {
2590 .link_setup = ccdc_link_setup,
a6d7a62d 2591 .link_validate = v4l2_subdev_link_validate,
de1135d4
LP		 2592};
2593
39099d09
LP		 2594void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc)
2595{
2596 v4l2_device_unregister_subdev(&ccdc->subdev);
2597 omap3isp_video_unregister(&ccdc->video_out);
2598}
2599
2600int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
2601 struct v4l2_device *vdev)
2602{
2603 int ret;
2604
2605 /* Register the subdev and video node. */
2606 ret = v4l2_device_register_subdev(vdev, &ccdc->subdev);
2607 if (ret < 0)
2608 goto error;
2609
2610 ret = omap3isp_video_register(&ccdc->video_out, vdev);
2611 if (ret < 0)
2612 goto error;
2613
2614 return 0;
2615
2616error:
2617 omap3isp_ccdc_unregister_entities(ccdc);
2618 return ret;
2619}
2620
2621/* -----------------------------------------------------------------------------
2622 * ISP CCDC initialisation and cleanup
2623 */
2624
de1135d4
LP		 2625/*
2626 * ccdc_init_entities - Initialize V4L2 subdev and media entity
2627 * @ccdc: ISP CCDC module
2628 *
2629 * Return 0 on success and a negative error code on failure.
2630 */
2631static int ccdc_init_entities(struct isp_ccdc_device *ccdc)
2632{
2633 struct v4l2_subdev *sd = &ccdc->subdev;
2634 struct media_pad *pads = ccdc->pads;
2635 struct media_entity *me = &sd->entity;
2636 int ret;
2637
2638 ccdc->input = CCDC_INPUT_NONE;
2639
2640 v4l2_subdev_init(sd, &ccdc_v4l2_ops);
2641 sd->internal_ops = &ccdc_v4l2_internal_ops;
2642 strlcpy(sd->name, "OMAP3 ISP CCDC", sizeof(sd->name));
2643 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2644 v4l2_set_subdevdata(sd, ccdc);
2645 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
de1135d4 2646
8dad936a
SA		 2647 pads[CCDC_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2648 | MEDIA_PAD_FL_MUST_CONNECT;
de1135d4
LP		 2649 pads[CCDC_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
2650 pads[CCDC_PAD_SOURCE_OF].flags = MEDIA_PAD_FL_SOURCE;
2651
2652 me->ops = &ccdc_media_ops;
2653 ret = media_entity_init(me, CCDC_PADS_NUM, pads, 0);
2654 if (ret < 0)
2655 return ret;
2656
2657 ccdc_init_formats(sd, NULL);
2658
2659 ccdc->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2660 ccdc->video_out.ops = &ccdc_video_ops;
2661 ccdc->video_out.isp = to_isp_device(ccdc);
2662 ccdc->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
2663 ccdc->video_out.bpl_alignment = 32;
2664
2665 ret = omap3isp_video_init(&ccdc->video_out, "CCDC");
2666 if (ret < 0)
9b6390bd 2667 goto error_video;
de1135d4
LP		 2668
2669 /* Connect the CCDC subdev to the video node. */
2670 ret = media_entity_create_link(&ccdc->subdev.entity, CCDC_PAD_SOURCE_OF,
2671 &ccdc->video_out.video.entity, 0, 0);
2672 if (ret < 0)
9b6390bd 2673 goto error_link;
de1135d4
LP		 2674
2675 return 0;
9b6390bd
LP		 2676
2677error_link:
2678 omap3isp_video_cleanup(&ccdc->video_out);
2679error_video:
2680 media_entity_cleanup(me);
2681 return ret;
de1135d4
LP		 2682}
2683
de1135d4
LP		 2684/*
2685 * omap3isp_ccdc_init - CCDC module initialization.
872aba51 2686 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2687 *
2688 * TODO: Get the initialisation values from platform data.
2689 *
2690 * Return 0 on success or a negative error code otherwise.
2691 */
2692int omap3isp_ccdc_init(struct isp_device *isp)
2693{
2694 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
9b6390bd 2695 int ret;
de1135d4
LP		 2696
2697 spin_lock_init(&ccdc->lock);
2698 init_waitqueue_head(&ccdc->wait);
2699 mutex_init(&ccdc->ioctl_lock);
2700
2701 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
2702
2703 INIT_WORK(&ccdc->lsc.table_work, ccdc_lsc_free_table_work);
2704 ccdc->lsc.state = LSC_STATE_STOPPED;
2705 INIT_LIST_HEAD(&ccdc->lsc.free_queue);
2706 spin_lock_init(&ccdc->lsc.req_lock);
2707
de1135d4
LP		 2708 ccdc->clamp.oblen = 0;
2709 ccdc->clamp.dcsubval = 0;
2710
de1135d4
LP		 2711 ccdc->update = OMAP3ISP_CCDC_BLCLAMP;
2712 ccdc_apply_controls(ccdc);
2713
9b6390bd
LP		 2714 ret = ccdc_init_entities(ccdc);
2715 if (ret < 0) {
2716 mutex_destroy(&ccdc->ioctl_lock);
2717 return ret;
2718 }
2719
2720 return 0;
de1135d4
LP		 2721}
2722
2723/*
2724 * omap3isp_ccdc_cleanup - CCDC module cleanup.
872aba51 2725 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2726 */
2727void omap3isp_ccdc_cleanup(struct isp_device *isp)
2728{
2729 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
2730
63b4ca23
LP		 2731 omap3isp_video_cleanup(&ccdc->video_out);
2732 media_entity_cleanup(&ccdc->subdev.entity);
2733
de1135d4
LP		 2734 /* Free LSC requests. As the CCDC is stopped there's no active request,
2735 * so only the pending request and the free queue need to be handled.
2736 */
2737 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
2738 cancel_work_sync(&ccdc->lsc.table_work);
2739 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
2740
c60e153d
LP		 2741 if (ccdc->fpc.addr != NULL)
2742 dma_free_coherent(isp->dev, ccdc->fpc.fpnum * 4, ccdc->fpc.addr,
2743 ccdc->fpc.dma);
ed33ac8e
LP		 2744
2745 mutex_destroy(&ccdc->ioctl_lock);
de1135d4 2746}
Linux kernel - Deliverables
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