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[media] omap3isp: ccdc: Add support for BT.656 YUV format at the CCDC input
[deliverable/linux.git] / drivers / media / platform / omap3isp / ispccdc.c
CommitLineData
de1135d4
LP		 1/*
2 * ispccdc.c
3 *
4 * TI OMAP3 ISP - CCDC module
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
de1135d4
LP		 15 */
16
17#include <linux/module.h>
18#include <linux/uaccess.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mm.h>
23#include <linux/sched.h>
e74d83aa 24#include <linux/slab.h>
de1135d4
LP		 25#include <media/v4l2-event.h>
26
27#include "isp.h"
28#include "ispreg.h"
29#include "ispccdc.h"
30
a64909b8
LP		 31#define CCDC_MIN_WIDTH 32
32#define CCDC_MIN_HEIGHT 32
33
de1135d4
LP		 34static struct v4l2_mbus_framefmt *
35__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
36 unsigned int pad, enum v4l2_subdev_format_whence which);
37
38static const unsigned int ccdc_fmts[] = {
39 V4L2_MBUS_FMT_Y8_1X8,
5782f97b
MJ		 40 V4L2_MBUS_FMT_Y10_1X10,
41 V4L2_MBUS_FMT_Y12_1X12,
42 V4L2_MBUS_FMT_SGRBG8_1X8,
43 V4L2_MBUS_FMT_SRGGB8_1X8,
44 V4L2_MBUS_FMT_SBGGR8_1X8,
45 V4L2_MBUS_FMT_SGBRG8_1X8,
de1135d4
LP		 46 V4L2_MBUS_FMT_SGRBG10_1X10,
47 V4L2_MBUS_FMT_SRGGB10_1X10,
48 V4L2_MBUS_FMT_SBGGR10_1X10,
49 V4L2_MBUS_FMT_SGBRG10_1X10,
50 V4L2_MBUS_FMT_SGRBG12_1X12,
51 V4L2_MBUS_FMT_SRGGB12_1X12,
52 V4L2_MBUS_FMT_SBGGR12_1X12,
53 V4L2_MBUS_FMT_SGBRG12_1X12,
c51364ca
LP		 54 V4L2_MBUS_FMT_YUYV8_2X8,
55 V4L2_MBUS_FMT_UYVY8_2X8,
de1135d4
LP		 56};
57
58/*
59 * ccdc_print_status - Print current CCDC Module register values.
60 * @ccdc: Pointer to ISP CCDC device.
61 *
62 * Also prints other debug information stored in the CCDC module.
63 */
64#define CCDC_PRINT_REGISTER(isp, name)\
65 dev_dbg(isp->dev, "###CCDC " #name "=0x%08x\n", \
66 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_##name))
67
68static void ccdc_print_status(struct isp_ccdc_device *ccdc)
69{
70 struct isp_device *isp = to_isp_device(ccdc);
71
72 dev_dbg(isp->dev, "-------------CCDC Register dump-------------\n");
73
74 CCDC_PRINT_REGISTER(isp, PCR);
75 CCDC_PRINT_REGISTER(isp, SYN_MODE);
76 CCDC_PRINT_REGISTER(isp, HD_VD_WID);
77 CCDC_PRINT_REGISTER(isp, PIX_LINES);
78 CCDC_PRINT_REGISTER(isp, HORZ_INFO);
79 CCDC_PRINT_REGISTER(isp, VERT_START);
80 CCDC_PRINT_REGISTER(isp, VERT_LINES);
81 CCDC_PRINT_REGISTER(isp, CULLING);
82 CCDC_PRINT_REGISTER(isp, HSIZE_OFF);
83 CCDC_PRINT_REGISTER(isp, SDOFST);
84 CCDC_PRINT_REGISTER(isp, SDR_ADDR);
85 CCDC_PRINT_REGISTER(isp, CLAMP);
86 CCDC_PRINT_REGISTER(isp, DCSUB);
87 CCDC_PRINT_REGISTER(isp, COLPTN);
88 CCDC_PRINT_REGISTER(isp, BLKCMP);
89 CCDC_PRINT_REGISTER(isp, FPC);
90 CCDC_PRINT_REGISTER(isp, FPC_ADDR);
91 CCDC_PRINT_REGISTER(isp, VDINT);
92 CCDC_PRINT_REGISTER(isp, ALAW);
93 CCDC_PRINT_REGISTER(isp, REC656IF);
94 CCDC_PRINT_REGISTER(isp, CFG);
95 CCDC_PRINT_REGISTER(isp, FMTCFG);
96 CCDC_PRINT_REGISTER(isp, FMT_HORZ);
97 CCDC_PRINT_REGISTER(isp, FMT_VERT);
98 CCDC_PRINT_REGISTER(isp, PRGEVEN0);
99 CCDC_PRINT_REGISTER(isp, PRGEVEN1);
100 CCDC_PRINT_REGISTER(isp, PRGODD0);
101 CCDC_PRINT_REGISTER(isp, PRGODD1);
102 CCDC_PRINT_REGISTER(isp, VP_OUT);
103 CCDC_PRINT_REGISTER(isp, LSC_CONFIG);
104 CCDC_PRINT_REGISTER(isp, LSC_INITIAL);
105 CCDC_PRINT_REGISTER(isp, LSC_TABLE_BASE);
106 CCDC_PRINT_REGISTER(isp, LSC_TABLE_OFFSET);
107
108 dev_dbg(isp->dev, "--------------------------------------------\n");
109}
110
111/*
112 * omap3isp_ccdc_busy - Get busy state of the CCDC.
113 * @ccdc: Pointer to ISP CCDC device.
114 */
115int omap3isp_ccdc_busy(struct isp_ccdc_device *ccdc)
116{
117 struct isp_device *isp = to_isp_device(ccdc);
118
119 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
120 ISPCCDC_PCR_BUSY;
121}
122
123/* -----------------------------------------------------------------------------
124 * Lens Shading Compensation
125 */
126
127/*
128 * ccdc_lsc_validate_config - Check that LSC configuration is valid.
129 * @ccdc: Pointer to ISP CCDC device.
130 * @lsc_cfg: the LSC configuration to check.
131 *
132 * Returns 0 if the LSC configuration is valid, or -EINVAL if invalid.
133 */
134static int ccdc_lsc_validate_config(struct isp_ccdc_device *ccdc,
135 struct omap3isp_ccdc_lsc_config *lsc_cfg)
136{
137 struct isp_device *isp = to_isp_device(ccdc);
138 struct v4l2_mbus_framefmt *format;
139 unsigned int paxel_width, paxel_height;
140 unsigned int paxel_shift_x, paxel_shift_y;
141 unsigned int min_width, min_height, min_size;
142 unsigned int input_width, input_height;
143
144 paxel_shift_x = lsc_cfg->gain_mode_m;
145 paxel_shift_y = lsc_cfg->gain_mode_n;
146
147 if ((paxel_shift_x < 2) || (paxel_shift_x > 6) ||
148 (paxel_shift_y < 2) || (paxel_shift_y > 6)) {
149 dev_dbg(isp->dev, "CCDC: LSC: Invalid paxel size\n");
150 return -EINVAL;
151 }
152
153 if (lsc_cfg->offset & 3) {
154 dev_dbg(isp->dev, "CCDC: LSC: Offset must be a multiple of "
155 "4\n");
156 return -EINVAL;
157 }
158
159 if ((lsc_cfg->initial_x & 1) || (lsc_cfg->initial_y & 1)) {
160 dev_dbg(isp->dev, "CCDC: LSC: initial_x and y must be even\n");
161 return -EINVAL;
162 }
163
164 format = __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
165 V4L2_SUBDEV_FORMAT_ACTIVE);
166 input_width = format->width;
167 input_height = format->height;
168
169 /* Calculate minimum bytesize for validation */
170 paxel_width = 1 << paxel_shift_x;
171 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1)
172 >> paxel_shift_x) + 1;
173
174 paxel_height = 1 << paxel_shift_y;
175 min_height = ((input_height + lsc_cfg->initial_y + paxel_height - 1)
176 >> paxel_shift_y) + 1;
177
178 min_size = 4 * min_width * min_height;
179 if (min_size > lsc_cfg->size) {
180 dev_dbg(isp->dev, "CCDC: LSC: too small table\n");
181 return -EINVAL;
182 }
183 if (lsc_cfg->offset < (min_width * 4)) {
184 dev_dbg(isp->dev, "CCDC: LSC: Offset is too small\n");
185 return -EINVAL;
186 }
187 if ((lsc_cfg->size / lsc_cfg->offset) < min_height) {
188 dev_dbg(isp->dev, "CCDC: LSC: Wrong size/offset combination\n");
189 return -EINVAL;
190 }
191 return 0;
192}
193
194/*
195 * ccdc_lsc_program_table - Program Lens Shading Compensation table address.
196 * @ccdc: Pointer to ISP CCDC device.
197 */
d33186d0
LP		 198static void ccdc_lsc_program_table(struct isp_ccdc_device *ccdc,
199 dma_addr_t addr)
de1135d4
LP		 200{
201 isp_reg_writel(to_isp_device(ccdc), addr,
202 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
203}
204
205/*
206 * ccdc_lsc_setup_regs - Configures the lens shading compensation module
207 * @ccdc: Pointer to ISP CCDC device.
208 */
209static void ccdc_lsc_setup_regs(struct isp_ccdc_device *ccdc,
210 struct omap3isp_ccdc_lsc_config *cfg)
211{
212 struct isp_device *isp = to_isp_device(ccdc);
213 int reg;
214
215 isp_reg_writel(isp, cfg->offset, OMAP3_ISP_IOMEM_CCDC,
216 ISPCCDC_LSC_TABLE_OFFSET);
217
218 reg = 0;
219 reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
220 reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
221 reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
222 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
223
224 reg = 0;
225 reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
226 reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
227 reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
228 reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
229 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC,
230 ISPCCDC_LSC_INITIAL);
231}
232
233static int ccdc_lsc_wait_prefetch(struct isp_ccdc_device *ccdc)
234{
235 struct isp_device *isp = to_isp_device(ccdc);
236 unsigned int wait;
237
238 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
239 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
240
241 /* timeout 1 ms */
242 for (wait = 0; wait < 1000; wait++) {
243 if (isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS) &
244 IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ) {
245 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
246 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
247 return 0;
248 }
249
250 rmb();
251 udelay(1);
252 }
253
254 return -ETIMEDOUT;
255}
256
257/*
258 * __ccdc_lsc_enable - Enables/Disables the Lens Shading Compensation module.
259 * @ccdc: Pointer to ISP CCDC device.
260 * @enable: 0 Disables LSC, 1 Enables LSC.
261 */
262static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable)
263{
264 struct isp_device *isp = to_isp_device(ccdc);
265 const struct v4l2_mbus_framefmt *format =
266 __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
267 V4L2_SUBDEV_FORMAT_ACTIVE);
268
269 if ((format->code != V4L2_MBUS_FMT_SGRBG10_1X10) &&
270 (format->code != V4L2_MBUS_FMT_SRGGB10_1X10) &&
271 (format->code != V4L2_MBUS_FMT_SBGGR10_1X10) &&
272 (format->code != V4L2_MBUS_FMT_SGBRG10_1X10))
273 return -EINVAL;
274
275 if (enable)
276 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_LSC_READ);
277
278 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
279 ISPCCDC_LSC_ENABLE, enable ? ISPCCDC_LSC_ENABLE : 0);
280
281 if (enable) {
282 if (ccdc_lsc_wait_prefetch(ccdc) < 0) {
283 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC,
284 ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE);
285 ccdc->lsc.state = LSC_STATE_STOPPED;
25aeb418 286 dev_warn(to_device(ccdc), "LSC prefetch timeout\n");
de1135d4
LP		 287 return -ETIMEDOUT;
288 }
289 ccdc->lsc.state = LSC_STATE_RUNNING;
290 } else {
291 ccdc->lsc.state = LSC_STATE_STOPPING;
292 }
293
294 return 0;
295}
296
297static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
298{
299 struct isp_device *isp = to_isp_device(ccdc);
300
301 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG) &
302 ISPCCDC_LSC_BUSY;
303}
304
305/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
306 * @ccdc: Pointer to ISP CCDC device
307 * @req: New configuration request
308 *
309 * context: in_interrupt()
310 */
311static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
312 struct ispccdc_lsc_config_req *req)
313{
314 if (!req->enable)
315 return -EINVAL;
316
317 if (ccdc_lsc_validate_config(ccdc, &req->config) < 0) {
318 dev_dbg(to_device(ccdc), "Discard LSC configuration\n");
319 return -EINVAL;
320 }
321
322 if (ccdc_lsc_busy(ccdc))
323 return -EBUSY;
324
325 ccdc_lsc_setup_regs(ccdc, &req->config);
d33186d0 326 ccdc_lsc_program_table(ccdc, req->table.dma);
de1135d4
LP		 327 return 0;
328}
329
330/*
331 * ccdc_lsc_error_handler - Handle LSC prefetch error scenario.
332 * @ccdc: Pointer to ISP CCDC device.
333 *
334 * Disables LSC, and defers enablement to shadow registers update time.
335 */
336static void ccdc_lsc_error_handler(struct isp_ccdc_device *ccdc)
337{
338 struct isp_device *isp = to_isp_device(ccdc);
339 /*
340 * From OMAP3 TRM: When this event is pending, the module
341 * goes into transparent mode (output =input). Normal
342 * operation can be resumed at the start of the next frame
343 * after:
344 * 1) Clearing this event
345 * 2) Disabling the LSC module
346 * 3) Enabling it
347 */
348 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
349 ISPCCDC_LSC_ENABLE);
350 ccdc->lsc.state = LSC_STATE_STOPPED;
351}
352
353static void ccdc_lsc_free_request(struct isp_ccdc_device *ccdc,
354 struct ispccdc_lsc_config_req *req)
355{
356 struct isp_device *isp = to_isp_device(ccdc);
357
358 if (req == NULL)
359 return;
360
d33186d0
LP		 361 if (req->table.addr) {
362 sg_free_table(&req->table.sgt);
363 dma_free_coherent(isp->dev, req->config.size, req->table.addr,
364 req->table.dma);
365 }
366
de1135d4
LP		 367 kfree(req);
368}
369
370static void ccdc_lsc_free_queue(struct isp_ccdc_device *ccdc,
371 struct list_head *queue)
372{
373 struct ispccdc_lsc_config_req *req, *n;
374 unsigned long flags;
375
376 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
377 list_for_each_entry_safe(req, n, queue, list) {
378 list_del(&req->list);
379 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
380 ccdc_lsc_free_request(ccdc, req);
381 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
382 }
383 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
384}
385
386static void ccdc_lsc_free_table_work(struct work_struct *work)
387{
388 struct isp_ccdc_device *ccdc;
389 struct ispccdc_lsc *lsc;
390
391 lsc = container_of(work, struct ispccdc_lsc, table_work);
392 ccdc = container_of(lsc, struct isp_ccdc_device, lsc);
393
394 ccdc_lsc_free_queue(ccdc, &lsc->free_queue);
395}
396
397/*
398 * ccdc_lsc_config - Configure the LSC module from a userspace request
399 *
400 * Store the request LSC configuration in the LSC engine request pointer. The
401 * configuration will be applied to the hardware when the CCDC will be enabled,
402 * or at the next LSC interrupt if the CCDC is already running.
403 */
404static int ccdc_lsc_config(struct isp_ccdc_device *ccdc,
405 struct omap3isp_ccdc_update_config *config)
406{
407 struct isp_device *isp = to_isp_device(ccdc);
408 struct ispccdc_lsc_config_req *req;
409 unsigned long flags;
de1135d4
LP		 410 u16 update;
411 int ret;
412
413 update = config->update &
414 (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC);
415 if (!update)
416 return 0;
417
418 if (update != (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC)) {
419 dev_dbg(to_device(ccdc), "%s: Both LSC configuration and table "
420 "need to be supplied\n", __func__);
421 return -EINVAL;
422 }
423
424 req = kzalloc(sizeof(*req), GFP_KERNEL);
425 if (req == NULL)
426 return -ENOMEM;
427
428 if (config->flag & OMAP3ISP_CCDC_CONFIG_LSC) {
429 if (copy_from_user(&req->config, config->lsc_cfg,
430 sizeof(req->config))) {
431 ret = -EFAULT;
432 goto done;
433 }
434
435 req->enable = 1;
436
d33186d0
LP		 437 req->table.addr = dma_alloc_coherent(isp->dev, req->config.size,
438 &req->table.dma,
439 GFP_KERNEL);
440 if (req->table.addr == NULL) {
de1135d4
LP		 441 ret = -ENOMEM;
442 goto done;
443 }
444
d33186d0
LP		 445 ret = dma_get_sgtable(isp->dev, &req->table.sgt,
446 req->table.addr, req->table.dma,
447 req->config.size);
448 if (ret < 0)
de1135d4 449 goto done;
de1135d4 450
d33186d0
LP		 451 dma_sync_sg_for_cpu(isp->dev, req->table.sgt.sgl,
452 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4 453
d33186d0
LP		 454 if (copy_from_user(req->table.addr, config->lsc,
455 req->config.size)) {
de1135d4
LP		 456 ret = -EFAULT;
457 goto done;
458 }
459
d33186d0
LP		 460 dma_sync_sg_for_device(isp->dev, req->table.sgt.sgl,
461 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4
LP		 462 }
463
464 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
465 if (ccdc->lsc.request) {
466 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
467 schedule_work(&ccdc->lsc.table_work);
468 }
469 ccdc->lsc.request = req;
470 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
471
472 ret = 0;
473
474done:
475 if (ret < 0)
476 ccdc_lsc_free_request(ccdc, req);
477
478 return ret;
479}
480
481static inline int ccdc_lsc_is_configured(struct isp_ccdc_device *ccdc)
482{
483 unsigned long flags;
484
485 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
486 if (ccdc->lsc.active) {
487 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
488 return 1;
489 }
490 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
491 return 0;
492}
493
494static int ccdc_lsc_enable(struct isp_ccdc_device *ccdc)
495{
496 struct ispccdc_lsc *lsc = &ccdc->lsc;
497
498 if (lsc->state != LSC_STATE_STOPPED)
499 return -EINVAL;
500
501 if (lsc->active) {
502 list_add_tail(&lsc->active->list, &lsc->free_queue);
503 lsc->active = NULL;
504 }
505
506 if (__ccdc_lsc_configure(ccdc, lsc->request) < 0) {
507 omap3isp_sbl_disable(to_isp_device(ccdc),
508 OMAP3_ISP_SBL_CCDC_LSC_READ);
509 list_add_tail(&lsc->request->list, &lsc->free_queue);
510 lsc->request = NULL;
511 goto done;
512 }
513
514 lsc->active = lsc->request;
515 lsc->request = NULL;
516 __ccdc_lsc_enable(ccdc, 1);
517
518done:
519 if (!list_empty(&lsc->free_queue))
520 schedule_work(&lsc->table_work);
521
522 return 0;
523}
524
525/* -----------------------------------------------------------------------------
526 * Parameters configuration
527 */
528
529/*
530 * ccdc_configure_clamp - Configure optical-black or digital clamping
531 * @ccdc: Pointer to ISP CCDC device.
532 *
533 * The CCDC performs either optical-black or digital clamp. Configure and enable
534 * the selected clamp method.
535 */
536static void ccdc_configure_clamp(struct isp_ccdc_device *ccdc)
537{
538 struct isp_device *isp = to_isp_device(ccdc);
539 u32 clamp;
540
541 if (ccdc->obclamp) {
542 clamp = ccdc->clamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
543 clamp |= ccdc->clamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
544 clamp |= ccdc->clamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
545 clamp |= ccdc->clamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
546 isp_reg_writel(isp, clamp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP);
547 } else {
548 isp_reg_writel(isp, ccdc->clamp.dcsubval,
549 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB);
550 }
551
552 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
553 ISPCCDC_CLAMP_CLAMPEN,
554 ccdc->obclamp ? ISPCCDC_CLAMP_CLAMPEN : 0);
555}
556
557/*
558 * ccdc_configure_fpc - Configure Faulty Pixel Correction
559 * @ccdc: Pointer to ISP CCDC device.
560 */
561static void ccdc_configure_fpc(struct isp_ccdc_device *ccdc)
562{
563 struct isp_device *isp = to_isp_device(ccdc);
564
565 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, ISPCCDC_FPC_FPCEN);
566
567 if (!ccdc->fpc_en)
568 return;
569
c60e153d 570 isp_reg_writel(isp, ccdc->fpc.dma, OMAP3_ISP_IOMEM_CCDC,
de1135d4
LP		 571 ISPCCDC_FPC_ADDR);
572 /* The FPNUM field must be set before enabling FPC. */
573 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
574 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
575 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT) |
576 ISPCCDC_FPC_FPCEN, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
577}
578
579/*
580 * ccdc_configure_black_comp - Configure Black Level Compensation.
581 * @ccdc: Pointer to ISP CCDC device.
582 */
583static void ccdc_configure_black_comp(struct isp_ccdc_device *ccdc)
584{
585 struct isp_device *isp = to_isp_device(ccdc);
586 u32 blcomp;
587
588 blcomp = ccdc->blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
589 blcomp |= ccdc->blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
590 blcomp |= ccdc->blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
591 blcomp |= ccdc->blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
592
593 isp_reg_writel(isp, blcomp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
594}
595
596/*
597 * ccdc_configure_lpf - Configure Low-Pass Filter (LPF).
598 * @ccdc: Pointer to ISP CCDC device.
599 */
600static void ccdc_configure_lpf(struct isp_ccdc_device *ccdc)
601{
602 struct isp_device *isp = to_isp_device(ccdc);
603
604 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
605 ISPCCDC_SYN_MODE_LPF,
606 ccdc->lpf ? ISPCCDC_SYN_MODE_LPF : 0);
607}
608
609/*
610 * ccdc_configure_alaw - Configure A-law compression.
611 * @ccdc: Pointer to ISP CCDC device.
612 */
613static void ccdc_configure_alaw(struct isp_ccdc_device *ccdc)
614{
615 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 616 const struct isp_format_info *info;
de1135d4
LP		 617 u32 alaw = 0;
618
73ea57eb
LP		 619 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
620
621 switch (info->width) {
de1135d4
LP		 622 case 8:
623 return;
624
625 case 10:
626 alaw = ISPCCDC_ALAW_GWDI_9_0;
627 break;
628 case 11:
629 alaw = ISPCCDC_ALAW_GWDI_10_1;
630 break;
631 case 12:
632 alaw = ISPCCDC_ALAW_GWDI_11_2;
633 break;
634 case 13:
635 alaw = ISPCCDC_ALAW_GWDI_12_3;
636 break;
637 }
638
639 if (ccdc->alaw)
640 alaw |= ISPCCDC_ALAW_CCDTBL;
641
642 isp_reg_writel(isp, alaw, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
643}
644
645/*
646 * ccdc_config_imgattr - Configure sensor image specific attributes.
647 * @ccdc: Pointer to ISP CCDC device.
648 * @colptn: Color pattern of the sensor.
649 */
650static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn)
651{
652 struct isp_device *isp = to_isp_device(ccdc);
653
654 isp_reg_writel(isp, colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
655}
656
657/*
658 * ccdc_config - Set CCDC configuration from userspace
659 * @ccdc: Pointer to ISP CCDC device.
872aba51 660 * @ccdc_struct: Structure containing CCDC configuration sent from userspace.
de1135d4
LP		 661 *
662 * Returns 0 if successful, -EINVAL if the pointer to the configuration
663 * structure is null, or the copy_from_user function fails to copy user space
664 * memory to kernel space memory.
665 */
666static int ccdc_config(struct isp_ccdc_device *ccdc,
667 struct omap3isp_ccdc_update_config *ccdc_struct)
668{
669 struct isp_device *isp = to_isp_device(ccdc);
670 unsigned long flags;
671
672 spin_lock_irqsave(&ccdc->lock, flags);
673 ccdc->shadow_update = 1;
674 spin_unlock_irqrestore(&ccdc->lock, flags);
675
676 if (OMAP3ISP_CCDC_ALAW & ccdc_struct->update) {
677 ccdc->alaw = !!(OMAP3ISP_CCDC_ALAW & ccdc_struct->flag);
678 ccdc->update |= OMAP3ISP_CCDC_ALAW;
679 }
680
681 if (OMAP3ISP_CCDC_LPF & ccdc_struct->update) {
682 ccdc->lpf = !!(OMAP3ISP_CCDC_LPF & ccdc_struct->flag);
683 ccdc->update |= OMAP3ISP_CCDC_LPF;
684 }
685
686 if (OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->update) {
687 if (copy_from_user(&ccdc->clamp, ccdc_struct->bclamp,
688 sizeof(ccdc->clamp))) {
689 ccdc->shadow_update = 0;
690 return -EFAULT;
691 }
692
693 ccdc->obclamp = !!(OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->flag);
694 ccdc->update |= OMAP3ISP_CCDC_BLCLAMP;
695 }
696
697 if (OMAP3ISP_CCDC_BCOMP & ccdc_struct->update) {
698 if (copy_from_user(&ccdc->blcomp, ccdc_struct->blcomp,
699 sizeof(ccdc->blcomp))) {
700 ccdc->shadow_update = 0;
701 return -EFAULT;
702 }
703
704 ccdc->update |= OMAP3ISP_CCDC_BCOMP;
705 }
706
707 ccdc->shadow_update = 0;
708
709 if (OMAP3ISP_CCDC_FPC & ccdc_struct->update) {
c60e153d
LP		 710 struct omap3isp_ccdc_fpc fpc;
711 struct ispccdc_fpc fpc_old = { .addr = NULL, };
712 struct ispccdc_fpc fpc_new;
de1135d4
LP		 713 u32 size;
714
715 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
716 return -EBUSY;
717
718 ccdc->fpc_en = !!(OMAP3ISP_CCDC_FPC & ccdc_struct->flag);
719
720 if (ccdc->fpc_en) {
c60e153d 721 if (copy_from_user(&fpc, ccdc_struct->fpc, sizeof(fpc)))
de1135d4
LP		 722 return -EFAULT;
723
c60e153d
LP		 724 size = fpc.fpnum * 4;
725
de1135d4 726 /*
c60e153d
LP		 727 * The table address must be 64-bytes aligned, which is
728 * guaranteed by dma_alloc_coherent().
de1135d4 729 */
c60e153d
LP		 730 fpc_new.fpnum = fpc.fpnum;
731 fpc_new.addr = dma_alloc_coherent(isp->dev, size,
732 &fpc_new.dma,
733 GFP_KERNEL);
734 if (fpc_new.addr == NULL)
de1135d4
LP		 735 return -ENOMEM;
736
c60e153d
LP		 737 if (copy_from_user(fpc_new.addr,
738 (__force void __user *)fpc.fpcaddr,
739 size)) {
740 dma_free_coherent(isp->dev, size, fpc_new.addr,
741 fpc_new.dma);
de1135d4
LP		 742 return -EFAULT;
743 }
744
c60e153d
LP		 745 fpc_old = ccdc->fpc;
746 ccdc->fpc = fpc_new;
de1135d4
LP		 747 }
748
749 ccdc_configure_fpc(ccdc);
c60e153d
LP		 750
751 if (fpc_old.addr != NULL)
752 dma_free_coherent(isp->dev, fpc_old.fpnum * 4,
753 fpc_old.addr, fpc_old.dma);
de1135d4
LP		 754 }
755
756 return ccdc_lsc_config(ccdc, ccdc_struct);
757}
758
759static void ccdc_apply_controls(struct isp_ccdc_device *ccdc)
760{
761 if (ccdc->update & OMAP3ISP_CCDC_ALAW) {
762 ccdc_configure_alaw(ccdc);
763 ccdc->update &= ~OMAP3ISP_CCDC_ALAW;
764 }
765
766 if (ccdc->update & OMAP3ISP_CCDC_LPF) {
767 ccdc_configure_lpf(ccdc);
768 ccdc->update &= ~OMAP3ISP_CCDC_LPF;
769 }
770
771 if (ccdc->update & OMAP3ISP_CCDC_BLCLAMP) {
772 ccdc_configure_clamp(ccdc);
773 ccdc->update &= ~OMAP3ISP_CCDC_BLCLAMP;
774 }
775
776 if (ccdc->update & OMAP3ISP_CCDC_BCOMP) {
777 ccdc_configure_black_comp(ccdc);
778 ccdc->update &= ~OMAP3ISP_CCDC_BCOMP;
779 }
780}
781
782/*
783 * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers
872aba51 784 * @isp: Pointer to ISP device
de1135d4
LP		 785 */
786void omap3isp_ccdc_restore_context(struct isp_device *isp)
787{
788 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
789
790 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
791
792 ccdc->update = OMAP3ISP_CCDC_ALAW | OMAP3ISP_CCDC_LPF
793 | OMAP3ISP_CCDC_BLCLAMP | OMAP3ISP_CCDC_BCOMP;
794 ccdc_apply_controls(ccdc);
795 ccdc_configure_fpc(ccdc);
796}
797
798/* -----------------------------------------------------------------------------
799 * Format- and pipeline-related configuration helpers
800 */
801
802/*
803 * ccdc_config_vp - Configure the Video Port.
804 * @ccdc: Pointer to ISP CCDC device.
805 */
806static void ccdc_config_vp(struct isp_ccdc_device *ccdc)
807{
808 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
809 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 810 const struct isp_format_info *info;
de1135d4
LP		 811 unsigned long l3_ick = pipe->l3_ick;
812 unsigned int max_div = isp->revision == ISP_REVISION_15_0 ? 64 : 8;
813 unsigned int div = 0;
814 u32 fmtcfg_vp;
815
816 fmtcfg_vp = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG)
817 & ~(ISPCCDC_FMTCFG_VPIN_MASK | ISPCCDC_FMTCFG_VPIF_FRQ_MASK);
818
73ea57eb
LP		 819 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
820
821 switch (info->width) {
de1135d4
LP		 822 case 8:
823 case 10:
824 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_9_0;
825 break;
826 case 11:
827 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_10_1;
828 break;
829 case 12:
830 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_11_2;
831 break;
832 case 13:
833 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_12_3;
834 break;
13eaaa7f 835 }
de1135d4
LP		 836
837 if (pipe->input)
838 div = DIV_ROUND_UP(l3_ick, pipe->max_rate);
c6c01f97
SA		 839 else if (pipe->external_rate)
840 div = l3_ick / pipe->external_rate;
de1135d4
LP		 841
842 div = clamp(div, 2U, max_div);
843 fmtcfg_vp |= (div - 2) << ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT;
844
845 isp_reg_writel(isp, fmtcfg_vp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
846}
847
848/*
849 * ccdc_enable_vp - Enable Video Port.
850 * @ccdc: Pointer to ISP CCDC device.
851 * @enable: 0 Disables VP, 1 Enables VP
852 *
853 * This is needed for outputting image to Preview, H3A and HIST ISP submodules.
854 */
855static void ccdc_enable_vp(struct isp_ccdc_device *ccdc, u8 enable)
856{
857 struct isp_device *isp = to_isp_device(ccdc);
858
859 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG,
860 ISPCCDC_FMTCFG_VPEN, enable ? ISPCCDC_FMTCFG_VPEN : 0);
861}
862
863/*
864 * ccdc_config_outlineoffset - Configure memory saving output line offset
865 * @ccdc: Pointer to ISP CCDC device.
bcb4e0ef
LP		 866 * @bpl: Number of bytes per line when stored in memory.
867 * @field: Field order when storing interlaced formats in memory.
de1135d4 868 *
bcb4e0ef
LP		 869 * Configure the offsets for the line output control:
870 *
871 * - The horizontal line offset is defined as the number of bytes between the
872 * start of two consecutive lines in memory. Set it to the given bytes per
873 * line value.
874 *
875 * - The field offset value is defined as the number of lines to offset the
876 * start of the field identified by FID = 1. Set it to one.
877 *
878 * - The line offset values are defined as the number of lines (as defined by
879 * the horizontal line offset) between the start of two consecutive lines for
880 * all combinations of odd/even lines in odd/even fields. When interleaving
881 * fields set them all to two lines, and to one line otherwise.
de1135d4
LP		 882 */
883static void ccdc_config_outlineoffset(struct isp_ccdc_device *ccdc,
bcb4e0ef
LP		 884 unsigned int bpl,
885 enum v4l2_field field)
de1135d4
LP		 886{
887 struct isp_device *isp = to_isp_device(ccdc);
bcb4e0ef 888 u32 sdofst = 0;
de1135d4 889
bcb4e0ef
LP		 890 isp_reg_writel(isp, bpl & 0xffff, OMAP3_ISP_IOMEM_CCDC,
891 ISPCCDC_HSIZE_OFF);
de1135d4 892
bcb4e0ef
LP		 893 switch (field) {
894 case V4L2_FIELD_INTERLACED_TB:
895 case V4L2_FIELD_INTERLACED_BT:
896 /* When interleaving fields in memory offset field one by one
897 * line and set the line offset to two lines.
898 */
899 sdofst |= (1 << ISPCCDC_SDOFST_LOFST0_SHIFT)
900 | (1 << ISPCCDC_SDOFST_LOFST1_SHIFT)
901 | (1 << ISPCCDC_SDOFST_LOFST2_SHIFT)
902 | (1 << ISPCCDC_SDOFST_LOFST3_SHIFT);
de1135d4 903 break;
bcb4e0ef 904
de1135d4 905 default:
bcb4e0ef 906 /* In all other cases set the line offsets to one line. */
de1135d4
LP		 907 break;
908 }
bcb4e0ef
LP		 909
910 isp_reg_writel(isp, sdofst, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST);
de1135d4
LP		 911}
912
913/*
914 * ccdc_set_outaddr - Set memory address to save output image
915 * @ccdc: Pointer to ISP CCDC device.
916 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
917 *
918 * Sets the memory address where the output will be saved.
919 */
920static void ccdc_set_outaddr(struct isp_ccdc_device *ccdc, u32 addr)
921{
922 struct isp_device *isp = to_isp_device(ccdc);
923
924 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
925}
926
927/*
928 * omap3isp_ccdc_max_rate - Calculate maximum input data rate based on the input
929 * @ccdc: Pointer to ISP CCDC device.
930 * @max_rate: Maximum calculated data rate.
931 *
932 * Returns in *max_rate less value between calculated and passed
933 */
934void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
935 unsigned int *max_rate)
936{
937 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
938 unsigned int rate;
939
940 if (pipe == NULL)
941 return;
942
943 /*
944 * TRM says that for parallel sensors the maximum data rate
945 * should be 90% form L3/2 clock, otherwise just L3/2.
946 */
947 if (ccdc->input == CCDC_INPUT_PARALLEL)
948 rate = pipe->l3_ick / 2 * 9 / 10;
949 else
950 rate = pipe->l3_ick / 2;
951
952 *max_rate = min(*max_rate, rate);
953}
954
955/*
956 * ccdc_config_sync_if - Set CCDC sync interface configuration
957 * @ccdc: Pointer to ISP CCDC device.
73ea57eb
LP		 958 * @pdata: Parallel interface platform data (may be NULL)
959 * @data_size: Data size
de1135d4
LP		 960 */
961static void ccdc_config_sync_if(struct isp_ccdc_device *ccdc,
73ea57eb
LP		 962 struct isp_parallel_platform_data *pdata,
963 unsigned int data_size)
de1135d4
LP		 964{
965 struct isp_device *isp = to_isp_device(ccdc);
c51364ca 966 const struct v4l2_mbus_framefmt *format;
cf7a3d91 967 u32 syn_mode = ISPCCDC_SYN_MODE_VDHDEN;
de1135d4 968
c51364ca
LP		 969 format = &ccdc->formats[CCDC_PAD_SINK];
970
971 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
972 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
9de7af4d
LP		 973 /* According to the OMAP3 TRM the input mode only affects SYNC
974 * mode, enabling BT.656 mode should take precedence. However,
975 * in practice setting the input mode to YCbCr data on 8 bits
976 * seems to be required in BT.656 mode. In SYNC mode set it to
977 * YCbCr on 16 bits as the bridge is enabled in that case.
c51364ca 978 */
9de7af4d
LP		 979 if (ccdc->bt656)
980 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
981 else
982 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
c51364ca
LP		 983 }
984
73ea57eb 985 switch (data_size) {
de1135d4
LP		 986 case 8:
987 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
988 break;
989 case 10:
990 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
991 break;
992 case 11:
993 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
994 break;
995 case 12:
996 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
997 break;
13eaaa7f 998 }
de1135d4 999
73ea57eb 1000 if (pdata && pdata->data_pol)
de1135d4 1001 syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
de1135d4 1002
73ea57eb 1003 if (pdata && pdata->hs_pol)
de1135d4 1004 syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
de1135d4 1005
9de7af4d
LP		 1006 /* The polarity of the vertical sync signal output by the BT.656
1007 * decoder is not documented and seems to be active low.
1008 */
1009 if ((pdata && pdata->vs_pol) || ccdc->bt656)
de1135d4 1010 syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
de1135d4 1011
9a36d8ed
LP		 1012 if (pdata && pdata->fld_pol)
1013 syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
1014
de1135d4 1015 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
c51364ca
LP		 1016
1017 /* The CCDC_CFG.Y8POS bit is used in YCbCr8 input mode only. The
1018 * hardware seems to ignore it in all other input modes.
1019 */
1020 if (format->code == V4L2_MBUS_FMT_UYVY8_2X8)
1021 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1022 ISPCCDC_CFG_Y8POS);
1023 else
1024 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1025 ISPCCDC_CFG_Y8POS);
1026
9de7af4d
LP		 1027 /* Enable or disable BT.656 mode, including error correction for the
1028 * synchronization codes.
1029 */
1030 if (ccdc->bt656)
1031 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1032 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1033 else
1034 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1035 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1036
de1135d4
LP		 1037}
1038
1039/* CCDC formats descriptions */
1040static const u32 ccdc_sgrbg_pattern =
1041 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1042 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1043 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1044 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1045 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1046 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1047 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1048 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1049 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1050 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1051 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1052 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1053 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1054 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1055 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1056 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1057
1058static const u32 ccdc_srggb_pattern =
1059 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1060 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1061 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1062 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1063 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1064 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1065 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1066 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1067 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1068 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1069 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1070 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1071 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1072 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1073 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1074 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1075
1076static const u32 ccdc_sbggr_pattern =
1077 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1078 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1079 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1080 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1081 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1082 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1083 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1084 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1085 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1086 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1087 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1088 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1089 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1090 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1091 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1092 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1093
1094static const u32 ccdc_sgbrg_pattern =
1095 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1096 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1097 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1098 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1099 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1100 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1101 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1102 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1103 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1104 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1105 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1106 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1107 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1108 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1109 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1110 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1111
1112static void ccdc_configure(struct isp_ccdc_device *ccdc)
1113{
1114 struct isp_device *isp = to_isp_device(ccdc);
1115 struct isp_parallel_platform_data *pdata = NULL;
1116 struct v4l2_subdev *sensor;
1117 struct v4l2_mbus_framefmt *format;
a64909b8 1118 const struct v4l2_rect *crop;
c09af044
MJ		 1119 const struct isp_format_info *fmt_info;
1120 struct v4l2_subdev_format fmt_src;
1121 unsigned int depth_out;
1122 unsigned int depth_in = 0;
de1135d4
LP		 1123 struct media_pad *pad;
1124 unsigned long flags;
c51364ca 1125 unsigned int bridge;
c09af044 1126 unsigned int shift;
9de7af4d
LP		 1127 unsigned int nph;
1128 unsigned int sph;
de1135d4
LP		 1129 u32 syn_mode;
1130 u32 ccdc_pattern;
1131
9de7af4d
LP		 1132 ccdc->bt656 = false;
1133
1bddf1b3 1134 pad = media_entity_remote_pad(&ccdc->pads[CCDC_PAD_SINK]);
c09af044 1135 sensor = media_entity_to_v4l2_subdev(pad->entity);
9de7af4d
LP		 1136 if (ccdc->input == CCDC_INPUT_PARALLEL) {
1137 struct v4l2_mbus_config cfg;
1138 int ret;
1139
1140 ret = v4l2_subdev_call(sensor, video, g_mbus_config, &cfg);
1141 if (!ret)
1142 ccdc->bt656 = cfg.type == V4L2_MBUS_BT656;
1143
de1135d4
LP		 1144 pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
1145 ->bus.parallel;
9de7af4d 1146 }
c09af044 1147
2e8f0172
LP		 1148 /* CCDC_PAD_SINK */
1149 format = &ccdc->formats[CCDC_PAD_SINK];
1150
c51364ca 1151 /* Compute the lane shifter shift value and enable the bridge when the
9de7af4d 1152 * input format is a non-BT.656 YUV variant.
c51364ca 1153 */
c09af044
MJ		 1154 fmt_src.pad = pad->index;
1155 fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1156 if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
1157 fmt_info = omap3isp_video_format_info(fmt_src.format.code);
1697e49a 1158 depth_in = fmt_info->width;
de1135d4
LP		 1159 }
1160
2e8f0172 1161 fmt_info = omap3isp_video_format_info(format->code);
1697e49a 1162 depth_out = fmt_info->width;
c09af044 1163 shift = depth_in - depth_out;
de1135d4 1164
9de7af4d
LP		 1165 if (ccdc->bt656)
1166 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
1167 else if (fmt_info->code == V4L2_MBUS_FMT_YUYV8_2X8)
c51364ca
LP		 1168 bridge = ISPCTRL_PAR_BRIDGE_LENDIAN;
1169 else if (fmt_info->code == V4L2_MBUS_FMT_UYVY8_2X8)
1170 bridge = ISPCTRL_PAR_BRIDGE_BENDIAN;
1171 else
1172 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
de1135d4 1173
c51364ca
LP		 1174 omap3isp_configure_bridge(isp, ccdc->input, pdata, shift, bridge);
1175
9a36d8ed 1176 /* Configure the sync interface. */
c51364ca 1177 ccdc_config_sync_if(ccdc, pdata, depth_out);
de1135d4
LP		 1178
1179 syn_mode = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1180
1181 /* Use the raw, unprocessed data when writing to memory. The H3A and
1182 * histogram modules are still fed with lens shading corrected data.
1183 */
1184 syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
1185
1186 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1187 syn_mode |= ISPCCDC_SYN_MODE_WEN;
1188 else
1189 syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
1190
1191 if (ccdc->output & CCDC_OUTPUT_RESIZER)
1192 syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
1193 else
1194 syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
1195
de1135d4
LP		 1196 /* Mosaic filter */
1197 switch (format->code) {
1198 case V4L2_MBUS_FMT_SRGGB10_1X10:
1199 case V4L2_MBUS_FMT_SRGGB12_1X12:
1200 ccdc_pattern = ccdc_srggb_pattern;
1201 break;
1202 case V4L2_MBUS_FMT_SBGGR10_1X10:
1203 case V4L2_MBUS_FMT_SBGGR12_1X12:
1204 ccdc_pattern = ccdc_sbggr_pattern;
1205 break;
1206 case V4L2_MBUS_FMT_SGBRG10_1X10:
1207 case V4L2_MBUS_FMT_SGBRG12_1X12:
1208 ccdc_pattern = ccdc_sgbrg_pattern;
1209 break;
1210 default:
1211 /* Use GRBG */
1212 ccdc_pattern = ccdc_sgrbg_pattern;
1213 break;
1214 }
1215 ccdc_config_imgattr(ccdc, ccdc_pattern);
1216
1217 /* Generate VD0 on the last line of the image and VD1 on the
1218 * 2/3 height line.
1219 */
1220 isp_reg_writel(isp, ((format->height - 2) << ISPCCDC_VDINT_0_SHIFT) |
1221 ((format->height * 2 / 3) << ISPCCDC_VDINT_1_SHIFT),
1222 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT);
1223
1224 /* CCDC_PAD_SOURCE_OF */
c51364ca 1225 format = &ccdc->formats[CCDC_PAD_SOURCE_OF];
a64909b8 1226 crop = &ccdc->crop;
de1135d4 1227
9de7af4d
LP		 1228 /* The horizontal coordinates are expressed in pixel clock cycles. We
1229 * need two cycles per pixel in BT.656 mode, and one cycle per pixel in
1230 * SYNC mode regardless of the format as the bridge is enabled for YUV
1231 * formats in that case.
1232 */
1233 if (ccdc->bt656) {
1234 sph = crop->left * 2;
1235 nph = crop->width * 2 - 1;
1236 } else {
1237 sph = crop->left;
1238 nph = crop->width - 1;
1239 }
1240
1241 isp_reg_writel(isp, (sph << ISPCCDC_HORZ_INFO_SPH_SHIFT) |
1242 (nph << ISPCCDC_HORZ_INFO_NPH_SHIFT),
de1135d4 1243 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO);
9de7af4d
LP		 1244 isp_reg_writel(isp, (crop->top << ISPCCDC_VERT_START_SLV0_SHIFT) |
1245 (crop->top << ISPCCDC_VERT_START_SLV1_SHIFT),
de1135d4 1246 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START);
a64909b8 1247 isp_reg_writel(isp, (crop->height - 1)
de1135d4
LP		 1248 << ISPCCDC_VERT_LINES_NLV_SHIFT,
1249 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES);
1250
bcb4e0ef
LP		 1251 ccdc_config_outlineoffset(ccdc, ccdc->video_out.bpl_value,
1252 format->field);
1253
1254 /* When interleaving fields enable processing of the field input signal.
1255 * This will cause the line output control module to apply the field
1256 * offset to field 1.
1257 */
1258 if (ccdc->formats[CCDC_PAD_SINK].field == V4L2_FIELD_ALTERNATE &&
1259 (format->field == V4L2_FIELD_INTERLACED_TB ||
1260 format->field == V4L2_FIELD_INTERLACED_BT))
1261 syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
de1135d4 1262
c51364ca
LP		 1263 /* The CCDC outputs data in UYVY order by default. Swap bytes to get
1264 * YUYV.
1265 */
1266 if (format->code == V4L2_MBUS_FMT_YUYV8_1X16)
1267 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1268 ISPCCDC_CFG_BSWD);
1269 else
1270 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1271 ISPCCDC_CFG_BSWD);
1272
9de7af4d
LP		 1273 /* Use PACK8 mode for 1byte per pixel formats. Check for BT.656 mode
1274 * explicitly as the driver reports 1X16 instead of 2X8 at the OF pad
1275 * for simplicity.
1276 */
1277 if (omap3isp_video_format_info(format->code)->width <= 8 || ccdc->bt656)
c51364ca
LP		 1278 syn_mode |= ISPCCDC_SYN_MODE_PACK8;
1279 else
1280 syn_mode &= ~ISPCCDC_SYN_MODE_PACK8;
1281
1282 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1283
de1135d4
LP		 1284 /* CCDC_PAD_SOURCE_VP */
1285 format = &ccdc->formats[CCDC_PAD_SOURCE_VP];
1286
1287 isp_reg_writel(isp, (0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
1288 (format->width << ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
1289 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ);
1290 isp_reg_writel(isp, (0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
1291 ((format->height + 1) << ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
1292 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT);
1293
1294 isp_reg_writel(isp, (format->width << ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
1295 (format->height << ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
1296 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
1297
c51364ca 1298 /* Lens shading correction. */
de1135d4
LP		 1299 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1300 if (ccdc->lsc.request == NULL)
1301 goto unlock;
1302
1303 WARN_ON(ccdc->lsc.active);
1304
1305 /* Get last good LSC configuration. If it is not supported for
1306 * the current active resolution discard it.
1307 */
1308 if (ccdc->lsc.active == NULL &&
1309 __ccdc_lsc_configure(ccdc, ccdc->lsc.request) == 0) {
1310 ccdc->lsc.active = ccdc->lsc.request;
1311 } else {
1312 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
1313 schedule_work(&ccdc->lsc.table_work);
1314 }
1315
1316 ccdc->lsc.request = NULL;
1317
1318unlock:
1319 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1320
1321 ccdc_apply_controls(ccdc);
1322}
1323
1324static void __ccdc_enable(struct isp_ccdc_device *ccdc, int enable)
1325{
1326 struct isp_device *isp = to_isp_device(ccdc);
1327
1328 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR,
1329 ISPCCDC_PCR_EN, enable ? ISPCCDC_PCR_EN : 0);
1330}
1331
1332static int ccdc_disable(struct isp_ccdc_device *ccdc)
1333{
1334 unsigned long flags;
1335 int ret = 0;
1336
1337 spin_lock_irqsave(&ccdc->lock, flags);
1338 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1339 ccdc->stopping = CCDC_STOP_REQUEST;
1340 spin_unlock_irqrestore(&ccdc->lock, flags);
1341
1342 ret = wait_event_timeout(ccdc->wait,
1343 ccdc->stopping == CCDC_STOP_FINISHED,
1344 msecs_to_jiffies(2000));
1345 if (ret == 0) {
1346 ret = -ETIMEDOUT;
1347 dev_warn(to_device(ccdc), "CCDC stop timeout!\n");
1348 }
1349
1350 omap3isp_sbl_disable(to_isp_device(ccdc), OMAP3_ISP_SBL_CCDC_LSC_READ);
1351
1352 mutex_lock(&ccdc->ioctl_lock);
1353 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
1354 ccdc->lsc.request = ccdc->lsc.active;
1355 ccdc->lsc.active = NULL;
1356 cancel_work_sync(&ccdc->lsc.table_work);
1357 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
1358 mutex_unlock(&ccdc->ioctl_lock);
1359
1360 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
1361
1362 return ret > 0 ? 0 : ret;
1363}
1364
1365static void ccdc_enable(struct isp_ccdc_device *ccdc)
1366{
1367 if (ccdc_lsc_is_configured(ccdc))
1368 __ccdc_lsc_enable(ccdc, 1);
1369 __ccdc_enable(ccdc, 1);
1370}
1371
1372/* -----------------------------------------------------------------------------
1373 * Interrupt handling
1374 */
1375
1376/*
1377 * ccdc_sbl_busy - Poll idle state of CCDC and related SBL memory write bits
1378 * @ccdc: Pointer to ISP CCDC device.
1379 *
1380 * Returns zero if the CCDC is idle and the image has been written to
1381 * memory, too.
1382 */
1383static int ccdc_sbl_busy(struct isp_ccdc_device *ccdc)
1384{
1385 struct isp_device *isp = to_isp_device(ccdc);
1386
1387 return omap3isp_ccdc_busy(ccdc)
1388 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
1389 ISPSBL_CCDC_WR_0_DATA_READY)
1390 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
1391 ISPSBL_CCDC_WR_0_DATA_READY)
1392 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
1393 ISPSBL_CCDC_WR_0_DATA_READY)
1394 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
1395 ISPSBL_CCDC_WR_0_DATA_READY);
1396}
1397
1398/*
1399 * ccdc_sbl_wait_idle - Wait until the CCDC and related SBL are idle
1400 * @ccdc: Pointer to ISP CCDC device.
1401 * @max_wait: Max retry count in us for wait for idle/busy transition.
1402 */
1403static int ccdc_sbl_wait_idle(struct isp_ccdc_device *ccdc,
1404 unsigned int max_wait)
1405{
1406 unsigned int wait = 0;
1407
1408 if (max_wait == 0)
1409 max_wait = 10000; /* 10 ms */
1410
1411 for (wait = 0; wait <= max_wait; wait++) {
1412 if (!ccdc_sbl_busy(ccdc))
1413 return 0;
1414
1415 rmb();
1416 udelay(1);
1417 }
1418
1419 return -EBUSY;
1420}
1421
1422/* __ccdc_handle_stopping - Handle CCDC and/or LSC stopping sequence
1423 * @ccdc: Pointer to ISP CCDC device.
1424 * @event: Pointing which event trigger handler
1425 *
2d4e9d1d 1426 * Return 1 when the event and stopping request combination is satisfied,
de1135d4
LP		 1427 * zero otherwise.
1428 */
1429static int __ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
1430{
1431 int rval = 0;
1432
1433 switch ((ccdc->stopping & 3) | event) {
1434 case CCDC_STOP_REQUEST | CCDC_EVENT_VD1:
1435 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1436 __ccdc_lsc_enable(ccdc, 0);
1437 __ccdc_enable(ccdc, 0);
1438 ccdc->stopping = CCDC_STOP_EXECUTED;
1439 return 1;
1440
1441 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD0:
1442 ccdc->stopping |= CCDC_STOP_CCDC_FINISHED;
1443 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1444 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1445 rval = 1;
1446 break;
1447
1448 case CCDC_STOP_EXECUTED | CCDC_EVENT_LSC_DONE:
1449 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1450 rval = 1;
1451 break;
1452
1453 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD1:
1454 return 1;
1455 }
1456
1457 if (ccdc->stopping == CCDC_STOP_FINISHED) {
1458 wake_up(&ccdc->wait);
1459 rval = 1;
1460 }
1461
1462 return rval;
1463}
1464
1465static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
1466{
bd0f2e6d 1467 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
63ae37ea 1468 struct video_device *vdev = ccdc->subdev.devnode;
de1135d4
LP		 1469 struct v4l2_event event;
1470
b43883d6
LP		 1471 /* Frame number propagation */
1472 atomic_inc(&pipe->frame_number);
1473
de1135d4 1474 memset(&event, 0, sizeof(event));
69d232ae
SA		 1475 event.type = V4L2_EVENT_FRAME_SYNC;
1476 event.u.frame_sync.frame_sequence = atomic_read(&pipe->frame_number);
de1135d4
LP		 1477
1478 v4l2_event_queue(vdev, &event);
1479}
1480
1481/*
1482 * ccdc_lsc_isr - Handle LSC events
1483 * @ccdc: Pointer to ISP CCDC device.
1484 * @events: LSC events
1485 */
1486static void ccdc_lsc_isr(struct isp_ccdc_device *ccdc, u32 events)
1487{
1488 unsigned long flags;
1489
1490 if (events & IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ) {
875e2e3e
LP		 1491 struct isp_pipeline *pipe =
1492 to_isp_pipeline(&ccdc->subdev.entity);
1493
de1135d4 1494 ccdc_lsc_error_handler(ccdc);
875e2e3e 1495 pipe->error = true;
de1135d4
LP		 1496 dev_dbg(to_device(ccdc), "lsc prefetch error\n");
1497 }
1498
1499 if (!(events & IRQ0STATUS_CCDC_LSC_DONE_IRQ))
1500 return;
1501
1502 /* LSC_DONE interrupt occur, there are two cases
1503 * 1. stopping for reconfiguration
1504 * 2. stopping because of STREAM OFF command
1505 */
1506 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1507
1508 if (ccdc->lsc.state == LSC_STATE_STOPPING)
1509 ccdc->lsc.state = LSC_STATE_STOPPED;
1510
1511 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_LSC_DONE))
1512 goto done;
1513
1514 if (ccdc->lsc.state != LSC_STATE_RECONFIG)
1515 goto done;
1516
1517 /* LSC is in STOPPING state, change to the new state */
1518 ccdc->lsc.state = LSC_STATE_STOPPED;
1519
1520 /* This is an exception. Start of frame and LSC_DONE interrupt
1521 * have been received on the same time. Skip this event and wait
1522 * for better times.
1523 */
1524 if (events & IRQ0STATUS_HS_VS_IRQ)
1525 goto done;
1526
1527 /* The LSC engine is stopped at this point. Enable it if there's a
1528 * pending request.
1529 */
1530 if (ccdc->lsc.request == NULL)
1531 goto done;
1532
1533 ccdc_lsc_enable(ccdc);
1534
1535done:
1536 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1537}
1538
1539static int ccdc_isr_buffer(struct isp_ccdc_device *ccdc)
1540{
1541 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1542 struct isp_device *isp = to_isp_device(ccdc);
1543 struct isp_buffer *buffer;
bcb4e0ef 1544 enum v4l2_field field;
de1135d4
LP		 1545
1546 /* The CCDC generates VD0 interrupts even when disabled (the datasheet
1547 * doesn't explicitly state if that's supposed to happen or not, so it
1548 * can be considered as a hardware bug or as a feature, but we have to
1549 * deal with it anyway). Disabling the CCDC when no buffer is available
1550 * would thus not be enough, we need to handle the situation explicitly.
1551 */
1552 if (list_empty(&ccdc->video_out.dmaqueue))
0a7b1a01 1553 return 0;
de1135d4
LP		 1554
1555 /* We're in continuous mode, and memory writes were disabled due to a
1556 * buffer underrun. Reenable them now that we have a buffer. The buffer
1557 * address has been set in ccdc_video_queue.
1558 */
1559 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && ccdc->underrun) {
de1135d4 1560 ccdc->underrun = 0;
0a7b1a01 1561 return 1;
de1135d4
LP		 1562 }
1563
bcb4e0ef
LP		 1564 /* Read the current field identifier. */
1565 field = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE)
1566 & ISPCCDC_SYN_MODE_FLDSTAT
1567 ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
9a36d8ed 1568
bcb4e0ef 1569 /* Wait for the CCDC to become idle. */
de1135d4
LP		 1570 if (ccdc_sbl_wait_idle(ccdc, 1000)) {
1571 dev_info(isp->dev, "CCDC won't become idle!\n");
9554b7db
LP		 1572 isp->crashed |= 1U << ccdc->subdev.entity.id;
1573 omap3isp_pipeline_cancel_stream(pipe);
0a7b1a01 1574 return 0;
de1135d4
LP		 1575 }
1576
bcb4e0ef
LP		 1577 switch (ccdc->formats[CCDC_PAD_SOURCE_OF].field) {
1578 case V4L2_FIELD_ALTERNATE:
1579 /* When capturing fields in alternate order store the current
1580 * field identifier in the pipeline.
1581 */
1582 pipe->field = field;
1583 break;
1584
1585 case V4L2_FIELD_INTERLACED_TB:
1586 /* When interleaving fields only complete the buffer after
1587 * capturing the second field.
1588 */
1589 if (field == V4L2_FIELD_TOP)
1590 return 1;
1591 break;
1592
1593 case V4L2_FIELD_INTERLACED_BT:
1594 if (field == V4L2_FIELD_BOTTOM)
1595 return 1;
1596 break;
1597 }
1598
875e2e3e 1599 buffer = omap3isp_video_buffer_next(&ccdc->video_out);
0a7b1a01 1600 if (buffer != NULL)
21d8582d 1601 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4
LP		 1602
1603 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1604
1605 if (ccdc->state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1606 isp_pipeline_ready(pipe))
1607 omap3isp_pipeline_set_stream(pipe,
1608 ISP_PIPELINE_STREAM_SINGLESHOT);
1609
0a7b1a01 1610 return buffer != NULL;
de1135d4
LP		 1611}
1612
1613/*
1614 * ccdc_vd0_isr - Handle VD0 event
1615 * @ccdc: Pointer to ISP CCDC device.
1616 *
1617 * Executes LSC deferred enablement before next frame starts.
1618 */
1619static void ccdc_vd0_isr(struct isp_ccdc_device *ccdc)
1620{
1621 unsigned long flags;
1622 int restart = 0;
1623
1624 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1625 restart = ccdc_isr_buffer(ccdc);
1626
1627 spin_lock_irqsave(&ccdc->lock, flags);
1628 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD0)) {
1629 spin_unlock_irqrestore(&ccdc->lock, flags);
1630 return;
1631 }
1632
1633 if (!ccdc->shadow_update)
1634 ccdc_apply_controls(ccdc);
1635 spin_unlock_irqrestore(&ccdc->lock, flags);
1636
1637 if (restart)
1638 ccdc_enable(ccdc);
1639}
1640
1641/*
1642 * ccdc_vd1_isr - Handle VD1 event
1643 * @ccdc: Pointer to ISP CCDC device.
1644 */
1645static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)
1646{
1647 unsigned long flags;
1648
9de7af4d
LP		 1649 /* In BT.656 mode the CCDC doesn't generate an HS/VS interrupt. We thus
1650 * need to increment the frame counter here.
1651 */
1652 if (ccdc->bt656) {
1653 struct isp_pipeline *pipe =
1654 to_isp_pipeline(&ccdc->subdev.entity);
1655
1656 atomic_inc(&pipe->frame_number);
1657 }
1658
de1135d4
LP		 1659 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1660
1661 /*
1662 * Depending on the CCDC pipeline state, CCDC stopping should be
1663 * handled differently. In SINGLESHOT we emulate an internal CCDC
1664 * stopping because the CCDC hw works only in continuous mode.
1665 * When CONTINUOUS pipeline state is used and the CCDC writes it's
1666 * data to memory the CCDC and LSC are stopped immediately but
1667 * without change the CCDC stopping state machine. The CCDC
1668 * stopping state machine should be used only when user request
1669 * for stopping is received (SINGLESHOT is an exeption).
1670 */
1671 switch (ccdc->state) {
1672 case ISP_PIPELINE_STREAM_SINGLESHOT:
1673 ccdc->stopping = CCDC_STOP_REQUEST;
1674 break;
1675
1676 case ISP_PIPELINE_STREAM_CONTINUOUS:
1677 if (ccdc->output & CCDC_OUTPUT_MEMORY) {
1678 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1679 __ccdc_lsc_enable(ccdc, 0);
1680 __ccdc_enable(ccdc, 0);
1681 }
1682 break;
1683
1684 case ISP_PIPELINE_STREAM_STOPPED:
1685 break;
1686 }
1687
1688 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))
1689 goto done;
1690
1691 if (ccdc->lsc.request == NULL)
1692 goto done;
1693
1694 /*
1695 * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ
1696 * do the appropriate changes in registers
1697 */
1698 if (ccdc->lsc.state == LSC_STATE_RUNNING) {
1699 __ccdc_lsc_enable(ccdc, 0);
1700 ccdc->lsc.state = LSC_STATE_RECONFIG;
1701 goto done;
1702 }
1703
1704 /* LSC has been in STOPPED state, enable it */
1705 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1706 ccdc_lsc_enable(ccdc);
1707
1708done:
1709 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1710}
1711
1712/*
1713 * omap3isp_ccdc_isr - Configure CCDC during interframe time.
1714 * @ccdc: Pointer to ISP CCDC device.
1715 * @events: CCDC events
1716 */
1717int omap3isp_ccdc_isr(struct isp_ccdc_device *ccdc, u32 events)
1718{
1719 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED)
1720 return 0;
1721
1722 if (events & IRQ0STATUS_CCDC_VD1_IRQ)
1723 ccdc_vd1_isr(ccdc);
1724
1725 ccdc_lsc_isr(ccdc, events);
1726
1727 if (events & IRQ0STATUS_CCDC_VD0_IRQ)
1728 ccdc_vd0_isr(ccdc);
1729
1730 if (events & IRQ0STATUS_HS_VS_IRQ)
1731 ccdc_hs_vs_isr(ccdc);
1732
1733 return 0;
1734}
1735
1736/* -----------------------------------------------------------------------------
1737 * ISP video operations
1738 */
1739
1740static int ccdc_video_queue(struct isp_video *video, struct isp_buffer *buffer)
1741{
1742 struct isp_ccdc_device *ccdc = &video->isp->isp_ccdc;
1743
1744 if (!(ccdc->output & CCDC_OUTPUT_MEMORY))
1745 return -ENODEV;
1746
21d8582d 1747 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4 1748
2d4e9d1d 1749 /* We now have a buffer queued on the output, restart the pipeline
de1135d4
LP		 1750 * on the next CCDC interrupt if running in continuous mode (or when
1751 * starting the stream).
1752 */
1753 ccdc->underrun = 1;
1754
1755 return 0;
1756}
1757
1758static const struct isp_video_operations ccdc_video_ops = {
1759 .queue = ccdc_video_queue,
1760};
1761
1762/* -----------------------------------------------------------------------------
1763 * V4L2 subdev operations
1764 */
1765
1766/*
1767 * ccdc_ioctl - CCDC module private ioctl's
1768 * @sd: ISP CCDC V4L2 subdevice
1769 * @cmd: ioctl command
1770 * @arg: ioctl argument
1771 *
1772 * Return 0 on success or a negative error code otherwise.
1773 */
1774static long ccdc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1775{
1776 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1777 int ret;
1778
1779 switch (cmd) {
1780 case VIDIOC_OMAP3ISP_CCDC_CFG:
1781 mutex_lock(&ccdc->ioctl_lock);
1782 ret = ccdc_config(ccdc, arg);
1783 mutex_unlock(&ccdc->ioctl_lock);
1784 break;
1785
1786 default:
1787 return -ENOIOCTLCMD;
1788 }
1789
1790 return ret;
1791}
1792
1793static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1794 struct v4l2_event_subscription *sub)
de1135d4 1795{
69d232ae
SA		 1796 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1797 return -EINVAL;
1798
1799 /* line number is zero at frame start */
1800 if (sub->id != 0)
de1135d4
LP		 1801 return -EINVAL;
1802
c53c2549 1803 return v4l2_event_subscribe(fh, sub, OMAP3ISP_CCDC_NEVENTS, NULL);
de1135d4
LP		 1804}
1805
1806static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1807 struct v4l2_event_subscription *sub)
de1135d4
LP		 1808{
1809 return v4l2_event_unsubscribe(fh, sub);
1810}
1811
1812/*
1813 * ccdc_set_stream - Enable/Disable streaming on the CCDC module
1814 * @sd: ISP CCDC V4L2 subdevice
1815 * @enable: Enable/disable stream
1816 *
1817 * When writing to memory, the CCDC hardware can't be enabled without a memory
1818 * buffer to write to. As the s_stream operation is called in response to a
1819 * STREAMON call without any buffer queued yet, just update the enabled field
1820 * and return immediately. The CCDC will be enabled in ccdc_isr_buffer().
1821 *
1822 * When not writing to memory enable the CCDC immediately.
1823 */
1824static int ccdc_set_stream(struct v4l2_subdev *sd, int enable)
1825{
1826 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1827 struct isp_device *isp = to_isp_device(ccdc);
1828 int ret = 0;
1829
1830 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED) {
1831 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1832 return 0;
1833
1834 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_CCDC);
1835 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1836 ISPCCDC_CFG_VDLC);
1837
1838 ccdc_configure(ccdc);
1839
1840 /* TODO: Don't configure the video port if all of its output
1841 * links are inactive.
1842 */
1843 ccdc_config_vp(ccdc);
1844 ccdc_enable_vp(ccdc, 1);
de1135d4
LP		 1845 ccdc_print_status(ccdc);
1846 }
1847
1848 switch (enable) {
1849 case ISP_PIPELINE_STREAM_CONTINUOUS:
1850 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1851 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1852
1853 if (ccdc->underrun || !(ccdc->output & CCDC_OUTPUT_MEMORY))
1854 ccdc_enable(ccdc);
1855
1856 ccdc->underrun = 0;
1857 break;
1858
1859 case ISP_PIPELINE_STREAM_SINGLESHOT:
1860 if (ccdc->output & CCDC_OUTPUT_MEMORY &&
1861 ccdc->state != ISP_PIPELINE_STREAM_SINGLESHOT)
1862 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1863
1864 ccdc_enable(ccdc);
1865 break;
1866
1867 case ISP_PIPELINE_STREAM_STOPPED:
1868 ret = ccdc_disable(ccdc);
1869 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1870 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1871 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_CCDC);
1872 ccdc->underrun = 0;
1873 break;
1874 }
1875
1876 ccdc->state = enable;
1877 return ret;
1878}
1879
1880static struct v4l2_mbus_framefmt *
1881__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1882 unsigned int pad, enum v4l2_subdev_format_whence which)
1883{
1884 if (which == V4L2_SUBDEV_FORMAT_TRY)
1885 return v4l2_subdev_get_try_format(fh, pad);
1886 else
1887 return &ccdc->formats[pad];
1888}
1889
a64909b8
LP		 1890static struct v4l2_rect *
1891__ccdc_get_crop(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1892 enum v4l2_subdev_format_whence which)
1893{
1894 if (which == V4L2_SUBDEV_FORMAT_TRY)
1895 return v4l2_subdev_get_try_crop(fh, CCDC_PAD_SOURCE_OF);
1896 else
1897 return &ccdc->crop;
1898}
1899
de1135d4
LP		 1900/*
1901 * ccdc_try_format - Try video format on a pad
1902 * @ccdc: ISP CCDC device
1903 * @fh : V4L2 subdev file handle
1904 * @pad: Pad number
1905 * @fmt: Format
1906 */
1907static void
1908ccdc_try_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1909 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
1910 enum v4l2_subdev_format_whence which)
1911{
de1135d4 1912 const struct isp_format_info *info;
c51364ca 1913 enum v4l2_mbus_pixelcode pixelcode;
de1135d4
LP		 1914 unsigned int width = fmt->width;
1915 unsigned int height = fmt->height;
a64909b8 1916 struct v4l2_rect *crop;
bcb4e0ef 1917 enum v4l2_field field;
de1135d4
LP		 1918 unsigned int i;
1919
1920 switch (pad) {
1921 case CCDC_PAD_SINK:
de1135d4
LP		 1922 for (i = 0; i < ARRAY_SIZE(ccdc_fmts); i++) {
1923 if (fmt->code == ccdc_fmts[i])
1924 break;
1925 }
1926
1927 /* If not found, use SGRBG10 as default */
1928 if (i >= ARRAY_SIZE(ccdc_fmts))
1929 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1930
1931 /* Clamp the input size. */
1932 fmt->width = clamp_t(u32, width, 32, 4096);
1933 fmt->height = clamp_t(u32, height, 32, 4096);
9a36d8ed
LP		 1934
1935 /* Default to progressive field order. */
1936 if (fmt->field == V4L2_FIELD_ANY)
1937 fmt->field = V4L2_FIELD_NONE;
1938
de1135d4
LP		 1939 break;
1940
1941 case CCDC_PAD_SOURCE_OF:
c51364ca 1942 pixelcode = fmt->code;
bcb4e0ef 1943 field = fmt->field;
c51364ca
LP		 1944 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
1945
9de7af4d
LP		 1946 /* In SYNC mode the bridge converts YUV formats from 2X8 to
1947 * 1X16. In BT.656 no such conversion occurs. As we don't know
1948 * at this point whether the source will use SYNC or BT.656 mode
1949 * let's pretend the conversion always occurs. The CCDC will be
1950 * configured to pack bytes in BT.656, hiding the inaccuracy.
1951 * In all cases bytes can be swapped.
c51364ca
LP		 1952 */
1953 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1954 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1955 /* Use the user requested format if YUV. */
1956 if (pixelcode == V4L2_MBUS_FMT_YUYV8_2X8 ||
1957 pixelcode == V4L2_MBUS_FMT_UYVY8_2X8 ||
1958 pixelcode == V4L2_MBUS_FMT_YUYV8_1X16 ||
1959 pixelcode == V4L2_MBUS_FMT_UYVY8_1X16)
1960 fmt->code = pixelcode;
1961
1962 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8)
1963 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1964 else if (fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1965 fmt->code = V4L2_MBUS_FMT_UYVY8_1X16;
1966 }
de1135d4 1967
a64909b8
LP		 1968 /* Hardcode the output size to the crop rectangle size. */
1969 crop = __ccdc_get_crop(ccdc, fh, which);
1970 fmt->width = crop->width;
1971 fmt->height = crop->height;
bcb4e0ef
LP		 1972
1973 /* When input format is interlaced with alternating fields the
1974 * CCDC can interleave the fields.
1975 */
1976 if (fmt->field == V4L2_FIELD_ALTERNATE &&
1977 (field == V4L2_FIELD_INTERLACED_TB ||
1978 field == V4L2_FIELD_INTERLACED_BT)) {
1979 fmt->field = field;
1980 fmt->height *= 2;
1981 }
1982
de1135d4
LP		 1983 break;
1984
1985 case CCDC_PAD_SOURCE_VP:
c51364ca 1986 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
de1135d4
LP		 1987
1988 /* The video port interface truncates the data to 10 bits. */
1989 info = omap3isp_video_format_info(fmt->code);
1990 fmt->code = info->truncated;
1991
c51364ca
LP		 1992 /* YUV formats are not supported by the video port. */
1993 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1994 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1995 fmt->code = 0;
1996
de1135d4
LP		 1997 /* The number of lines that can be clocked out from the video
1998 * port output must be at least one line less than the number
1999 * of input lines.
2000 */
2001 fmt->width = clamp_t(u32, width, 32, fmt->width);
2002 fmt->height = clamp_t(u32, height, 32, fmt->height - 1);
2003 break;
2004 }
2005
2006 /* Data is written to memory unpacked, each 10-bit or 12-bit pixel is
2007 * stored on 2 bytes.
2008 */
2009 fmt->colorspace = V4L2_COLORSPACE_SRGB;
de1135d4
LP		 2010}
2011
a64909b8
LP		 2012/*
2013 * ccdc_try_crop - Validate a crop rectangle
2014 * @ccdc: ISP CCDC device
2015 * @sink: format on the sink pad
2016 * @crop: crop rectangle to be validated
2017 */
2018static void ccdc_try_crop(struct isp_ccdc_device *ccdc,
2019 const struct v4l2_mbus_framefmt *sink,
2020 struct v4l2_rect *crop)
2021{
2022 const struct isp_format_info *info;
2023 unsigned int max_width;
2024
2025 /* For Bayer formats, restrict left/top and width/height to even values
2026 * to keep the Bayer pattern.
2027 */
2028 info = omap3isp_video_format_info(sink->code);
2029 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2030 crop->left &= ~1;
2031 crop->top &= ~1;
2032 }
2033
2034 crop->left = clamp_t(u32, crop->left, 0, sink->width - CCDC_MIN_WIDTH);
2035 crop->top = clamp_t(u32, crop->top, 0, sink->height - CCDC_MIN_HEIGHT);
2036
2037 /* The data formatter truncates the number of horizontal output pixels
2038 * to a multiple of 16. To avoid clipping data, allow callers to request
2039 * an output size bigger than the input size up to the nearest multiple
2040 * of 16.
2041 */
2042 max_width = (sink->width - crop->left + 15) & ~15;
2043 crop->width = clamp_t(u32, crop->width, CCDC_MIN_WIDTH, max_width)
2044 & ~15;
2045 crop->height = clamp_t(u32, crop->height, CCDC_MIN_HEIGHT,
2046 sink->height - crop->top);
2047
2048 /* Odd width/height values don't make sense for Bayer formats. */
2049 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2050 crop->width &= ~1;
2051 crop->height &= ~1;
2052 }
2053}
2054
de1135d4
LP		 2055/*
2056 * ccdc_enum_mbus_code - Handle pixel format enumeration
2057 * @sd : pointer to v4l2 subdev structure
2058 * @fh : V4L2 subdev file handle
2059 * @code : pointer to v4l2_subdev_mbus_code_enum structure
2060 * return -EINVAL or zero on success
2061 */
2062static int ccdc_enum_mbus_code(struct v4l2_subdev *sd,
2063 struct v4l2_subdev_fh *fh,
2064 struct v4l2_subdev_mbus_code_enum *code)
2065{
2066 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2067 struct v4l2_mbus_framefmt *format;
2068
2069 switch (code->pad) {
2070 case CCDC_PAD_SINK:
2071 if (code->index >= ARRAY_SIZE(ccdc_fmts))
2072 return -EINVAL;
2073
2074 code->code = ccdc_fmts[code->index];
2075 break;
2076
2077 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 2078 format = __ccdc_get_format(ccdc, fh, code->pad,
2079 V4L2_SUBDEV_FORMAT_TRY);
2080
2081 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
2082 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
2083 /* In YUV mode the CCDC can swap bytes. */
2084 if (code->index == 0)
2085 code->code = V4L2_MBUS_FMT_YUYV8_1X16;
2086 else if (code->index == 1)
2087 code->code = V4L2_MBUS_FMT_UYVY8_1X16;
2088 else
2089 return -EINVAL;
2090 } else {
2091 /* In raw mode, no configurable format confversion is
2092 * available.
2093 */
2094 if (code->index == 0)
2095 code->code = format->code;
2096 else
2097 return -EINVAL;
2098 }
2099 break;
2100
de1135d4 2101 case CCDC_PAD_SOURCE_VP:
c51364ca
LP		 2102 /* The CCDC supports no configurable format conversion
2103 * compatible with the video port. Enumerate a single output
2104 * format code.
2105 */
de1135d4
LP		 2106 if (code->index != 0)
2107 return -EINVAL;
2108
c51364ca 2109 format = __ccdc_get_format(ccdc, fh, code->pad,
de1135d4
LP		 2110 V4L2_SUBDEV_FORMAT_TRY);
2111
c51364ca
LP		 2112 /* A pixel code equal to 0 means that the video port doesn't
2113 * support the input format. Don't enumerate any pixel code.
2114 */
2115 if (format->code == 0)
2116 return -EINVAL;
2117
de1135d4
LP		 2118 code->code = format->code;
2119 break;
2120
2121 default:
2122 return -EINVAL;
2123 }
2124
2125 return 0;
2126}
2127
2128static int ccdc_enum_frame_size(struct v4l2_subdev *sd,
2129 struct v4l2_subdev_fh *fh,
2130 struct v4l2_subdev_frame_size_enum *fse)
2131{
2132 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2133 struct v4l2_mbus_framefmt format;
2134
2135 if (fse->index != 0)
2136 return -EINVAL;
2137
2138 format.code = fse->code;
2139 format.width = 1;
2140 format.height = 1;
2141 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2142 fse->min_width = format.width;
2143 fse->min_height = format.height;
2144
2145 if (format.code != fse->code)
2146 return -EINVAL;
2147
2148 format.code = fse->code;
2149 format.width = -1;
2150 format.height = -1;
2151 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2152 fse->max_width = format.width;
2153 fse->max_height = format.height;
2154
2155 return 0;
2156}
2157
a64909b8
LP		 2158/*
2159 * ccdc_get_selection - Retrieve a selection rectangle on a pad
2160 * @sd: ISP CCDC V4L2 subdevice
2161 * @fh: V4L2 subdev file handle
2162 * @sel: Selection rectangle
2163 *
2164 * The only supported rectangles are the crop rectangles on the output formatter
2165 * source pad.
2166 *
2167 * Return 0 on success or a negative error code otherwise.
2168 */
2169static int ccdc_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2170 struct v4l2_subdev_selection *sel)
2171{
2172 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2173 struct v4l2_mbus_framefmt *format;
2174
2175 if (sel->pad != CCDC_PAD_SOURCE_OF)
2176 return -EINVAL;
2177
2178 switch (sel->target) {
5689b288 2179 case V4L2_SEL_TGT_CROP_BOUNDS:
a64909b8
LP		 2180 sel->r.left = 0;
2181 sel->r.top = 0;
2182 sel->r.width = INT_MAX;
2183 sel->r.height = INT_MAX;
2184
2185 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2186 ccdc_try_crop(ccdc, format, &sel->r);
2187 break;
2188
5689b288 2189 case V4L2_SEL_TGT_CROP:
a64909b8
LP		 2190 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2191 break;
2192
2193 default:
2194 return -EINVAL;
2195 }
2196
2197 return 0;
2198}
2199
2200/*
2201 * ccdc_set_selection - Set a selection rectangle on a pad
2202 * @sd: ISP CCDC V4L2 subdevice
2203 * @fh: V4L2 subdev file handle
2204 * @sel: Selection rectangle
2205 *
2206 * The only supported rectangle is the actual crop rectangle on the output
2207 * formatter source pad.
2208 *
2209 * Return 0 on success or a negative error code otherwise.
2210 */
2211static int ccdc_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2212 struct v4l2_subdev_selection *sel)
2213{
2214 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2215 struct v4l2_mbus_framefmt *format;
2216
5689b288 2217 if (sel->target != V4L2_SEL_TGT_CROP ||
a64909b8
LP		 2218 sel->pad != CCDC_PAD_SOURCE_OF)
2219 return -EINVAL;
2220
2221 /* The crop rectangle can't be changed while streaming. */
2222 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
2223 return -EBUSY;
2224
2225 /* Modifying the crop rectangle always changes the format on the source
2226 * pad. If the KEEP_CONFIG flag is set, just return the current crop
2227 * rectangle.
2228 */
563df3d0 2229 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
a64909b8
LP		 2230 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2231 return 0;
2232 }
2233
2234 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2235 ccdc_try_crop(ccdc, format, &sel->r);
2236 *__ccdc_get_crop(ccdc, fh, sel->which) = sel->r;
2237
2238 /* Update the source format. */
2239 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF, sel->which);
2240 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format, sel->which);
2241
2242 return 0;
2243}
2244
de1135d4
LP		 2245/*
2246 * ccdc_get_format - Retrieve the video format on a pad
2247 * @sd : ISP CCDC V4L2 subdevice
2248 * @fh : V4L2 subdev file handle
2249 * @fmt: Format
2250 *
2251 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2252 * to the format type.
2253 */
2254static int ccdc_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2255 struct v4l2_subdev_format *fmt)
2256{
2257 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2258 struct v4l2_mbus_framefmt *format;
2259
2260 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2261 if (format == NULL)
2262 return -EINVAL;
2263
2264 fmt->format = *format;
2265 return 0;
2266}
2267
2268/*
2269 * ccdc_set_format - Set the video format on a pad
2270 * @sd : ISP CCDC V4L2 subdevice
2271 * @fh : V4L2 subdev file handle
2272 * @fmt: Format
2273 *
2274 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2275 * to the format type.
2276 */
2277static int ccdc_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2278 struct v4l2_subdev_format *fmt)
2279{
2280 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2281 struct v4l2_mbus_framefmt *format;
a64909b8 2282 struct v4l2_rect *crop;
de1135d4
LP		 2283
2284 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2285 if (format == NULL)
2286 return -EINVAL;
2287
2288 ccdc_try_format(ccdc, fh, fmt->pad, &fmt->format, fmt->which);
2289 *format = fmt->format;
2290
2291 /* Propagate the format from sink to source */
2292 if (fmt->pad == CCDC_PAD_SINK) {
a64909b8
LP		 2293 /* Reset the crop rectangle. */
2294 crop = __ccdc_get_crop(ccdc, fh, fmt->which);
2295 crop->left = 0;
2296 crop->top = 0;
2297 crop->width = fmt->format.width;
2298 crop->height = fmt->format.height;
2299
2300 ccdc_try_crop(ccdc, &fmt->format, crop);
2301
2302 /* Update the source formats. */
de1135d4
LP		 2303 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF,
2304 fmt->which);
2305 *format = fmt->format;
2306 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format,
2307 fmt->which);
2308
2309 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_VP,
2310 fmt->which);
2311 *format = fmt->format;
2312 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_VP, format,
2313 fmt->which);
2314 }
2315
2316 return 0;
2317}
2318
a6d7a62d
SA		 2319/*
2320 * Decide whether desired output pixel code can be obtained with
2321 * the lane shifter by shifting the input pixel code.
2322 * @in: input pixelcode to shifter
2323 * @out: output pixelcode from shifter
2324 * @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
2325 *
2326 * return true if the combination is possible
2327 * return false otherwise
2328 */
2329static bool ccdc_is_shiftable(enum v4l2_mbus_pixelcode in,
2330 enum v4l2_mbus_pixelcode out,
2331 unsigned int additional_shift)
2332{
2333 const struct isp_format_info *in_info, *out_info;
2334
2335 if (in == out)
2336 return true;
2337
2338 in_info = omap3isp_video_format_info(in);
2339 out_info = omap3isp_video_format_info(out);
2340
2341 if ((in_info->flavor == 0) || (out_info->flavor == 0))
2342 return false;
2343
2344 if (in_info->flavor != out_info->flavor)
2345 return false;
2346
1697e49a 2347 return in_info->width - out_info->width + additional_shift <= 6;
a6d7a62d
SA		 2348}
2349
2350static int ccdc_link_validate(struct v4l2_subdev *sd,
2351 struct media_link *link,
2352 struct v4l2_subdev_format *source_fmt,
2353 struct v4l2_subdev_format *sink_fmt)
2354{
2355 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2356 unsigned long parallel_shift;
2357
2358 /* Check if the two ends match */
2359 if (source_fmt->format.width != sink_fmt->format.width ||
2360 source_fmt->format.height != sink_fmt->format.height)
2361 return -EPIPE;
2362
2363 /* We've got a parallel sensor here. */
2364 if (ccdc->input == CCDC_INPUT_PARALLEL) {
2365 struct isp_parallel_platform_data *pdata =
2366 &((struct isp_v4l2_subdevs_group *)
2367 media_entity_to_v4l2_subdev(link->source->entity)
2368 ->host_priv)->bus.parallel;
2369 parallel_shift = pdata->data_lane_shift * 2;
2370 } else {
2371 parallel_shift = 0;
2372 }
2373
2374 /* Lane shifter may be used to drop bits on CCDC sink pad */
2375 if (!ccdc_is_shiftable(source_fmt->format.code,
2376 sink_fmt->format.code, parallel_shift))
2377 return -EPIPE;
2378
2379 return 0;
2380}
2381
de1135d4
LP		 2382/*
2383 * ccdc_init_formats - Initialize formats on all pads
2384 * @sd: ISP CCDC V4L2 subdevice
2385 * @fh: V4L2 subdev file handle
2386 *
2387 * Initialize all pad formats with default values. If fh is not NULL, try
2388 * formats are initialized on the file handle. Otherwise active formats are
2389 * initialized on the device.
2390 */
2391static int ccdc_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2392{
2393 struct v4l2_subdev_format format;
2394
2395 memset(&format, 0, sizeof(format));
2396 format.pad = CCDC_PAD_SINK;
2397 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
2398 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
2399 format.format.width = 4096;
2400 format.format.height = 4096;
2401 ccdc_set_format(sd, fh, &format);
2402
2403 return 0;
2404}
2405
2406/* V4L2 subdev core operations */
2407static const struct v4l2_subdev_core_ops ccdc_v4l2_core_ops = {
2408 .ioctl = ccdc_ioctl,
2409 .subscribe_event = ccdc_subscribe_event,
2410 .unsubscribe_event = ccdc_unsubscribe_event,
2411};
2412
2413/* V4L2 subdev video operations */
2414static const struct v4l2_subdev_video_ops ccdc_v4l2_video_ops = {
2415 .s_stream = ccdc_set_stream,
2416};
2417
2418/* V4L2 subdev pad operations */
2419static const struct v4l2_subdev_pad_ops ccdc_v4l2_pad_ops = {
2420 .enum_mbus_code = ccdc_enum_mbus_code,
2421 .enum_frame_size = ccdc_enum_frame_size,
2422 .get_fmt = ccdc_get_format,
2423 .set_fmt = ccdc_set_format,
a64909b8
LP		 2424 .get_selection = ccdc_get_selection,
2425 .set_selection = ccdc_set_selection,
a6d7a62d 2426 .link_validate = ccdc_link_validate,
de1135d4
LP		 2427};
2428
2429/* V4L2 subdev operations */
2430static const struct v4l2_subdev_ops ccdc_v4l2_ops = {
2431 .core = &ccdc_v4l2_core_ops,
2432 .video = &ccdc_v4l2_video_ops,
2433 .pad = &ccdc_v4l2_pad_ops,
2434};
2435
2436/* V4L2 subdev internal operations */
2437static const struct v4l2_subdev_internal_ops ccdc_v4l2_internal_ops = {
2438 .open = ccdc_init_formats,
2439};
2440
2441/* -----------------------------------------------------------------------------
2442 * Media entity operations
2443 */
2444
2445/*
2446 * ccdc_link_setup - Setup CCDC connections
2447 * @entity: CCDC media entity
2448 * @local: Pad at the local end of the link
2449 * @remote: Pad at the remote end of the link
2450 * @flags: Link flags
2451 *
2452 * return -EINVAL or zero on success
2453 */
2454static int ccdc_link_setup(struct media_entity *entity,
2455 const struct media_pad *local,
2456 const struct media_pad *remote, u32 flags)
2457{
2458 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2459 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2460 struct isp_device *isp = to_isp_device(ccdc);
2461
2462 switch (local->index | media_entity_type(remote->entity)) {
2463 case CCDC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2464 /* Read from the sensor (parallel interface), CCP2, CSI2a or
2465 * CSI2c.
2466 */
2467 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
2468 ccdc->input = CCDC_INPUT_NONE;
2469 break;
2470 }
2471
2472 if (ccdc->input != CCDC_INPUT_NONE)
2473 return -EBUSY;
2474
2475 if (remote->entity == &isp->isp_ccp2.subdev.entity)
2476 ccdc->input = CCDC_INPUT_CCP2B;
2477 else if (remote->entity == &isp->isp_csi2a.subdev.entity)
2478 ccdc->input = CCDC_INPUT_CSI2A;
2479 else if (remote->entity == &isp->isp_csi2c.subdev.entity)
2480 ccdc->input = CCDC_INPUT_CSI2C;
2481 else
2482 ccdc->input = CCDC_INPUT_PARALLEL;
2483
2484 break;
2485
2486 /*
2487 * The ISP core doesn't support pipelines with multiple video outputs.
2488 * Revisit this when it will be implemented, and return -EBUSY for now.
2489 */
2490
2491 case CCDC_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
2492 /* Write to preview engine, histogram and H3A. When none of
2493 * those links are active, the video port can be disabled.
2494 */
2495 if (flags & MEDIA_LNK_FL_ENABLED) {
2496 if (ccdc->output & ~CCDC_OUTPUT_PREVIEW)
2497 return -EBUSY;
2498 ccdc->output |= CCDC_OUTPUT_PREVIEW;
2499 } else {
2500 ccdc->output &= ~CCDC_OUTPUT_PREVIEW;
2501 }
2502 break;
2503
2504 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_DEVNODE:
2505 /* Write to memory */
2506 if (flags & MEDIA_LNK_FL_ENABLED) {
2507 if (ccdc->output & ~CCDC_OUTPUT_MEMORY)
2508 return -EBUSY;
2509 ccdc->output |= CCDC_OUTPUT_MEMORY;
2510 } else {
2511 ccdc->output &= ~CCDC_OUTPUT_MEMORY;
2512 }
2513 break;
2514
2515 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_V4L2_SUBDEV:
2516 /* Write to resizer */
2517 if (flags & MEDIA_LNK_FL_ENABLED) {
2518 if (ccdc->output & ~CCDC_OUTPUT_RESIZER)
2519 return -EBUSY;
2520 ccdc->output |= CCDC_OUTPUT_RESIZER;
2521 } else {
2522 ccdc->output &= ~CCDC_OUTPUT_RESIZER;
2523 }
2524 break;
2525
2526 default:
2527 return -EINVAL;
2528 }
2529
2530 return 0;
2531}
2532
2533/* media operations */
2534static const struct media_entity_operations ccdc_media_ops = {
2535 .link_setup = ccdc_link_setup,
a6d7a62d 2536 .link_validate = v4l2_subdev_link_validate,
de1135d4
LP		 2537};
2538
39099d09
LP		 2539void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc)
2540{
2541 v4l2_device_unregister_subdev(&ccdc->subdev);
2542 omap3isp_video_unregister(&ccdc->video_out);
2543}
2544
2545int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
2546 struct v4l2_device *vdev)
2547{
2548 int ret;
2549
2550 /* Register the subdev and video node. */
2551 ret = v4l2_device_register_subdev(vdev, &ccdc->subdev);
2552 if (ret < 0)
2553 goto error;
2554
2555 ret = omap3isp_video_register(&ccdc->video_out, vdev);
2556 if (ret < 0)
2557 goto error;
2558
2559 return 0;
2560
2561error:
2562 omap3isp_ccdc_unregister_entities(ccdc);
2563 return ret;
2564}
2565
2566/* -----------------------------------------------------------------------------
2567 * ISP CCDC initialisation and cleanup
2568 */
2569
de1135d4
LP		 2570/*
2571 * ccdc_init_entities - Initialize V4L2 subdev and media entity
2572 * @ccdc: ISP CCDC module
2573 *
2574 * Return 0 on success and a negative error code on failure.
2575 */
2576static int ccdc_init_entities(struct isp_ccdc_device *ccdc)
2577{
2578 struct v4l2_subdev *sd = &ccdc->subdev;
2579 struct media_pad *pads = ccdc->pads;
2580 struct media_entity *me = &sd->entity;
2581 int ret;
2582
2583 ccdc->input = CCDC_INPUT_NONE;
2584
2585 v4l2_subdev_init(sd, &ccdc_v4l2_ops);
2586 sd->internal_ops = &ccdc_v4l2_internal_ops;
2587 strlcpy(sd->name, "OMAP3 ISP CCDC", sizeof(sd->name));
2588 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2589 v4l2_set_subdevdata(sd, ccdc);
2590 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
de1135d4 2591
8dad936a
SA		 2592 pads[CCDC_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2593 | MEDIA_PAD_FL_MUST_CONNECT;
de1135d4
LP		 2594 pads[CCDC_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
2595 pads[CCDC_PAD_SOURCE_OF].flags = MEDIA_PAD_FL_SOURCE;
2596
2597 me->ops = &ccdc_media_ops;
2598 ret = media_entity_init(me, CCDC_PADS_NUM, pads, 0);
2599 if (ret < 0)
2600 return ret;
2601
2602 ccdc_init_formats(sd, NULL);
2603
2604 ccdc->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2605 ccdc->video_out.ops = &ccdc_video_ops;
2606 ccdc->video_out.isp = to_isp_device(ccdc);
2607 ccdc->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
2608 ccdc->video_out.bpl_alignment = 32;
2609
2610 ret = omap3isp_video_init(&ccdc->video_out, "CCDC");
2611 if (ret < 0)
9b6390bd 2612 goto error_video;
de1135d4
LP		 2613
2614 /* Connect the CCDC subdev to the video node. */
2615 ret = media_entity_create_link(&ccdc->subdev.entity, CCDC_PAD_SOURCE_OF,
2616 &ccdc->video_out.video.entity, 0, 0);
2617 if (ret < 0)
9b6390bd 2618 goto error_link;
de1135d4
LP		 2619
2620 return 0;
9b6390bd
LP		 2621
2622error_link:
2623 omap3isp_video_cleanup(&ccdc->video_out);
2624error_video:
2625 media_entity_cleanup(me);
2626 return ret;
de1135d4
LP		 2627}
2628
de1135d4
LP		 2629/*
2630 * omap3isp_ccdc_init - CCDC module initialization.
872aba51 2631 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2632 *
2633 * TODO: Get the initialisation values from platform data.
2634 *
2635 * Return 0 on success or a negative error code otherwise.
2636 */
2637int omap3isp_ccdc_init(struct isp_device *isp)
2638{
2639 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
9b6390bd 2640 int ret;
de1135d4
LP		 2641
2642 spin_lock_init(&ccdc->lock);
2643 init_waitqueue_head(&ccdc->wait);
2644 mutex_init(&ccdc->ioctl_lock);
2645
2646 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
2647
2648 INIT_WORK(&ccdc->lsc.table_work, ccdc_lsc_free_table_work);
2649 ccdc->lsc.state = LSC_STATE_STOPPED;
2650 INIT_LIST_HEAD(&ccdc->lsc.free_queue);
2651 spin_lock_init(&ccdc->lsc.req_lock);
2652
de1135d4
LP		 2653 ccdc->clamp.oblen = 0;
2654 ccdc->clamp.dcsubval = 0;
2655
de1135d4
LP		 2656 ccdc->update = OMAP3ISP_CCDC_BLCLAMP;
2657 ccdc_apply_controls(ccdc);
2658
9b6390bd
LP		 2659 ret = ccdc_init_entities(ccdc);
2660 if (ret < 0) {
2661 mutex_destroy(&ccdc->ioctl_lock);
2662 return ret;
2663 }
2664
2665 return 0;
de1135d4
LP		 2666}
2667
2668/*
2669 * omap3isp_ccdc_cleanup - CCDC module cleanup.
872aba51 2670 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2671 */
2672void omap3isp_ccdc_cleanup(struct isp_device *isp)
2673{
2674 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
2675
63b4ca23
LP		 2676 omap3isp_video_cleanup(&ccdc->video_out);
2677 media_entity_cleanup(&ccdc->subdev.entity);
2678
de1135d4
LP		 2679 /* Free LSC requests. As the CCDC is stopped there's no active request,
2680 * so only the pending request and the free queue need to be handled.
2681 */
2682 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
2683 cancel_work_sync(&ccdc->lsc.table_work);
2684 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
2685
c60e153d
LP		 2686 if (ccdc->fpc.addr != NULL)
2687 dma_free_coherent(isp->dev, ccdc->fpc.fpnum * 4, ccdc->fpc.addr,
2688 ccdc->fpc.dma);
ed33ac8e
LP		 2689
2690 mutex_destroy(&ccdc->ioctl_lock);
de1135d4 2691}
Linux kernel - Deliverables
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