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[media] omap3isp: ccdc: Disable the video port when unused
[deliverable/linux.git] / drivers / media / platform / omap3isp / ispccdc.c
CommitLineData
de1135d4
LP		 1/*
2 * ispccdc.c
3 *
4 * TI OMAP3 ISP - CCDC module
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
de1135d4
LP		 15 */
16
17#include <linux/module.h>
18#include <linux/uaccess.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mm.h>
23#include <linux/sched.h>
e74d83aa 24#include <linux/slab.h>
de1135d4
LP		 25#include <media/v4l2-event.h>
26
27#include "isp.h"
28#include "ispreg.h"
29#include "ispccdc.h"
30
a64909b8
LP		 31#define CCDC_MIN_WIDTH 32
32#define CCDC_MIN_HEIGHT 32
33
de1135d4
LP		 34static struct v4l2_mbus_framefmt *
35__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
36 unsigned int pad, enum v4l2_subdev_format_whence which);
37
38static const unsigned int ccdc_fmts[] = {
39 V4L2_MBUS_FMT_Y8_1X8,
5782f97b
MJ		 40 V4L2_MBUS_FMT_Y10_1X10,
41 V4L2_MBUS_FMT_Y12_1X12,
42 V4L2_MBUS_FMT_SGRBG8_1X8,
43 V4L2_MBUS_FMT_SRGGB8_1X8,
44 V4L2_MBUS_FMT_SBGGR8_1X8,
45 V4L2_MBUS_FMT_SGBRG8_1X8,
de1135d4
LP		 46 V4L2_MBUS_FMT_SGRBG10_1X10,
47 V4L2_MBUS_FMT_SRGGB10_1X10,
48 V4L2_MBUS_FMT_SBGGR10_1X10,
49 V4L2_MBUS_FMT_SGBRG10_1X10,
50 V4L2_MBUS_FMT_SGRBG12_1X12,
51 V4L2_MBUS_FMT_SRGGB12_1X12,
52 V4L2_MBUS_FMT_SBGGR12_1X12,
53 V4L2_MBUS_FMT_SGBRG12_1X12,
c51364ca
LP		 54 V4L2_MBUS_FMT_YUYV8_2X8,
55 V4L2_MBUS_FMT_UYVY8_2X8,
de1135d4
LP		 56};
57
58/*
59 * ccdc_print_status - Print current CCDC Module register values.
60 * @ccdc: Pointer to ISP CCDC device.
61 *
62 * Also prints other debug information stored in the CCDC module.
63 */
64#define CCDC_PRINT_REGISTER(isp, name)\
65 dev_dbg(isp->dev, "###CCDC " #name "=0x%08x\n", \
66 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_##name))
67
68static void ccdc_print_status(struct isp_ccdc_device *ccdc)
69{
70 struct isp_device *isp = to_isp_device(ccdc);
71
72 dev_dbg(isp->dev, "-------------CCDC Register dump-------------\n");
73
74 CCDC_PRINT_REGISTER(isp, PCR);
75 CCDC_PRINT_REGISTER(isp, SYN_MODE);
76 CCDC_PRINT_REGISTER(isp, HD_VD_WID);
77 CCDC_PRINT_REGISTER(isp, PIX_LINES);
78 CCDC_PRINT_REGISTER(isp, HORZ_INFO);
79 CCDC_PRINT_REGISTER(isp, VERT_START);
80 CCDC_PRINT_REGISTER(isp, VERT_LINES);
81 CCDC_PRINT_REGISTER(isp, CULLING);
82 CCDC_PRINT_REGISTER(isp, HSIZE_OFF);
83 CCDC_PRINT_REGISTER(isp, SDOFST);
84 CCDC_PRINT_REGISTER(isp, SDR_ADDR);
85 CCDC_PRINT_REGISTER(isp, CLAMP);
86 CCDC_PRINT_REGISTER(isp, DCSUB);
87 CCDC_PRINT_REGISTER(isp, COLPTN);
88 CCDC_PRINT_REGISTER(isp, BLKCMP);
89 CCDC_PRINT_REGISTER(isp, FPC);
90 CCDC_PRINT_REGISTER(isp, FPC_ADDR);
91 CCDC_PRINT_REGISTER(isp, VDINT);
92 CCDC_PRINT_REGISTER(isp, ALAW);
93 CCDC_PRINT_REGISTER(isp, REC656IF);
94 CCDC_PRINT_REGISTER(isp, CFG);
95 CCDC_PRINT_REGISTER(isp, FMTCFG);
96 CCDC_PRINT_REGISTER(isp, FMT_HORZ);
97 CCDC_PRINT_REGISTER(isp, FMT_VERT);
98 CCDC_PRINT_REGISTER(isp, PRGEVEN0);
99 CCDC_PRINT_REGISTER(isp, PRGEVEN1);
100 CCDC_PRINT_REGISTER(isp, PRGODD0);
101 CCDC_PRINT_REGISTER(isp, PRGODD1);
102 CCDC_PRINT_REGISTER(isp, VP_OUT);
103 CCDC_PRINT_REGISTER(isp, LSC_CONFIG);
104 CCDC_PRINT_REGISTER(isp, LSC_INITIAL);
105 CCDC_PRINT_REGISTER(isp, LSC_TABLE_BASE);
106 CCDC_PRINT_REGISTER(isp, LSC_TABLE_OFFSET);
107
108 dev_dbg(isp->dev, "--------------------------------------------\n");
109}
110
111/*
112 * omap3isp_ccdc_busy - Get busy state of the CCDC.
113 * @ccdc: Pointer to ISP CCDC device.
114 */
115int omap3isp_ccdc_busy(struct isp_ccdc_device *ccdc)
116{
117 struct isp_device *isp = to_isp_device(ccdc);
118
119 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
120 ISPCCDC_PCR_BUSY;
121}
122
123/* -----------------------------------------------------------------------------
124 * Lens Shading Compensation
125 */
126
127/*
128 * ccdc_lsc_validate_config - Check that LSC configuration is valid.
129 * @ccdc: Pointer to ISP CCDC device.
130 * @lsc_cfg: the LSC configuration to check.
131 *
132 * Returns 0 if the LSC configuration is valid, or -EINVAL if invalid.
133 */
134static int ccdc_lsc_validate_config(struct isp_ccdc_device *ccdc,
135 struct omap3isp_ccdc_lsc_config *lsc_cfg)
136{
137 struct isp_device *isp = to_isp_device(ccdc);
138 struct v4l2_mbus_framefmt *format;
139 unsigned int paxel_width, paxel_height;
140 unsigned int paxel_shift_x, paxel_shift_y;
141 unsigned int min_width, min_height, min_size;
142 unsigned int input_width, input_height;
143
144 paxel_shift_x = lsc_cfg->gain_mode_m;
145 paxel_shift_y = lsc_cfg->gain_mode_n;
146
147 if ((paxel_shift_x < 2) || (paxel_shift_x > 6) ||
148 (paxel_shift_y < 2) || (paxel_shift_y > 6)) {
149 dev_dbg(isp->dev, "CCDC: LSC: Invalid paxel size\n");
150 return -EINVAL;
151 }
152
153 if (lsc_cfg->offset & 3) {
154 dev_dbg(isp->dev, "CCDC: LSC: Offset must be a multiple of "
155 "4\n");
156 return -EINVAL;
157 }
158
159 if ((lsc_cfg->initial_x & 1) || (lsc_cfg->initial_y & 1)) {
160 dev_dbg(isp->dev, "CCDC: LSC: initial_x and y must be even\n");
161 return -EINVAL;
162 }
163
164 format = __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
165 V4L2_SUBDEV_FORMAT_ACTIVE);
166 input_width = format->width;
167 input_height = format->height;
168
169 /* Calculate minimum bytesize for validation */
170 paxel_width = 1 << paxel_shift_x;
171 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1)
172 >> paxel_shift_x) + 1;
173
174 paxel_height = 1 << paxel_shift_y;
175 min_height = ((input_height + lsc_cfg->initial_y + paxel_height - 1)
176 >> paxel_shift_y) + 1;
177
178 min_size = 4 * min_width * min_height;
179 if (min_size > lsc_cfg->size) {
180 dev_dbg(isp->dev, "CCDC: LSC: too small table\n");
181 return -EINVAL;
182 }
183 if (lsc_cfg->offset < (min_width * 4)) {
184 dev_dbg(isp->dev, "CCDC: LSC: Offset is too small\n");
185 return -EINVAL;
186 }
187 if ((lsc_cfg->size / lsc_cfg->offset) < min_height) {
188 dev_dbg(isp->dev, "CCDC: LSC: Wrong size/offset combination\n");
189 return -EINVAL;
190 }
191 return 0;
192}
193
194/*
195 * ccdc_lsc_program_table - Program Lens Shading Compensation table address.
196 * @ccdc: Pointer to ISP CCDC device.
197 */
d33186d0
LP		 198static void ccdc_lsc_program_table(struct isp_ccdc_device *ccdc,
199 dma_addr_t addr)
de1135d4
LP		 200{
201 isp_reg_writel(to_isp_device(ccdc), addr,
202 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
203}
204
205/*
206 * ccdc_lsc_setup_regs - Configures the lens shading compensation module
207 * @ccdc: Pointer to ISP CCDC device.
208 */
209static void ccdc_lsc_setup_regs(struct isp_ccdc_device *ccdc,
210 struct omap3isp_ccdc_lsc_config *cfg)
211{
212 struct isp_device *isp = to_isp_device(ccdc);
213 int reg;
214
215 isp_reg_writel(isp, cfg->offset, OMAP3_ISP_IOMEM_CCDC,
216 ISPCCDC_LSC_TABLE_OFFSET);
217
218 reg = 0;
219 reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
220 reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
221 reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
222 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
223
224 reg = 0;
225 reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
226 reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
227 reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
228 reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
229 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC,
230 ISPCCDC_LSC_INITIAL);
231}
232
233static int ccdc_lsc_wait_prefetch(struct isp_ccdc_device *ccdc)
234{
235 struct isp_device *isp = to_isp_device(ccdc);
236 unsigned int wait;
237
238 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
239 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
240
241 /* timeout 1 ms */
242 for (wait = 0; wait < 1000; wait++) {
243 if (isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS) &
244 IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ) {
245 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
246 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
247 return 0;
248 }
249
250 rmb();
251 udelay(1);
252 }
253
254 return -ETIMEDOUT;
255}
256
257/*
258 * __ccdc_lsc_enable - Enables/Disables the Lens Shading Compensation module.
259 * @ccdc: Pointer to ISP CCDC device.
260 * @enable: 0 Disables LSC, 1 Enables LSC.
261 */
262static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable)
263{
264 struct isp_device *isp = to_isp_device(ccdc);
265 const struct v4l2_mbus_framefmt *format =
266 __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
267 V4L2_SUBDEV_FORMAT_ACTIVE);
268
269 if ((format->code != V4L2_MBUS_FMT_SGRBG10_1X10) &&
270 (format->code != V4L2_MBUS_FMT_SRGGB10_1X10) &&
271 (format->code != V4L2_MBUS_FMT_SBGGR10_1X10) &&
272 (format->code != V4L2_MBUS_FMT_SGBRG10_1X10))
273 return -EINVAL;
274
275 if (enable)
276 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_LSC_READ);
277
278 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
279 ISPCCDC_LSC_ENABLE, enable ? ISPCCDC_LSC_ENABLE : 0);
280
281 if (enable) {
282 if (ccdc_lsc_wait_prefetch(ccdc) < 0) {
283 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC,
284 ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE);
285 ccdc->lsc.state = LSC_STATE_STOPPED;
25aeb418 286 dev_warn(to_device(ccdc), "LSC prefetch timeout\n");
de1135d4
LP		 287 return -ETIMEDOUT;
288 }
289 ccdc->lsc.state = LSC_STATE_RUNNING;
290 } else {
291 ccdc->lsc.state = LSC_STATE_STOPPING;
292 }
293
294 return 0;
295}
296
297static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
298{
299 struct isp_device *isp = to_isp_device(ccdc);
300
301 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG) &
302 ISPCCDC_LSC_BUSY;
303}
304
305/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
306 * @ccdc: Pointer to ISP CCDC device
307 * @req: New configuration request
308 *
309 * context: in_interrupt()
310 */
311static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
312 struct ispccdc_lsc_config_req *req)
313{
314 if (!req->enable)
315 return -EINVAL;
316
317 if (ccdc_lsc_validate_config(ccdc, &req->config) < 0) {
318 dev_dbg(to_device(ccdc), "Discard LSC configuration\n");
319 return -EINVAL;
320 }
321
322 if (ccdc_lsc_busy(ccdc))
323 return -EBUSY;
324
325 ccdc_lsc_setup_regs(ccdc, &req->config);
d33186d0 326 ccdc_lsc_program_table(ccdc, req->table.dma);
de1135d4
LP		 327 return 0;
328}
329
330/*
331 * ccdc_lsc_error_handler - Handle LSC prefetch error scenario.
332 * @ccdc: Pointer to ISP CCDC device.
333 *
334 * Disables LSC, and defers enablement to shadow registers update time.
335 */
336static void ccdc_lsc_error_handler(struct isp_ccdc_device *ccdc)
337{
338 struct isp_device *isp = to_isp_device(ccdc);
339 /*
340 * From OMAP3 TRM: When this event is pending, the module
341 * goes into transparent mode (output =input). Normal
342 * operation can be resumed at the start of the next frame
343 * after:
344 * 1) Clearing this event
345 * 2) Disabling the LSC module
346 * 3) Enabling it
347 */
348 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
349 ISPCCDC_LSC_ENABLE);
350 ccdc->lsc.state = LSC_STATE_STOPPED;
351}
352
353static void ccdc_lsc_free_request(struct isp_ccdc_device *ccdc,
354 struct ispccdc_lsc_config_req *req)
355{
356 struct isp_device *isp = to_isp_device(ccdc);
357
358 if (req == NULL)
359 return;
360
d33186d0
LP		 361 if (req->table.addr) {
362 sg_free_table(&req->table.sgt);
363 dma_free_coherent(isp->dev, req->config.size, req->table.addr,
364 req->table.dma);
365 }
366
de1135d4
LP		 367 kfree(req);
368}
369
370static void ccdc_lsc_free_queue(struct isp_ccdc_device *ccdc,
371 struct list_head *queue)
372{
373 struct ispccdc_lsc_config_req *req, *n;
374 unsigned long flags;
375
376 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
377 list_for_each_entry_safe(req, n, queue, list) {
378 list_del(&req->list);
379 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
380 ccdc_lsc_free_request(ccdc, req);
381 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
382 }
383 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
384}
385
386static void ccdc_lsc_free_table_work(struct work_struct *work)
387{
388 struct isp_ccdc_device *ccdc;
389 struct ispccdc_lsc *lsc;
390
391 lsc = container_of(work, struct ispccdc_lsc, table_work);
392 ccdc = container_of(lsc, struct isp_ccdc_device, lsc);
393
394 ccdc_lsc_free_queue(ccdc, &lsc->free_queue);
395}
396
397/*
398 * ccdc_lsc_config - Configure the LSC module from a userspace request
399 *
400 * Store the request LSC configuration in the LSC engine request pointer. The
401 * configuration will be applied to the hardware when the CCDC will be enabled,
402 * or at the next LSC interrupt if the CCDC is already running.
403 */
404static int ccdc_lsc_config(struct isp_ccdc_device *ccdc,
405 struct omap3isp_ccdc_update_config *config)
406{
407 struct isp_device *isp = to_isp_device(ccdc);
408 struct ispccdc_lsc_config_req *req;
409 unsigned long flags;
de1135d4
LP		 410 u16 update;
411 int ret;
412
413 update = config->update &
414 (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC);
415 if (!update)
416 return 0;
417
418 if (update != (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC)) {
419 dev_dbg(to_device(ccdc), "%s: Both LSC configuration and table "
420 "need to be supplied\n", __func__);
421 return -EINVAL;
422 }
423
424 req = kzalloc(sizeof(*req), GFP_KERNEL);
425 if (req == NULL)
426 return -ENOMEM;
427
428 if (config->flag & OMAP3ISP_CCDC_CONFIG_LSC) {
429 if (copy_from_user(&req->config, config->lsc_cfg,
430 sizeof(req->config))) {
431 ret = -EFAULT;
432 goto done;
433 }
434
435 req->enable = 1;
436
d33186d0
LP		 437 req->table.addr = dma_alloc_coherent(isp->dev, req->config.size,
438 &req->table.dma,
439 GFP_KERNEL);
440 if (req->table.addr == NULL) {
de1135d4
LP		 441 ret = -ENOMEM;
442 goto done;
443 }
444
d33186d0
LP		 445 ret = dma_get_sgtable(isp->dev, &req->table.sgt,
446 req->table.addr, req->table.dma,
447 req->config.size);
448 if (ret < 0)
de1135d4 449 goto done;
de1135d4 450
d33186d0
LP		 451 dma_sync_sg_for_cpu(isp->dev, req->table.sgt.sgl,
452 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4 453
d33186d0
LP		 454 if (copy_from_user(req->table.addr, config->lsc,
455 req->config.size)) {
de1135d4
LP		 456 ret = -EFAULT;
457 goto done;
458 }
459
d33186d0
LP		 460 dma_sync_sg_for_device(isp->dev, req->table.sgt.sgl,
461 req->table.sgt.nents, DMA_TO_DEVICE);
de1135d4
LP		 462 }
463
464 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
465 if (ccdc->lsc.request) {
466 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
467 schedule_work(&ccdc->lsc.table_work);
468 }
469 ccdc->lsc.request = req;
470 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
471
472 ret = 0;
473
474done:
475 if (ret < 0)
476 ccdc_lsc_free_request(ccdc, req);
477
478 return ret;
479}
480
481static inline int ccdc_lsc_is_configured(struct isp_ccdc_device *ccdc)
482{
483 unsigned long flags;
484
485 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
486 if (ccdc->lsc.active) {
487 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
488 return 1;
489 }
490 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
491 return 0;
492}
493
494static int ccdc_lsc_enable(struct isp_ccdc_device *ccdc)
495{
496 struct ispccdc_lsc *lsc = &ccdc->lsc;
497
498 if (lsc->state != LSC_STATE_STOPPED)
499 return -EINVAL;
500
501 if (lsc->active) {
502 list_add_tail(&lsc->active->list, &lsc->free_queue);
503 lsc->active = NULL;
504 }
505
506 if (__ccdc_lsc_configure(ccdc, lsc->request) < 0) {
507 omap3isp_sbl_disable(to_isp_device(ccdc),
508 OMAP3_ISP_SBL_CCDC_LSC_READ);
509 list_add_tail(&lsc->request->list, &lsc->free_queue);
510 lsc->request = NULL;
511 goto done;
512 }
513
514 lsc->active = lsc->request;
515 lsc->request = NULL;
516 __ccdc_lsc_enable(ccdc, 1);
517
518done:
519 if (!list_empty(&lsc->free_queue))
520 schedule_work(&lsc->table_work);
521
522 return 0;
523}
524
525/* -----------------------------------------------------------------------------
526 * Parameters configuration
527 */
528
529/*
530 * ccdc_configure_clamp - Configure optical-black or digital clamping
531 * @ccdc: Pointer to ISP CCDC device.
532 *
533 * The CCDC performs either optical-black or digital clamp. Configure and enable
534 * the selected clamp method.
535 */
536static void ccdc_configure_clamp(struct isp_ccdc_device *ccdc)
537{
538 struct isp_device *isp = to_isp_device(ccdc);
539 u32 clamp;
540
541 if (ccdc->obclamp) {
542 clamp = ccdc->clamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
543 clamp |= ccdc->clamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
544 clamp |= ccdc->clamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
545 clamp |= ccdc->clamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
546 isp_reg_writel(isp, clamp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP);
547 } else {
548 isp_reg_writel(isp, ccdc->clamp.dcsubval,
549 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB);
550 }
551
552 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
553 ISPCCDC_CLAMP_CLAMPEN,
554 ccdc->obclamp ? ISPCCDC_CLAMP_CLAMPEN : 0);
555}
556
557/*
558 * ccdc_configure_fpc - Configure Faulty Pixel Correction
559 * @ccdc: Pointer to ISP CCDC device.
560 */
561static void ccdc_configure_fpc(struct isp_ccdc_device *ccdc)
562{
563 struct isp_device *isp = to_isp_device(ccdc);
564
565 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, ISPCCDC_FPC_FPCEN);
566
567 if (!ccdc->fpc_en)
568 return;
569
c60e153d 570 isp_reg_writel(isp, ccdc->fpc.dma, OMAP3_ISP_IOMEM_CCDC,
de1135d4
LP		 571 ISPCCDC_FPC_ADDR);
572 /* The FPNUM field must be set before enabling FPC. */
573 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
574 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
575 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT) |
576 ISPCCDC_FPC_FPCEN, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
577}
578
579/*
580 * ccdc_configure_black_comp - Configure Black Level Compensation.
581 * @ccdc: Pointer to ISP CCDC device.
582 */
583static void ccdc_configure_black_comp(struct isp_ccdc_device *ccdc)
584{
585 struct isp_device *isp = to_isp_device(ccdc);
586 u32 blcomp;
587
588 blcomp = ccdc->blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
589 blcomp |= ccdc->blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
590 blcomp |= ccdc->blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
591 blcomp |= ccdc->blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
592
593 isp_reg_writel(isp, blcomp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
594}
595
596/*
597 * ccdc_configure_lpf - Configure Low-Pass Filter (LPF).
598 * @ccdc: Pointer to ISP CCDC device.
599 */
600static void ccdc_configure_lpf(struct isp_ccdc_device *ccdc)
601{
602 struct isp_device *isp = to_isp_device(ccdc);
603
604 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
605 ISPCCDC_SYN_MODE_LPF,
606 ccdc->lpf ? ISPCCDC_SYN_MODE_LPF : 0);
607}
608
609/*
610 * ccdc_configure_alaw - Configure A-law compression.
611 * @ccdc: Pointer to ISP CCDC device.
612 */
613static void ccdc_configure_alaw(struct isp_ccdc_device *ccdc)
614{
615 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 616 const struct isp_format_info *info;
de1135d4
LP		 617 u32 alaw = 0;
618
73ea57eb
LP		 619 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
620
621 switch (info->width) {
de1135d4
LP		 622 case 8:
623 return;
624
625 case 10:
626 alaw = ISPCCDC_ALAW_GWDI_9_0;
627 break;
628 case 11:
629 alaw = ISPCCDC_ALAW_GWDI_10_1;
630 break;
631 case 12:
632 alaw = ISPCCDC_ALAW_GWDI_11_2;
633 break;
634 case 13:
635 alaw = ISPCCDC_ALAW_GWDI_12_3;
636 break;
637 }
638
639 if (ccdc->alaw)
640 alaw |= ISPCCDC_ALAW_CCDTBL;
641
642 isp_reg_writel(isp, alaw, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
643}
644
645/*
646 * ccdc_config_imgattr - Configure sensor image specific attributes.
647 * @ccdc: Pointer to ISP CCDC device.
648 * @colptn: Color pattern of the sensor.
649 */
650static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn)
651{
652 struct isp_device *isp = to_isp_device(ccdc);
653
654 isp_reg_writel(isp, colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
655}
656
657/*
658 * ccdc_config - Set CCDC configuration from userspace
659 * @ccdc: Pointer to ISP CCDC device.
872aba51 660 * @ccdc_struct: Structure containing CCDC configuration sent from userspace.
de1135d4
LP		 661 *
662 * Returns 0 if successful, -EINVAL if the pointer to the configuration
663 * structure is null, or the copy_from_user function fails to copy user space
664 * memory to kernel space memory.
665 */
666static int ccdc_config(struct isp_ccdc_device *ccdc,
667 struct omap3isp_ccdc_update_config *ccdc_struct)
668{
669 struct isp_device *isp = to_isp_device(ccdc);
670 unsigned long flags;
671
672 spin_lock_irqsave(&ccdc->lock, flags);
673 ccdc->shadow_update = 1;
674 spin_unlock_irqrestore(&ccdc->lock, flags);
675
676 if (OMAP3ISP_CCDC_ALAW & ccdc_struct->update) {
677 ccdc->alaw = !!(OMAP3ISP_CCDC_ALAW & ccdc_struct->flag);
678 ccdc->update |= OMAP3ISP_CCDC_ALAW;
679 }
680
681 if (OMAP3ISP_CCDC_LPF & ccdc_struct->update) {
682 ccdc->lpf = !!(OMAP3ISP_CCDC_LPF & ccdc_struct->flag);
683 ccdc->update |= OMAP3ISP_CCDC_LPF;
684 }
685
686 if (OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->update) {
687 if (copy_from_user(&ccdc->clamp, ccdc_struct->bclamp,
688 sizeof(ccdc->clamp))) {
689 ccdc->shadow_update = 0;
690 return -EFAULT;
691 }
692
693 ccdc->obclamp = !!(OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->flag);
694 ccdc->update |= OMAP3ISP_CCDC_BLCLAMP;
695 }
696
697 if (OMAP3ISP_CCDC_BCOMP & ccdc_struct->update) {
698 if (copy_from_user(&ccdc->blcomp, ccdc_struct->blcomp,
699 sizeof(ccdc->blcomp))) {
700 ccdc->shadow_update = 0;
701 return -EFAULT;
702 }
703
704 ccdc->update |= OMAP3ISP_CCDC_BCOMP;
705 }
706
707 ccdc->shadow_update = 0;
708
709 if (OMAP3ISP_CCDC_FPC & ccdc_struct->update) {
c60e153d
LP		 710 struct omap3isp_ccdc_fpc fpc;
711 struct ispccdc_fpc fpc_old = { .addr = NULL, };
712 struct ispccdc_fpc fpc_new;
de1135d4
LP		 713 u32 size;
714
715 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
716 return -EBUSY;
717
718 ccdc->fpc_en = !!(OMAP3ISP_CCDC_FPC & ccdc_struct->flag);
719
720 if (ccdc->fpc_en) {
c60e153d 721 if (copy_from_user(&fpc, ccdc_struct->fpc, sizeof(fpc)))
de1135d4
LP		 722 return -EFAULT;
723
c60e153d
LP		 724 size = fpc.fpnum * 4;
725
de1135d4 726 /*
c60e153d
LP		 727 * The table address must be 64-bytes aligned, which is
728 * guaranteed by dma_alloc_coherent().
de1135d4 729 */
c60e153d
LP		 730 fpc_new.fpnum = fpc.fpnum;
731 fpc_new.addr = dma_alloc_coherent(isp->dev, size,
732 &fpc_new.dma,
733 GFP_KERNEL);
734 if (fpc_new.addr == NULL)
de1135d4
LP		 735 return -ENOMEM;
736
c60e153d
LP		 737 if (copy_from_user(fpc_new.addr,
738 (__force void __user *)fpc.fpcaddr,
739 size)) {
740 dma_free_coherent(isp->dev, size, fpc_new.addr,
741 fpc_new.dma);
de1135d4
LP		 742 return -EFAULT;
743 }
744
c60e153d
LP		 745 fpc_old = ccdc->fpc;
746 ccdc->fpc = fpc_new;
de1135d4
LP		 747 }
748
749 ccdc_configure_fpc(ccdc);
c60e153d
LP		 750
751 if (fpc_old.addr != NULL)
752 dma_free_coherent(isp->dev, fpc_old.fpnum * 4,
753 fpc_old.addr, fpc_old.dma);
de1135d4
LP		 754 }
755
756 return ccdc_lsc_config(ccdc, ccdc_struct);
757}
758
759static void ccdc_apply_controls(struct isp_ccdc_device *ccdc)
760{
761 if (ccdc->update & OMAP3ISP_CCDC_ALAW) {
762 ccdc_configure_alaw(ccdc);
763 ccdc->update &= ~OMAP3ISP_CCDC_ALAW;
764 }
765
766 if (ccdc->update & OMAP3ISP_CCDC_LPF) {
767 ccdc_configure_lpf(ccdc);
768 ccdc->update &= ~OMAP3ISP_CCDC_LPF;
769 }
770
771 if (ccdc->update & OMAP3ISP_CCDC_BLCLAMP) {
772 ccdc_configure_clamp(ccdc);
773 ccdc->update &= ~OMAP3ISP_CCDC_BLCLAMP;
774 }
775
776 if (ccdc->update & OMAP3ISP_CCDC_BCOMP) {
777 ccdc_configure_black_comp(ccdc);
778 ccdc->update &= ~OMAP3ISP_CCDC_BCOMP;
779 }
780}
781
782/*
783 * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers
872aba51 784 * @isp: Pointer to ISP device
de1135d4
LP		 785 */
786void omap3isp_ccdc_restore_context(struct isp_device *isp)
787{
788 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
789
790 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
791
792 ccdc->update = OMAP3ISP_CCDC_ALAW | OMAP3ISP_CCDC_LPF
793 | OMAP3ISP_CCDC_BLCLAMP | OMAP3ISP_CCDC_BCOMP;
794 ccdc_apply_controls(ccdc);
795 ccdc_configure_fpc(ccdc);
796}
797
798/* -----------------------------------------------------------------------------
799 * Format- and pipeline-related configuration helpers
800 */
801
802/*
803 * ccdc_config_vp - Configure the Video Port.
804 * @ccdc: Pointer to ISP CCDC device.
805 */
806static void ccdc_config_vp(struct isp_ccdc_device *ccdc)
807{
808 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
809 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 810 const struct isp_format_info *info;
aec2de0e 811 struct v4l2_mbus_framefmt *format;
de1135d4
LP		 812 unsigned long l3_ick = pipe->l3_ick;
813 unsigned int max_div = isp->revision == ISP_REVISION_15_0 ? 64 : 8;
814 unsigned int div = 0;
aec2de0e
LP		 815 u32 fmtcfg = ISPCCDC_FMTCFG_VPEN;
816
817 format = &ccdc->formats[CCDC_PAD_SOURCE_VP];
818
819 if (!format->code) {
820 /* Disable the video port when the input format isn't supported.
821 * This is indicated by a pixel code set to 0.
822 */
823 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
824 return;
825 }
826
827 isp_reg_writel(isp, (0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
828 (format->width << ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
829 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ);
830 isp_reg_writel(isp, (0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
831 ((format->height + 1) << ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
832 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT);
de1135d4 833
aec2de0e
LP		 834 isp_reg_writel(isp, (format->width << ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
835 (format->height << ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
836 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
de1135d4 837
73ea57eb
LP		 838 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
839
840 switch (info->width) {
de1135d4
LP		 841 case 8:
842 case 10:
aec2de0e 843 fmtcfg |= ISPCCDC_FMTCFG_VPIN_9_0;
de1135d4
LP		 844 break;
845 case 11:
aec2de0e 846 fmtcfg |= ISPCCDC_FMTCFG_VPIN_10_1;
de1135d4
LP		 847 break;
848 case 12:
aec2de0e 849 fmtcfg |= ISPCCDC_FMTCFG_VPIN_11_2;
de1135d4
LP		 850 break;
851 case 13:
aec2de0e 852 fmtcfg |= ISPCCDC_FMTCFG_VPIN_12_3;
de1135d4 853 break;
13eaaa7f 854 }
de1135d4
LP		 855
856 if (pipe->input)
857 div = DIV_ROUND_UP(l3_ick, pipe->max_rate);
c6c01f97
SA		 858 else if (pipe->external_rate)
859 div = l3_ick / pipe->external_rate;
de1135d4
LP		 860
861 div = clamp(div, 2U, max_div);
aec2de0e 862 fmtcfg |= (div - 2) << ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT;
de1135d4 863
aec2de0e 864 isp_reg_writel(isp, fmtcfg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
de1135d4
LP		 865}
866
867/*
868 * ccdc_config_outlineoffset - Configure memory saving output line offset
869 * @ccdc: Pointer to ISP CCDC device.
bcb4e0ef
LP		 870 * @bpl: Number of bytes per line when stored in memory.
871 * @field: Field order when storing interlaced formats in memory.
de1135d4 872 *
bcb4e0ef
LP		 873 * Configure the offsets for the line output control:
874 *
875 * - The horizontal line offset is defined as the number of bytes between the
876 * start of two consecutive lines in memory. Set it to the given bytes per
877 * line value.
878 *
879 * - The field offset value is defined as the number of lines to offset the
880 * start of the field identified by FID = 1. Set it to one.
881 *
882 * - The line offset values are defined as the number of lines (as defined by
883 * the horizontal line offset) between the start of two consecutive lines for
884 * all combinations of odd/even lines in odd/even fields. When interleaving
885 * fields set them all to two lines, and to one line otherwise.
de1135d4
LP		 886 */
887static void ccdc_config_outlineoffset(struct isp_ccdc_device *ccdc,
bcb4e0ef
LP		 888 unsigned int bpl,
889 enum v4l2_field field)
de1135d4
LP		 890{
891 struct isp_device *isp = to_isp_device(ccdc);
bcb4e0ef 892 u32 sdofst = 0;
de1135d4 893
bcb4e0ef
LP		 894 isp_reg_writel(isp, bpl & 0xffff, OMAP3_ISP_IOMEM_CCDC,
895 ISPCCDC_HSIZE_OFF);
de1135d4 896
bcb4e0ef
LP		 897 switch (field) {
898 case V4L2_FIELD_INTERLACED_TB:
899 case V4L2_FIELD_INTERLACED_BT:
900 /* When interleaving fields in memory offset field one by one
901 * line and set the line offset to two lines.
902 */
903 sdofst |= (1 << ISPCCDC_SDOFST_LOFST0_SHIFT)
904 | (1 << ISPCCDC_SDOFST_LOFST1_SHIFT)
905 | (1 << ISPCCDC_SDOFST_LOFST2_SHIFT)
906 | (1 << ISPCCDC_SDOFST_LOFST3_SHIFT);
de1135d4 907 break;
bcb4e0ef 908
de1135d4 909 default:
bcb4e0ef 910 /* In all other cases set the line offsets to one line. */
de1135d4
LP		 911 break;
912 }
bcb4e0ef
LP		 913
914 isp_reg_writel(isp, sdofst, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST);
de1135d4
LP		 915}
916
917/*
918 * ccdc_set_outaddr - Set memory address to save output image
919 * @ccdc: Pointer to ISP CCDC device.
920 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
921 *
922 * Sets the memory address where the output will be saved.
923 */
924static void ccdc_set_outaddr(struct isp_ccdc_device *ccdc, u32 addr)
925{
926 struct isp_device *isp = to_isp_device(ccdc);
927
928 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
929}
930
931/*
932 * omap3isp_ccdc_max_rate - Calculate maximum input data rate based on the input
933 * @ccdc: Pointer to ISP CCDC device.
934 * @max_rate: Maximum calculated data rate.
935 *
936 * Returns in *max_rate less value between calculated and passed
937 */
938void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
939 unsigned int *max_rate)
940{
941 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
942 unsigned int rate;
943
944 if (pipe == NULL)
945 return;
946
947 /*
948 * TRM says that for parallel sensors the maximum data rate
949 * should be 90% form L3/2 clock, otherwise just L3/2.
950 */
951 if (ccdc->input == CCDC_INPUT_PARALLEL)
952 rate = pipe->l3_ick / 2 * 9 / 10;
953 else
954 rate = pipe->l3_ick / 2;
955
956 *max_rate = min(*max_rate, rate);
957}
958
959/*
960 * ccdc_config_sync_if - Set CCDC sync interface configuration
961 * @ccdc: Pointer to ISP CCDC device.
73ea57eb
LP		 962 * @pdata: Parallel interface platform data (may be NULL)
963 * @data_size: Data size
de1135d4
LP		 964 */
965static void ccdc_config_sync_if(struct isp_ccdc_device *ccdc,
73ea57eb
LP		 966 struct isp_parallel_platform_data *pdata,
967 unsigned int data_size)
de1135d4
LP		 968{
969 struct isp_device *isp = to_isp_device(ccdc);
c51364ca 970 const struct v4l2_mbus_framefmt *format;
cf7a3d91 971 u32 syn_mode = ISPCCDC_SYN_MODE_VDHDEN;
de1135d4 972
c51364ca
LP		 973 format = &ccdc->formats[CCDC_PAD_SINK];
974
975 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
976 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
9de7af4d
LP		 977 /* According to the OMAP3 TRM the input mode only affects SYNC
978 * mode, enabling BT.656 mode should take precedence. However,
979 * in practice setting the input mode to YCbCr data on 8 bits
980 * seems to be required in BT.656 mode. In SYNC mode set it to
981 * YCbCr on 16 bits as the bridge is enabled in that case.
c51364ca 982 */
9de7af4d
LP		 983 if (ccdc->bt656)
984 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
985 else
986 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
c51364ca
LP		 987 }
988
73ea57eb 989 switch (data_size) {
de1135d4
LP		 990 case 8:
991 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
992 break;
993 case 10:
994 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
995 break;
996 case 11:
997 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
998 break;
999 case 12:
1000 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
1001 break;
13eaaa7f 1002 }
de1135d4 1003
73ea57eb 1004 if (pdata && pdata->data_pol)
de1135d4 1005 syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
de1135d4 1006
73ea57eb 1007 if (pdata && pdata->hs_pol)
de1135d4 1008 syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
de1135d4 1009
9de7af4d
LP		 1010 /* The polarity of the vertical sync signal output by the BT.656
1011 * decoder is not documented and seems to be active low.
1012 */
1013 if ((pdata && pdata->vs_pol) || ccdc->bt656)
de1135d4 1014 syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
de1135d4 1015
9a36d8ed
LP		 1016 if (pdata && pdata->fld_pol)
1017 syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
1018
de1135d4 1019 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
c51364ca
LP		 1020
1021 /* The CCDC_CFG.Y8POS bit is used in YCbCr8 input mode only. The
1022 * hardware seems to ignore it in all other input modes.
1023 */
1024 if (format->code == V4L2_MBUS_FMT_UYVY8_2X8)
1025 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1026 ISPCCDC_CFG_Y8POS);
1027 else
1028 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1029 ISPCCDC_CFG_Y8POS);
1030
9de7af4d
LP		 1031 /* Enable or disable BT.656 mode, including error correction for the
1032 * synchronization codes.
1033 */
1034 if (ccdc->bt656)
1035 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1036 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1037 else
1038 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1039 ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH);
1040
de1135d4
LP		 1041}
1042
1043/* CCDC formats descriptions */
1044static const u32 ccdc_sgrbg_pattern =
1045 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1046 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1047 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1048 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1049 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1050 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1051 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1052 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1053 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1054 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1055 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1056 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1057 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1058 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1059 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1060 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1061
1062static const u32 ccdc_srggb_pattern =
1063 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1064 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1065 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1066 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1067 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1068 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1069 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1070 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1071 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1072 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1073 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1074 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1075 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1076 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1077 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1078 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1079
1080static const u32 ccdc_sbggr_pattern =
1081 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1082 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1083 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1084 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1085 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1086 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1087 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1088 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1089 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1090 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1091 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1092 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1093 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1094 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1095 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1096 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1097
1098static const u32 ccdc_sgbrg_pattern =
1099 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1100 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1101 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1102 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1103 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1104 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1105 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1106 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1107 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1108 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1109 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1110 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1111 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1112 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1113 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1114 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1115
1116static void ccdc_configure(struct isp_ccdc_device *ccdc)
1117{
1118 struct isp_device *isp = to_isp_device(ccdc);
1119 struct isp_parallel_platform_data *pdata = NULL;
1120 struct v4l2_subdev *sensor;
1121 struct v4l2_mbus_framefmt *format;
a64909b8 1122 const struct v4l2_rect *crop;
c09af044
MJ		 1123 const struct isp_format_info *fmt_info;
1124 struct v4l2_subdev_format fmt_src;
1125 unsigned int depth_out;
1126 unsigned int depth_in = 0;
de1135d4
LP		 1127 struct media_pad *pad;
1128 unsigned long flags;
c51364ca 1129 unsigned int bridge;
c09af044 1130 unsigned int shift;
9de7af4d
LP		 1131 unsigned int nph;
1132 unsigned int sph;
de1135d4
LP		 1133 u32 syn_mode;
1134 u32 ccdc_pattern;
1135
9de7af4d
LP		 1136 ccdc->bt656 = false;
1137
1bddf1b3 1138 pad = media_entity_remote_pad(&ccdc->pads[CCDC_PAD_SINK]);
c09af044 1139 sensor = media_entity_to_v4l2_subdev(pad->entity);
9de7af4d
LP		 1140 if (ccdc->input == CCDC_INPUT_PARALLEL) {
1141 struct v4l2_mbus_config cfg;
1142 int ret;
1143
1144 ret = v4l2_subdev_call(sensor, video, g_mbus_config, &cfg);
1145 if (!ret)
1146 ccdc->bt656 = cfg.type == V4L2_MBUS_BT656;
1147
de1135d4
LP		 1148 pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
1149 ->bus.parallel;
9de7af4d 1150 }
c09af044 1151
2e8f0172
LP		 1152 /* CCDC_PAD_SINK */
1153 format = &ccdc->formats[CCDC_PAD_SINK];
1154
c51364ca 1155 /* Compute the lane shifter shift value and enable the bridge when the
9de7af4d 1156 * input format is a non-BT.656 YUV variant.
c51364ca 1157 */
c09af044
MJ		 1158 fmt_src.pad = pad->index;
1159 fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1160 if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
1161 fmt_info = omap3isp_video_format_info(fmt_src.format.code);
1697e49a 1162 depth_in = fmt_info->width;
de1135d4
LP		 1163 }
1164
2e8f0172 1165 fmt_info = omap3isp_video_format_info(format->code);
1697e49a 1166 depth_out = fmt_info->width;
c09af044 1167 shift = depth_in - depth_out;
de1135d4 1168
9de7af4d
LP		 1169 if (ccdc->bt656)
1170 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
1171 else if (fmt_info->code == V4L2_MBUS_FMT_YUYV8_2X8)
c51364ca
LP		 1172 bridge = ISPCTRL_PAR_BRIDGE_LENDIAN;
1173 else if (fmt_info->code == V4L2_MBUS_FMT_UYVY8_2X8)
1174 bridge = ISPCTRL_PAR_BRIDGE_BENDIAN;
1175 else
1176 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
de1135d4 1177
c51364ca
LP		 1178 omap3isp_configure_bridge(isp, ccdc->input, pdata, shift, bridge);
1179
9a36d8ed 1180 /* Configure the sync interface. */
c51364ca 1181 ccdc_config_sync_if(ccdc, pdata, depth_out);
de1135d4
LP		 1182
1183 syn_mode = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1184
1185 /* Use the raw, unprocessed data when writing to memory. The H3A and
1186 * histogram modules are still fed with lens shading corrected data.
1187 */
1188 syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
1189
1190 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1191 syn_mode |= ISPCCDC_SYN_MODE_WEN;
1192 else
1193 syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
1194
1195 if (ccdc->output & CCDC_OUTPUT_RESIZER)
1196 syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
1197 else
1198 syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
1199
de1135d4
LP		 1200 /* Mosaic filter */
1201 switch (format->code) {
1202 case V4L2_MBUS_FMT_SRGGB10_1X10:
1203 case V4L2_MBUS_FMT_SRGGB12_1X12:
1204 ccdc_pattern = ccdc_srggb_pattern;
1205 break;
1206 case V4L2_MBUS_FMT_SBGGR10_1X10:
1207 case V4L2_MBUS_FMT_SBGGR12_1X12:
1208 ccdc_pattern = ccdc_sbggr_pattern;
1209 break;
1210 case V4L2_MBUS_FMT_SGBRG10_1X10:
1211 case V4L2_MBUS_FMT_SGBRG12_1X12:
1212 ccdc_pattern = ccdc_sgbrg_pattern;
1213 break;
1214 default:
1215 /* Use GRBG */
1216 ccdc_pattern = ccdc_sgrbg_pattern;
1217 break;
1218 }
1219 ccdc_config_imgattr(ccdc, ccdc_pattern);
1220
1221 /* Generate VD0 on the last line of the image and VD1 on the
1222 * 2/3 height line.
1223 */
1224 isp_reg_writel(isp, ((format->height - 2) << ISPCCDC_VDINT_0_SHIFT) |
1225 ((format->height * 2 / 3) << ISPCCDC_VDINT_1_SHIFT),
1226 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT);
1227
1228 /* CCDC_PAD_SOURCE_OF */
c51364ca 1229 format = &ccdc->formats[CCDC_PAD_SOURCE_OF];
a64909b8 1230 crop = &ccdc->crop;
de1135d4 1231
9de7af4d
LP		 1232 /* The horizontal coordinates are expressed in pixel clock cycles. We
1233 * need two cycles per pixel in BT.656 mode, and one cycle per pixel in
1234 * SYNC mode regardless of the format as the bridge is enabled for YUV
1235 * formats in that case.
1236 */
1237 if (ccdc->bt656) {
1238 sph = crop->left * 2;
1239 nph = crop->width * 2 - 1;
1240 } else {
1241 sph = crop->left;
1242 nph = crop->width - 1;
1243 }
1244
1245 isp_reg_writel(isp, (sph << ISPCCDC_HORZ_INFO_SPH_SHIFT) |
1246 (nph << ISPCCDC_HORZ_INFO_NPH_SHIFT),
de1135d4 1247 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO);
9de7af4d
LP		 1248 isp_reg_writel(isp, (crop->top << ISPCCDC_VERT_START_SLV0_SHIFT) |
1249 (crop->top << ISPCCDC_VERT_START_SLV1_SHIFT),
de1135d4 1250 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START);
a64909b8 1251 isp_reg_writel(isp, (crop->height - 1)
de1135d4
LP		 1252 << ISPCCDC_VERT_LINES_NLV_SHIFT,
1253 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES);
1254
bcb4e0ef
LP		 1255 ccdc_config_outlineoffset(ccdc, ccdc->video_out.bpl_value,
1256 format->field);
1257
1258 /* When interleaving fields enable processing of the field input signal.
1259 * This will cause the line output control module to apply the field
1260 * offset to field 1.
1261 */
1262 if (ccdc->formats[CCDC_PAD_SINK].field == V4L2_FIELD_ALTERNATE &&
1263 (format->field == V4L2_FIELD_INTERLACED_TB ||
1264 format->field == V4L2_FIELD_INTERLACED_BT))
1265 syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
de1135d4 1266
c51364ca
LP		 1267 /* The CCDC outputs data in UYVY order by default. Swap bytes to get
1268 * YUYV.
1269 */
1270 if (format->code == V4L2_MBUS_FMT_YUYV8_1X16)
1271 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1272 ISPCCDC_CFG_BSWD);
1273 else
1274 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1275 ISPCCDC_CFG_BSWD);
1276
9de7af4d
LP		 1277 /* Use PACK8 mode for 1byte per pixel formats. Check for BT.656 mode
1278 * explicitly as the driver reports 1X16 instead of 2X8 at the OF pad
1279 * for simplicity.
1280 */
1281 if (omap3isp_video_format_info(format->code)->width <= 8 || ccdc->bt656)
c51364ca
LP		 1282 syn_mode |= ISPCCDC_SYN_MODE_PACK8;
1283 else
1284 syn_mode &= ~ISPCCDC_SYN_MODE_PACK8;
1285
1286 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1287
de1135d4 1288 /* CCDC_PAD_SOURCE_VP */
aec2de0e 1289 ccdc_config_vp(ccdc);
de1135d4 1290
c51364ca 1291 /* Lens shading correction. */
de1135d4
LP		 1292 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1293 if (ccdc->lsc.request == NULL)
1294 goto unlock;
1295
1296 WARN_ON(ccdc->lsc.active);
1297
1298 /* Get last good LSC configuration. If it is not supported for
1299 * the current active resolution discard it.
1300 */
1301 if (ccdc->lsc.active == NULL &&
1302 __ccdc_lsc_configure(ccdc, ccdc->lsc.request) == 0) {
1303 ccdc->lsc.active = ccdc->lsc.request;
1304 } else {
1305 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
1306 schedule_work(&ccdc->lsc.table_work);
1307 }
1308
1309 ccdc->lsc.request = NULL;
1310
1311unlock:
1312 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1313
1314 ccdc_apply_controls(ccdc);
1315}
1316
1317static void __ccdc_enable(struct isp_ccdc_device *ccdc, int enable)
1318{
1319 struct isp_device *isp = to_isp_device(ccdc);
1320
1321 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR,
1322 ISPCCDC_PCR_EN, enable ? ISPCCDC_PCR_EN : 0);
1323}
1324
1325static int ccdc_disable(struct isp_ccdc_device *ccdc)
1326{
1327 unsigned long flags;
1328 int ret = 0;
1329
1330 spin_lock_irqsave(&ccdc->lock, flags);
1331 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1332 ccdc->stopping = CCDC_STOP_REQUEST;
1333 spin_unlock_irqrestore(&ccdc->lock, flags);
1334
1335 ret = wait_event_timeout(ccdc->wait,
1336 ccdc->stopping == CCDC_STOP_FINISHED,
1337 msecs_to_jiffies(2000));
1338 if (ret == 0) {
1339 ret = -ETIMEDOUT;
1340 dev_warn(to_device(ccdc), "CCDC stop timeout!\n");
1341 }
1342
1343 omap3isp_sbl_disable(to_isp_device(ccdc), OMAP3_ISP_SBL_CCDC_LSC_READ);
1344
1345 mutex_lock(&ccdc->ioctl_lock);
1346 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
1347 ccdc->lsc.request = ccdc->lsc.active;
1348 ccdc->lsc.active = NULL;
1349 cancel_work_sync(&ccdc->lsc.table_work);
1350 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
1351 mutex_unlock(&ccdc->ioctl_lock);
1352
1353 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
1354
1355 return ret > 0 ? 0 : ret;
1356}
1357
1358static void ccdc_enable(struct isp_ccdc_device *ccdc)
1359{
1360 if (ccdc_lsc_is_configured(ccdc))
1361 __ccdc_lsc_enable(ccdc, 1);
1362 __ccdc_enable(ccdc, 1);
1363}
1364
1365/* -----------------------------------------------------------------------------
1366 * Interrupt handling
1367 */
1368
1369/*
1370 * ccdc_sbl_busy - Poll idle state of CCDC and related SBL memory write bits
1371 * @ccdc: Pointer to ISP CCDC device.
1372 *
1373 * Returns zero if the CCDC is idle and the image has been written to
1374 * memory, too.
1375 */
1376static int ccdc_sbl_busy(struct isp_ccdc_device *ccdc)
1377{
1378 struct isp_device *isp = to_isp_device(ccdc);
1379
1380 return omap3isp_ccdc_busy(ccdc)
1381 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
1382 ISPSBL_CCDC_WR_0_DATA_READY)
1383 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
1384 ISPSBL_CCDC_WR_0_DATA_READY)
1385 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
1386 ISPSBL_CCDC_WR_0_DATA_READY)
1387 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
1388 ISPSBL_CCDC_WR_0_DATA_READY);
1389}
1390
1391/*
1392 * ccdc_sbl_wait_idle - Wait until the CCDC and related SBL are idle
1393 * @ccdc: Pointer to ISP CCDC device.
1394 * @max_wait: Max retry count in us for wait for idle/busy transition.
1395 */
1396static int ccdc_sbl_wait_idle(struct isp_ccdc_device *ccdc,
1397 unsigned int max_wait)
1398{
1399 unsigned int wait = 0;
1400
1401 if (max_wait == 0)
1402 max_wait = 10000; /* 10 ms */
1403
1404 for (wait = 0; wait <= max_wait; wait++) {
1405 if (!ccdc_sbl_busy(ccdc))
1406 return 0;
1407
1408 rmb();
1409 udelay(1);
1410 }
1411
1412 return -EBUSY;
1413}
1414
1415/* __ccdc_handle_stopping - Handle CCDC and/or LSC stopping sequence
1416 * @ccdc: Pointer to ISP CCDC device.
1417 * @event: Pointing which event trigger handler
1418 *
2d4e9d1d 1419 * Return 1 when the event and stopping request combination is satisfied,
de1135d4
LP		 1420 * zero otherwise.
1421 */
1422static int __ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
1423{
1424 int rval = 0;
1425
1426 switch ((ccdc->stopping & 3) | event) {
1427 case CCDC_STOP_REQUEST | CCDC_EVENT_VD1:
1428 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1429 __ccdc_lsc_enable(ccdc, 0);
1430 __ccdc_enable(ccdc, 0);
1431 ccdc->stopping = CCDC_STOP_EXECUTED;
1432 return 1;
1433
1434 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD0:
1435 ccdc->stopping |= CCDC_STOP_CCDC_FINISHED;
1436 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1437 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1438 rval = 1;
1439 break;
1440
1441 case CCDC_STOP_EXECUTED | CCDC_EVENT_LSC_DONE:
1442 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1443 rval = 1;
1444 break;
1445
1446 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD1:
1447 return 1;
1448 }
1449
1450 if (ccdc->stopping == CCDC_STOP_FINISHED) {
1451 wake_up(&ccdc->wait);
1452 rval = 1;
1453 }
1454
1455 return rval;
1456}
1457
1458static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
1459{
bd0f2e6d 1460 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
63ae37ea 1461 struct video_device *vdev = ccdc->subdev.devnode;
de1135d4
LP		 1462 struct v4l2_event event;
1463
b43883d6
LP		 1464 /* Frame number propagation */
1465 atomic_inc(&pipe->frame_number);
1466
de1135d4 1467 memset(&event, 0, sizeof(event));
69d232ae
SA		 1468 event.type = V4L2_EVENT_FRAME_SYNC;
1469 event.u.frame_sync.frame_sequence = atomic_read(&pipe->frame_number);
de1135d4
LP		 1470
1471 v4l2_event_queue(vdev, &event);
1472}
1473
1474/*
1475 * ccdc_lsc_isr - Handle LSC events
1476 * @ccdc: Pointer to ISP CCDC device.
1477 * @events: LSC events
1478 */
1479static void ccdc_lsc_isr(struct isp_ccdc_device *ccdc, u32 events)
1480{
1481 unsigned long flags;
1482
1483 if (events & IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ) {
875e2e3e
LP		 1484 struct isp_pipeline *pipe =
1485 to_isp_pipeline(&ccdc->subdev.entity);
1486
de1135d4 1487 ccdc_lsc_error_handler(ccdc);
875e2e3e 1488 pipe->error = true;
de1135d4
LP		 1489 dev_dbg(to_device(ccdc), "lsc prefetch error\n");
1490 }
1491
1492 if (!(events & IRQ0STATUS_CCDC_LSC_DONE_IRQ))
1493 return;
1494
1495 /* LSC_DONE interrupt occur, there are two cases
1496 * 1. stopping for reconfiguration
1497 * 2. stopping because of STREAM OFF command
1498 */
1499 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1500
1501 if (ccdc->lsc.state == LSC_STATE_STOPPING)
1502 ccdc->lsc.state = LSC_STATE_STOPPED;
1503
1504 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_LSC_DONE))
1505 goto done;
1506
1507 if (ccdc->lsc.state != LSC_STATE_RECONFIG)
1508 goto done;
1509
1510 /* LSC is in STOPPING state, change to the new state */
1511 ccdc->lsc.state = LSC_STATE_STOPPED;
1512
1513 /* This is an exception. Start of frame and LSC_DONE interrupt
1514 * have been received on the same time. Skip this event and wait
1515 * for better times.
1516 */
1517 if (events & IRQ0STATUS_HS_VS_IRQ)
1518 goto done;
1519
1520 /* The LSC engine is stopped at this point. Enable it if there's a
1521 * pending request.
1522 */
1523 if (ccdc->lsc.request == NULL)
1524 goto done;
1525
1526 ccdc_lsc_enable(ccdc);
1527
1528done:
1529 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1530}
1531
1532static int ccdc_isr_buffer(struct isp_ccdc_device *ccdc)
1533{
1534 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1535 struct isp_device *isp = to_isp_device(ccdc);
1536 struct isp_buffer *buffer;
bcb4e0ef 1537 enum v4l2_field field;
de1135d4
LP		 1538
1539 /* The CCDC generates VD0 interrupts even when disabled (the datasheet
1540 * doesn't explicitly state if that's supposed to happen or not, so it
1541 * can be considered as a hardware bug or as a feature, but we have to
1542 * deal with it anyway). Disabling the CCDC when no buffer is available
1543 * would thus not be enough, we need to handle the situation explicitly.
1544 */
1545 if (list_empty(&ccdc->video_out.dmaqueue))
0a7b1a01 1546 return 0;
de1135d4
LP		 1547
1548 /* We're in continuous mode, and memory writes were disabled due to a
1549 * buffer underrun. Reenable them now that we have a buffer. The buffer
1550 * address has been set in ccdc_video_queue.
1551 */
1552 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && ccdc->underrun) {
de1135d4 1553 ccdc->underrun = 0;
0a7b1a01 1554 return 1;
de1135d4
LP		 1555 }
1556
bcb4e0ef
LP		 1557 /* Read the current field identifier. */
1558 field = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE)
1559 & ISPCCDC_SYN_MODE_FLDSTAT
1560 ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
9a36d8ed 1561
bcb4e0ef 1562 /* Wait for the CCDC to become idle. */
de1135d4
LP		 1563 if (ccdc_sbl_wait_idle(ccdc, 1000)) {
1564 dev_info(isp->dev, "CCDC won't become idle!\n");
9554b7db
LP		 1565 isp->crashed |= 1U << ccdc->subdev.entity.id;
1566 omap3isp_pipeline_cancel_stream(pipe);
0a7b1a01 1567 return 0;
de1135d4
LP		 1568 }
1569
bcb4e0ef
LP		 1570 switch (ccdc->formats[CCDC_PAD_SOURCE_OF].field) {
1571 case V4L2_FIELD_ALTERNATE:
1572 /* When capturing fields in alternate order store the current
1573 * field identifier in the pipeline.
1574 */
1575 pipe->field = field;
1576 break;
1577
1578 case V4L2_FIELD_INTERLACED_TB:
1579 /* When interleaving fields only complete the buffer after
1580 * capturing the second field.
1581 */
1582 if (field == V4L2_FIELD_TOP)
1583 return 1;
1584 break;
1585
1586 case V4L2_FIELD_INTERLACED_BT:
1587 if (field == V4L2_FIELD_BOTTOM)
1588 return 1;
1589 break;
1590 }
1591
875e2e3e 1592 buffer = omap3isp_video_buffer_next(&ccdc->video_out);
0a7b1a01 1593 if (buffer != NULL)
21d8582d 1594 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4
LP		 1595
1596 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1597
1598 if (ccdc->state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1599 isp_pipeline_ready(pipe))
1600 omap3isp_pipeline_set_stream(pipe,
1601 ISP_PIPELINE_STREAM_SINGLESHOT);
1602
0a7b1a01 1603 return buffer != NULL;
de1135d4
LP		 1604}
1605
1606/*
1607 * ccdc_vd0_isr - Handle VD0 event
1608 * @ccdc: Pointer to ISP CCDC device.
1609 *
1610 * Executes LSC deferred enablement before next frame starts.
1611 */
1612static void ccdc_vd0_isr(struct isp_ccdc_device *ccdc)
1613{
1614 unsigned long flags;
1615 int restart = 0;
1616
1617 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1618 restart = ccdc_isr_buffer(ccdc);
1619
1620 spin_lock_irqsave(&ccdc->lock, flags);
1621 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD0)) {
1622 spin_unlock_irqrestore(&ccdc->lock, flags);
1623 return;
1624 }
1625
1626 if (!ccdc->shadow_update)
1627 ccdc_apply_controls(ccdc);
1628 spin_unlock_irqrestore(&ccdc->lock, flags);
1629
1630 if (restart)
1631 ccdc_enable(ccdc);
1632}
1633
1634/*
1635 * ccdc_vd1_isr - Handle VD1 event
1636 * @ccdc: Pointer to ISP CCDC device.
1637 */
1638static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)
1639{
1640 unsigned long flags;
1641
9de7af4d
LP		 1642 /* In BT.656 mode the CCDC doesn't generate an HS/VS interrupt. We thus
1643 * need to increment the frame counter here.
1644 */
1645 if (ccdc->bt656) {
1646 struct isp_pipeline *pipe =
1647 to_isp_pipeline(&ccdc->subdev.entity);
1648
1649 atomic_inc(&pipe->frame_number);
1650 }
1651
de1135d4
LP		 1652 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1653
1654 /*
1655 * Depending on the CCDC pipeline state, CCDC stopping should be
1656 * handled differently. In SINGLESHOT we emulate an internal CCDC
1657 * stopping because the CCDC hw works only in continuous mode.
1658 * When CONTINUOUS pipeline state is used and the CCDC writes it's
1659 * data to memory the CCDC and LSC are stopped immediately but
1660 * without change the CCDC stopping state machine. The CCDC
1661 * stopping state machine should be used only when user request
1662 * for stopping is received (SINGLESHOT is an exeption).
1663 */
1664 switch (ccdc->state) {
1665 case ISP_PIPELINE_STREAM_SINGLESHOT:
1666 ccdc->stopping = CCDC_STOP_REQUEST;
1667 break;
1668
1669 case ISP_PIPELINE_STREAM_CONTINUOUS:
1670 if (ccdc->output & CCDC_OUTPUT_MEMORY) {
1671 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1672 __ccdc_lsc_enable(ccdc, 0);
1673 __ccdc_enable(ccdc, 0);
1674 }
1675 break;
1676
1677 case ISP_PIPELINE_STREAM_STOPPED:
1678 break;
1679 }
1680
1681 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))
1682 goto done;
1683
1684 if (ccdc->lsc.request == NULL)
1685 goto done;
1686
1687 /*
1688 * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ
1689 * do the appropriate changes in registers
1690 */
1691 if (ccdc->lsc.state == LSC_STATE_RUNNING) {
1692 __ccdc_lsc_enable(ccdc, 0);
1693 ccdc->lsc.state = LSC_STATE_RECONFIG;
1694 goto done;
1695 }
1696
1697 /* LSC has been in STOPPED state, enable it */
1698 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1699 ccdc_lsc_enable(ccdc);
1700
1701done:
1702 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1703}
1704
1705/*
1706 * omap3isp_ccdc_isr - Configure CCDC during interframe time.
1707 * @ccdc: Pointer to ISP CCDC device.
1708 * @events: CCDC events
1709 */
1710int omap3isp_ccdc_isr(struct isp_ccdc_device *ccdc, u32 events)
1711{
1712 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED)
1713 return 0;
1714
1715 if (events & IRQ0STATUS_CCDC_VD1_IRQ)
1716 ccdc_vd1_isr(ccdc);
1717
1718 ccdc_lsc_isr(ccdc, events);
1719
1720 if (events & IRQ0STATUS_CCDC_VD0_IRQ)
1721 ccdc_vd0_isr(ccdc);
1722
1723 if (events & IRQ0STATUS_HS_VS_IRQ)
1724 ccdc_hs_vs_isr(ccdc);
1725
1726 return 0;
1727}
1728
1729/* -----------------------------------------------------------------------------
1730 * ISP video operations
1731 */
1732
1733static int ccdc_video_queue(struct isp_video *video, struct isp_buffer *buffer)
1734{
1735 struct isp_ccdc_device *ccdc = &video->isp->isp_ccdc;
1736
1737 if (!(ccdc->output & CCDC_OUTPUT_MEMORY))
1738 return -ENODEV;
1739
21d8582d 1740 ccdc_set_outaddr(ccdc, buffer->dma);
de1135d4 1741
2d4e9d1d 1742 /* We now have a buffer queued on the output, restart the pipeline
de1135d4
LP		 1743 * on the next CCDC interrupt if running in continuous mode (or when
1744 * starting the stream).
1745 */
1746 ccdc->underrun = 1;
1747
1748 return 0;
1749}
1750
1751static const struct isp_video_operations ccdc_video_ops = {
1752 .queue = ccdc_video_queue,
1753};
1754
1755/* -----------------------------------------------------------------------------
1756 * V4L2 subdev operations
1757 */
1758
1759/*
1760 * ccdc_ioctl - CCDC module private ioctl's
1761 * @sd: ISP CCDC V4L2 subdevice
1762 * @cmd: ioctl command
1763 * @arg: ioctl argument
1764 *
1765 * Return 0 on success or a negative error code otherwise.
1766 */
1767static long ccdc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1768{
1769 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1770 int ret;
1771
1772 switch (cmd) {
1773 case VIDIOC_OMAP3ISP_CCDC_CFG:
1774 mutex_lock(&ccdc->ioctl_lock);
1775 ret = ccdc_config(ccdc, arg);
1776 mutex_unlock(&ccdc->ioctl_lock);
1777 break;
1778
1779 default:
1780 return -ENOIOCTLCMD;
1781 }
1782
1783 return ret;
1784}
1785
1786static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1787 struct v4l2_event_subscription *sub)
de1135d4 1788{
69d232ae
SA		 1789 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1790 return -EINVAL;
1791
1792 /* line number is zero at frame start */
1793 if (sub->id != 0)
de1135d4
LP		 1794 return -EINVAL;
1795
c53c2549 1796 return v4l2_event_subscribe(fh, sub, OMAP3ISP_CCDC_NEVENTS, NULL);
de1135d4
LP		 1797}
1798
1799static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1800 struct v4l2_event_subscription *sub)
de1135d4
LP		 1801{
1802 return v4l2_event_unsubscribe(fh, sub);
1803}
1804
1805/*
1806 * ccdc_set_stream - Enable/Disable streaming on the CCDC module
1807 * @sd: ISP CCDC V4L2 subdevice
1808 * @enable: Enable/disable stream
1809 *
1810 * When writing to memory, the CCDC hardware can't be enabled without a memory
1811 * buffer to write to. As the s_stream operation is called in response to a
1812 * STREAMON call without any buffer queued yet, just update the enabled field
1813 * and return immediately. The CCDC will be enabled in ccdc_isr_buffer().
1814 *
1815 * When not writing to memory enable the CCDC immediately.
1816 */
1817static int ccdc_set_stream(struct v4l2_subdev *sd, int enable)
1818{
1819 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1820 struct isp_device *isp = to_isp_device(ccdc);
1821 int ret = 0;
1822
1823 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED) {
1824 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1825 return 0;
1826
1827 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_CCDC);
1828 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1829 ISPCCDC_CFG_VDLC);
1830
1831 ccdc_configure(ccdc);
1832
de1135d4
LP		 1833 ccdc_print_status(ccdc);
1834 }
1835
1836 switch (enable) {
1837 case ISP_PIPELINE_STREAM_CONTINUOUS:
1838 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1839 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1840
1841 if (ccdc->underrun || !(ccdc->output & CCDC_OUTPUT_MEMORY))
1842 ccdc_enable(ccdc);
1843
1844 ccdc->underrun = 0;
1845 break;
1846
1847 case ISP_PIPELINE_STREAM_SINGLESHOT:
1848 if (ccdc->output & CCDC_OUTPUT_MEMORY &&
1849 ccdc->state != ISP_PIPELINE_STREAM_SINGLESHOT)
1850 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1851
1852 ccdc_enable(ccdc);
1853 break;
1854
1855 case ISP_PIPELINE_STREAM_STOPPED:
1856 ret = ccdc_disable(ccdc);
1857 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1858 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1859 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_CCDC);
1860 ccdc->underrun = 0;
1861 break;
1862 }
1863
1864 ccdc->state = enable;
1865 return ret;
1866}
1867
1868static struct v4l2_mbus_framefmt *
1869__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1870 unsigned int pad, enum v4l2_subdev_format_whence which)
1871{
1872 if (which == V4L2_SUBDEV_FORMAT_TRY)
1873 return v4l2_subdev_get_try_format(fh, pad);
1874 else
1875 return &ccdc->formats[pad];
1876}
1877
a64909b8
LP		 1878static struct v4l2_rect *
1879__ccdc_get_crop(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1880 enum v4l2_subdev_format_whence which)
1881{
1882 if (which == V4L2_SUBDEV_FORMAT_TRY)
1883 return v4l2_subdev_get_try_crop(fh, CCDC_PAD_SOURCE_OF);
1884 else
1885 return &ccdc->crop;
1886}
1887
de1135d4
LP		 1888/*
1889 * ccdc_try_format - Try video format on a pad
1890 * @ccdc: ISP CCDC device
1891 * @fh : V4L2 subdev file handle
1892 * @pad: Pad number
1893 * @fmt: Format
1894 */
1895static void
1896ccdc_try_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1897 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
1898 enum v4l2_subdev_format_whence which)
1899{
de1135d4 1900 const struct isp_format_info *info;
c51364ca 1901 enum v4l2_mbus_pixelcode pixelcode;
de1135d4
LP		 1902 unsigned int width = fmt->width;
1903 unsigned int height = fmt->height;
a64909b8 1904 struct v4l2_rect *crop;
bcb4e0ef 1905 enum v4l2_field field;
de1135d4
LP		 1906 unsigned int i;
1907
1908 switch (pad) {
1909 case CCDC_PAD_SINK:
de1135d4
LP		 1910 for (i = 0; i < ARRAY_SIZE(ccdc_fmts); i++) {
1911 if (fmt->code == ccdc_fmts[i])
1912 break;
1913 }
1914
1915 /* If not found, use SGRBG10 as default */
1916 if (i >= ARRAY_SIZE(ccdc_fmts))
1917 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1918
1919 /* Clamp the input size. */
1920 fmt->width = clamp_t(u32, width, 32, 4096);
1921 fmt->height = clamp_t(u32, height, 32, 4096);
9a36d8ed
LP		 1922
1923 /* Default to progressive field order. */
1924 if (fmt->field == V4L2_FIELD_ANY)
1925 fmt->field = V4L2_FIELD_NONE;
1926
de1135d4
LP		 1927 break;
1928
1929 case CCDC_PAD_SOURCE_OF:
c51364ca 1930 pixelcode = fmt->code;
bcb4e0ef 1931 field = fmt->field;
c51364ca
LP		 1932 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
1933
9de7af4d
LP		 1934 /* In SYNC mode the bridge converts YUV formats from 2X8 to
1935 * 1X16. In BT.656 no such conversion occurs. As we don't know
1936 * at this point whether the source will use SYNC or BT.656 mode
1937 * let's pretend the conversion always occurs. The CCDC will be
1938 * configured to pack bytes in BT.656, hiding the inaccuracy.
1939 * In all cases bytes can be swapped.
c51364ca
LP		 1940 */
1941 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1942 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1943 /* Use the user requested format if YUV. */
1944 if (pixelcode == V4L2_MBUS_FMT_YUYV8_2X8 ||
1945 pixelcode == V4L2_MBUS_FMT_UYVY8_2X8 ||
1946 pixelcode == V4L2_MBUS_FMT_YUYV8_1X16 ||
1947 pixelcode == V4L2_MBUS_FMT_UYVY8_1X16)
1948 fmt->code = pixelcode;
1949
1950 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8)
1951 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1952 else if (fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1953 fmt->code = V4L2_MBUS_FMT_UYVY8_1X16;
1954 }
de1135d4 1955
a64909b8
LP		 1956 /* Hardcode the output size to the crop rectangle size. */
1957 crop = __ccdc_get_crop(ccdc, fh, which);
1958 fmt->width = crop->width;
1959 fmt->height = crop->height;
bcb4e0ef
LP		 1960
1961 /* When input format is interlaced with alternating fields the
1962 * CCDC can interleave the fields.
1963 */
1964 if (fmt->field == V4L2_FIELD_ALTERNATE &&
1965 (field == V4L2_FIELD_INTERLACED_TB ||
1966 field == V4L2_FIELD_INTERLACED_BT)) {
1967 fmt->field = field;
1968 fmt->height *= 2;
1969 }
1970
de1135d4
LP		 1971 break;
1972
1973 case CCDC_PAD_SOURCE_VP:
c51364ca 1974 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
de1135d4
LP		 1975
1976 /* The video port interface truncates the data to 10 bits. */
1977 info = omap3isp_video_format_info(fmt->code);
1978 fmt->code = info->truncated;
1979
c51364ca
LP		 1980 /* YUV formats are not supported by the video port. */
1981 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1982 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1983 fmt->code = 0;
1984
de1135d4
LP		 1985 /* The number of lines that can be clocked out from the video
1986 * port output must be at least one line less than the number
1987 * of input lines.
1988 */
1989 fmt->width = clamp_t(u32, width, 32, fmt->width);
1990 fmt->height = clamp_t(u32, height, 32, fmt->height - 1);
1991 break;
1992 }
1993
1994 /* Data is written to memory unpacked, each 10-bit or 12-bit pixel is
1995 * stored on 2 bytes.
1996 */
1997 fmt->colorspace = V4L2_COLORSPACE_SRGB;
de1135d4
LP		 1998}
1999
a64909b8
LP		 2000/*
2001 * ccdc_try_crop - Validate a crop rectangle
2002 * @ccdc: ISP CCDC device
2003 * @sink: format on the sink pad
2004 * @crop: crop rectangle to be validated
2005 */
2006static void ccdc_try_crop(struct isp_ccdc_device *ccdc,
2007 const struct v4l2_mbus_framefmt *sink,
2008 struct v4l2_rect *crop)
2009{
2010 const struct isp_format_info *info;
2011 unsigned int max_width;
2012
2013 /* For Bayer formats, restrict left/top and width/height to even values
2014 * to keep the Bayer pattern.
2015 */
2016 info = omap3isp_video_format_info(sink->code);
2017 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2018 crop->left &= ~1;
2019 crop->top &= ~1;
2020 }
2021
2022 crop->left = clamp_t(u32, crop->left, 0, sink->width - CCDC_MIN_WIDTH);
2023 crop->top = clamp_t(u32, crop->top, 0, sink->height - CCDC_MIN_HEIGHT);
2024
2025 /* The data formatter truncates the number of horizontal output pixels
2026 * to a multiple of 16. To avoid clipping data, allow callers to request
2027 * an output size bigger than the input size up to the nearest multiple
2028 * of 16.
2029 */
2030 max_width = (sink->width - crop->left + 15) & ~15;
2031 crop->width = clamp_t(u32, crop->width, CCDC_MIN_WIDTH, max_width)
2032 & ~15;
2033 crop->height = clamp_t(u32, crop->height, CCDC_MIN_HEIGHT,
2034 sink->height - crop->top);
2035
2036 /* Odd width/height values don't make sense for Bayer formats. */
2037 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
2038 crop->width &= ~1;
2039 crop->height &= ~1;
2040 }
2041}
2042
de1135d4
LP		 2043/*
2044 * ccdc_enum_mbus_code - Handle pixel format enumeration
2045 * @sd : pointer to v4l2 subdev structure
2046 * @fh : V4L2 subdev file handle
2047 * @code : pointer to v4l2_subdev_mbus_code_enum structure
2048 * return -EINVAL or zero on success
2049 */
2050static int ccdc_enum_mbus_code(struct v4l2_subdev *sd,
2051 struct v4l2_subdev_fh *fh,
2052 struct v4l2_subdev_mbus_code_enum *code)
2053{
2054 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2055 struct v4l2_mbus_framefmt *format;
2056
2057 switch (code->pad) {
2058 case CCDC_PAD_SINK:
2059 if (code->index >= ARRAY_SIZE(ccdc_fmts))
2060 return -EINVAL;
2061
2062 code->code = ccdc_fmts[code->index];
2063 break;
2064
2065 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 2066 format = __ccdc_get_format(ccdc, fh, code->pad,
2067 V4L2_SUBDEV_FORMAT_TRY);
2068
2069 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
2070 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
2071 /* In YUV mode the CCDC can swap bytes. */
2072 if (code->index == 0)
2073 code->code = V4L2_MBUS_FMT_YUYV8_1X16;
2074 else if (code->index == 1)
2075 code->code = V4L2_MBUS_FMT_UYVY8_1X16;
2076 else
2077 return -EINVAL;
2078 } else {
2079 /* In raw mode, no configurable format confversion is
2080 * available.
2081 */
2082 if (code->index == 0)
2083 code->code = format->code;
2084 else
2085 return -EINVAL;
2086 }
2087 break;
2088
de1135d4 2089 case CCDC_PAD_SOURCE_VP:
c51364ca
LP		 2090 /* The CCDC supports no configurable format conversion
2091 * compatible with the video port. Enumerate a single output
2092 * format code.
2093 */
de1135d4
LP		 2094 if (code->index != 0)
2095 return -EINVAL;
2096
c51364ca 2097 format = __ccdc_get_format(ccdc, fh, code->pad,
de1135d4
LP		 2098 V4L2_SUBDEV_FORMAT_TRY);
2099
c51364ca
LP		 2100 /* A pixel code equal to 0 means that the video port doesn't
2101 * support the input format. Don't enumerate any pixel code.
2102 */
2103 if (format->code == 0)
2104 return -EINVAL;
2105
de1135d4
LP		 2106 code->code = format->code;
2107 break;
2108
2109 default:
2110 return -EINVAL;
2111 }
2112
2113 return 0;
2114}
2115
2116static int ccdc_enum_frame_size(struct v4l2_subdev *sd,
2117 struct v4l2_subdev_fh *fh,
2118 struct v4l2_subdev_frame_size_enum *fse)
2119{
2120 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2121 struct v4l2_mbus_framefmt format;
2122
2123 if (fse->index != 0)
2124 return -EINVAL;
2125
2126 format.code = fse->code;
2127 format.width = 1;
2128 format.height = 1;
2129 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2130 fse->min_width = format.width;
2131 fse->min_height = format.height;
2132
2133 if (format.code != fse->code)
2134 return -EINVAL;
2135
2136 format.code = fse->code;
2137 format.width = -1;
2138 format.height = -1;
2139 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2140 fse->max_width = format.width;
2141 fse->max_height = format.height;
2142
2143 return 0;
2144}
2145
a64909b8
LP		 2146/*
2147 * ccdc_get_selection - Retrieve a selection rectangle on a pad
2148 * @sd: ISP CCDC V4L2 subdevice
2149 * @fh: V4L2 subdev file handle
2150 * @sel: Selection rectangle
2151 *
2152 * The only supported rectangles are the crop rectangles on the output formatter
2153 * source pad.
2154 *
2155 * Return 0 on success or a negative error code otherwise.
2156 */
2157static int ccdc_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2158 struct v4l2_subdev_selection *sel)
2159{
2160 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2161 struct v4l2_mbus_framefmt *format;
2162
2163 if (sel->pad != CCDC_PAD_SOURCE_OF)
2164 return -EINVAL;
2165
2166 switch (sel->target) {
5689b288 2167 case V4L2_SEL_TGT_CROP_BOUNDS:
a64909b8
LP		 2168 sel->r.left = 0;
2169 sel->r.top = 0;
2170 sel->r.width = INT_MAX;
2171 sel->r.height = INT_MAX;
2172
2173 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2174 ccdc_try_crop(ccdc, format, &sel->r);
2175 break;
2176
5689b288 2177 case V4L2_SEL_TGT_CROP:
a64909b8
LP		 2178 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2179 break;
2180
2181 default:
2182 return -EINVAL;
2183 }
2184
2185 return 0;
2186}
2187
2188/*
2189 * ccdc_set_selection - Set a selection rectangle on a pad
2190 * @sd: ISP CCDC V4L2 subdevice
2191 * @fh: V4L2 subdev file handle
2192 * @sel: Selection rectangle
2193 *
2194 * The only supported rectangle is the actual crop rectangle on the output
2195 * formatter source pad.
2196 *
2197 * Return 0 on success or a negative error code otherwise.
2198 */
2199static int ccdc_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2200 struct v4l2_subdev_selection *sel)
2201{
2202 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2203 struct v4l2_mbus_framefmt *format;
2204
5689b288 2205 if (sel->target != V4L2_SEL_TGT_CROP ||
a64909b8
LP		 2206 sel->pad != CCDC_PAD_SOURCE_OF)
2207 return -EINVAL;
2208
2209 /* The crop rectangle can't be changed while streaming. */
2210 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
2211 return -EBUSY;
2212
2213 /* Modifying the crop rectangle always changes the format on the source
2214 * pad. If the KEEP_CONFIG flag is set, just return the current crop
2215 * rectangle.
2216 */
563df3d0 2217 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
a64909b8
LP		 2218 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2219 return 0;
2220 }
2221
2222 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2223 ccdc_try_crop(ccdc, format, &sel->r);
2224 *__ccdc_get_crop(ccdc, fh, sel->which) = sel->r;
2225
2226 /* Update the source format. */
2227 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF, sel->which);
2228 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format, sel->which);
2229
2230 return 0;
2231}
2232
de1135d4
LP		 2233/*
2234 * ccdc_get_format - Retrieve the video format on a pad
2235 * @sd : ISP CCDC V4L2 subdevice
2236 * @fh : V4L2 subdev file handle
2237 * @fmt: Format
2238 *
2239 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2240 * to the format type.
2241 */
2242static int ccdc_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2243 struct v4l2_subdev_format *fmt)
2244{
2245 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2246 struct v4l2_mbus_framefmt *format;
2247
2248 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2249 if (format == NULL)
2250 return -EINVAL;
2251
2252 fmt->format = *format;
2253 return 0;
2254}
2255
2256/*
2257 * ccdc_set_format - Set the video format on a pad
2258 * @sd : ISP CCDC V4L2 subdevice
2259 * @fh : V4L2 subdev file handle
2260 * @fmt: Format
2261 *
2262 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2263 * to the format type.
2264 */
2265static int ccdc_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2266 struct v4l2_subdev_format *fmt)
2267{
2268 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2269 struct v4l2_mbus_framefmt *format;
a64909b8 2270 struct v4l2_rect *crop;
de1135d4
LP		 2271
2272 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2273 if (format == NULL)
2274 return -EINVAL;
2275
2276 ccdc_try_format(ccdc, fh, fmt->pad, &fmt->format, fmt->which);
2277 *format = fmt->format;
2278
2279 /* Propagate the format from sink to source */
2280 if (fmt->pad == CCDC_PAD_SINK) {
a64909b8
LP		 2281 /* Reset the crop rectangle. */
2282 crop = __ccdc_get_crop(ccdc, fh, fmt->which);
2283 crop->left = 0;
2284 crop->top = 0;
2285 crop->width = fmt->format.width;
2286 crop->height = fmt->format.height;
2287
2288 ccdc_try_crop(ccdc, &fmt->format, crop);
2289
2290 /* Update the source formats. */
de1135d4
LP		 2291 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF,
2292 fmt->which);
2293 *format = fmt->format;
2294 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format,
2295 fmt->which);
2296
2297 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_VP,
2298 fmt->which);
2299 *format = fmt->format;
2300 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_VP, format,
2301 fmt->which);
2302 }
2303
2304 return 0;
2305}
2306
a6d7a62d
SA		 2307/*
2308 * Decide whether desired output pixel code can be obtained with
2309 * the lane shifter by shifting the input pixel code.
2310 * @in: input pixelcode to shifter
2311 * @out: output pixelcode from shifter
2312 * @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
2313 *
2314 * return true if the combination is possible
2315 * return false otherwise
2316 */
2317static bool ccdc_is_shiftable(enum v4l2_mbus_pixelcode in,
2318 enum v4l2_mbus_pixelcode out,
2319 unsigned int additional_shift)
2320{
2321 const struct isp_format_info *in_info, *out_info;
2322
2323 if (in == out)
2324 return true;
2325
2326 in_info = omap3isp_video_format_info(in);
2327 out_info = omap3isp_video_format_info(out);
2328
2329 if ((in_info->flavor == 0) || (out_info->flavor == 0))
2330 return false;
2331
2332 if (in_info->flavor != out_info->flavor)
2333 return false;
2334
1697e49a 2335 return in_info->width - out_info->width + additional_shift <= 6;
a6d7a62d
SA		 2336}
2337
2338static int ccdc_link_validate(struct v4l2_subdev *sd,
2339 struct media_link *link,
2340 struct v4l2_subdev_format *source_fmt,
2341 struct v4l2_subdev_format *sink_fmt)
2342{
2343 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2344 unsigned long parallel_shift;
2345
2346 /* Check if the two ends match */
2347 if (source_fmt->format.width != sink_fmt->format.width ||
2348 source_fmt->format.height != sink_fmt->format.height)
2349 return -EPIPE;
2350
2351 /* We've got a parallel sensor here. */
2352 if (ccdc->input == CCDC_INPUT_PARALLEL) {
2353 struct isp_parallel_platform_data *pdata =
2354 &((struct isp_v4l2_subdevs_group *)
2355 media_entity_to_v4l2_subdev(link->source->entity)
2356 ->host_priv)->bus.parallel;
2357 parallel_shift = pdata->data_lane_shift * 2;
2358 } else {
2359 parallel_shift = 0;
2360 }
2361
2362 /* Lane shifter may be used to drop bits on CCDC sink pad */
2363 if (!ccdc_is_shiftable(source_fmt->format.code,
2364 sink_fmt->format.code, parallel_shift))
2365 return -EPIPE;
2366
2367 return 0;
2368}
2369
de1135d4
LP		 2370/*
2371 * ccdc_init_formats - Initialize formats on all pads
2372 * @sd: ISP CCDC V4L2 subdevice
2373 * @fh: V4L2 subdev file handle
2374 *
2375 * Initialize all pad formats with default values. If fh is not NULL, try
2376 * formats are initialized on the file handle. Otherwise active formats are
2377 * initialized on the device.
2378 */
2379static int ccdc_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2380{
2381 struct v4l2_subdev_format format;
2382
2383 memset(&format, 0, sizeof(format));
2384 format.pad = CCDC_PAD_SINK;
2385 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
2386 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
2387 format.format.width = 4096;
2388 format.format.height = 4096;
2389 ccdc_set_format(sd, fh, &format);
2390
2391 return 0;
2392}
2393
2394/* V4L2 subdev core operations */
2395static const struct v4l2_subdev_core_ops ccdc_v4l2_core_ops = {
2396 .ioctl = ccdc_ioctl,
2397 .subscribe_event = ccdc_subscribe_event,
2398 .unsubscribe_event = ccdc_unsubscribe_event,
2399};
2400
2401/* V4L2 subdev video operations */
2402static const struct v4l2_subdev_video_ops ccdc_v4l2_video_ops = {
2403 .s_stream = ccdc_set_stream,
2404};
2405
2406/* V4L2 subdev pad operations */
2407static const struct v4l2_subdev_pad_ops ccdc_v4l2_pad_ops = {
2408 .enum_mbus_code = ccdc_enum_mbus_code,
2409 .enum_frame_size = ccdc_enum_frame_size,
2410 .get_fmt = ccdc_get_format,
2411 .set_fmt = ccdc_set_format,
a64909b8
LP		 2412 .get_selection = ccdc_get_selection,
2413 .set_selection = ccdc_set_selection,
a6d7a62d 2414 .link_validate = ccdc_link_validate,
de1135d4
LP		 2415};
2416
2417/* V4L2 subdev operations */
2418static const struct v4l2_subdev_ops ccdc_v4l2_ops = {
2419 .core = &ccdc_v4l2_core_ops,
2420 .video = &ccdc_v4l2_video_ops,
2421 .pad = &ccdc_v4l2_pad_ops,
2422};
2423
2424/* V4L2 subdev internal operations */
2425static const struct v4l2_subdev_internal_ops ccdc_v4l2_internal_ops = {
2426 .open = ccdc_init_formats,
2427};
2428
2429/* -----------------------------------------------------------------------------
2430 * Media entity operations
2431 */
2432
2433/*
2434 * ccdc_link_setup - Setup CCDC connections
2435 * @entity: CCDC media entity
2436 * @local: Pad at the local end of the link
2437 * @remote: Pad at the remote end of the link
2438 * @flags: Link flags
2439 *
2440 * return -EINVAL or zero on success
2441 */
2442static int ccdc_link_setup(struct media_entity *entity,
2443 const struct media_pad *local,
2444 const struct media_pad *remote, u32 flags)
2445{
2446 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2447 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2448 struct isp_device *isp = to_isp_device(ccdc);
2449
2450 switch (local->index | media_entity_type(remote->entity)) {
2451 case CCDC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2452 /* Read from the sensor (parallel interface), CCP2, CSI2a or
2453 * CSI2c.
2454 */
2455 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
2456 ccdc->input = CCDC_INPUT_NONE;
2457 break;
2458 }
2459
2460 if (ccdc->input != CCDC_INPUT_NONE)
2461 return -EBUSY;
2462
2463 if (remote->entity == &isp->isp_ccp2.subdev.entity)
2464 ccdc->input = CCDC_INPUT_CCP2B;
2465 else if (remote->entity == &isp->isp_csi2a.subdev.entity)
2466 ccdc->input = CCDC_INPUT_CSI2A;
2467 else if (remote->entity == &isp->isp_csi2c.subdev.entity)
2468 ccdc->input = CCDC_INPUT_CSI2C;
2469 else
2470 ccdc->input = CCDC_INPUT_PARALLEL;
2471
2472 break;
2473
2474 /*
2475 * The ISP core doesn't support pipelines with multiple video outputs.
2476 * Revisit this when it will be implemented, and return -EBUSY for now.
2477 */
2478
2479 case CCDC_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
2480 /* Write to preview engine, histogram and H3A. When none of
2481 * those links are active, the video port can be disabled.
2482 */
2483 if (flags & MEDIA_LNK_FL_ENABLED) {
2484 if (ccdc->output & ~CCDC_OUTPUT_PREVIEW)
2485 return -EBUSY;
2486 ccdc->output |= CCDC_OUTPUT_PREVIEW;
2487 } else {
2488 ccdc->output &= ~CCDC_OUTPUT_PREVIEW;
2489 }
2490 break;
2491
2492 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_DEVNODE:
2493 /* Write to memory */
2494 if (flags & MEDIA_LNK_FL_ENABLED) {
2495 if (ccdc->output & ~CCDC_OUTPUT_MEMORY)
2496 return -EBUSY;
2497 ccdc->output |= CCDC_OUTPUT_MEMORY;
2498 } else {
2499 ccdc->output &= ~CCDC_OUTPUT_MEMORY;
2500 }
2501 break;
2502
2503 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_V4L2_SUBDEV:
2504 /* Write to resizer */
2505 if (flags & MEDIA_LNK_FL_ENABLED) {
2506 if (ccdc->output & ~CCDC_OUTPUT_RESIZER)
2507 return -EBUSY;
2508 ccdc->output |= CCDC_OUTPUT_RESIZER;
2509 } else {
2510 ccdc->output &= ~CCDC_OUTPUT_RESIZER;
2511 }
2512 break;
2513
2514 default:
2515 return -EINVAL;
2516 }
2517
2518 return 0;
2519}
2520
2521/* media operations */
2522static const struct media_entity_operations ccdc_media_ops = {
2523 .link_setup = ccdc_link_setup,
a6d7a62d 2524 .link_validate = v4l2_subdev_link_validate,
de1135d4
LP		 2525};
2526
39099d09
LP		 2527void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc)
2528{
2529 v4l2_device_unregister_subdev(&ccdc->subdev);
2530 omap3isp_video_unregister(&ccdc->video_out);
2531}
2532
2533int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
2534 struct v4l2_device *vdev)
2535{
2536 int ret;
2537
2538 /* Register the subdev and video node. */
2539 ret = v4l2_device_register_subdev(vdev, &ccdc->subdev);
2540 if (ret < 0)
2541 goto error;
2542
2543 ret = omap3isp_video_register(&ccdc->video_out, vdev);
2544 if (ret < 0)
2545 goto error;
2546
2547 return 0;
2548
2549error:
2550 omap3isp_ccdc_unregister_entities(ccdc);
2551 return ret;
2552}
2553
2554/* -----------------------------------------------------------------------------
2555 * ISP CCDC initialisation and cleanup
2556 */
2557
de1135d4
LP		 2558/*
2559 * ccdc_init_entities - Initialize V4L2 subdev and media entity
2560 * @ccdc: ISP CCDC module
2561 *
2562 * Return 0 on success and a negative error code on failure.
2563 */
2564static int ccdc_init_entities(struct isp_ccdc_device *ccdc)
2565{
2566 struct v4l2_subdev *sd = &ccdc->subdev;
2567 struct media_pad *pads = ccdc->pads;
2568 struct media_entity *me = &sd->entity;
2569 int ret;
2570
2571 ccdc->input = CCDC_INPUT_NONE;
2572
2573 v4l2_subdev_init(sd, &ccdc_v4l2_ops);
2574 sd->internal_ops = &ccdc_v4l2_internal_ops;
2575 strlcpy(sd->name, "OMAP3 ISP CCDC", sizeof(sd->name));
2576 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2577 v4l2_set_subdevdata(sd, ccdc);
2578 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
de1135d4 2579
8dad936a
SA		 2580 pads[CCDC_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2581 | MEDIA_PAD_FL_MUST_CONNECT;
de1135d4
LP		 2582 pads[CCDC_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
2583 pads[CCDC_PAD_SOURCE_OF].flags = MEDIA_PAD_FL_SOURCE;
2584
2585 me->ops = &ccdc_media_ops;
2586 ret = media_entity_init(me, CCDC_PADS_NUM, pads, 0);
2587 if (ret < 0)
2588 return ret;
2589
2590 ccdc_init_formats(sd, NULL);
2591
2592 ccdc->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2593 ccdc->video_out.ops = &ccdc_video_ops;
2594 ccdc->video_out.isp = to_isp_device(ccdc);
2595 ccdc->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
2596 ccdc->video_out.bpl_alignment = 32;
2597
2598 ret = omap3isp_video_init(&ccdc->video_out, "CCDC");
2599 if (ret < 0)
9b6390bd 2600 goto error_video;
de1135d4
LP		 2601
2602 /* Connect the CCDC subdev to the video node. */
2603 ret = media_entity_create_link(&ccdc->subdev.entity, CCDC_PAD_SOURCE_OF,
2604 &ccdc->video_out.video.entity, 0, 0);
2605 if (ret < 0)
9b6390bd 2606 goto error_link;
de1135d4
LP		 2607
2608 return 0;
9b6390bd
LP		 2609
2610error_link:
2611 omap3isp_video_cleanup(&ccdc->video_out);
2612error_video:
2613 media_entity_cleanup(me);
2614 return ret;
de1135d4
LP		 2615}
2616
de1135d4
LP		 2617/*
2618 * omap3isp_ccdc_init - CCDC module initialization.
872aba51 2619 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2620 *
2621 * TODO: Get the initialisation values from platform data.
2622 *
2623 * Return 0 on success or a negative error code otherwise.
2624 */
2625int omap3isp_ccdc_init(struct isp_device *isp)
2626{
2627 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
9b6390bd 2628 int ret;
de1135d4
LP		 2629
2630 spin_lock_init(&ccdc->lock);
2631 init_waitqueue_head(&ccdc->wait);
2632 mutex_init(&ccdc->ioctl_lock);
2633
2634 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
2635
2636 INIT_WORK(&ccdc->lsc.table_work, ccdc_lsc_free_table_work);
2637 ccdc->lsc.state = LSC_STATE_STOPPED;
2638 INIT_LIST_HEAD(&ccdc->lsc.free_queue);
2639 spin_lock_init(&ccdc->lsc.req_lock);
2640
de1135d4
LP		 2641 ccdc->clamp.oblen = 0;
2642 ccdc->clamp.dcsubval = 0;
2643
de1135d4
LP		 2644 ccdc->update = OMAP3ISP_CCDC_BLCLAMP;
2645 ccdc_apply_controls(ccdc);
2646
9b6390bd
LP		 2647 ret = ccdc_init_entities(ccdc);
2648 if (ret < 0) {
2649 mutex_destroy(&ccdc->ioctl_lock);
2650 return ret;
2651 }
2652
2653 return 0;
de1135d4
LP		 2654}
2655
2656/*
2657 * omap3isp_ccdc_cleanup - CCDC module cleanup.
872aba51 2658 * @isp: Device pointer specific to the OMAP3 ISP.
de1135d4
LP		 2659 */
2660void omap3isp_ccdc_cleanup(struct isp_device *isp)
2661{
2662 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
2663
63b4ca23
LP		 2664 omap3isp_video_cleanup(&ccdc->video_out);
2665 media_entity_cleanup(&ccdc->subdev.entity);
2666
de1135d4
LP		 2667 /* Free LSC requests. As the CCDC is stopped there's no active request,
2668 * so only the pending request and the free queue need to be handled.
2669 */
2670 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
2671 cancel_work_sync(&ccdc->lsc.table_work);
2672 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
2673
c60e153d
LP		 2674 if (ccdc->fpc.addr != NULL)
2675 dma_free_coherent(isp->dev, ccdc->fpc.fpnum * 4, ccdc->fpc.addr,
2676 ccdc->fpc.dma);
ed33ac8e
LP		 2677
2678 mutex_destroy(&ccdc->ioctl_lock);
de1135d4 2679}
Linux kernel - Deliverables
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