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[media] uvcvideo: Add bayer 8-bit patterns to uvcvideo
[deliverable/linux.git] / drivers / media / platform / omap3isp / ispccdc.c
CommitLineData
de1135d4
LP		 1/*
2 * ispccdc.c
3 *
4 * TI OMAP3 ISP - CCDC module
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27#include <linux/module.h>
28#include <linux/uaccess.h>
29#include <linux/delay.h>
30#include <linux/device.h>
31#include <linux/dma-mapping.h>
32#include <linux/mm.h>
c8d35c84 33#include <linux/omap-iommu.h>
de1135d4 34#include <linux/sched.h>
e74d83aa 35#include <linux/slab.h>
de1135d4
LP		 36#include <media/v4l2-event.h>
37
38#include "isp.h"
39#include "ispreg.h"
40#include "ispccdc.h"
41
a64909b8
LP		 42#define CCDC_MIN_WIDTH 32
43#define CCDC_MIN_HEIGHT 32
44
de1135d4
LP		 45static struct v4l2_mbus_framefmt *
46__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
47 unsigned int pad, enum v4l2_subdev_format_whence which);
48
49static const unsigned int ccdc_fmts[] = {
50 V4L2_MBUS_FMT_Y8_1X8,
5782f97b
MJ		 51 V4L2_MBUS_FMT_Y10_1X10,
52 V4L2_MBUS_FMT_Y12_1X12,
53 V4L2_MBUS_FMT_SGRBG8_1X8,
54 V4L2_MBUS_FMT_SRGGB8_1X8,
55 V4L2_MBUS_FMT_SBGGR8_1X8,
56 V4L2_MBUS_FMT_SGBRG8_1X8,
de1135d4
LP		 57 V4L2_MBUS_FMT_SGRBG10_1X10,
58 V4L2_MBUS_FMT_SRGGB10_1X10,
59 V4L2_MBUS_FMT_SBGGR10_1X10,
60 V4L2_MBUS_FMT_SGBRG10_1X10,
61 V4L2_MBUS_FMT_SGRBG12_1X12,
62 V4L2_MBUS_FMT_SRGGB12_1X12,
63 V4L2_MBUS_FMT_SBGGR12_1X12,
64 V4L2_MBUS_FMT_SGBRG12_1X12,
c51364ca
LP		 65 V4L2_MBUS_FMT_YUYV8_2X8,
66 V4L2_MBUS_FMT_UYVY8_2X8,
de1135d4
LP		 67};
68
69/*
70 * ccdc_print_status - Print current CCDC Module register values.
71 * @ccdc: Pointer to ISP CCDC device.
72 *
73 * Also prints other debug information stored in the CCDC module.
74 */
75#define CCDC_PRINT_REGISTER(isp, name)\
76 dev_dbg(isp->dev, "###CCDC " #name "=0x%08x\n", \
77 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_##name))
78
79static void ccdc_print_status(struct isp_ccdc_device *ccdc)
80{
81 struct isp_device *isp = to_isp_device(ccdc);
82
83 dev_dbg(isp->dev, "-------------CCDC Register dump-------------\n");
84
85 CCDC_PRINT_REGISTER(isp, PCR);
86 CCDC_PRINT_REGISTER(isp, SYN_MODE);
87 CCDC_PRINT_REGISTER(isp, HD_VD_WID);
88 CCDC_PRINT_REGISTER(isp, PIX_LINES);
89 CCDC_PRINT_REGISTER(isp, HORZ_INFO);
90 CCDC_PRINT_REGISTER(isp, VERT_START);
91 CCDC_PRINT_REGISTER(isp, VERT_LINES);
92 CCDC_PRINT_REGISTER(isp, CULLING);
93 CCDC_PRINT_REGISTER(isp, HSIZE_OFF);
94 CCDC_PRINT_REGISTER(isp, SDOFST);
95 CCDC_PRINT_REGISTER(isp, SDR_ADDR);
96 CCDC_PRINT_REGISTER(isp, CLAMP);
97 CCDC_PRINT_REGISTER(isp, DCSUB);
98 CCDC_PRINT_REGISTER(isp, COLPTN);
99 CCDC_PRINT_REGISTER(isp, BLKCMP);
100 CCDC_PRINT_REGISTER(isp, FPC);
101 CCDC_PRINT_REGISTER(isp, FPC_ADDR);
102 CCDC_PRINT_REGISTER(isp, VDINT);
103 CCDC_PRINT_REGISTER(isp, ALAW);
104 CCDC_PRINT_REGISTER(isp, REC656IF);
105 CCDC_PRINT_REGISTER(isp, CFG);
106 CCDC_PRINT_REGISTER(isp, FMTCFG);
107 CCDC_PRINT_REGISTER(isp, FMT_HORZ);
108 CCDC_PRINT_REGISTER(isp, FMT_VERT);
109 CCDC_PRINT_REGISTER(isp, PRGEVEN0);
110 CCDC_PRINT_REGISTER(isp, PRGEVEN1);
111 CCDC_PRINT_REGISTER(isp, PRGODD0);
112 CCDC_PRINT_REGISTER(isp, PRGODD1);
113 CCDC_PRINT_REGISTER(isp, VP_OUT);
114 CCDC_PRINT_REGISTER(isp, LSC_CONFIG);
115 CCDC_PRINT_REGISTER(isp, LSC_INITIAL);
116 CCDC_PRINT_REGISTER(isp, LSC_TABLE_BASE);
117 CCDC_PRINT_REGISTER(isp, LSC_TABLE_OFFSET);
118
119 dev_dbg(isp->dev, "--------------------------------------------\n");
120}
121
122/*
123 * omap3isp_ccdc_busy - Get busy state of the CCDC.
124 * @ccdc: Pointer to ISP CCDC device.
125 */
126int omap3isp_ccdc_busy(struct isp_ccdc_device *ccdc)
127{
128 struct isp_device *isp = to_isp_device(ccdc);
129
130 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
131 ISPCCDC_PCR_BUSY;
132}
133
134/* -----------------------------------------------------------------------------
135 * Lens Shading Compensation
136 */
137
138/*
139 * ccdc_lsc_validate_config - Check that LSC configuration is valid.
140 * @ccdc: Pointer to ISP CCDC device.
141 * @lsc_cfg: the LSC configuration to check.
142 *
143 * Returns 0 if the LSC configuration is valid, or -EINVAL if invalid.
144 */
145static int ccdc_lsc_validate_config(struct isp_ccdc_device *ccdc,
146 struct omap3isp_ccdc_lsc_config *lsc_cfg)
147{
148 struct isp_device *isp = to_isp_device(ccdc);
149 struct v4l2_mbus_framefmt *format;
150 unsigned int paxel_width, paxel_height;
151 unsigned int paxel_shift_x, paxel_shift_y;
152 unsigned int min_width, min_height, min_size;
153 unsigned int input_width, input_height;
154
155 paxel_shift_x = lsc_cfg->gain_mode_m;
156 paxel_shift_y = lsc_cfg->gain_mode_n;
157
158 if ((paxel_shift_x < 2) || (paxel_shift_x > 6) ||
159 (paxel_shift_y < 2) || (paxel_shift_y > 6)) {
160 dev_dbg(isp->dev, "CCDC: LSC: Invalid paxel size\n");
161 return -EINVAL;
162 }
163
164 if (lsc_cfg->offset & 3) {
165 dev_dbg(isp->dev, "CCDC: LSC: Offset must be a multiple of "
166 "4\n");
167 return -EINVAL;
168 }
169
170 if ((lsc_cfg->initial_x & 1) || (lsc_cfg->initial_y & 1)) {
171 dev_dbg(isp->dev, "CCDC: LSC: initial_x and y must be even\n");
172 return -EINVAL;
173 }
174
175 format = __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
176 V4L2_SUBDEV_FORMAT_ACTIVE);
177 input_width = format->width;
178 input_height = format->height;
179
180 /* Calculate minimum bytesize for validation */
181 paxel_width = 1 << paxel_shift_x;
182 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1)
183 >> paxel_shift_x) + 1;
184
185 paxel_height = 1 << paxel_shift_y;
186 min_height = ((input_height + lsc_cfg->initial_y + paxel_height - 1)
187 >> paxel_shift_y) + 1;
188
189 min_size = 4 * min_width * min_height;
190 if (min_size > lsc_cfg->size) {
191 dev_dbg(isp->dev, "CCDC: LSC: too small table\n");
192 return -EINVAL;
193 }
194 if (lsc_cfg->offset < (min_width * 4)) {
195 dev_dbg(isp->dev, "CCDC: LSC: Offset is too small\n");
196 return -EINVAL;
197 }
198 if ((lsc_cfg->size / lsc_cfg->offset) < min_height) {
199 dev_dbg(isp->dev, "CCDC: LSC: Wrong size/offset combination\n");
200 return -EINVAL;
201 }
202 return 0;
203}
204
205/*
206 * ccdc_lsc_program_table - Program Lens Shading Compensation table address.
207 * @ccdc: Pointer to ISP CCDC device.
208 */
209static void ccdc_lsc_program_table(struct isp_ccdc_device *ccdc, u32 addr)
210{
211 isp_reg_writel(to_isp_device(ccdc), addr,
212 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
213}
214
215/*
216 * ccdc_lsc_setup_regs - Configures the lens shading compensation module
217 * @ccdc: Pointer to ISP CCDC device.
218 */
219static void ccdc_lsc_setup_regs(struct isp_ccdc_device *ccdc,
220 struct omap3isp_ccdc_lsc_config *cfg)
221{
222 struct isp_device *isp = to_isp_device(ccdc);
223 int reg;
224
225 isp_reg_writel(isp, cfg->offset, OMAP3_ISP_IOMEM_CCDC,
226 ISPCCDC_LSC_TABLE_OFFSET);
227
228 reg = 0;
229 reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
230 reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
231 reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
232 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
233
234 reg = 0;
235 reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
236 reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
237 reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
238 reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
239 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC,
240 ISPCCDC_LSC_INITIAL);
241}
242
243static int ccdc_lsc_wait_prefetch(struct isp_ccdc_device *ccdc)
244{
245 struct isp_device *isp = to_isp_device(ccdc);
246 unsigned int wait;
247
248 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
249 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
250
251 /* timeout 1 ms */
252 for (wait = 0; wait < 1000; wait++) {
253 if (isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS) &
254 IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ) {
255 isp_reg_writel(isp, IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ,
256 OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
257 return 0;
258 }
259
260 rmb();
261 udelay(1);
262 }
263
264 return -ETIMEDOUT;
265}
266
267/*
268 * __ccdc_lsc_enable - Enables/Disables the Lens Shading Compensation module.
269 * @ccdc: Pointer to ISP CCDC device.
270 * @enable: 0 Disables LSC, 1 Enables LSC.
271 */
272static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable)
273{
274 struct isp_device *isp = to_isp_device(ccdc);
275 const struct v4l2_mbus_framefmt *format =
276 __ccdc_get_format(ccdc, NULL, CCDC_PAD_SINK,
277 V4L2_SUBDEV_FORMAT_ACTIVE);
278
279 if ((format->code != V4L2_MBUS_FMT_SGRBG10_1X10) &&
280 (format->code != V4L2_MBUS_FMT_SRGGB10_1X10) &&
281 (format->code != V4L2_MBUS_FMT_SBGGR10_1X10) &&
282 (format->code != V4L2_MBUS_FMT_SGBRG10_1X10))
283 return -EINVAL;
284
285 if (enable)
286 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_LSC_READ);
287
288 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
289 ISPCCDC_LSC_ENABLE, enable ? ISPCCDC_LSC_ENABLE : 0);
290
291 if (enable) {
292 if (ccdc_lsc_wait_prefetch(ccdc) < 0) {
293 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC,
294 ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE);
295 ccdc->lsc.state = LSC_STATE_STOPPED;
296 dev_warn(to_device(ccdc), "LSC prefecth timeout\n");
297 return -ETIMEDOUT;
298 }
299 ccdc->lsc.state = LSC_STATE_RUNNING;
300 } else {
301 ccdc->lsc.state = LSC_STATE_STOPPING;
302 }
303
304 return 0;
305}
306
307static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
308{
309 struct isp_device *isp = to_isp_device(ccdc);
310
311 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG) &
312 ISPCCDC_LSC_BUSY;
313}
314
315/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
316 * @ccdc: Pointer to ISP CCDC device
317 * @req: New configuration request
318 *
319 * context: in_interrupt()
320 */
321static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
322 struct ispccdc_lsc_config_req *req)
323{
324 if (!req->enable)
325 return -EINVAL;
326
327 if (ccdc_lsc_validate_config(ccdc, &req->config) < 0) {
328 dev_dbg(to_device(ccdc), "Discard LSC configuration\n");
329 return -EINVAL;
330 }
331
332 if (ccdc_lsc_busy(ccdc))
333 return -EBUSY;
334
335 ccdc_lsc_setup_regs(ccdc, &req->config);
336 ccdc_lsc_program_table(ccdc, req->table);
337 return 0;
338}
339
340/*
341 * ccdc_lsc_error_handler - Handle LSC prefetch error scenario.
342 * @ccdc: Pointer to ISP CCDC device.
343 *
344 * Disables LSC, and defers enablement to shadow registers update time.
345 */
346static void ccdc_lsc_error_handler(struct isp_ccdc_device *ccdc)
347{
348 struct isp_device *isp = to_isp_device(ccdc);
349 /*
350 * From OMAP3 TRM: When this event is pending, the module
351 * goes into transparent mode (output =input). Normal
352 * operation can be resumed at the start of the next frame
353 * after:
354 * 1) Clearing this event
355 * 2) Disabling the LSC module
356 * 3) Enabling it
357 */
358 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG,
359 ISPCCDC_LSC_ENABLE);
360 ccdc->lsc.state = LSC_STATE_STOPPED;
361}
362
363static void ccdc_lsc_free_request(struct isp_ccdc_device *ccdc,
364 struct ispccdc_lsc_config_req *req)
365{
366 struct isp_device *isp = to_isp_device(ccdc);
367
368 if (req == NULL)
369 return;
370
371 if (req->iovm)
372 dma_unmap_sg(isp->dev, req->iovm->sgt->sgl,
373 req->iovm->sgt->nents, DMA_TO_DEVICE);
374 if (req->table)
fabdbca8 375 omap_iommu_vfree(isp->domain, isp->dev, req->table);
de1135d4
LP		 376 kfree(req);
377}
378
379static void ccdc_lsc_free_queue(struct isp_ccdc_device *ccdc,
380 struct list_head *queue)
381{
382 struct ispccdc_lsc_config_req *req, *n;
383 unsigned long flags;
384
385 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
386 list_for_each_entry_safe(req, n, queue, list) {
387 list_del(&req->list);
388 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
389 ccdc_lsc_free_request(ccdc, req);
390 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
391 }
392 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
393}
394
395static void ccdc_lsc_free_table_work(struct work_struct *work)
396{
397 struct isp_ccdc_device *ccdc;
398 struct ispccdc_lsc *lsc;
399
400 lsc = container_of(work, struct ispccdc_lsc, table_work);
401 ccdc = container_of(lsc, struct isp_ccdc_device, lsc);
402
403 ccdc_lsc_free_queue(ccdc, &lsc->free_queue);
404}
405
406/*
407 * ccdc_lsc_config - Configure the LSC module from a userspace request
408 *
409 * Store the request LSC configuration in the LSC engine request pointer. The
410 * configuration will be applied to the hardware when the CCDC will be enabled,
411 * or at the next LSC interrupt if the CCDC is already running.
412 */
413static int ccdc_lsc_config(struct isp_ccdc_device *ccdc,
414 struct omap3isp_ccdc_update_config *config)
415{
416 struct isp_device *isp = to_isp_device(ccdc);
417 struct ispccdc_lsc_config_req *req;
418 unsigned long flags;
419 void *table;
420 u16 update;
421 int ret;
422
423 update = config->update &
424 (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC);
425 if (!update)
426 return 0;
427
428 if (update != (OMAP3ISP_CCDC_CONFIG_LSC | OMAP3ISP_CCDC_TBL_LSC)) {
429 dev_dbg(to_device(ccdc), "%s: Both LSC configuration and table "
430 "need to be supplied\n", __func__);
431 return -EINVAL;
432 }
433
434 req = kzalloc(sizeof(*req), GFP_KERNEL);
435 if (req == NULL)
436 return -ENOMEM;
437
438 if (config->flag & OMAP3ISP_CCDC_CONFIG_LSC) {
439 if (copy_from_user(&req->config, config->lsc_cfg,
440 sizeof(req->config))) {
441 ret = -EFAULT;
442 goto done;
443 }
444
445 req->enable = 1;
446
fabdbca8 447 req->table = omap_iommu_vmalloc(isp->domain, isp->dev, 0,
f626b52d 448 req->config.size, IOMMU_FLAG);
de1135d4
LP		 449 if (IS_ERR_VALUE(req->table)) {
450 req->table = 0;
451 ret = -ENOMEM;
452 goto done;
453 }
454
fabdbca8 455 req->iovm = omap_find_iovm_area(isp->dev, req->table);
de1135d4
LP		 456 if (req->iovm == NULL) {
457 ret = -ENOMEM;
458 goto done;
459 }
460
461 if (!dma_map_sg(isp->dev, req->iovm->sgt->sgl,
462 req->iovm->sgt->nents, DMA_TO_DEVICE)) {
463 ret = -ENOMEM;
464 req->iovm = NULL;
465 goto done;
466 }
467
468 dma_sync_sg_for_cpu(isp->dev, req->iovm->sgt->sgl,
469 req->iovm->sgt->nents, DMA_TO_DEVICE);
470
fabdbca8 471 table = omap_da_to_va(isp->dev, req->table);
de1135d4
LP		 472 if (copy_from_user(table, config->lsc, req->config.size)) {
473 ret = -EFAULT;
474 goto done;
475 }
476
477 dma_sync_sg_for_device(isp->dev, req->iovm->sgt->sgl,
478 req->iovm->sgt->nents, DMA_TO_DEVICE);
479 }
480
481 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
482 if (ccdc->lsc.request) {
483 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
484 schedule_work(&ccdc->lsc.table_work);
485 }
486 ccdc->lsc.request = req;
487 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
488
489 ret = 0;
490
491done:
492 if (ret < 0)
493 ccdc_lsc_free_request(ccdc, req);
494
495 return ret;
496}
497
498static inline int ccdc_lsc_is_configured(struct isp_ccdc_device *ccdc)
499{
500 unsigned long flags;
501
502 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
503 if (ccdc->lsc.active) {
504 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
505 return 1;
506 }
507 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
508 return 0;
509}
510
511static int ccdc_lsc_enable(struct isp_ccdc_device *ccdc)
512{
513 struct ispccdc_lsc *lsc = &ccdc->lsc;
514
515 if (lsc->state != LSC_STATE_STOPPED)
516 return -EINVAL;
517
518 if (lsc->active) {
519 list_add_tail(&lsc->active->list, &lsc->free_queue);
520 lsc->active = NULL;
521 }
522
523 if (__ccdc_lsc_configure(ccdc, lsc->request) < 0) {
524 omap3isp_sbl_disable(to_isp_device(ccdc),
525 OMAP3_ISP_SBL_CCDC_LSC_READ);
526 list_add_tail(&lsc->request->list, &lsc->free_queue);
527 lsc->request = NULL;
528 goto done;
529 }
530
531 lsc->active = lsc->request;
532 lsc->request = NULL;
533 __ccdc_lsc_enable(ccdc, 1);
534
535done:
536 if (!list_empty(&lsc->free_queue))
537 schedule_work(&lsc->table_work);
538
539 return 0;
540}
541
542/* -----------------------------------------------------------------------------
543 * Parameters configuration
544 */
545
546/*
547 * ccdc_configure_clamp - Configure optical-black or digital clamping
548 * @ccdc: Pointer to ISP CCDC device.
549 *
550 * The CCDC performs either optical-black or digital clamp. Configure and enable
551 * the selected clamp method.
552 */
553static void ccdc_configure_clamp(struct isp_ccdc_device *ccdc)
554{
555 struct isp_device *isp = to_isp_device(ccdc);
556 u32 clamp;
557
558 if (ccdc->obclamp) {
559 clamp = ccdc->clamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
560 clamp |= ccdc->clamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
561 clamp |= ccdc->clamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
562 clamp |= ccdc->clamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
563 isp_reg_writel(isp, clamp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP);
564 } else {
565 isp_reg_writel(isp, ccdc->clamp.dcsubval,
566 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB);
567 }
568
569 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
570 ISPCCDC_CLAMP_CLAMPEN,
571 ccdc->obclamp ? ISPCCDC_CLAMP_CLAMPEN : 0);
572}
573
574/*
575 * ccdc_configure_fpc - Configure Faulty Pixel Correction
576 * @ccdc: Pointer to ISP CCDC device.
577 */
578static void ccdc_configure_fpc(struct isp_ccdc_device *ccdc)
579{
580 struct isp_device *isp = to_isp_device(ccdc);
581
582 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, ISPCCDC_FPC_FPCEN);
583
584 if (!ccdc->fpc_en)
585 return;
586
587 isp_reg_writel(isp, ccdc->fpc.fpcaddr, OMAP3_ISP_IOMEM_CCDC,
588 ISPCCDC_FPC_ADDR);
589 /* The FPNUM field must be set before enabling FPC. */
590 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
591 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
592 isp_reg_writel(isp, (ccdc->fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT) |
593 ISPCCDC_FPC_FPCEN, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
594}
595
596/*
597 * ccdc_configure_black_comp - Configure Black Level Compensation.
598 * @ccdc: Pointer to ISP CCDC device.
599 */
600static void ccdc_configure_black_comp(struct isp_ccdc_device *ccdc)
601{
602 struct isp_device *isp = to_isp_device(ccdc);
603 u32 blcomp;
604
605 blcomp = ccdc->blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
606 blcomp |= ccdc->blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
607 blcomp |= ccdc->blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
608 blcomp |= ccdc->blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
609
610 isp_reg_writel(isp, blcomp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
611}
612
613/*
614 * ccdc_configure_lpf - Configure Low-Pass Filter (LPF).
615 * @ccdc: Pointer to ISP CCDC device.
616 */
617static void ccdc_configure_lpf(struct isp_ccdc_device *ccdc)
618{
619 struct isp_device *isp = to_isp_device(ccdc);
620
621 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
622 ISPCCDC_SYN_MODE_LPF,
623 ccdc->lpf ? ISPCCDC_SYN_MODE_LPF : 0);
624}
625
626/*
627 * ccdc_configure_alaw - Configure A-law compression.
628 * @ccdc: Pointer to ISP CCDC device.
629 */
630static void ccdc_configure_alaw(struct isp_ccdc_device *ccdc)
631{
632 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 633 const struct isp_format_info *info;
de1135d4
LP		 634 u32 alaw = 0;
635
73ea57eb
LP		 636 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
637
638 switch (info->width) {
de1135d4
LP		 639 case 8:
640 return;
641
642 case 10:
643 alaw = ISPCCDC_ALAW_GWDI_9_0;
644 break;
645 case 11:
646 alaw = ISPCCDC_ALAW_GWDI_10_1;
647 break;
648 case 12:
649 alaw = ISPCCDC_ALAW_GWDI_11_2;
650 break;
651 case 13:
652 alaw = ISPCCDC_ALAW_GWDI_12_3;
653 break;
654 }
655
656 if (ccdc->alaw)
657 alaw |= ISPCCDC_ALAW_CCDTBL;
658
659 isp_reg_writel(isp, alaw, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
660}
661
662/*
663 * ccdc_config_imgattr - Configure sensor image specific attributes.
664 * @ccdc: Pointer to ISP CCDC device.
665 * @colptn: Color pattern of the sensor.
666 */
667static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn)
668{
669 struct isp_device *isp = to_isp_device(ccdc);
670
671 isp_reg_writel(isp, colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
672}
673
674/*
675 * ccdc_config - Set CCDC configuration from userspace
676 * @ccdc: Pointer to ISP CCDC device.
677 * @userspace_add: Structure containing CCDC configuration sent from userspace.
678 *
679 * Returns 0 if successful, -EINVAL if the pointer to the configuration
680 * structure is null, or the copy_from_user function fails to copy user space
681 * memory to kernel space memory.
682 */
683static int ccdc_config(struct isp_ccdc_device *ccdc,
684 struct omap3isp_ccdc_update_config *ccdc_struct)
685{
686 struct isp_device *isp = to_isp_device(ccdc);
687 unsigned long flags;
688
689 spin_lock_irqsave(&ccdc->lock, flags);
690 ccdc->shadow_update = 1;
691 spin_unlock_irqrestore(&ccdc->lock, flags);
692
693 if (OMAP3ISP_CCDC_ALAW & ccdc_struct->update) {
694 ccdc->alaw = !!(OMAP3ISP_CCDC_ALAW & ccdc_struct->flag);
695 ccdc->update |= OMAP3ISP_CCDC_ALAW;
696 }
697
698 if (OMAP3ISP_CCDC_LPF & ccdc_struct->update) {
699 ccdc->lpf = !!(OMAP3ISP_CCDC_LPF & ccdc_struct->flag);
700 ccdc->update |= OMAP3ISP_CCDC_LPF;
701 }
702
703 if (OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->update) {
704 if (copy_from_user(&ccdc->clamp, ccdc_struct->bclamp,
705 sizeof(ccdc->clamp))) {
706 ccdc->shadow_update = 0;
707 return -EFAULT;
708 }
709
710 ccdc->obclamp = !!(OMAP3ISP_CCDC_BLCLAMP & ccdc_struct->flag);
711 ccdc->update |= OMAP3ISP_CCDC_BLCLAMP;
712 }
713
714 if (OMAP3ISP_CCDC_BCOMP & ccdc_struct->update) {
715 if (copy_from_user(&ccdc->blcomp, ccdc_struct->blcomp,
716 sizeof(ccdc->blcomp))) {
717 ccdc->shadow_update = 0;
718 return -EFAULT;
719 }
720
721 ccdc->update |= OMAP3ISP_CCDC_BCOMP;
722 }
723
724 ccdc->shadow_update = 0;
725
726 if (OMAP3ISP_CCDC_FPC & ccdc_struct->update) {
727 u32 table_old = 0;
728 u32 table_new;
729 u32 size;
730
731 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
732 return -EBUSY;
733
734 ccdc->fpc_en = !!(OMAP3ISP_CCDC_FPC & ccdc_struct->flag);
735
736 if (ccdc->fpc_en) {
737 if (copy_from_user(&ccdc->fpc, ccdc_struct->fpc,
738 sizeof(ccdc->fpc)))
739 return -EFAULT;
740
741 /*
742 * table_new must be 64-bytes aligned, but it's
6c32df43 743 * already done by omap_iommu_vmalloc().
de1135d4
LP		 744 */
745 size = ccdc->fpc.fpnum * 4;
fabdbca8 746 table_new = omap_iommu_vmalloc(isp->domain, isp->dev,
6c32df43 747 0, size, IOMMU_FLAG);
de1135d4
LP		 748 if (IS_ERR_VALUE(table_new))
749 return -ENOMEM;
750
fabdbca8 751 if (copy_from_user(omap_da_to_va(isp->dev, table_new),
de1135d4
LP		 752 (__force void __user *)
753 ccdc->fpc.fpcaddr, size)) {
fabdbca8 754 omap_iommu_vfree(isp->domain, isp->dev,
6c32df43 755 table_new);
de1135d4
LP		 756 return -EFAULT;
757 }
758
759 table_old = ccdc->fpc.fpcaddr;
760 ccdc->fpc.fpcaddr = table_new;
761 }
762
763 ccdc_configure_fpc(ccdc);
764 if (table_old != 0)
fabdbca8 765 omap_iommu_vfree(isp->domain, isp->dev, table_old);
de1135d4
LP		 766 }
767
768 return ccdc_lsc_config(ccdc, ccdc_struct);
769}
770
771static void ccdc_apply_controls(struct isp_ccdc_device *ccdc)
772{
773 if (ccdc->update & OMAP3ISP_CCDC_ALAW) {
774 ccdc_configure_alaw(ccdc);
775 ccdc->update &= ~OMAP3ISP_CCDC_ALAW;
776 }
777
778 if (ccdc->update & OMAP3ISP_CCDC_LPF) {
779 ccdc_configure_lpf(ccdc);
780 ccdc->update &= ~OMAP3ISP_CCDC_LPF;
781 }
782
783 if (ccdc->update & OMAP3ISP_CCDC_BLCLAMP) {
784 ccdc_configure_clamp(ccdc);
785 ccdc->update &= ~OMAP3ISP_CCDC_BLCLAMP;
786 }
787
788 if (ccdc->update & OMAP3ISP_CCDC_BCOMP) {
789 ccdc_configure_black_comp(ccdc);
790 ccdc->update &= ~OMAP3ISP_CCDC_BCOMP;
791 }
792}
793
794/*
795 * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers
796 * @dev: Pointer to ISP device
797 */
798void omap3isp_ccdc_restore_context(struct isp_device *isp)
799{
800 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
801
802 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
803
804 ccdc->update = OMAP3ISP_CCDC_ALAW | OMAP3ISP_CCDC_LPF
805 | OMAP3ISP_CCDC_BLCLAMP | OMAP3ISP_CCDC_BCOMP;
806 ccdc_apply_controls(ccdc);
807 ccdc_configure_fpc(ccdc);
808}
809
810/* -----------------------------------------------------------------------------
811 * Format- and pipeline-related configuration helpers
812 */
813
814/*
815 * ccdc_config_vp - Configure the Video Port.
816 * @ccdc: Pointer to ISP CCDC device.
817 */
818static void ccdc_config_vp(struct isp_ccdc_device *ccdc)
819{
820 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
821 struct isp_device *isp = to_isp_device(ccdc);
73ea57eb 822 const struct isp_format_info *info;
de1135d4
LP		 823 unsigned long l3_ick = pipe->l3_ick;
824 unsigned int max_div = isp->revision == ISP_REVISION_15_0 ? 64 : 8;
825 unsigned int div = 0;
826 u32 fmtcfg_vp;
827
828 fmtcfg_vp = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG)
829 & ~(ISPCCDC_FMTCFG_VPIN_MASK | ISPCCDC_FMTCFG_VPIF_FRQ_MASK);
830
73ea57eb
LP		 831 info = omap3isp_video_format_info(ccdc->formats[CCDC_PAD_SINK].code);
832
833 switch (info->width) {
de1135d4
LP		 834 case 8:
835 case 10:
836 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_9_0;
837 break;
838 case 11:
839 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_10_1;
840 break;
841 case 12:
842 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_11_2;
843 break;
844 case 13:
845 fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_12_3;
846 break;
13eaaa7f 847 }
de1135d4
LP		 848
849 if (pipe->input)
850 div = DIV_ROUND_UP(l3_ick, pipe->max_rate);
c6c01f97
SA		 851 else if (pipe->external_rate)
852 div = l3_ick / pipe->external_rate;
de1135d4
LP		 853
854 div = clamp(div, 2U, max_div);
855 fmtcfg_vp |= (div - 2) << ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT;
856
857 isp_reg_writel(isp, fmtcfg_vp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
858}
859
860/*
861 * ccdc_enable_vp - Enable Video Port.
862 * @ccdc: Pointer to ISP CCDC device.
863 * @enable: 0 Disables VP, 1 Enables VP
864 *
865 * This is needed for outputting image to Preview, H3A and HIST ISP submodules.
866 */
867static void ccdc_enable_vp(struct isp_ccdc_device *ccdc, u8 enable)
868{
869 struct isp_device *isp = to_isp_device(ccdc);
870
871 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG,
872 ISPCCDC_FMTCFG_VPEN, enable ? ISPCCDC_FMTCFG_VPEN : 0);
873}
874
875/*
876 * ccdc_config_outlineoffset - Configure memory saving output line offset
877 * @ccdc: Pointer to ISP CCDC device.
878 * @offset: Address offset to start a new line. Must be twice the
879 * Output width and aligned on 32 byte boundary
880 * @oddeven: Specifies the odd/even line pattern to be chosen to store the
881 * output.
882 * @numlines: Set the value 0-3 for +1-4lines, 4-7 for -1-4lines.
883 *
884 * - Configures the output line offset when stored in memory
885 * - Sets the odd/even line pattern to store the output
886 * (EVENEVEN (1), ODDEVEN (2), EVENODD (3), ODDODD (4))
887 * - Configures the number of even and odd line fields in case of rearranging
888 * the lines.
889 */
890static void ccdc_config_outlineoffset(struct isp_ccdc_device *ccdc,
891 u32 offset, u8 oddeven, u8 numlines)
892{
893 struct isp_device *isp = to_isp_device(ccdc);
894
895 isp_reg_writel(isp, offset & 0xffff,
896 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HSIZE_OFF);
897
898 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
899 ISPCCDC_SDOFST_FINV);
900
901 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
902 ISPCCDC_SDOFST_FOFST_4L);
903
904 switch (oddeven) {
905 case EVENEVEN:
906 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
907 (numlines & 0x7) << ISPCCDC_SDOFST_LOFST0_SHIFT);
908 break;
909 case ODDEVEN:
910 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
911 (numlines & 0x7) << ISPCCDC_SDOFST_LOFST1_SHIFT);
912 break;
913 case EVENODD:
914 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
915 (numlines & 0x7) << ISPCCDC_SDOFST_LOFST2_SHIFT);
916 break;
917 case ODDODD:
918 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
919 (numlines & 0x7) << ISPCCDC_SDOFST_LOFST3_SHIFT);
920 break;
921 default:
922 break;
923 }
924}
925
926/*
927 * ccdc_set_outaddr - Set memory address to save output image
928 * @ccdc: Pointer to ISP CCDC device.
929 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
930 *
931 * Sets the memory address where the output will be saved.
932 */
933static void ccdc_set_outaddr(struct isp_ccdc_device *ccdc, u32 addr)
934{
935 struct isp_device *isp = to_isp_device(ccdc);
936
937 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
938}
939
940/*
941 * omap3isp_ccdc_max_rate - Calculate maximum input data rate based on the input
942 * @ccdc: Pointer to ISP CCDC device.
943 * @max_rate: Maximum calculated data rate.
944 *
945 * Returns in *max_rate less value between calculated and passed
946 */
947void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
948 unsigned int *max_rate)
949{
950 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
951 unsigned int rate;
952
953 if (pipe == NULL)
954 return;
955
956 /*
957 * TRM says that for parallel sensors the maximum data rate
958 * should be 90% form L3/2 clock, otherwise just L3/2.
959 */
960 if (ccdc->input == CCDC_INPUT_PARALLEL)
961 rate = pipe->l3_ick / 2 * 9 / 10;
962 else
963 rate = pipe->l3_ick / 2;
964
965 *max_rate = min(*max_rate, rate);
966}
967
968/*
969 * ccdc_config_sync_if - Set CCDC sync interface configuration
970 * @ccdc: Pointer to ISP CCDC device.
73ea57eb
LP		 971 * @pdata: Parallel interface platform data (may be NULL)
972 * @data_size: Data size
de1135d4
LP		 973 */
974static void ccdc_config_sync_if(struct isp_ccdc_device *ccdc,
73ea57eb
LP		 975 struct isp_parallel_platform_data *pdata,
976 unsigned int data_size)
de1135d4
LP		 977{
978 struct isp_device *isp = to_isp_device(ccdc);
c51364ca 979 const struct v4l2_mbus_framefmt *format;
cf7a3d91 980 u32 syn_mode = ISPCCDC_SYN_MODE_VDHDEN;
de1135d4 981
c51364ca
LP		 982 format = &ccdc->formats[CCDC_PAD_SINK];
983
984 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
985 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
986 /* The bridge is enabled for YUV8 formats. Configure the input
987 * mode accordingly.
988 */
989 syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
990 }
991
73ea57eb 992 switch (data_size) {
de1135d4
LP		 993 case 8:
994 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
995 break;
996 case 10:
997 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
998 break;
999 case 11:
1000 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
1001 break;
1002 case 12:
1003 syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
1004 break;
13eaaa7f 1005 }
de1135d4 1006
73ea57eb 1007 if (pdata && pdata->data_pol)
de1135d4 1008 syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
de1135d4 1009
73ea57eb 1010 if (pdata && pdata->hs_pol)
de1135d4 1011 syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
de1135d4 1012
73ea57eb 1013 if (pdata && pdata->vs_pol)
de1135d4 1014 syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
de1135d4
LP		 1015
1016 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
c51364ca
LP		 1017
1018 /* The CCDC_CFG.Y8POS bit is used in YCbCr8 input mode only. The
1019 * hardware seems to ignore it in all other input modes.
1020 */
1021 if (format->code == V4L2_MBUS_FMT_UYVY8_2X8)
1022 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1023 ISPCCDC_CFG_Y8POS);
1024 else
1025 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1026 ISPCCDC_CFG_Y8POS);
1027
1028 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
1029 ISPCCDC_REC656IF_R656ON);
de1135d4
LP		 1030}
1031
1032/* CCDC formats descriptions */
1033static const u32 ccdc_sgrbg_pattern =
1034 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1035 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1036 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1037 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1038 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1039 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1040 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1041 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1042 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1043 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1044 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1045 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1046 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1047 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1048 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1049 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1050
1051static const u32 ccdc_srggb_pattern =
1052 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1053 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1054 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1055 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1056 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1057 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1058 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1059 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1060 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1061 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1062 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1063 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1064 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1065 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1066 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1067 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1068
1069static const u32 ccdc_sbggr_pattern =
1070 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1071 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1072 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1073 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1074 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1075 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1076 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1077 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1078 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1079 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1080 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1081 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1082 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1083 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1084 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1085 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1086
1087static const u32 ccdc_sgbrg_pattern =
1088 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
1089 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
1090 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
1091 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
1092 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
1093 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
1094 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
1095 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
1096 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
1097 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
1098 ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
1099 ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
1100 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
1101 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
1102 ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
1103 ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
1104
1105static void ccdc_configure(struct isp_ccdc_device *ccdc)
1106{
1107 struct isp_device *isp = to_isp_device(ccdc);
1108 struct isp_parallel_platform_data *pdata = NULL;
1109 struct v4l2_subdev *sensor;
1110 struct v4l2_mbus_framefmt *format;
a64909b8 1111 const struct v4l2_rect *crop;
c09af044
MJ		 1112 const struct isp_format_info *fmt_info;
1113 struct v4l2_subdev_format fmt_src;
1114 unsigned int depth_out;
1115 unsigned int depth_in = 0;
de1135d4
LP		 1116 struct media_pad *pad;
1117 unsigned long flags;
c51364ca 1118 unsigned int bridge;
c09af044 1119 unsigned int shift;
de1135d4
LP		 1120 u32 syn_mode;
1121 u32 ccdc_pattern;
1122
1bddf1b3 1123 pad = media_entity_remote_pad(&ccdc->pads[CCDC_PAD_SINK]);
c09af044
MJ		 1124 sensor = media_entity_to_v4l2_subdev(pad->entity);
1125 if (ccdc->input == CCDC_INPUT_PARALLEL)
de1135d4
LP		 1126 pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
1127 ->bus.parallel;
c09af044 1128
c51364ca
LP		 1129 /* Compute the lane shifter shift value and enable the bridge when the
1130 * input format is YUV.
1131 */
c09af044
MJ		 1132 fmt_src.pad = pad->index;
1133 fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1134 if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
1135 fmt_info = omap3isp_video_format_info(fmt_src.format.code);
1697e49a 1136 depth_in = fmt_info->width;
de1135d4
LP		 1137 }
1138
c09af044
MJ		 1139 fmt_info = omap3isp_video_format_info
1140 (isp->isp_ccdc.formats[CCDC_PAD_SINK].code);
1697e49a 1141 depth_out = fmt_info->width;
c09af044 1142 shift = depth_in - depth_out;
de1135d4 1143
c51364ca
LP		 1144 if (fmt_info->code == V4L2_MBUS_FMT_YUYV8_2X8)
1145 bridge = ISPCTRL_PAR_BRIDGE_LENDIAN;
1146 else if (fmt_info->code == V4L2_MBUS_FMT_UYVY8_2X8)
1147 bridge = ISPCTRL_PAR_BRIDGE_BENDIAN;
1148 else
1149 bridge = ISPCTRL_PAR_BRIDGE_DISABLE;
de1135d4 1150
c51364ca
LP		 1151 omap3isp_configure_bridge(isp, ccdc->input, pdata, shift, bridge);
1152
1153 ccdc_config_sync_if(ccdc, pdata, depth_out);
de1135d4
LP		 1154
1155 syn_mode = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1156
1157 /* Use the raw, unprocessed data when writing to memory. The H3A and
1158 * histogram modules are still fed with lens shading corrected data.
1159 */
1160 syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
1161
1162 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1163 syn_mode |= ISPCCDC_SYN_MODE_WEN;
1164 else
1165 syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
1166
1167 if (ccdc->output & CCDC_OUTPUT_RESIZER)
1168 syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
1169 else
1170 syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
1171
c51364ca
LP		 1172 /* CCDC_PAD_SINK */
1173 format = &ccdc->formats[CCDC_PAD_SINK];
de1135d4
LP		 1174
1175 /* Mosaic filter */
1176 switch (format->code) {
1177 case V4L2_MBUS_FMT_SRGGB10_1X10:
1178 case V4L2_MBUS_FMT_SRGGB12_1X12:
1179 ccdc_pattern = ccdc_srggb_pattern;
1180 break;
1181 case V4L2_MBUS_FMT_SBGGR10_1X10:
1182 case V4L2_MBUS_FMT_SBGGR12_1X12:
1183 ccdc_pattern = ccdc_sbggr_pattern;
1184 break;
1185 case V4L2_MBUS_FMT_SGBRG10_1X10:
1186 case V4L2_MBUS_FMT_SGBRG12_1X12:
1187 ccdc_pattern = ccdc_sgbrg_pattern;
1188 break;
1189 default:
1190 /* Use GRBG */
1191 ccdc_pattern = ccdc_sgrbg_pattern;
1192 break;
1193 }
1194 ccdc_config_imgattr(ccdc, ccdc_pattern);
1195
1196 /* Generate VD0 on the last line of the image and VD1 on the
1197 * 2/3 height line.
1198 */
1199 isp_reg_writel(isp, ((format->height - 2) << ISPCCDC_VDINT_0_SHIFT) |
1200 ((format->height * 2 / 3) << ISPCCDC_VDINT_1_SHIFT),
1201 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT);
1202
1203 /* CCDC_PAD_SOURCE_OF */
c51364ca 1204 format = &ccdc->formats[CCDC_PAD_SOURCE_OF];
a64909b8 1205 crop = &ccdc->crop;
de1135d4 1206
a64909b8
LP		 1207 isp_reg_writel(isp, (crop->left << ISPCCDC_HORZ_INFO_SPH_SHIFT) |
1208 ((crop->width - 1) << ISPCCDC_HORZ_INFO_NPH_SHIFT),
de1135d4 1209 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO);
a64909b8 1210 isp_reg_writel(isp, crop->top << ISPCCDC_VERT_START_SLV0_SHIFT,
de1135d4 1211 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START);
a64909b8 1212 isp_reg_writel(isp, (crop->height - 1)
de1135d4
LP		 1213 << ISPCCDC_VERT_LINES_NLV_SHIFT,
1214 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES);
1215
1216 ccdc_config_outlineoffset(ccdc, ccdc->video_out.bpl_value, 0, 0);
1217
c51364ca
LP		 1218 /* The CCDC outputs data in UYVY order by default. Swap bytes to get
1219 * YUYV.
1220 */
1221 if (format->code == V4L2_MBUS_FMT_YUYV8_1X16)
1222 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1223 ISPCCDC_CFG_BSWD);
1224 else
1225 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1226 ISPCCDC_CFG_BSWD);
1227
1228 /* Use PACK8 mode for 1byte per pixel formats. */
1229 if (omap3isp_video_format_info(format->code)->width <= 8)
1230 syn_mode |= ISPCCDC_SYN_MODE_PACK8;
1231 else
1232 syn_mode &= ~ISPCCDC_SYN_MODE_PACK8;
1233
1234 isp_reg_writel(isp, syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
1235
de1135d4
LP		 1236 /* CCDC_PAD_SOURCE_VP */
1237 format = &ccdc->formats[CCDC_PAD_SOURCE_VP];
1238
1239 isp_reg_writel(isp, (0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
1240 (format->width << ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
1241 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ);
1242 isp_reg_writel(isp, (0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
1243 ((format->height + 1) << ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
1244 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT);
1245
1246 isp_reg_writel(isp, (format->width << ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
1247 (format->height << ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
1248 OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
1249
c51364ca 1250 /* Lens shading correction. */
de1135d4
LP		 1251 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1252 if (ccdc->lsc.request == NULL)
1253 goto unlock;
1254
1255 WARN_ON(ccdc->lsc.active);
1256
1257 /* Get last good LSC configuration. If it is not supported for
1258 * the current active resolution discard it.
1259 */
1260 if (ccdc->lsc.active == NULL &&
1261 __ccdc_lsc_configure(ccdc, ccdc->lsc.request) == 0) {
1262 ccdc->lsc.active = ccdc->lsc.request;
1263 } else {
1264 list_add_tail(&ccdc->lsc.request->list, &ccdc->lsc.free_queue);
1265 schedule_work(&ccdc->lsc.table_work);
1266 }
1267
1268 ccdc->lsc.request = NULL;
1269
1270unlock:
1271 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1272
1273 ccdc_apply_controls(ccdc);
1274}
1275
1276static void __ccdc_enable(struct isp_ccdc_device *ccdc, int enable)
1277{
1278 struct isp_device *isp = to_isp_device(ccdc);
1279
1280 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR,
1281 ISPCCDC_PCR_EN, enable ? ISPCCDC_PCR_EN : 0);
1282}
1283
1284static int ccdc_disable(struct isp_ccdc_device *ccdc)
1285{
1286 unsigned long flags;
1287 int ret = 0;
1288
1289 spin_lock_irqsave(&ccdc->lock, flags);
1290 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1291 ccdc->stopping = CCDC_STOP_REQUEST;
1292 spin_unlock_irqrestore(&ccdc->lock, flags);
1293
1294 ret = wait_event_timeout(ccdc->wait,
1295 ccdc->stopping == CCDC_STOP_FINISHED,
1296 msecs_to_jiffies(2000));
1297 if (ret == 0) {
1298 ret = -ETIMEDOUT;
1299 dev_warn(to_device(ccdc), "CCDC stop timeout!\n");
1300 }
1301
1302 omap3isp_sbl_disable(to_isp_device(ccdc), OMAP3_ISP_SBL_CCDC_LSC_READ);
1303
1304 mutex_lock(&ccdc->ioctl_lock);
1305 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
1306 ccdc->lsc.request = ccdc->lsc.active;
1307 ccdc->lsc.active = NULL;
1308 cancel_work_sync(&ccdc->lsc.table_work);
1309 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
1310 mutex_unlock(&ccdc->ioctl_lock);
1311
1312 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
1313
1314 return ret > 0 ? 0 : ret;
1315}
1316
1317static void ccdc_enable(struct isp_ccdc_device *ccdc)
1318{
1319 if (ccdc_lsc_is_configured(ccdc))
1320 __ccdc_lsc_enable(ccdc, 1);
1321 __ccdc_enable(ccdc, 1);
1322}
1323
1324/* -----------------------------------------------------------------------------
1325 * Interrupt handling
1326 */
1327
1328/*
1329 * ccdc_sbl_busy - Poll idle state of CCDC and related SBL memory write bits
1330 * @ccdc: Pointer to ISP CCDC device.
1331 *
1332 * Returns zero if the CCDC is idle and the image has been written to
1333 * memory, too.
1334 */
1335static int ccdc_sbl_busy(struct isp_ccdc_device *ccdc)
1336{
1337 struct isp_device *isp = to_isp_device(ccdc);
1338
1339 return omap3isp_ccdc_busy(ccdc)
1340 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
1341 ISPSBL_CCDC_WR_0_DATA_READY)
1342 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
1343 ISPSBL_CCDC_WR_0_DATA_READY)
1344 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
1345 ISPSBL_CCDC_WR_0_DATA_READY)
1346 | (isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
1347 ISPSBL_CCDC_WR_0_DATA_READY);
1348}
1349
1350/*
1351 * ccdc_sbl_wait_idle - Wait until the CCDC and related SBL are idle
1352 * @ccdc: Pointer to ISP CCDC device.
1353 * @max_wait: Max retry count in us for wait for idle/busy transition.
1354 */
1355static int ccdc_sbl_wait_idle(struct isp_ccdc_device *ccdc,
1356 unsigned int max_wait)
1357{
1358 unsigned int wait = 0;
1359
1360 if (max_wait == 0)
1361 max_wait = 10000; /* 10 ms */
1362
1363 for (wait = 0; wait <= max_wait; wait++) {
1364 if (!ccdc_sbl_busy(ccdc))
1365 return 0;
1366
1367 rmb();
1368 udelay(1);
1369 }
1370
1371 return -EBUSY;
1372}
1373
1374/* __ccdc_handle_stopping - Handle CCDC and/or LSC stopping sequence
1375 * @ccdc: Pointer to ISP CCDC device.
1376 * @event: Pointing which event trigger handler
1377 *
2d4e9d1d 1378 * Return 1 when the event and stopping request combination is satisfied,
de1135d4
LP		 1379 * zero otherwise.
1380 */
1381static int __ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
1382{
1383 int rval = 0;
1384
1385 switch ((ccdc->stopping & 3) | event) {
1386 case CCDC_STOP_REQUEST | CCDC_EVENT_VD1:
1387 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1388 __ccdc_lsc_enable(ccdc, 0);
1389 __ccdc_enable(ccdc, 0);
1390 ccdc->stopping = CCDC_STOP_EXECUTED;
1391 return 1;
1392
1393 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD0:
1394 ccdc->stopping |= CCDC_STOP_CCDC_FINISHED;
1395 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1396 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1397 rval = 1;
1398 break;
1399
1400 case CCDC_STOP_EXECUTED | CCDC_EVENT_LSC_DONE:
1401 ccdc->stopping |= CCDC_STOP_LSC_FINISHED;
1402 rval = 1;
1403 break;
1404
1405 case CCDC_STOP_EXECUTED | CCDC_EVENT_VD1:
1406 return 1;
1407 }
1408
1409 if (ccdc->stopping == CCDC_STOP_FINISHED) {
1410 wake_up(&ccdc->wait);
1411 rval = 1;
1412 }
1413
1414 return rval;
1415}
1416
1417static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
1418{
bd0f2e6d 1419 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
63ae37ea 1420 struct video_device *vdev = ccdc->subdev.devnode;
de1135d4
LP		 1421 struct v4l2_event event;
1422
b43883d6
LP		 1423 /* Frame number propagation */
1424 atomic_inc(&pipe->frame_number);
1425
de1135d4 1426 memset(&event, 0, sizeof(event));
69d232ae
SA		 1427 event.type = V4L2_EVENT_FRAME_SYNC;
1428 event.u.frame_sync.frame_sequence = atomic_read(&pipe->frame_number);
de1135d4
LP		 1429
1430 v4l2_event_queue(vdev, &event);
1431}
1432
1433/*
1434 * ccdc_lsc_isr - Handle LSC events
1435 * @ccdc: Pointer to ISP CCDC device.
1436 * @events: LSC events
1437 */
1438static void ccdc_lsc_isr(struct isp_ccdc_device *ccdc, u32 events)
1439{
1440 unsigned long flags;
1441
1442 if (events & IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ) {
875e2e3e
LP		 1443 struct isp_pipeline *pipe =
1444 to_isp_pipeline(&ccdc->subdev.entity);
1445
de1135d4 1446 ccdc_lsc_error_handler(ccdc);
875e2e3e 1447 pipe->error = true;
de1135d4
LP		 1448 dev_dbg(to_device(ccdc), "lsc prefetch error\n");
1449 }
1450
1451 if (!(events & IRQ0STATUS_CCDC_LSC_DONE_IRQ))
1452 return;
1453
1454 /* LSC_DONE interrupt occur, there are two cases
1455 * 1. stopping for reconfiguration
1456 * 2. stopping because of STREAM OFF command
1457 */
1458 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1459
1460 if (ccdc->lsc.state == LSC_STATE_STOPPING)
1461 ccdc->lsc.state = LSC_STATE_STOPPED;
1462
1463 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_LSC_DONE))
1464 goto done;
1465
1466 if (ccdc->lsc.state != LSC_STATE_RECONFIG)
1467 goto done;
1468
1469 /* LSC is in STOPPING state, change to the new state */
1470 ccdc->lsc.state = LSC_STATE_STOPPED;
1471
1472 /* This is an exception. Start of frame and LSC_DONE interrupt
1473 * have been received on the same time. Skip this event and wait
1474 * for better times.
1475 */
1476 if (events & IRQ0STATUS_HS_VS_IRQ)
1477 goto done;
1478
1479 /* The LSC engine is stopped at this point. Enable it if there's a
1480 * pending request.
1481 */
1482 if (ccdc->lsc.request == NULL)
1483 goto done;
1484
1485 ccdc_lsc_enable(ccdc);
1486
1487done:
1488 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1489}
1490
1491static int ccdc_isr_buffer(struct isp_ccdc_device *ccdc)
1492{
1493 struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
1494 struct isp_device *isp = to_isp_device(ccdc);
1495 struct isp_buffer *buffer;
1496 int restart = 0;
1497
1498 /* The CCDC generates VD0 interrupts even when disabled (the datasheet
1499 * doesn't explicitly state if that's supposed to happen or not, so it
1500 * can be considered as a hardware bug or as a feature, but we have to
1501 * deal with it anyway). Disabling the CCDC when no buffer is available
1502 * would thus not be enough, we need to handle the situation explicitly.
1503 */
1504 if (list_empty(&ccdc->video_out.dmaqueue))
1505 goto done;
1506
1507 /* We're in continuous mode, and memory writes were disabled due to a
1508 * buffer underrun. Reenable them now that we have a buffer. The buffer
1509 * address has been set in ccdc_video_queue.
1510 */
1511 if (ccdc->state == ISP_PIPELINE_STREAM_CONTINUOUS && ccdc->underrun) {
1512 restart = 1;
1513 ccdc->underrun = 0;
1514 goto done;
1515 }
1516
1517 if (ccdc_sbl_wait_idle(ccdc, 1000)) {
1518 dev_info(isp->dev, "CCDC won't become idle!\n");
9554b7db
LP		 1519 isp->crashed |= 1U << ccdc->subdev.entity.id;
1520 omap3isp_pipeline_cancel_stream(pipe);
de1135d4
LP		 1521 goto done;
1522 }
1523
875e2e3e 1524 buffer = omap3isp_video_buffer_next(&ccdc->video_out);
de1135d4
LP		 1525 if (buffer != NULL) {
1526 ccdc_set_outaddr(ccdc, buffer->isp_addr);
1527 restart = 1;
1528 }
1529
1530 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1531
1532 if (ccdc->state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1533 isp_pipeline_ready(pipe))
1534 omap3isp_pipeline_set_stream(pipe,
1535 ISP_PIPELINE_STREAM_SINGLESHOT);
1536
1537done:
de1135d4
LP		 1538 return restart;
1539}
1540
1541/*
1542 * ccdc_vd0_isr - Handle VD0 event
1543 * @ccdc: Pointer to ISP CCDC device.
1544 *
1545 * Executes LSC deferred enablement before next frame starts.
1546 */
1547static void ccdc_vd0_isr(struct isp_ccdc_device *ccdc)
1548{
1549 unsigned long flags;
1550 int restart = 0;
1551
1552 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1553 restart = ccdc_isr_buffer(ccdc);
1554
1555 spin_lock_irqsave(&ccdc->lock, flags);
1556 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD0)) {
1557 spin_unlock_irqrestore(&ccdc->lock, flags);
1558 return;
1559 }
1560
1561 if (!ccdc->shadow_update)
1562 ccdc_apply_controls(ccdc);
1563 spin_unlock_irqrestore(&ccdc->lock, flags);
1564
1565 if (restart)
1566 ccdc_enable(ccdc);
1567}
1568
1569/*
1570 * ccdc_vd1_isr - Handle VD1 event
1571 * @ccdc: Pointer to ISP CCDC device.
1572 */
1573static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)
1574{
1575 unsigned long flags;
1576
1577 spin_lock_irqsave(&ccdc->lsc.req_lock, flags);
1578
1579 /*
1580 * Depending on the CCDC pipeline state, CCDC stopping should be
1581 * handled differently. In SINGLESHOT we emulate an internal CCDC
1582 * stopping because the CCDC hw works only in continuous mode.
1583 * When CONTINUOUS pipeline state is used and the CCDC writes it's
1584 * data to memory the CCDC and LSC are stopped immediately but
1585 * without change the CCDC stopping state machine. The CCDC
1586 * stopping state machine should be used only when user request
1587 * for stopping is received (SINGLESHOT is an exeption).
1588 */
1589 switch (ccdc->state) {
1590 case ISP_PIPELINE_STREAM_SINGLESHOT:
1591 ccdc->stopping = CCDC_STOP_REQUEST;
1592 break;
1593
1594 case ISP_PIPELINE_STREAM_CONTINUOUS:
1595 if (ccdc->output & CCDC_OUTPUT_MEMORY) {
1596 if (ccdc->lsc.state != LSC_STATE_STOPPED)
1597 __ccdc_lsc_enable(ccdc, 0);
1598 __ccdc_enable(ccdc, 0);
1599 }
1600 break;
1601
1602 case ISP_PIPELINE_STREAM_STOPPED:
1603 break;
1604 }
1605
1606 if (__ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))
1607 goto done;
1608
1609 if (ccdc->lsc.request == NULL)
1610 goto done;
1611
1612 /*
1613 * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ
1614 * do the appropriate changes in registers
1615 */
1616 if (ccdc->lsc.state == LSC_STATE_RUNNING) {
1617 __ccdc_lsc_enable(ccdc, 0);
1618 ccdc->lsc.state = LSC_STATE_RECONFIG;
1619 goto done;
1620 }
1621
1622 /* LSC has been in STOPPED state, enable it */
1623 if (ccdc->lsc.state == LSC_STATE_STOPPED)
1624 ccdc_lsc_enable(ccdc);
1625
1626done:
1627 spin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);
1628}
1629
1630/*
1631 * omap3isp_ccdc_isr - Configure CCDC during interframe time.
1632 * @ccdc: Pointer to ISP CCDC device.
1633 * @events: CCDC events
1634 */
1635int omap3isp_ccdc_isr(struct isp_ccdc_device *ccdc, u32 events)
1636{
1637 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED)
1638 return 0;
1639
1640 if (events & IRQ0STATUS_CCDC_VD1_IRQ)
1641 ccdc_vd1_isr(ccdc);
1642
1643 ccdc_lsc_isr(ccdc, events);
1644
1645 if (events & IRQ0STATUS_CCDC_VD0_IRQ)
1646 ccdc_vd0_isr(ccdc);
1647
1648 if (events & IRQ0STATUS_HS_VS_IRQ)
1649 ccdc_hs_vs_isr(ccdc);
1650
1651 return 0;
1652}
1653
1654/* -----------------------------------------------------------------------------
1655 * ISP video operations
1656 */
1657
1658static int ccdc_video_queue(struct isp_video *video, struct isp_buffer *buffer)
1659{
1660 struct isp_ccdc_device *ccdc = &video->isp->isp_ccdc;
1661
1662 if (!(ccdc->output & CCDC_OUTPUT_MEMORY))
1663 return -ENODEV;
1664
1665 ccdc_set_outaddr(ccdc, buffer->isp_addr);
1666
2d4e9d1d 1667 /* We now have a buffer queued on the output, restart the pipeline
de1135d4
LP		 1668 * on the next CCDC interrupt if running in continuous mode (or when
1669 * starting the stream).
1670 */
1671 ccdc->underrun = 1;
1672
1673 return 0;
1674}
1675
1676static const struct isp_video_operations ccdc_video_ops = {
1677 .queue = ccdc_video_queue,
1678};
1679
1680/* -----------------------------------------------------------------------------
1681 * V4L2 subdev operations
1682 */
1683
1684/*
1685 * ccdc_ioctl - CCDC module private ioctl's
1686 * @sd: ISP CCDC V4L2 subdevice
1687 * @cmd: ioctl command
1688 * @arg: ioctl argument
1689 *
1690 * Return 0 on success or a negative error code otherwise.
1691 */
1692static long ccdc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1693{
1694 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1695 int ret;
1696
1697 switch (cmd) {
1698 case VIDIOC_OMAP3ISP_CCDC_CFG:
1699 mutex_lock(&ccdc->ioctl_lock);
1700 ret = ccdc_config(ccdc, arg);
1701 mutex_unlock(&ccdc->ioctl_lock);
1702 break;
1703
1704 default:
1705 return -ENOIOCTLCMD;
1706 }
1707
1708 return ret;
1709}
1710
1711static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1712 struct v4l2_event_subscription *sub)
de1135d4 1713{
69d232ae
SA		 1714 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1715 return -EINVAL;
1716
1717 /* line number is zero at frame start */
1718 if (sub->id != 0)
de1135d4
LP		 1719 return -EINVAL;
1720
c53c2549 1721 return v4l2_event_subscribe(fh, sub, OMAP3ISP_CCDC_NEVENTS, NULL);
de1135d4
LP		 1722}
1723
1724static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
55c85046 1725 struct v4l2_event_subscription *sub)
de1135d4
LP		 1726{
1727 return v4l2_event_unsubscribe(fh, sub);
1728}
1729
1730/*
1731 * ccdc_set_stream - Enable/Disable streaming on the CCDC module
1732 * @sd: ISP CCDC V4L2 subdevice
1733 * @enable: Enable/disable stream
1734 *
1735 * When writing to memory, the CCDC hardware can't be enabled without a memory
1736 * buffer to write to. As the s_stream operation is called in response to a
1737 * STREAMON call without any buffer queued yet, just update the enabled field
1738 * and return immediately. The CCDC will be enabled in ccdc_isr_buffer().
1739 *
1740 * When not writing to memory enable the CCDC immediately.
1741 */
1742static int ccdc_set_stream(struct v4l2_subdev *sd, int enable)
1743{
1744 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1745 struct isp_device *isp = to_isp_device(ccdc);
1746 int ret = 0;
1747
1748 if (ccdc->state == ISP_PIPELINE_STREAM_STOPPED) {
1749 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1750 return 0;
1751
1752 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_CCDC);
1753 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
1754 ISPCCDC_CFG_VDLC);
1755
1756 ccdc_configure(ccdc);
1757
1758 /* TODO: Don't configure the video port if all of its output
1759 * links are inactive.
1760 */
1761 ccdc_config_vp(ccdc);
1762 ccdc_enable_vp(ccdc, 1);
de1135d4
LP		 1763 ccdc_print_status(ccdc);
1764 }
1765
1766 switch (enable) {
1767 case ISP_PIPELINE_STREAM_CONTINUOUS:
1768 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1769 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1770
1771 if (ccdc->underrun || !(ccdc->output & CCDC_OUTPUT_MEMORY))
1772 ccdc_enable(ccdc);
1773
1774 ccdc->underrun = 0;
1775 break;
1776
1777 case ISP_PIPELINE_STREAM_SINGLESHOT:
1778 if (ccdc->output & CCDC_OUTPUT_MEMORY &&
1779 ccdc->state != ISP_PIPELINE_STREAM_SINGLESHOT)
1780 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1781
1782 ccdc_enable(ccdc);
1783 break;
1784
1785 case ISP_PIPELINE_STREAM_STOPPED:
1786 ret = ccdc_disable(ccdc);
1787 if (ccdc->output & CCDC_OUTPUT_MEMORY)
1788 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CCDC_WRITE);
1789 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_CCDC);
1790 ccdc->underrun = 0;
1791 break;
1792 }
1793
1794 ccdc->state = enable;
1795 return ret;
1796}
1797
1798static struct v4l2_mbus_framefmt *
1799__ccdc_get_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1800 unsigned int pad, enum v4l2_subdev_format_whence which)
1801{
1802 if (which == V4L2_SUBDEV_FORMAT_TRY)
1803 return v4l2_subdev_get_try_format(fh, pad);
1804 else
1805 return &ccdc->formats[pad];
1806}
1807
a64909b8
LP		 1808static struct v4l2_rect *
1809__ccdc_get_crop(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1810 enum v4l2_subdev_format_whence which)
1811{
1812 if (which == V4L2_SUBDEV_FORMAT_TRY)
1813 return v4l2_subdev_get_try_crop(fh, CCDC_PAD_SOURCE_OF);
1814 else
1815 return &ccdc->crop;
1816}
1817
de1135d4
LP		 1818/*
1819 * ccdc_try_format - Try video format on a pad
1820 * @ccdc: ISP CCDC device
1821 * @fh : V4L2 subdev file handle
1822 * @pad: Pad number
1823 * @fmt: Format
1824 */
1825static void
1826ccdc_try_format(struct isp_ccdc_device *ccdc, struct v4l2_subdev_fh *fh,
1827 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
1828 enum v4l2_subdev_format_whence which)
1829{
de1135d4 1830 const struct isp_format_info *info;
c51364ca 1831 enum v4l2_mbus_pixelcode pixelcode;
de1135d4
LP		 1832 unsigned int width = fmt->width;
1833 unsigned int height = fmt->height;
a64909b8 1834 struct v4l2_rect *crop;
de1135d4
LP		 1835 unsigned int i;
1836
1837 switch (pad) {
1838 case CCDC_PAD_SINK:
de1135d4
LP		 1839 for (i = 0; i < ARRAY_SIZE(ccdc_fmts); i++) {
1840 if (fmt->code == ccdc_fmts[i])
1841 break;
1842 }
1843
1844 /* If not found, use SGRBG10 as default */
1845 if (i >= ARRAY_SIZE(ccdc_fmts))
1846 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1847
1848 /* Clamp the input size. */
1849 fmt->width = clamp_t(u32, width, 32, 4096);
1850 fmt->height = clamp_t(u32, height, 32, 4096);
1851 break;
1852
1853 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 1854 pixelcode = fmt->code;
1855 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
1856
1857 /* YUV formats are converted from 2X8 to 1X16 by the bridge and
1858 * can be byte-swapped.
1859 */
1860 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1861 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1862 /* Use the user requested format if YUV. */
1863 if (pixelcode == V4L2_MBUS_FMT_YUYV8_2X8 ||
1864 pixelcode == V4L2_MBUS_FMT_UYVY8_2X8 ||
1865 pixelcode == V4L2_MBUS_FMT_YUYV8_1X16 ||
1866 pixelcode == V4L2_MBUS_FMT_UYVY8_1X16)
1867 fmt->code = pixelcode;
1868
1869 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8)
1870 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1871 else if (fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1872 fmt->code = V4L2_MBUS_FMT_UYVY8_1X16;
1873 }
de1135d4 1874
a64909b8
LP		 1875 /* Hardcode the output size to the crop rectangle size. */
1876 crop = __ccdc_get_crop(ccdc, fh, which);
1877 fmt->width = crop->width;
1878 fmt->height = crop->height;
de1135d4
LP		 1879 break;
1880
1881 case CCDC_PAD_SOURCE_VP:
c51364ca 1882 *fmt = *__ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, which);
de1135d4
LP		 1883
1884 /* The video port interface truncates the data to 10 bits. */
1885 info = omap3isp_video_format_info(fmt->code);
1886 fmt->code = info->truncated;
1887
c51364ca
LP		 1888 /* YUV formats are not supported by the video port. */
1889 if (fmt->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1890 fmt->code == V4L2_MBUS_FMT_UYVY8_2X8)
1891 fmt->code = 0;
1892
de1135d4
LP		 1893 /* The number of lines that can be clocked out from the video
1894 * port output must be at least one line less than the number
1895 * of input lines.
1896 */
1897 fmt->width = clamp_t(u32, width, 32, fmt->width);
1898 fmt->height = clamp_t(u32, height, 32, fmt->height - 1);
1899 break;
1900 }
1901
1902 /* Data is written to memory unpacked, each 10-bit or 12-bit pixel is
1903 * stored on 2 bytes.
1904 */
1905 fmt->colorspace = V4L2_COLORSPACE_SRGB;
1906 fmt->field = V4L2_FIELD_NONE;
1907}
1908
a64909b8
LP		 1909/*
1910 * ccdc_try_crop - Validate a crop rectangle
1911 * @ccdc: ISP CCDC device
1912 * @sink: format on the sink pad
1913 * @crop: crop rectangle to be validated
1914 */
1915static void ccdc_try_crop(struct isp_ccdc_device *ccdc,
1916 const struct v4l2_mbus_framefmt *sink,
1917 struct v4l2_rect *crop)
1918{
1919 const struct isp_format_info *info;
1920 unsigned int max_width;
1921
1922 /* For Bayer formats, restrict left/top and width/height to even values
1923 * to keep the Bayer pattern.
1924 */
1925 info = omap3isp_video_format_info(sink->code);
1926 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
1927 crop->left &= ~1;
1928 crop->top &= ~1;
1929 }
1930
1931 crop->left = clamp_t(u32, crop->left, 0, sink->width - CCDC_MIN_WIDTH);
1932 crop->top = clamp_t(u32, crop->top, 0, sink->height - CCDC_MIN_HEIGHT);
1933
1934 /* The data formatter truncates the number of horizontal output pixels
1935 * to a multiple of 16. To avoid clipping data, allow callers to request
1936 * an output size bigger than the input size up to the nearest multiple
1937 * of 16.
1938 */
1939 max_width = (sink->width - crop->left + 15) & ~15;
1940 crop->width = clamp_t(u32, crop->width, CCDC_MIN_WIDTH, max_width)
1941 & ~15;
1942 crop->height = clamp_t(u32, crop->height, CCDC_MIN_HEIGHT,
1943 sink->height - crop->top);
1944
1945 /* Odd width/height values don't make sense for Bayer formats. */
1946 if (info->flavor != V4L2_MBUS_FMT_Y8_1X8) {
1947 crop->width &= ~1;
1948 crop->height &= ~1;
1949 }
1950}
1951
de1135d4
LP		 1952/*
1953 * ccdc_enum_mbus_code - Handle pixel format enumeration
1954 * @sd : pointer to v4l2 subdev structure
1955 * @fh : V4L2 subdev file handle
1956 * @code : pointer to v4l2_subdev_mbus_code_enum structure
1957 * return -EINVAL or zero on success
1958 */
1959static int ccdc_enum_mbus_code(struct v4l2_subdev *sd,
1960 struct v4l2_subdev_fh *fh,
1961 struct v4l2_subdev_mbus_code_enum *code)
1962{
1963 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
1964 struct v4l2_mbus_framefmt *format;
1965
1966 switch (code->pad) {
1967 case CCDC_PAD_SINK:
1968 if (code->index >= ARRAY_SIZE(ccdc_fmts))
1969 return -EINVAL;
1970
1971 code->code = ccdc_fmts[code->index];
1972 break;
1973
1974 case CCDC_PAD_SOURCE_OF:
c51364ca
LP		 1975 format = __ccdc_get_format(ccdc, fh, code->pad,
1976 V4L2_SUBDEV_FORMAT_TRY);
1977
1978 if (format->code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1979 format->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1980 /* In YUV mode the CCDC can swap bytes. */
1981 if (code->index == 0)
1982 code->code = V4L2_MBUS_FMT_YUYV8_1X16;
1983 else if (code->index == 1)
1984 code->code = V4L2_MBUS_FMT_UYVY8_1X16;
1985 else
1986 return -EINVAL;
1987 } else {
1988 /* In raw mode, no configurable format confversion is
1989 * available.
1990 */
1991 if (code->index == 0)
1992 code->code = format->code;
1993 else
1994 return -EINVAL;
1995 }
1996 break;
1997
de1135d4 1998 case CCDC_PAD_SOURCE_VP:
c51364ca
LP		 1999 /* The CCDC supports no configurable format conversion
2000 * compatible with the video port. Enumerate a single output
2001 * format code.
2002 */
de1135d4
LP		 2003 if (code->index != 0)
2004 return -EINVAL;
2005
c51364ca 2006 format = __ccdc_get_format(ccdc, fh, code->pad,
de1135d4
LP		 2007 V4L2_SUBDEV_FORMAT_TRY);
2008
c51364ca
LP		 2009 /* A pixel code equal to 0 means that the video port doesn't
2010 * support the input format. Don't enumerate any pixel code.
2011 */
2012 if (format->code == 0)
2013 return -EINVAL;
2014
de1135d4
LP		 2015 code->code = format->code;
2016 break;
2017
2018 default:
2019 return -EINVAL;
2020 }
2021
2022 return 0;
2023}
2024
2025static int ccdc_enum_frame_size(struct v4l2_subdev *sd,
2026 struct v4l2_subdev_fh *fh,
2027 struct v4l2_subdev_frame_size_enum *fse)
2028{
2029 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2030 struct v4l2_mbus_framefmt format;
2031
2032 if (fse->index != 0)
2033 return -EINVAL;
2034
2035 format.code = fse->code;
2036 format.width = 1;
2037 format.height = 1;
2038 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2039 fse->min_width = format.width;
2040 fse->min_height = format.height;
2041
2042 if (format.code != fse->code)
2043 return -EINVAL;
2044
2045 format.code = fse->code;
2046 format.width = -1;
2047 format.height = -1;
2048 ccdc_try_format(ccdc, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
2049 fse->max_width = format.width;
2050 fse->max_height = format.height;
2051
2052 return 0;
2053}
2054
a64909b8
LP		 2055/*
2056 * ccdc_get_selection - Retrieve a selection rectangle on a pad
2057 * @sd: ISP CCDC V4L2 subdevice
2058 * @fh: V4L2 subdev file handle
2059 * @sel: Selection rectangle
2060 *
2061 * The only supported rectangles are the crop rectangles on the output formatter
2062 * source pad.
2063 *
2064 * Return 0 on success or a negative error code otherwise.
2065 */
2066static int ccdc_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2067 struct v4l2_subdev_selection *sel)
2068{
2069 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2070 struct v4l2_mbus_framefmt *format;
2071
2072 if (sel->pad != CCDC_PAD_SOURCE_OF)
2073 return -EINVAL;
2074
2075 switch (sel->target) {
5689b288 2076 case V4L2_SEL_TGT_CROP_BOUNDS:
a64909b8
LP		 2077 sel->r.left = 0;
2078 sel->r.top = 0;
2079 sel->r.width = INT_MAX;
2080 sel->r.height = INT_MAX;
2081
2082 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2083 ccdc_try_crop(ccdc, format, &sel->r);
2084 break;
2085
5689b288 2086 case V4L2_SEL_TGT_CROP:
a64909b8
LP		 2087 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2088 break;
2089
2090 default:
2091 return -EINVAL;
2092 }
2093
2094 return 0;
2095}
2096
2097/*
2098 * ccdc_set_selection - Set a selection rectangle on a pad
2099 * @sd: ISP CCDC V4L2 subdevice
2100 * @fh: V4L2 subdev file handle
2101 * @sel: Selection rectangle
2102 *
2103 * The only supported rectangle is the actual crop rectangle on the output
2104 * formatter source pad.
2105 *
2106 * Return 0 on success or a negative error code otherwise.
2107 */
2108static int ccdc_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2109 struct v4l2_subdev_selection *sel)
2110{
2111 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2112 struct v4l2_mbus_framefmt *format;
2113
5689b288 2114 if (sel->target != V4L2_SEL_TGT_CROP ||
a64909b8
LP		 2115 sel->pad != CCDC_PAD_SOURCE_OF)
2116 return -EINVAL;
2117
2118 /* The crop rectangle can't be changed while streaming. */
2119 if (ccdc->state != ISP_PIPELINE_STREAM_STOPPED)
2120 return -EBUSY;
2121
2122 /* Modifying the crop rectangle always changes the format on the source
2123 * pad. If the KEEP_CONFIG flag is set, just return the current crop
2124 * rectangle.
2125 */
563df3d0 2126 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
a64909b8
LP		 2127 sel->r = *__ccdc_get_crop(ccdc, fh, sel->which);
2128 return 0;
2129 }
2130
2131 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SINK, sel->which);
2132 ccdc_try_crop(ccdc, format, &sel->r);
2133 *__ccdc_get_crop(ccdc, fh, sel->which) = sel->r;
2134
2135 /* Update the source format. */
2136 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF, sel->which);
2137 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format, sel->which);
2138
2139 return 0;
2140}
2141
de1135d4
LP		 2142/*
2143 * ccdc_get_format - Retrieve the video format on a pad
2144 * @sd : ISP CCDC V4L2 subdevice
2145 * @fh : V4L2 subdev file handle
2146 * @fmt: Format
2147 *
2148 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2149 * to the format type.
2150 */
2151static int ccdc_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2152 struct v4l2_subdev_format *fmt)
2153{
2154 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2155 struct v4l2_mbus_framefmt *format;
2156
2157 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2158 if (format == NULL)
2159 return -EINVAL;
2160
2161 fmt->format = *format;
2162 return 0;
2163}
2164
2165/*
2166 * ccdc_set_format - Set the video format on a pad
2167 * @sd : ISP CCDC V4L2 subdevice
2168 * @fh : V4L2 subdev file handle
2169 * @fmt: Format
2170 *
2171 * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond
2172 * to the format type.
2173 */
2174static int ccdc_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2175 struct v4l2_subdev_format *fmt)
2176{
2177 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2178 struct v4l2_mbus_framefmt *format;
a64909b8 2179 struct v4l2_rect *crop;
de1135d4
LP		 2180
2181 format = __ccdc_get_format(ccdc, fh, fmt->pad, fmt->which);
2182 if (format == NULL)
2183 return -EINVAL;
2184
2185 ccdc_try_format(ccdc, fh, fmt->pad, &fmt->format, fmt->which);
2186 *format = fmt->format;
2187
2188 /* Propagate the format from sink to source */
2189 if (fmt->pad == CCDC_PAD_SINK) {
a64909b8
LP		 2190 /* Reset the crop rectangle. */
2191 crop = __ccdc_get_crop(ccdc, fh, fmt->which);
2192 crop->left = 0;
2193 crop->top = 0;
2194 crop->width = fmt->format.width;
2195 crop->height = fmt->format.height;
2196
2197 ccdc_try_crop(ccdc, &fmt->format, crop);
2198
2199 /* Update the source formats. */
de1135d4
LP		 2200 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_OF,
2201 fmt->which);
2202 *format = fmt->format;
2203 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_OF, format,
2204 fmt->which);
2205
2206 format = __ccdc_get_format(ccdc, fh, CCDC_PAD_SOURCE_VP,
2207 fmt->which);
2208 *format = fmt->format;
2209 ccdc_try_format(ccdc, fh, CCDC_PAD_SOURCE_VP, format,
2210 fmt->which);
2211 }
2212
2213 return 0;
2214}
2215
a6d7a62d
SA		 2216/*
2217 * Decide whether desired output pixel code can be obtained with
2218 * the lane shifter by shifting the input pixel code.
2219 * @in: input pixelcode to shifter
2220 * @out: output pixelcode from shifter
2221 * @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
2222 *
2223 * return true if the combination is possible
2224 * return false otherwise
2225 */
2226static bool ccdc_is_shiftable(enum v4l2_mbus_pixelcode in,
2227 enum v4l2_mbus_pixelcode out,
2228 unsigned int additional_shift)
2229{
2230 const struct isp_format_info *in_info, *out_info;
2231
2232 if (in == out)
2233 return true;
2234
2235 in_info = omap3isp_video_format_info(in);
2236 out_info = omap3isp_video_format_info(out);
2237
2238 if ((in_info->flavor == 0) || (out_info->flavor == 0))
2239 return false;
2240
2241 if (in_info->flavor != out_info->flavor)
2242 return false;
2243
1697e49a 2244 return in_info->width - out_info->width + additional_shift <= 6;
a6d7a62d
SA		 2245}
2246
2247static int ccdc_link_validate(struct v4l2_subdev *sd,
2248 struct media_link *link,
2249 struct v4l2_subdev_format *source_fmt,
2250 struct v4l2_subdev_format *sink_fmt)
2251{
2252 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2253 unsigned long parallel_shift;
2254
2255 /* Check if the two ends match */
2256 if (source_fmt->format.width != sink_fmt->format.width ||
2257 source_fmt->format.height != sink_fmt->format.height)
2258 return -EPIPE;
2259
2260 /* We've got a parallel sensor here. */
2261 if (ccdc->input == CCDC_INPUT_PARALLEL) {
2262 struct isp_parallel_platform_data *pdata =
2263 &((struct isp_v4l2_subdevs_group *)
2264 media_entity_to_v4l2_subdev(link->source->entity)
2265 ->host_priv)->bus.parallel;
2266 parallel_shift = pdata->data_lane_shift * 2;
2267 } else {
2268 parallel_shift = 0;
2269 }
2270
2271 /* Lane shifter may be used to drop bits on CCDC sink pad */
2272 if (!ccdc_is_shiftable(source_fmt->format.code,
2273 sink_fmt->format.code, parallel_shift))
2274 return -EPIPE;
2275
2276 return 0;
2277}
2278
de1135d4
LP		 2279/*
2280 * ccdc_init_formats - Initialize formats on all pads
2281 * @sd: ISP CCDC V4L2 subdevice
2282 * @fh: V4L2 subdev file handle
2283 *
2284 * Initialize all pad formats with default values. If fh is not NULL, try
2285 * formats are initialized on the file handle. Otherwise active formats are
2286 * initialized on the device.
2287 */
2288static int ccdc_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2289{
2290 struct v4l2_subdev_format format;
2291
2292 memset(&format, 0, sizeof(format));
2293 format.pad = CCDC_PAD_SINK;
2294 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
2295 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
2296 format.format.width = 4096;
2297 format.format.height = 4096;
2298 ccdc_set_format(sd, fh, &format);
2299
2300 return 0;
2301}
2302
2303/* V4L2 subdev core operations */
2304static const struct v4l2_subdev_core_ops ccdc_v4l2_core_ops = {
2305 .ioctl = ccdc_ioctl,
2306 .subscribe_event = ccdc_subscribe_event,
2307 .unsubscribe_event = ccdc_unsubscribe_event,
2308};
2309
2310/* V4L2 subdev video operations */
2311static const struct v4l2_subdev_video_ops ccdc_v4l2_video_ops = {
2312 .s_stream = ccdc_set_stream,
2313};
2314
2315/* V4L2 subdev pad operations */
2316static const struct v4l2_subdev_pad_ops ccdc_v4l2_pad_ops = {
2317 .enum_mbus_code = ccdc_enum_mbus_code,
2318 .enum_frame_size = ccdc_enum_frame_size,
2319 .get_fmt = ccdc_get_format,
2320 .set_fmt = ccdc_set_format,
a64909b8
LP		 2321 .get_selection = ccdc_get_selection,
2322 .set_selection = ccdc_set_selection,
a6d7a62d 2323 .link_validate = ccdc_link_validate,
de1135d4
LP		 2324};
2325
2326/* V4L2 subdev operations */
2327static const struct v4l2_subdev_ops ccdc_v4l2_ops = {
2328 .core = &ccdc_v4l2_core_ops,
2329 .video = &ccdc_v4l2_video_ops,
2330 .pad = &ccdc_v4l2_pad_ops,
2331};
2332
2333/* V4L2 subdev internal operations */
2334static const struct v4l2_subdev_internal_ops ccdc_v4l2_internal_ops = {
2335 .open = ccdc_init_formats,
2336};
2337
2338/* -----------------------------------------------------------------------------
2339 * Media entity operations
2340 */
2341
2342/*
2343 * ccdc_link_setup - Setup CCDC connections
2344 * @entity: CCDC media entity
2345 * @local: Pad at the local end of the link
2346 * @remote: Pad at the remote end of the link
2347 * @flags: Link flags
2348 *
2349 * return -EINVAL or zero on success
2350 */
2351static int ccdc_link_setup(struct media_entity *entity,
2352 const struct media_pad *local,
2353 const struct media_pad *remote, u32 flags)
2354{
2355 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2356 struct isp_ccdc_device *ccdc = v4l2_get_subdevdata(sd);
2357 struct isp_device *isp = to_isp_device(ccdc);
2358
2359 switch (local->index | media_entity_type(remote->entity)) {
2360 case CCDC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2361 /* Read from the sensor (parallel interface), CCP2, CSI2a or
2362 * CSI2c.
2363 */
2364 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
2365 ccdc->input = CCDC_INPUT_NONE;
2366 break;
2367 }
2368
2369 if (ccdc->input != CCDC_INPUT_NONE)
2370 return -EBUSY;
2371
2372 if (remote->entity == &isp->isp_ccp2.subdev.entity)
2373 ccdc->input = CCDC_INPUT_CCP2B;
2374 else if (remote->entity == &isp->isp_csi2a.subdev.entity)
2375 ccdc->input = CCDC_INPUT_CSI2A;
2376 else if (remote->entity == &isp->isp_csi2c.subdev.entity)
2377 ccdc->input = CCDC_INPUT_CSI2C;
2378 else
2379 ccdc->input = CCDC_INPUT_PARALLEL;
2380
2381 break;
2382
2383 /*
2384 * The ISP core doesn't support pipelines with multiple video outputs.
2385 * Revisit this when it will be implemented, and return -EBUSY for now.
2386 */
2387
2388 case CCDC_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
2389 /* Write to preview engine, histogram and H3A. When none of
2390 * those links are active, the video port can be disabled.
2391 */
2392 if (flags & MEDIA_LNK_FL_ENABLED) {
2393 if (ccdc->output & ~CCDC_OUTPUT_PREVIEW)
2394 return -EBUSY;
2395 ccdc->output |= CCDC_OUTPUT_PREVIEW;
2396 } else {
2397 ccdc->output &= ~CCDC_OUTPUT_PREVIEW;
2398 }
2399 break;
2400
2401 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_DEVNODE:
2402 /* Write to memory */
2403 if (flags & MEDIA_LNK_FL_ENABLED) {
2404 if (ccdc->output & ~CCDC_OUTPUT_MEMORY)
2405 return -EBUSY;
2406 ccdc->output |= CCDC_OUTPUT_MEMORY;
2407 } else {
2408 ccdc->output &= ~CCDC_OUTPUT_MEMORY;
2409 }
2410 break;
2411
2412 case CCDC_PAD_SOURCE_OF | MEDIA_ENT_T_V4L2_SUBDEV:
2413 /* Write to resizer */
2414 if (flags & MEDIA_LNK_FL_ENABLED) {
2415 if (ccdc->output & ~CCDC_OUTPUT_RESIZER)
2416 return -EBUSY;
2417 ccdc->output |= CCDC_OUTPUT_RESIZER;
2418 } else {
2419 ccdc->output &= ~CCDC_OUTPUT_RESIZER;
2420 }
2421 break;
2422
2423 default:
2424 return -EINVAL;
2425 }
2426
2427 return 0;
2428}
2429
2430/* media operations */
2431static const struct media_entity_operations ccdc_media_ops = {
2432 .link_setup = ccdc_link_setup,
a6d7a62d 2433 .link_validate = v4l2_subdev_link_validate,
de1135d4
LP		 2434};
2435
39099d09
LP		 2436void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc)
2437{
2438 v4l2_device_unregister_subdev(&ccdc->subdev);
2439 omap3isp_video_unregister(&ccdc->video_out);
2440}
2441
2442int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
2443 struct v4l2_device *vdev)
2444{
2445 int ret;
2446
2447 /* Register the subdev and video node. */
2448 ret = v4l2_device_register_subdev(vdev, &ccdc->subdev);
2449 if (ret < 0)
2450 goto error;
2451
2452 ret = omap3isp_video_register(&ccdc->video_out, vdev);
2453 if (ret < 0)
2454 goto error;
2455
2456 return 0;
2457
2458error:
2459 omap3isp_ccdc_unregister_entities(ccdc);
2460 return ret;
2461}
2462
2463/* -----------------------------------------------------------------------------
2464 * ISP CCDC initialisation and cleanup
2465 */
2466
de1135d4
LP		 2467/*
2468 * ccdc_init_entities - Initialize V4L2 subdev and media entity
2469 * @ccdc: ISP CCDC module
2470 *
2471 * Return 0 on success and a negative error code on failure.
2472 */
2473static int ccdc_init_entities(struct isp_ccdc_device *ccdc)
2474{
2475 struct v4l2_subdev *sd = &ccdc->subdev;
2476 struct media_pad *pads = ccdc->pads;
2477 struct media_entity *me = &sd->entity;
2478 int ret;
2479
2480 ccdc->input = CCDC_INPUT_NONE;
2481
2482 v4l2_subdev_init(sd, &ccdc_v4l2_ops);
2483 sd->internal_ops = &ccdc_v4l2_internal_ops;
2484 strlcpy(sd->name, "OMAP3 ISP CCDC", sizeof(sd->name));
2485 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2486 v4l2_set_subdevdata(sd, ccdc);
2487 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
de1135d4 2488
8dad936a
SA		 2489 pads[CCDC_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2490 | MEDIA_PAD_FL_MUST_CONNECT;
de1135d4
LP		 2491 pads[CCDC_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
2492 pads[CCDC_PAD_SOURCE_OF].flags = MEDIA_PAD_FL_SOURCE;
2493
2494 me->ops = &ccdc_media_ops;
2495 ret = media_entity_init(me, CCDC_PADS_NUM, pads, 0);
2496 if (ret < 0)
2497 return ret;
2498
2499 ccdc_init_formats(sd, NULL);
2500
2501 ccdc->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2502 ccdc->video_out.ops = &ccdc_video_ops;
2503 ccdc->video_out.isp = to_isp_device(ccdc);
2504 ccdc->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
2505 ccdc->video_out.bpl_alignment = 32;
2506
2507 ret = omap3isp_video_init(&ccdc->video_out, "CCDC");
2508 if (ret < 0)
9b6390bd 2509 goto error_video;
de1135d4
LP		 2510
2511 /* Connect the CCDC subdev to the video node. */
2512 ret = media_entity_create_link(&ccdc->subdev.entity, CCDC_PAD_SOURCE_OF,
2513 &ccdc->video_out.video.entity, 0, 0);
2514 if (ret < 0)
9b6390bd 2515 goto error_link;
de1135d4
LP		 2516
2517 return 0;
9b6390bd
LP		 2518
2519error_link:
2520 omap3isp_video_cleanup(&ccdc->video_out);
2521error_video:
2522 media_entity_cleanup(me);
2523 return ret;
de1135d4
LP		 2524}
2525
de1135d4
LP		 2526/*
2527 * omap3isp_ccdc_init - CCDC module initialization.
2528 * @dev: Device pointer specific to the OMAP3 ISP.
2529 *
2530 * TODO: Get the initialisation values from platform data.
2531 *
2532 * Return 0 on success or a negative error code otherwise.
2533 */
2534int omap3isp_ccdc_init(struct isp_device *isp)
2535{
2536 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
9b6390bd 2537 int ret;
de1135d4
LP		 2538
2539 spin_lock_init(&ccdc->lock);
2540 init_waitqueue_head(&ccdc->wait);
2541 mutex_init(&ccdc->ioctl_lock);
2542
2543 ccdc->stopping = CCDC_STOP_NOT_REQUESTED;
2544
2545 INIT_WORK(&ccdc->lsc.table_work, ccdc_lsc_free_table_work);
2546 ccdc->lsc.state = LSC_STATE_STOPPED;
2547 INIT_LIST_HEAD(&ccdc->lsc.free_queue);
2548 spin_lock_init(&ccdc->lsc.req_lock);
2549
de1135d4
LP		 2550 ccdc->clamp.oblen = 0;
2551 ccdc->clamp.dcsubval = 0;
2552
de1135d4
LP		 2553 ccdc->update = OMAP3ISP_CCDC_BLCLAMP;
2554 ccdc_apply_controls(ccdc);
2555
9b6390bd
LP		 2556 ret = ccdc_init_entities(ccdc);
2557 if (ret < 0) {
2558 mutex_destroy(&ccdc->ioctl_lock);
2559 return ret;
2560 }
2561
2562 return 0;
de1135d4
LP		 2563}
2564
2565/*
2566 * omap3isp_ccdc_cleanup - CCDC module cleanup.
2567 * @dev: Device pointer specific to the OMAP3 ISP.
2568 */
2569void omap3isp_ccdc_cleanup(struct isp_device *isp)
2570{
2571 struct isp_ccdc_device *ccdc = &isp->isp_ccdc;
2572
63b4ca23
LP		 2573 omap3isp_video_cleanup(&ccdc->video_out);
2574 media_entity_cleanup(&ccdc->subdev.entity);
2575
de1135d4
LP		 2576 /* Free LSC requests. As the CCDC is stopped there's no active request,
2577 * so only the pending request and the free queue need to be handled.
2578 */
2579 ccdc_lsc_free_request(ccdc, ccdc->lsc.request);
2580 cancel_work_sync(&ccdc->lsc.table_work);
2581 ccdc_lsc_free_queue(ccdc, &ccdc->lsc.free_queue);
2582
2583 if (ccdc->fpc.fpcaddr != 0)
fabdbca8 2584 omap_iommu_vfree(isp->domain, isp->dev, ccdc->fpc.fpcaddr);
ed33ac8e
LP		 2585
2586 mutex_destroy(&ccdc->ioctl_lock);
de1135d4 2587}
Linux kernel - Deliverables
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