Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
97d97422 | 2 | * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver |
5fd8f738 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5fd8f738 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published | |
9 | * by the Free Software Foundation, either version 2 of the License, | |
10 | * or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
5fd8f738 SN |
15 | #include <linux/types.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/platform_device.h> | |
e9e21083 | 21 | #include <linux/pm_runtime.h> |
5fd8f738 SN |
22 | #include <linux/list.h> |
23 | #include <linux/io.h> | |
e80cb1fa SN |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
5fd8f738 SN |
26 | #include <linux/slab.h> |
27 | #include <linux/clk.h> | |
28 | #include <media/v4l2-ioctl.h> | |
2dab38e2 SN |
29 | #include <media/videobuf2-core.h> |
30 | #include <media/videobuf2-dma-contig.h> | |
5fd8f738 SN |
31 | |
32 | #include "fimc-core.h" | |
c83a1ff0 | 33 | #include "fimc-reg.h" |
d3953223 | 34 | #include "fimc-mdevice.h" |
5fd8f738 | 35 | |
a25be18d | 36 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { |
ebdfea81 | 37 | "sclk_fimc", "fimc" |
a25be18d | 38 | }; |
5fd8f738 SN |
39 | |
40 | static struct fimc_fmt fimc_formats[] = { | |
41 | { | |
ef7af59b | 42 | .name = "RGB565", |
f83f71fd | 43 | .fourcc = V4L2_PIX_FMT_RGB565, |
ef7af59b | 44 | .depth = { 16 }, |
3d112d9a | 45 | .color = FIMC_FMT_RGB565, |
ef7af59b SN |
46 | .memplanes = 1, |
47 | .colplanes = 1, | |
ef7af59b | 48 | .flags = FMT_FLAGS_M2M, |
5fd8f738 | 49 | }, { |
ef7af59b SN |
50 | .name = "BGR666", |
51 | .fourcc = V4L2_PIX_FMT_BGR666, | |
52 | .depth = { 32 }, | |
3d112d9a | 53 | .color = FIMC_FMT_RGB666, |
ef7af59b SN |
54 | .memplanes = 1, |
55 | .colplanes = 1, | |
56 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 57 | }, { |
dafb9c70 | 58 | .name = "ARGB8888, 32 bpp", |
ef7af59b SN |
59 | .fourcc = V4L2_PIX_FMT_RGB32, |
60 | .depth = { 32 }, | |
3d112d9a | 61 | .color = FIMC_FMT_RGB888, |
ef7af59b SN |
62 | .memplanes = 1, |
63 | .colplanes = 1, | |
dafb9c70 SN |
64 | .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA, |
65 | }, { | |
66 | .name = "ARGB1555", | |
67 | .fourcc = V4L2_PIX_FMT_RGB555, | |
68 | .depth = { 16 }, | |
3d112d9a | 69 | .color = FIMC_FMT_RGB555, |
dafb9c70 SN |
70 | .memplanes = 1, |
71 | .colplanes = 1, | |
72 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
73 | }, { | |
74 | .name = "ARGB4444", | |
75 | .fourcc = V4L2_PIX_FMT_RGB444, | |
76 | .depth = { 16 }, | |
3d112d9a | 77 | .color = FIMC_FMT_RGB444, |
dafb9c70 SN |
78 | .memplanes = 1, |
79 | .colplanes = 1, | |
80 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
5fd8f738 | 81 | }, { |
ef7af59b SN |
82 | .name = "YUV 4:2:2 packed, YCbYCr", |
83 | .fourcc = V4L2_PIX_FMT_YUYV, | |
84 | .depth = { 16 }, | |
3d112d9a | 85 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
86 | .memplanes = 1, |
87 | .colplanes = 1, | |
88 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
89 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5f3cc447 | 90 | }, { |
ef7af59b SN |
91 | .name = "YUV 4:2:2 packed, CbYCrY", |
92 | .fourcc = V4L2_PIX_FMT_UYVY, | |
93 | .depth = { 16 }, | |
3d112d9a | 94 | .color = FIMC_FMT_CBYCRY422, |
ef7af59b SN |
95 | .memplanes = 1, |
96 | .colplanes = 1, | |
97 | .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, | |
98 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 99 | }, { |
ef7af59b SN |
100 | .name = "YUV 4:2:2 packed, CrYCbY", |
101 | .fourcc = V4L2_PIX_FMT_VYUY, | |
102 | .depth = { 16 }, | |
3d112d9a | 103 | .color = FIMC_FMT_CRYCBY422, |
ef7af59b SN |
104 | .memplanes = 1, |
105 | .colplanes = 1, | |
106 | .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, | |
107 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 108 | }, { |
ef7af59b SN |
109 | .name = "YUV 4:2:2 packed, YCrYCb", |
110 | .fourcc = V4L2_PIX_FMT_YVYU, | |
111 | .depth = { 16 }, | |
3d112d9a | 112 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
113 | .memplanes = 1, |
114 | .colplanes = 1, | |
115 | .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, | |
116 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 117 | }, { |
ef7af59b SN |
118 | .name = "YUV 4:2:2 planar, Y/Cb/Cr", |
119 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
120 | .depth = { 12 }, | |
3d112d9a | 121 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
122 | .memplanes = 1, |
123 | .colplanes = 3, | |
124 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 125 | }, { |
ef7af59b SN |
126 | .name = "YUV 4:2:2 planar, Y/CbCr", |
127 | .fourcc = V4L2_PIX_FMT_NV16, | |
128 | .depth = { 16 }, | |
3d112d9a | 129 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
130 | .memplanes = 1, |
131 | .colplanes = 2, | |
132 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 133 | }, { |
ef7af59b SN |
134 | .name = "YUV 4:2:2 planar, Y/CrCb", |
135 | .fourcc = V4L2_PIX_FMT_NV61, | |
136 | .depth = { 16 }, | |
3d112d9a | 137 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
138 | .memplanes = 1, |
139 | .colplanes = 2, | |
140 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 141 | }, { |
ef7af59b SN |
142 | .name = "YUV 4:2:0 planar, YCbCr", |
143 | .fourcc = V4L2_PIX_FMT_YUV420, | |
144 | .depth = { 12 }, | |
3d112d9a | 145 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
146 | .memplanes = 1, |
147 | .colplanes = 3, | |
148 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 149 | }, { |
ef7af59b SN |
150 | .name = "YUV 4:2:0 planar, Y/CbCr", |
151 | .fourcc = V4L2_PIX_FMT_NV12, | |
152 | .depth = { 12 }, | |
3d112d9a | 153 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
154 | .memplanes = 1, |
155 | .colplanes = 2, | |
156 | .flags = FMT_FLAGS_M2M, | |
157 | }, { | |
0a198bcd | 158 | .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr", |
ef7af59b | 159 | .fourcc = V4L2_PIX_FMT_NV12M, |
3d112d9a | 160 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
161 | .depth = { 8, 4 }, |
162 | .memplanes = 2, | |
163 | .colplanes = 2, | |
164 | .flags = FMT_FLAGS_M2M, | |
165 | }, { | |
0a198bcd | 166 | .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr", |
ef7af59b | 167 | .fourcc = V4L2_PIX_FMT_YUV420M, |
3d112d9a | 168 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
169 | .depth = { 8, 2, 2 }, |
170 | .memplanes = 3, | |
171 | .colplanes = 3, | |
172 | .flags = FMT_FLAGS_M2M, | |
173 | }, { | |
0a198bcd | 174 | .name = "YUV 4:2:0 non-contig. 2p, tiled", |
ef7af59b | 175 | .fourcc = V4L2_PIX_FMT_NV12MT, |
3d112d9a | 176 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
177 | .depth = { 8, 4 }, |
178 | .memplanes = 2, | |
179 | .colplanes = 2, | |
180 | .flags = FMT_FLAGS_M2M, | |
ee7160e5 SN |
181 | }, { |
182 | .name = "JPEG encoded data", | |
183 | .fourcc = V4L2_PIX_FMT_JPEG, | |
3d112d9a | 184 | .color = FIMC_FMT_JPEG, |
ee7160e5 SN |
185 | .depth = { 8 }, |
186 | .memplanes = 1, | |
187 | .colplanes = 1, | |
188 | .mbus_code = V4L2_MBUS_FMT_JPEG_1X8, | |
14783d25 SN |
189 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, |
190 | }, { | |
191 | .name = "S5C73MX interleaved UYVY/JPEG", | |
192 | .fourcc = V4L2_PIX_FMT_S5C_UYVY_JPG, | |
193 | .color = FIMC_FMT_YUYV_JPEG, | |
194 | .depth = { 8 }, | |
195 | .memplanes = 2, | |
196 | .colplanes = 1, | |
197 | .mdataplanes = 0x2, /* plane 1 holds frame meta data */ | |
198 | .mbus_code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
199 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, | |
5f3cc447 | 200 | }, |
548aafcd | 201 | }; |
5fd8f738 | 202 | |
bb7c276e | 203 | struct fimc_fmt *fimc_get_format(unsigned int index) |
dafb9c70 | 204 | { |
97d97422 SN |
205 | if (index >= ARRAY_SIZE(fimc_formats)) |
206 | return NULL; | |
207 | ||
208 | return &fimc_formats[index]; | |
dafb9c70 SN |
209 | } |
210 | ||
ee7160e5 SN |
211 | int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh, |
212 | int dw, int dh, int rotation) | |
5fd8f738 | 213 | { |
ee7160e5 SN |
214 | if (rotation == 90 || rotation == 270) |
215 | swap(dw, dh); | |
5fd8f738 | 216 | |
ee7160e5 SN |
217 | if (!ctx->scaler.enabled) |
218 | return (sw == dw && sh == dh) ? 0 : -EINVAL; | |
5fd8f738 | 219 | |
ee7160e5 | 220 | if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh)) |
1b09f292 HK |
221 | return -EINVAL; |
222 | ||
5fd8f738 SN |
223 | return 0; |
224 | } | |
225 | ||
226 | static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) | |
227 | { | |
548aafcd SN |
228 | u32 sh = 6; |
229 | ||
230 | if (src >= 64 * tar) | |
5fd8f738 | 231 | return -EINVAL; |
548aafcd SN |
232 | |
233 | while (sh--) { | |
234 | u32 tmp = 1 << sh; | |
235 | if (src >= tar * tmp) { | |
236 | *shift = sh, *ratio = tmp; | |
237 | return 0; | |
238 | } | |
5fd8f738 | 239 | } |
548aafcd | 240 | *shift = 0, *ratio = 1; |
5fd8f738 SN |
241 | return 0; |
242 | } | |
243 | ||
5f3cc447 | 244 | int fimc_set_scaler_info(struct fimc_ctx *ctx) |
5fd8f738 | 245 | { |
405f230c | 246 | const struct fimc_variant *variant = ctx->fimc_dev->variant; |
30c9939d | 247 | struct device *dev = &ctx->fimc_dev->pdev->dev; |
5fd8f738 SN |
248 | struct fimc_scaler *sc = &ctx->scaler; |
249 | struct fimc_frame *s_frame = &ctx->s_frame; | |
250 | struct fimc_frame *d_frame = &ctx->d_frame; | |
251 | int tx, ty, sx, sy; | |
252 | int ret; | |
253 | ||
47654df8 SN |
254 | if (ctx->rotation == 90 || ctx->rotation == 270) { |
255 | ty = d_frame->width; | |
256 | tx = d_frame->height; | |
257 | } else { | |
258 | tx = d_frame->width; | |
259 | ty = d_frame->height; | |
260 | } | |
5fd8f738 | 261 | if (tx <= 0 || ty <= 0) { |
969e877c | 262 | dev_err(dev, "Invalid target size: %dx%d\n", tx, ty); |
5fd8f738 SN |
263 | return -EINVAL; |
264 | } | |
265 | ||
266 | sx = s_frame->width; | |
267 | sy = s_frame->height; | |
268 | if (sx <= 0 || sy <= 0) { | |
969e877c | 269 | dev_err(dev, "Invalid source size: %dx%d\n", sx, sy); |
5fd8f738 SN |
270 | return -EINVAL; |
271 | } | |
5fd8f738 SN |
272 | sc->real_width = sx; |
273 | sc->real_height = sy; | |
5fd8f738 SN |
274 | |
275 | ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); | |
276 | if (ret) | |
277 | return ret; | |
278 | ||
279 | ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); | |
280 | if (ret) | |
281 | return ret; | |
282 | ||
283 | sc->pre_dst_width = sx / sc->pre_hratio; | |
284 | sc->pre_dst_height = sy / sc->pre_vratio; | |
285 | ||
b241c6d6 HK |
286 | if (variant->has_mainscaler_ext) { |
287 | sc->main_hratio = (sx << 14) / (tx << sc->hfactor); | |
288 | sc->main_vratio = (sy << 14) / (ty << sc->vfactor); | |
289 | } else { | |
290 | sc->main_hratio = (sx << 8) / (tx << sc->hfactor); | |
291 | sc->main_vratio = (sy << 8) / (ty << sc->vfactor); | |
292 | ||
293 | } | |
5fd8f738 SN |
294 | |
295 | sc->scaleup_h = (tx >= sx) ? 1 : 0; | |
296 | sc->scaleup_v = (ty >= sy) ? 1 : 0; | |
297 | ||
298 | /* check to see if input and output size/format differ */ | |
299 | if (s_frame->fmt->color == d_frame->fmt->color | |
300 | && s_frame->width == d_frame->width | |
301 | && s_frame->height == d_frame->height) | |
302 | sc->copy_mode = 1; | |
303 | else | |
304 | sc->copy_mode = 0; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
e9e21083 | 309 | static irqreturn_t fimc_irq_handler(int irq, void *priv) |
5fd8f738 | 310 | { |
548aafcd | 311 | struct fimc_dev *fimc = priv; |
4ecbf5d1 | 312 | struct fimc_ctx *ctx; |
5fd8f738 | 313 | |
5fd8f738 SN |
314 | fimc_hw_clear_irq(fimc); |
315 | ||
e9e21083 SN |
316 | spin_lock(&fimc->slock); |
317 | ||
4ecbf5d1 | 318 | if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) { |
e9e21083 SN |
319 | if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) { |
320 | set_bit(ST_M2M_SUSPENDED, &fimc->state); | |
321 | wake_up(&fimc->irq_queue); | |
322 | goto out; | |
323 | } | |
4ecbf5d1 SN |
324 | ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev); |
325 | if (ctx != NULL) { | |
e9e21083 | 326 | spin_unlock(&fimc->slock); |
4ecbf5d1 | 327 | fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE); |
5fd8f738 | 328 | |
4ecbf5d1 SN |
329 | if (ctx->state & FIMC_CTX_SHUT) { |
330 | ctx->state &= ~FIMC_CTX_SHUT; | |
331 | wake_up(&fimc->irq_queue); | |
332 | } | |
efb13c3d | 333 | return IRQ_HANDLED; |
5fd8f738 | 334 | } |
ee7160e5 | 335 | } else if (test_bit(ST_CAPT_PEND, &fimc->state)) { |
97d97422 SN |
336 | int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) && |
337 | fimc->vid_cap.reqbufs_count == 1; | |
338 | fimc_capture_irq_handler(fimc, !last_buf); | |
5fd8f738 | 339 | } |
e9e21083 | 340 | out: |
5fd8f738 SN |
341 | spin_unlock(&fimc->slock); |
342 | return IRQ_HANDLED; | |
343 | } | |
344 | ||
ef7af59b | 345 | /* The color format (colplanes, memplanes) must be already configured. */ |
2dab38e2 | 346 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
548aafcd | 347 | struct fimc_frame *frame, struct fimc_addr *paddr) |
5fd8f738 | 348 | { |
5fd8f738 | 349 | int ret = 0; |
548aafcd | 350 | u32 pix_size; |
5fd8f738 | 351 | |
2dab38e2 | 352 | if (vb == NULL || frame == NULL) |
5fd8f738 SN |
353 | return -EINVAL; |
354 | ||
355 | pix_size = frame->width * frame->height; | |
356 | ||
ef7af59b SN |
357 | dbg("memplanes= %d, colplanes= %d, pix_size= %d", |
358 | frame->fmt->memplanes, frame->fmt->colplanes, pix_size); | |
359 | ||
ba7fcb0c | 360 | paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0); |
5fd8f738 | 361 | |
ef7af59b SN |
362 | if (frame->fmt->memplanes == 1) { |
363 | switch (frame->fmt->colplanes) { | |
5fd8f738 SN |
364 | case 1: |
365 | paddr->cb = 0; | |
366 | paddr->cr = 0; | |
367 | break; | |
368 | case 2: | |
369 | /* decompose Y into Y/Cb */ | |
370 | paddr->cb = (u32)(paddr->y + pix_size); | |
371 | paddr->cr = 0; | |
372 | break; | |
373 | case 3: | |
374 | paddr->cb = (u32)(paddr->y + pix_size); | |
375 | /* decompose Y into Y/Cb/Cr */ | |
3d112d9a | 376 | if (FIMC_FMT_YCBCR420 == frame->fmt->color) |
5fd8f738 SN |
377 | paddr->cr = (u32)(paddr->cb |
378 | + (pix_size >> 2)); | |
379 | else /* 422 */ | |
380 | paddr->cr = (u32)(paddr->cb | |
381 | + (pix_size >> 1)); | |
382 | break; | |
383 | default: | |
384 | return -EINVAL; | |
385 | } | |
14783d25 | 386 | } else if (!frame->fmt->mdataplanes) { |
ef7af59b | 387 | if (frame->fmt->memplanes >= 2) |
ba7fcb0c | 388 | paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1); |
ef7af59b SN |
389 | |
390 | if (frame->fmt->memplanes == 3) | |
ba7fcb0c | 391 | paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2); |
5fd8f738 SN |
392 | } |
393 | ||
548aafcd SN |
394 | dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d", |
395 | paddr->y, paddr->cb, paddr->cr, ret); | |
5fd8f738 SN |
396 | |
397 | return ret; | |
398 | } | |
399 | ||
400 | /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */ | |
9e803a04 | 401 | void fimc_set_yuv_order(struct fimc_ctx *ctx) |
5fd8f738 SN |
402 | { |
403 | /* The one only mode supported in SoC. */ | |
c83a1ff0 SN |
404 | ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
405 | ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; | |
5fd8f738 SN |
406 | |
407 | /* Set order for 1 plane input formats. */ | |
408 | switch (ctx->s_frame.fmt->color) { | |
3d112d9a | 409 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 410 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; |
5fd8f738 | 411 | break; |
3d112d9a | 412 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 413 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; |
5fd8f738 | 414 | break; |
3d112d9a | 415 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 416 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; |
5fd8f738 | 417 | break; |
3d112d9a | 418 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 419 | default: |
c83a1ff0 | 420 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
421 | break; |
422 | } | |
423 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); | |
424 | ||
425 | switch (ctx->d_frame.fmt->color) { | |
3d112d9a | 426 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 427 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; |
5fd8f738 | 428 | break; |
3d112d9a | 429 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 430 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; |
5fd8f738 | 431 | break; |
3d112d9a | 432 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 433 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; |
5fd8f738 | 434 | break; |
3d112d9a | 435 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 436 | default: |
c83a1ff0 | 437 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
438 | break; |
439 | } | |
440 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); | |
441 | } | |
442 | ||
9e803a04 | 443 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f) |
ddc79e0f | 444 | { |
e80cb1fa | 445 | bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff; |
ef7af59b SN |
446 | u32 i, depth = 0; |
447 | ||
448 | for (i = 0; i < f->fmt->colplanes; i++) | |
449 | depth += f->fmt->depth[i]; | |
ddc79e0f SN |
450 | |
451 | f->dma_offset.y_h = f->offs_h; | |
e80cb1fa | 452 | if (!pix_hoff) |
ef7af59b | 453 | f->dma_offset.y_h *= (depth >> 3); |
ddc79e0f SN |
454 | |
455 | f->dma_offset.y_v = f->offs_v; | |
456 | ||
457 | f->dma_offset.cb_h = f->offs_h; | |
458 | f->dma_offset.cb_v = f->offs_v; | |
459 | ||
460 | f->dma_offset.cr_h = f->offs_h; | |
461 | f->dma_offset.cr_v = f->offs_v; | |
462 | ||
e80cb1fa | 463 | if (!pix_hoff) { |
ef7af59b | 464 | if (f->fmt->colplanes == 3) { |
ddc79e0f SN |
465 | f->dma_offset.cb_h >>= 1; |
466 | f->dma_offset.cr_h >>= 1; | |
467 | } | |
3d112d9a | 468 | if (f->fmt->color == FIMC_FMT_YCBCR420) { |
ddc79e0f SN |
469 | f->dma_offset.cb_v >>= 1; |
470 | f->dma_offset.cr_v >>= 1; | |
471 | } | |
472 | } | |
473 | ||
474 | dbg("in_offset: color= %d, y_h= %d, y_v= %d", | |
475 | f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v); | |
476 | } | |
477 | ||
7e566be2 | 478 | static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx) |
9448ab7d SN |
479 | { |
480 | struct fimc_effect *effect = &ctx->effect; | |
481 | ||
482 | switch (colorfx) { | |
483 | case V4L2_COLORFX_NONE: | |
484 | effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS; | |
485 | break; | |
486 | case V4L2_COLORFX_BW: | |
487 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
488 | effect->pat_cb = 128; | |
489 | effect->pat_cr = 128; | |
490 | break; | |
491 | case V4L2_COLORFX_SEPIA: | |
492 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
493 | effect->pat_cb = 115; | |
494 | effect->pat_cr = 145; | |
495 | break; | |
496 | case V4L2_COLORFX_NEGATIVE: | |
497 | effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE; | |
498 | break; | |
499 | case V4L2_COLORFX_EMBOSS: | |
500 | effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING; | |
501 | break; | |
502 | case V4L2_COLORFX_ART_FREEZE: | |
503 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE; | |
504 | break; | |
505 | case V4L2_COLORFX_SILHOUETTE: | |
506 | effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE; | |
507 | break; | |
508 | case V4L2_COLORFX_SET_CBCR: | |
509 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
510 | effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8; | |
511 | effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff; | |
512 | break; | |
513 | default: | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
131b6c61 SN |
520 | /* |
521 | * V4L2 controls handling | |
522 | */ | |
523 | #define ctrl_to_ctx(__ctrl) \ | |
9448ab7d | 524 | container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler) |
131b6c61 | 525 | |
dafb9c70 | 526 | static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl) |
131b6c61 | 527 | { |
131b6c61 | 528 | struct fimc_dev *fimc = ctx->fimc_dev; |
405f230c | 529 | const struct fimc_variant *variant = fimc->variant; |
131b6c61 SN |
530 | int ret = 0; |
531 | ||
532 | if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) | |
533 | return 0; | |
534 | ||
535 | switch (ctrl->id) { | |
536 | case V4L2_CID_HFLIP: | |
131b6c61 SN |
537 | ctx->hflip = ctrl->val; |
538 | break; | |
539 | ||
540 | case V4L2_CID_VFLIP: | |
131b6c61 SN |
541 | ctx->vflip = ctrl->val; |
542 | break; | |
543 | ||
544 | case V4L2_CID_ROTATE: | |
81619ce1 | 545 | if (fimc_capture_pending(fimc)) { |
ee7160e5 | 546 | ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width, |
131b6c61 SN |
547 | ctx->s_frame.height, ctx->d_frame.width, |
548 | ctx->d_frame.height, ctrl->val); | |
dafb9c70 SN |
549 | if (ret) |
550 | return -EINVAL; | |
131b6c61 SN |
551 | } |
552 | if ((ctrl->val == 90 || ctrl->val == 270) && | |
553 | !variant->has_out_rot) | |
554 | return -EINVAL; | |
dafb9c70 | 555 | |
131b6c61 SN |
556 | ctx->rotation = ctrl->val; |
557 | break; | |
558 | ||
dafb9c70 SN |
559 | case V4L2_CID_ALPHA_COMPONENT: |
560 | ctx->d_frame.alpha = ctrl->val; | |
561 | break; | |
9448ab7d SN |
562 | |
563 | case V4L2_CID_COLORFX: | |
564 | ret = fimc_set_color_effect(ctx, ctrl->val); | |
565 | if (ret) | |
566 | return ret; | |
567 | break; | |
131b6c61 | 568 | } |
9448ab7d | 569 | |
131b6c61 SN |
570 | ctx->state |= FIMC_PARAMS; |
571 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
131b6c61 SN |
572 | return 0; |
573 | } | |
574 | ||
dafb9c70 SN |
575 | static int fimc_s_ctrl(struct v4l2_ctrl *ctrl) |
576 | { | |
577 | struct fimc_ctx *ctx = ctrl_to_ctx(ctrl); | |
578 | unsigned long flags; | |
579 | int ret; | |
580 | ||
efb13c3d | 581 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
dafb9c70 | 582 | ret = __fimc_s_ctrl(ctx, ctrl); |
efb13c3d | 583 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
dafb9c70 SN |
584 | |
585 | return ret; | |
586 | } | |
587 | ||
131b6c61 SN |
588 | static const struct v4l2_ctrl_ops fimc_ctrl_ops = { |
589 | .s_ctrl = fimc_s_ctrl, | |
590 | }; | |
591 | ||
592 | int fimc_ctrls_create(struct fimc_ctx *ctx) | |
593 | { | |
dafb9c70 | 594 | unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt); |
9448ab7d SN |
595 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
596 | struct v4l2_ctrl_handler *handler = &ctrls->handler; | |
dafb9c70 | 597 | |
9448ab7d | 598 | if (ctx->ctrls.ready) |
131b6c61 | 599 | return 0; |
131b6c61 | 600 | |
9448ab7d SN |
601 | v4l2_ctrl_handler_init(handler, 6); |
602 | ||
603 | ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
53e5ab94 | 604 | V4L2_CID_ROTATE, 0, 270, 90, 0); |
9448ab7d | 605 | ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 606 | V4L2_CID_HFLIP, 0, 1, 1, 0); |
9448ab7d | 607 | ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 608 | V4L2_CID_VFLIP, 0, 1, 1, 0); |
9448ab7d | 609 | |
e80cb1fa | 610 | if (ctx->fimc_dev->drv_data->alpha_color) |
9448ab7d SN |
611 | ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
612 | V4L2_CID_ALPHA_COMPONENT, | |
613 | 0, max_alpha, 1, 0); | |
dafb9c70 | 614 | else |
9448ab7d SN |
615 | ctrls->alpha = NULL; |
616 | ||
617 | ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops, | |
618 | V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, | |
619 | ~0x983f, V4L2_COLORFX_NONE); | |
620 | ||
621 | ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
622 | V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); | |
dafb9c70 | 623 | |
9448ab7d | 624 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 | 625 | |
9448ab7d | 626 | if (!handler->error) { |
4c4ed226 | 627 | v4l2_ctrl_cluster(2, &ctrls->colorfx); |
9448ab7d SN |
628 | ctrls->ready = true; |
629 | } | |
630 | ||
631 | return handler->error; | |
131b6c61 SN |
632 | } |
633 | ||
634 | void fimc_ctrls_delete(struct fimc_ctx *ctx) | |
635 | { | |
9448ab7d SN |
636 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
637 | ||
638 | if (ctrls->ready) { | |
639 | v4l2_ctrl_handler_free(&ctrls->handler); | |
640 | ctrls->ready = false; | |
641 | ctrls->alpha = NULL; | |
131b6c61 SN |
642 | } |
643 | } | |
644 | ||
645 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active) | |
646 | { | |
dafb9c70 | 647 | unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA; |
9448ab7d | 648 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
dafb9c70 | 649 | |
9448ab7d | 650 | if (!ctrls->ready) |
131b6c61 SN |
651 | return; |
652 | ||
8183e7a7 | 653 | mutex_lock(ctrls->handler.lock); |
9448ab7d SN |
654 | v4l2_ctrl_activate(ctrls->rotate, active); |
655 | v4l2_ctrl_activate(ctrls->hflip, active); | |
656 | v4l2_ctrl_activate(ctrls->vflip, active); | |
657 | v4l2_ctrl_activate(ctrls->colorfx, active); | |
658 | if (ctrls->alpha) | |
659 | v4l2_ctrl_activate(ctrls->alpha, active && has_alpha); | |
131b6c61 SN |
660 | |
661 | if (active) { | |
9448ab7d SN |
662 | fimc_set_color_effect(ctx, ctrls->colorfx->cur.val); |
663 | ctx->rotation = ctrls->rotate->val; | |
664 | ctx->hflip = ctrls->hflip->val; | |
665 | ctx->vflip = ctrls->vflip->val; | |
131b6c61 | 666 | } else { |
9448ab7d | 667 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 SN |
668 | ctx->rotation = 0; |
669 | ctx->hflip = 0; | |
670 | ctx->vflip = 0; | |
671 | } | |
8183e7a7 | 672 | mutex_unlock(ctrls->handler.lock); |
131b6c61 SN |
673 | } |
674 | ||
dafb9c70 SN |
675 | /* Update maximum value of the alpha color control */ |
676 | void fimc_alpha_ctrl_update(struct fimc_ctx *ctx) | |
677 | { | |
678 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9448ab7d | 679 | struct v4l2_ctrl *ctrl = ctx->ctrls.alpha; |
dafb9c70 | 680 | |
e80cb1fa | 681 | if (ctrl == NULL || !fimc->drv_data->alpha_color) |
dafb9c70 SN |
682 | return; |
683 | ||
684 | v4l2_ctrl_lock(ctrl); | |
685 | ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt); | |
686 | ||
687 | if (ctrl->cur.val > ctrl->maximum) | |
688 | ctrl->cur.val = ctrl->maximum; | |
689 | ||
690 | v4l2_ctrl_unlock(ctrl); | |
691 | } | |
692 | ||
fa8880be | 693 | void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f) |
5fd8f738 | 694 | { |
e578588e | 695 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; |
91707b8b | 696 | int i; |
5fd8f738 | 697 | |
e578588e SN |
698 | pixm->width = frame->o_width; |
699 | pixm->height = frame->o_height; | |
700 | pixm->field = V4L2_FIELD_NONE; | |
701 | pixm->pixelformat = frame->fmt->fourcc; | |
702 | pixm->colorspace = V4L2_COLORSPACE_JPEG; | |
703 | pixm->num_planes = frame->fmt->memplanes; | |
91707b8b SN |
704 | |
705 | for (i = 0; i < pixm->num_planes; ++i) { | |
fa8880be SN |
706 | pixm->plane_fmt[i].bytesperline = frame->bytesperline[i]; |
707 | pixm->plane_fmt[i].sizeimage = frame->payload[i]; | |
91707b8b | 708 | } |
5fd8f738 SN |
709 | } |
710 | ||
4db5e27e SN |
711 | /** |
712 | * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane | |
713 | * @fmt: fimc pixel format description (input) | |
714 | * @width: requested pixel width | |
715 | * @height: requested pixel height | |
716 | * @pix: multi-plane format to adjust | |
717 | */ | |
718 | void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height, | |
719 | struct v4l2_pix_format_mplane *pix) | |
720 | { | |
721 | u32 bytesperline = 0; | |
722 | int i; | |
723 | ||
724 | pix->colorspace = V4L2_COLORSPACE_JPEG; | |
725 | pix->field = V4L2_FIELD_NONE; | |
726 | pix->num_planes = fmt->memplanes; | |
dafb9c70 | 727 | pix->pixelformat = fmt->fourcc; |
4db5e27e SN |
728 | pix->height = height; |
729 | pix->width = width; | |
730 | ||
731 | for (i = 0; i < pix->num_planes; ++i) { | |
d547ab66 SN |
732 | struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i]; |
733 | u32 bpl = plane_fmt->bytesperline; | |
4db5e27e SN |
734 | |
735 | if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width)) | |
736 | bpl = pix->width; /* Planar */ | |
737 | ||
738 | if (fmt->colplanes == 1 && /* Packed */ | |
739 | (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width)) | |
740 | bpl = (pix->width * fmt->depth[0]) / 8; | |
fa8880be SN |
741 | /* |
742 | * Currently bytesperline for each plane is same, except | |
743 | * V4L2_PIX_FMT_YUV420M format. This calculation may need | |
744 | * to be changed when other multi-planar formats are added | |
745 | * to the fimc_formats[] array. | |
746 | */ | |
747 | if (i == 0) | |
4db5e27e | 748 | bytesperline = bpl; |
fa8880be SN |
749 | else if (i == 1 && fmt->memplanes == 3) |
750 | bytesperline /= 2; | |
4db5e27e | 751 | |
d547ab66 SN |
752 | plane_fmt->bytesperline = bytesperline; |
753 | plane_fmt->sizeimage = max((pix->width * pix->height * | |
754 | fmt->depth[i]) / 8, plane_fmt->sizeimage); | |
4db5e27e SN |
755 | } |
756 | } | |
757 | ||
cf52df8a SN |
758 | /** |
759 | * fimc_find_format - lookup fimc color format by fourcc or media bus format | |
760 | * @pixelformat: fourcc to match, ignored if null | |
761 | * @mbus_code: media bus code to match, ignored if null | |
762 | * @mask: the color flags to match | |
763 | * @index: offset in the fimc_formats array, ignored if negative | |
764 | */ | |
63746be5 | 765 | struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code, |
cf52df8a | 766 | unsigned int mask, int index) |
5fd8f738 | 767 | { |
cf52df8a | 768 | struct fimc_fmt *fmt, *def_fmt = NULL; |
5fd8f738 | 769 | unsigned int i; |
cf52df8a | 770 | int id = 0; |
5fd8f738 | 771 | |
63746be5 | 772 | if (index >= (int)ARRAY_SIZE(fimc_formats)) |
cf52df8a | 773 | return NULL; |
5f3cc447 SN |
774 | |
775 | for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) { | |
776 | fmt = &fimc_formats[i]; | |
cf52df8a SN |
777 | if (!(fmt->flags & mask)) |
778 | continue; | |
779 | if (pixelformat && fmt->fourcc == *pixelformat) | |
780 | return fmt; | |
781 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
782 | return fmt; | |
783 | if (index == id) | |
784 | def_fmt = fmt; | |
785 | id++; | |
5f3cc447 | 786 | } |
cf52df8a | 787 | return def_fmt; |
5f3cc447 SN |
788 | } |
789 | ||
e9e21083 | 790 | static void fimc_clk_put(struct fimc_dev *fimc) |
5fd8f738 SN |
791 | { |
792 | int i; | |
6ec0163b | 793 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
b71b56b2 | 794 | if (IS_ERR(fimc->clock[i])) |
bd7d8888 SN |
795 | continue; |
796 | clk_unprepare(fimc->clock[i]); | |
797 | clk_put(fimc->clock[i]); | |
b71b56b2 | 798 | fimc->clock[i] = ERR_PTR(-EINVAL); |
5fd8f738 SN |
799 | } |
800 | } | |
801 | ||
802 | static int fimc_clk_get(struct fimc_dev *fimc) | |
803 | { | |
bd7d8888 SN |
804 | int i, ret; |
805 | ||
b71b56b2 SN |
806 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) |
807 | fimc->clock[i] = ERR_PTR(-EINVAL); | |
808 | ||
6ec0163b | 809 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
a25be18d | 810 | fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]); |
b71b56b2 SN |
811 | if (IS_ERR(fimc->clock[i])) { |
812 | ret = PTR_ERR(fimc->clock[i]); | |
bd7d8888 | 813 | goto err; |
b71b56b2 | 814 | } |
bd7d8888 SN |
815 | ret = clk_prepare(fimc->clock[i]); |
816 | if (ret < 0) { | |
817 | clk_put(fimc->clock[i]); | |
b71b56b2 | 818 | fimc->clock[i] = ERR_PTR(-EINVAL); |
bd7d8888 SN |
819 | goto err; |
820 | } | |
5fd8f738 | 821 | } |
e9e21083 | 822 | return 0; |
bd7d8888 SN |
823 | err: |
824 | fimc_clk_put(fimc); | |
825 | dev_err(&fimc->pdev->dev, "failed to get clock: %s\n", | |
826 | fimc_clocks[i]); | |
827 | return -ENXIO; | |
e9e21083 SN |
828 | } |
829 | ||
830 | static int fimc_m2m_suspend(struct fimc_dev *fimc) | |
831 | { | |
832 | unsigned long flags; | |
833 | int timeout; | |
834 | ||
835 | spin_lock_irqsave(&fimc->slock, flags); | |
836 | if (!fimc_m2m_pending(fimc)) { | |
837 | spin_unlock_irqrestore(&fimc->slock, flags); | |
838 | return 0; | |
839 | } | |
840 | clear_bit(ST_M2M_SUSPENDED, &fimc->state); | |
841 | set_bit(ST_M2M_SUSPENDING, &fimc->state); | |
842 | spin_unlock_irqrestore(&fimc->slock, flags); | |
843 | ||
844 | timeout = wait_event_timeout(fimc->irq_queue, | |
845 | test_bit(ST_M2M_SUSPENDED, &fimc->state), | |
846 | FIMC_SHUTDOWN_TIMEOUT); | |
847 | ||
848 | clear_bit(ST_M2M_SUSPENDING, &fimc->state); | |
849 | return timeout == 0 ? -EAGAIN : 0; | |
850 | } | |
851 | ||
852 | static int fimc_m2m_resume(struct fimc_dev *fimc) | |
853 | { | |
854 | unsigned long flags; | |
855 | ||
856 | spin_lock_irqsave(&fimc->slock, flags); | |
857 | /* Clear for full H/W setup in first run after resume */ | |
858 | fimc->m2m.ctx = NULL; | |
859 | spin_unlock_irqrestore(&fimc->slock, flags); | |
860 | ||
861 | if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state)) | |
862 | fimc_m2m_job_finish(fimc->m2m.ctx, | |
863 | VB2_BUF_STATE_ERROR); | |
5fd8f738 SN |
864 | return 0; |
865 | } | |
866 | ||
e80cb1fa SN |
867 | static const struct of_device_id fimc_of_match[]; |
868 | ||
869 | static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq) | |
870 | { | |
871 | struct device *dev = &fimc->pdev->dev; | |
872 | struct device_node *node = dev->of_node; | |
873 | const struct of_device_id *of_id; | |
874 | struct fimc_variant *v; | |
875 | struct fimc_pix_limit *lim; | |
876 | u32 args[FIMC_PIX_LIMITS_MAX]; | |
877 | int ret; | |
878 | ||
879 | if (of_property_read_bool(node, "samsung,lcd-wb")) | |
880 | return -ENODEV; | |
881 | ||
882 | v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL); | |
883 | if (!v) | |
884 | return -ENOMEM; | |
885 | ||
886 | of_id = of_match_node(fimc_of_match, node); | |
887 | if (!of_id) | |
888 | return -EINVAL; | |
889 | fimc->drv_data = of_id->data; | |
890 | ret = of_property_read_u32_array(node, "samsung,pix-limits", | |
891 | args, FIMC_PIX_LIMITS_MAX); | |
892 | if (ret < 0) | |
893 | return ret; | |
894 | ||
895 | lim = (struct fimc_pix_limit *)&v[1]; | |
896 | ||
897 | lim->scaler_en_w = args[0]; | |
898 | lim->scaler_dis_w = args[1]; | |
899 | lim->out_rot_en_w = args[2]; | |
900 | lim->out_rot_dis_w = args[3]; | |
901 | v->pix_limit = lim; | |
902 | ||
903 | ret = of_property_read_u32_array(node, "samsung,min-pix-sizes", | |
904 | args, 2); | |
905 | v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0]; | |
906 | v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1]; | |
907 | ret = of_property_read_u32_array(node, "samsung,min-pix-alignment", | |
908 | args, 2); | |
909 | v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0]; | |
910 | v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1]; | |
911 | ||
912 | ret = of_property_read_u32(node, "samsung,rotators", &args[1]); | |
913 | v->has_inp_rot = ret ? 1 : args[1] & 0x01; | |
914 | v->has_out_rot = ret ? 1 : args[1] & 0x10; | |
915 | v->has_mainscaler_ext = of_property_read_bool(node, | |
916 | "samsung,mainscaler-ext"); | |
917 | ||
918 | v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb"); | |
919 | v->has_cam_if = of_property_read_bool(node, "samsung,cam-if"); | |
920 | of_property_read_u32(node, "clock-frequency", clk_freq); | |
921 | fimc->id = of_alias_get_id(node, "fimc"); | |
922 | ||
923 | fimc->variant = v; | |
924 | return 0; | |
925 | } | |
926 | ||
5fd8f738 SN |
927 | static int fimc_probe(struct platform_device *pdev) |
928 | { | |
e80cb1fa SN |
929 | struct device *dev = &pdev->dev; |
930 | u32 lclk_freq = 0; | |
5fd8f738 SN |
931 | struct fimc_dev *fimc; |
932 | struct resource *res; | |
5fd8f738 SN |
933 | int ret = 0; |
934 | ||
e80cb1fa | 935 | fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL); |
5fd8f738 SN |
936 | if (!fimc) |
937 | return -ENOMEM; | |
938 | ||
5fd8f738 | 939 | fimc->pdev = pdev; |
e80cb1fa SN |
940 | |
941 | if (dev->of_node) { | |
942 | ret = fimc_parse_dt(fimc, &lclk_freq); | |
943 | if (ret < 0) | |
944 | return ret; | |
945 | } else { | |
946 | fimc->drv_data = fimc_get_drvdata(pdev); | |
947 | fimc->id = pdev->id; | |
948 | } | |
949 | if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities || | |
950 | fimc->id < 0) { | |
951 | dev_err(dev, "Invalid driver data or device id (%d/%d)\n", | |
952 | fimc->id, fimc->drv_data->num_entities); | |
953 | return -EINVAL; | |
954 | } | |
955 | if (!dev->of_node) | |
956 | fimc->variant = fimc->drv_data->variant[fimc->id]; | |
e9e21083 | 957 | |
5f3cc447 | 958 | init_waitqueue_head(&fimc->irq_queue); |
5fd8f738 | 959 | spin_lock_init(&fimc->slock); |
5fd8f738 SN |
960 | mutex_init(&fimc->lock); |
961 | ||
962 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
e80cb1fa | 963 | fimc->regs = devm_ioremap_resource(dev, res); |
f23999ec TR |
964 | if (IS_ERR(fimc->regs)) |
965 | return PTR_ERR(fimc->regs); | |
5fd8f738 | 966 | |
5fd8f738 | 967 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
6d91a51a | 968 | if (res == NULL) { |
e80cb1fa | 969 | dev_err(dev, "Failed to get IRQ resource\n"); |
6d91a51a | 970 | return -ENXIO; |
5fd8f738 | 971 | } |
5fd8f738 | 972 | |
e9e21083 SN |
973 | ret = fimc_clk_get(fimc); |
974 | if (ret) | |
6d91a51a | 975 | return ret; |
b71b56b2 | 976 | |
e80cb1fa SN |
977 | if (lclk_freq == 0) |
978 | lclk_freq = fimc->drv_data->lclk_frequency; | |
979 | ||
980 | ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq); | |
b71b56b2 SN |
981 | if (ret < 0) |
982 | return ret; | |
983 | ||
984 | ret = clk_enable(fimc->clock[CLK_BUS]); | |
985 | if (ret < 0) | |
986 | return ret; | |
e9e21083 | 987 | |
e80cb1fa SN |
988 | ret = devm_request_irq(dev, res->start, fimc_irq_handler, |
989 | 0, dev_name(dev), fimc); | |
5fd8f738 | 990 | if (ret) { |
e80cb1fa | 991 | dev_err(dev, "failed to install irq (%d)\n", ret); |
5fd8f738 SN |
992 | goto err_clk; |
993 | } | |
994 | ||
693f5c40 SN |
995 | ret = fimc_initialize_capture_subdev(fimc); |
996 | if (ret) | |
997 | goto err_clk; | |
998 | ||
999 | platform_set_drvdata(pdev, fimc); | |
e80cb1fa SN |
1000 | pm_runtime_enable(dev); |
1001 | ret = pm_runtime_get_sync(dev); | |
e9e21083 | 1002 | if (ret < 0) |
693f5c40 | 1003 | goto err_sd; |
2dab38e2 | 1004 | /* Initialize contiguous memory allocator */ |
e80cb1fa | 1005 | fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev); |
2dab38e2 SN |
1006 | if (IS_ERR(fimc->alloc_ctx)) { |
1007 | ret = PTR_ERR(fimc->alloc_ctx); | |
e9e21083 | 1008 | goto err_pm; |
2dab38e2 SN |
1009 | } |
1010 | ||
e80cb1fa | 1011 | dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id); |
5fd8f738 | 1012 | |
e80cb1fa | 1013 | pm_runtime_put(dev); |
5fd8f738 | 1014 | return 0; |
e9e21083 | 1015 | err_pm: |
e80cb1fa | 1016 | pm_runtime_put(dev); |
693f5c40 SN |
1017 | err_sd: |
1018 | fimc_unregister_capture_subdev(fimc); | |
5fd8f738 | 1019 | err_clk: |
b71b56b2 | 1020 | clk_disable(fimc->clock[CLK_BUS]); |
e9e21083 | 1021 | fimc_clk_put(fimc); |
5fd8f738 SN |
1022 | return ret; |
1023 | } | |
1024 | ||
e9e21083 | 1025 | static int fimc_runtime_resume(struct device *dev) |
5fd8f738 | 1026 | { |
e9e21083 | 1027 | struct fimc_dev *fimc = dev_get_drvdata(dev); |
5fd8f738 | 1028 | |
e9e21083 SN |
1029 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); |
1030 | ||
1031 | /* Enable clocks and perform basic initalization */ | |
1032 | clk_enable(fimc->clock[CLK_GATE]); | |
5fd8f738 | 1033 | fimc_hw_reset(fimc); |
e9e21083 SN |
1034 | |
1035 | /* Resume the capture or mem-to-mem device */ | |
1036 | if (fimc_capture_busy(fimc)) | |
1037 | return fimc_capture_resume(fimc); | |
f664684a SN |
1038 | |
1039 | return fimc_m2m_resume(fimc); | |
e9e21083 SN |
1040 | } |
1041 | ||
1042 | static int fimc_runtime_suspend(struct device *dev) | |
1043 | { | |
1044 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1045 | int ret = 0; | |
1046 | ||
1047 | if (fimc_capture_busy(fimc)) | |
1048 | ret = fimc_capture_suspend(fimc); | |
1049 | else | |
1050 | ret = fimc_m2m_suspend(fimc); | |
1051 | if (!ret) | |
1052 | clk_disable(fimc->clock[CLK_GATE]); | |
1053 | ||
1054 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | #ifdef CONFIG_PM_SLEEP | |
1059 | static int fimc_resume(struct device *dev) | |
1060 | { | |
1061 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1062 | unsigned long flags; | |
1063 | ||
1064 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1065 | ||
1066 | /* Do not resume if the device was idle before system suspend */ | |
1067 | spin_lock_irqsave(&fimc->slock, flags); | |
1068 | if (!test_and_clear_bit(ST_LPM, &fimc->state) || | |
1069 | (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) { | |
1070 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1071 | return 0; | |
1072 | } | |
1073 | fimc_hw_reset(fimc); | |
e9e21083 SN |
1074 | spin_unlock_irqrestore(&fimc->slock, flags); |
1075 | ||
1076 | if (fimc_capture_busy(fimc)) | |
1077 | return fimc_capture_resume(fimc); | |
1078 | ||
1079 | return fimc_m2m_resume(fimc); | |
1080 | } | |
1081 | ||
1082 | static int fimc_suspend(struct device *dev) | |
1083 | { | |
1084 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1085 | ||
1086 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1087 | ||
1088 | if (test_and_set_bit(ST_LPM, &fimc->state)) | |
1089 | return 0; | |
1090 | if (fimc_capture_busy(fimc)) | |
1091 | return fimc_capture_suspend(fimc); | |
1092 | ||
1093 | return fimc_m2m_suspend(fimc); | |
1094 | } | |
1095 | #endif /* CONFIG_PM_SLEEP */ | |
1096 | ||
4c62e976 | 1097 | static int fimc_remove(struct platform_device *pdev) |
e9e21083 SN |
1098 | { |
1099 | struct fimc_dev *fimc = platform_get_drvdata(pdev); | |
1100 | ||
1101 | pm_runtime_disable(&pdev->dev); | |
e9e21083 | 1102 | pm_runtime_set_suspended(&pdev->dev); |
5fd8f738 | 1103 | |
693f5c40 | 1104 | fimc_unregister_capture_subdev(fimc); |
2dab38e2 SN |
1105 | vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx); |
1106 | ||
e9e21083 SN |
1107 | clk_disable(fimc->clock[CLK_BUS]); |
1108 | fimc_clk_put(fimc); | |
548aafcd | 1109 | |
e9e21083 | 1110 | dev_info(&pdev->dev, "driver unloaded\n"); |
5fd8f738 SN |
1111 | return 0; |
1112 | } | |
1113 | ||
a7d5bbcf | 1114 | /* Image pixel limits, similar across several FIMC HW revisions. */ |
405f230c | 1115 | static const struct fimc_pix_limit s5p_pix_limit[4] = { |
a7d5bbcf SN |
1116 | [0] = { |
1117 | .scaler_en_w = 3264, | |
1118 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1119 | .out_rot_en_w = 1920, |
1120 | .out_rot_dis_w = 4224, | |
1121 | }, | |
1122 | [1] = { | |
1123 | .scaler_en_w = 4224, | |
1124 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1125 | .out_rot_en_w = 1920, |
1126 | .out_rot_dis_w = 4224, | |
1127 | }, | |
1128 | [2] = { | |
1129 | .scaler_en_w = 1920, | |
1130 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1131 | .out_rot_en_w = 1280, |
1132 | .out_rot_dis_w = 1920, | |
1133 | }, | |
25b9875f SN |
1134 | [3] = { |
1135 | .scaler_en_w = 1920, | |
1136 | .scaler_dis_w = 8192, | |
1137 | .in_rot_en_h = 1366, | |
1138 | .in_rot_dis_w = 8192, | |
1139 | .out_rot_en_w = 1366, | |
1140 | .out_rot_dis_w = 1920, | |
1141 | }, | |
a7d5bbcf SN |
1142 | }; |
1143 | ||
405f230c | 1144 | static const struct fimc_variant fimc0_variant_s5p = { |
a7d5bbcf SN |
1145 | .has_inp_rot = 1, |
1146 | .has_out_rot = 1, | |
d3953223 | 1147 | .has_cam_if = 1, |
5fd8f738 SN |
1148 | .min_inp_pixsize = 16, |
1149 | .min_out_pixsize = 16, | |
a7d5bbcf | 1150 | .hor_offs_align = 8, |
9c63afcb | 1151 | .min_vsize_align = 16, |
a7d5bbcf | 1152 | .pix_limit = &s5p_pix_limit[0], |
5fd8f738 SN |
1153 | }; |
1154 | ||
405f230c | 1155 | static const struct fimc_variant fimc2_variant_s5p = { |
d3953223 | 1156 | .has_cam_if = 1, |
5fd8f738 SN |
1157 | .min_inp_pixsize = 16, |
1158 | .min_out_pixsize = 16, | |
a7d5bbcf | 1159 | .hor_offs_align = 8, |
9c63afcb | 1160 | .min_vsize_align = 16, |
bb7c276e | 1161 | .pix_limit = &s5p_pix_limit[1], |
5fd8f738 SN |
1162 | }; |
1163 | ||
405f230c | 1164 | static const struct fimc_variant fimc0_variant_s5pv210 = { |
a7d5bbcf SN |
1165 | .has_inp_rot = 1, |
1166 | .has_out_rot = 1, | |
d3953223 | 1167 | .has_cam_if = 1, |
5fd8f738 | 1168 | .min_inp_pixsize = 16, |
548aafcd | 1169 | .min_out_pixsize = 16, |
a7d5bbcf | 1170 | .hor_offs_align = 8, |
9c63afcb | 1171 | .min_vsize_align = 16, |
a7d5bbcf SN |
1172 | .pix_limit = &s5p_pix_limit[1], |
1173 | }; | |
5fd8f738 | 1174 | |
405f230c | 1175 | static const struct fimc_variant fimc1_variant_s5pv210 = { |
a7d5bbcf SN |
1176 | .has_inp_rot = 1, |
1177 | .has_out_rot = 1, | |
d3953223 | 1178 | .has_cam_if = 1, |
b241c6d6 | 1179 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1180 | .min_inp_pixsize = 16, |
1181 | .min_out_pixsize = 16, | |
1182 | .hor_offs_align = 1, | |
9c63afcb | 1183 | .min_vsize_align = 1, |
a7d5bbcf | 1184 | .pix_limit = &s5p_pix_limit[2], |
5fd8f738 SN |
1185 | }; |
1186 | ||
405f230c | 1187 | static const struct fimc_variant fimc2_variant_s5pv210 = { |
d3953223 | 1188 | .has_cam_if = 1, |
5fd8f738 | 1189 | .min_inp_pixsize = 16, |
548aafcd | 1190 | .min_out_pixsize = 16, |
a7d5bbcf | 1191 | .hor_offs_align = 8, |
9c63afcb | 1192 | .min_vsize_align = 16, |
a7d5bbcf SN |
1193 | .pix_limit = &s5p_pix_limit[2], |
1194 | }; | |
5fd8f738 | 1195 | |
405f230c | 1196 | static const struct fimc_variant fimc0_variant_exynos4210 = { |
a7d5bbcf SN |
1197 | .has_inp_rot = 1, |
1198 | .has_out_rot = 1, | |
d3953223 | 1199 | .has_cam_if = 1, |
b241c6d6 | 1200 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1201 | .min_inp_pixsize = 16, |
1202 | .min_out_pixsize = 16, | |
566afaac | 1203 | .hor_offs_align = 2, |
9c63afcb | 1204 | .min_vsize_align = 1, |
a7d5bbcf SN |
1205 | .pix_limit = &s5p_pix_limit[1], |
1206 | }; | |
1207 | ||
405f230c | 1208 | static const struct fimc_variant fimc3_variant_exynos4210 = { |
b241c6d6 | 1209 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1210 | .min_inp_pixsize = 16, |
1211 | .min_out_pixsize = 16, | |
566afaac | 1212 | .hor_offs_align = 2, |
9c63afcb | 1213 | .min_vsize_align = 1, |
25b9875f | 1214 | .pix_limit = &s5p_pix_limit[3], |
5fd8f738 SN |
1215 | }; |
1216 | ||
a7d5bbcf | 1217 | /* S5PC100 */ |
405f230c | 1218 | static const struct fimc_drvdata fimc_drvdata_s5p = { |
5fd8f738 | 1219 | .variant = { |
a7d5bbcf SN |
1220 | [0] = &fimc0_variant_s5p, |
1221 | [1] = &fimc0_variant_s5p, | |
5fd8f738 SN |
1222 | [2] = &fimc2_variant_s5p, |
1223 | }, | |
e80cb1fa | 1224 | .num_entities = 3, |
a7d5bbcf | 1225 | .lclk_frequency = 133000000UL, |
e80cb1fa | 1226 | .out_buf_count = 4, |
5fd8f738 SN |
1227 | }; |
1228 | ||
a7d5bbcf | 1229 | /* S5PV210, S5PC110 */ |
405f230c | 1230 | static const struct fimc_drvdata fimc_drvdata_s5pv210 = { |
5fd8f738 | 1231 | .variant = { |
a7d5bbcf SN |
1232 | [0] = &fimc0_variant_s5pv210, |
1233 | [1] = &fimc1_variant_s5pv210, | |
5fd8f738 SN |
1234 | [2] = &fimc2_variant_s5pv210, |
1235 | }, | |
e80cb1fa SN |
1236 | .num_entities = 3, |
1237 | .lclk_frequency = 166000000UL, | |
1238 | .out_buf_count = 4, | |
1239 | .dma_pix_hoff = 1, | |
a7d5bbcf SN |
1240 | }; |
1241 | ||
bb7c276e | 1242 | /* EXYNOS4210, S5PV310, S5PC210 */ |
405f230c SN |
1243 | static const struct fimc_drvdata fimc_drvdata_exynos4210 = { |
1244 | .variant = { | |
1245 | [0] = &fimc0_variant_exynos4210, | |
1246 | [1] = &fimc0_variant_exynos4210, | |
1247 | [2] = &fimc0_variant_exynos4210, | |
1248 | [3] = &fimc3_variant_exynos4210, | |
1249 | }, | |
e80cb1fa | 1250 | .num_entities = 4, |
405f230c | 1251 | .lclk_frequency = 166000000UL, |
e80cb1fa SN |
1252 | .dma_pix_hoff = 1, |
1253 | .cistatus2 = 1, | |
1254 | .alpha_color = 1, | |
1255 | .out_buf_count = 32, | |
405f230c SN |
1256 | }; |
1257 | ||
1258 | /* EXYNOS4212, EXYNOS4412 */ | |
1259 | static const struct fimc_drvdata fimc_drvdata_exynos4x12 = { | |
e80cb1fa SN |
1260 | .num_entities = 4, |
1261 | .lclk_frequency = 166000000UL, | |
1262 | .dma_pix_hoff = 1, | |
1263 | .cistatus2 = 1, | |
1264 | .alpha_color = 1, | |
1265 | .out_buf_count = 32, | |
5fd8f738 SN |
1266 | }; |
1267 | ||
405f230c | 1268 | static const struct platform_device_id fimc_driver_ids[] = { |
5fd8f738 SN |
1269 | { |
1270 | .name = "s5p-fimc", | |
1271 | .driver_data = (unsigned long)&fimc_drvdata_s5p, | |
1272 | }, { | |
1273 | .name = "s5pv210-fimc", | |
1274 | .driver_data = (unsigned long)&fimc_drvdata_s5pv210, | |
a7d5bbcf | 1275 | }, { |
25b9875f | 1276 | .name = "exynos4-fimc", |
405f230c SN |
1277 | .driver_data = (unsigned long)&fimc_drvdata_exynos4210, |
1278 | }, { | |
1279 | .name = "exynos4x12-fimc", | |
1280 | .driver_data = (unsigned long)&fimc_drvdata_exynos4x12, | |
5fd8f738 | 1281 | }, |
e80cb1fa | 1282 | { }, |
5fd8f738 | 1283 | }; |
5fd8f738 | 1284 | |
e80cb1fa SN |
1285 | static const struct of_device_id fimc_of_match[] = { |
1286 | { | |
1287 | .compatible = "samsung,s5pv210-fimc", | |
1288 | .data = &fimc_drvdata_s5pv210, | |
1289 | }, { | |
1290 | .compatible = "samsung,exynos4210-fimc", | |
1291 | .data = &fimc_drvdata_exynos4210, | |
1292 | }, { | |
1293 | .compatible = "samsung,exynos4212-fimc", | |
1294 | .data = &fimc_drvdata_exynos4x12, | |
1295 | }, | |
1296 | { /* sentinel */ }, | |
1297 | }; | |
1298 | ||
e9e21083 SN |
1299 | static const struct dev_pm_ops fimc_pm_ops = { |
1300 | SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) | |
1301 | SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) | |
1302 | }; | |
1303 | ||
5fd8f738 SN |
1304 | static struct platform_driver fimc_driver = { |
1305 | .probe = fimc_probe, | |
4c62e976 | 1306 | .remove = fimc_remove, |
5fd8f738 SN |
1307 | .id_table = fimc_driver_ids, |
1308 | .driver = { | |
e80cb1fa SN |
1309 | .of_match_table = fimc_of_match, |
1310 | .name = FIMC_MODULE_NAME, | |
1311 | .owner = THIS_MODULE, | |
1312 | .pm = &fimc_pm_ops, | |
5fd8f738 SN |
1313 | } |
1314 | }; | |
1315 | ||
d3953223 | 1316 | int __init fimc_register_driver(void) |
5fd8f738 | 1317 | { |
ecd9acbf | 1318 | return platform_driver_register(&fimc_driver); |
5fd8f738 SN |
1319 | } |
1320 | ||
d3953223 | 1321 | void __exit fimc_unregister_driver(void) |
5fd8f738 SN |
1322 | { |
1323 | platform_driver_unregister(&fimc_driver); | |
1324 | } |