Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
97d97422 | 2 | * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver |
5fd8f738 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5fd8f738 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published | |
9 | * by the Free Software Foundation, either version 2 of the License, | |
10 | * or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
5fd8f738 SN |
15 | #include <linux/types.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/platform_device.h> | |
e9e21083 | 21 | #include <linux/pm_runtime.h> |
5fd8f738 SN |
22 | #include <linux/list.h> |
23 | #include <linux/io.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/clk.h> | |
26 | #include <media/v4l2-ioctl.h> | |
2dab38e2 SN |
27 | #include <media/videobuf2-core.h> |
28 | #include <media/videobuf2-dma-contig.h> | |
5fd8f738 SN |
29 | |
30 | #include "fimc-core.h" | |
c83a1ff0 | 31 | #include "fimc-reg.h" |
d3953223 | 32 | #include "fimc-mdevice.h" |
5fd8f738 | 33 | |
a25be18d | 34 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { |
ebdfea81 | 35 | "sclk_fimc", "fimc" |
a25be18d | 36 | }; |
5fd8f738 SN |
37 | |
38 | static struct fimc_fmt fimc_formats[] = { | |
39 | { | |
ef7af59b | 40 | .name = "RGB565", |
f83f71fd | 41 | .fourcc = V4L2_PIX_FMT_RGB565, |
ef7af59b | 42 | .depth = { 16 }, |
3d112d9a | 43 | .color = FIMC_FMT_RGB565, |
ef7af59b SN |
44 | .memplanes = 1, |
45 | .colplanes = 1, | |
ef7af59b | 46 | .flags = FMT_FLAGS_M2M, |
5fd8f738 | 47 | }, { |
ef7af59b SN |
48 | .name = "BGR666", |
49 | .fourcc = V4L2_PIX_FMT_BGR666, | |
50 | .depth = { 32 }, | |
3d112d9a | 51 | .color = FIMC_FMT_RGB666, |
ef7af59b SN |
52 | .memplanes = 1, |
53 | .colplanes = 1, | |
54 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 55 | }, { |
dafb9c70 | 56 | .name = "ARGB8888, 32 bpp", |
ef7af59b SN |
57 | .fourcc = V4L2_PIX_FMT_RGB32, |
58 | .depth = { 32 }, | |
3d112d9a | 59 | .color = FIMC_FMT_RGB888, |
ef7af59b SN |
60 | .memplanes = 1, |
61 | .colplanes = 1, | |
dafb9c70 SN |
62 | .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA, |
63 | }, { | |
64 | .name = "ARGB1555", | |
65 | .fourcc = V4L2_PIX_FMT_RGB555, | |
66 | .depth = { 16 }, | |
3d112d9a | 67 | .color = FIMC_FMT_RGB555, |
dafb9c70 SN |
68 | .memplanes = 1, |
69 | .colplanes = 1, | |
70 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
71 | }, { | |
72 | .name = "ARGB4444", | |
73 | .fourcc = V4L2_PIX_FMT_RGB444, | |
74 | .depth = { 16 }, | |
3d112d9a | 75 | .color = FIMC_FMT_RGB444, |
dafb9c70 SN |
76 | .memplanes = 1, |
77 | .colplanes = 1, | |
78 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
5fd8f738 | 79 | }, { |
ef7af59b SN |
80 | .name = "YUV 4:2:2 packed, YCbYCr", |
81 | .fourcc = V4L2_PIX_FMT_YUYV, | |
82 | .depth = { 16 }, | |
3d112d9a | 83 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
84 | .memplanes = 1, |
85 | .colplanes = 1, | |
86 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
87 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5f3cc447 | 88 | }, { |
ef7af59b SN |
89 | .name = "YUV 4:2:2 packed, CbYCrY", |
90 | .fourcc = V4L2_PIX_FMT_UYVY, | |
91 | .depth = { 16 }, | |
3d112d9a | 92 | .color = FIMC_FMT_CBYCRY422, |
ef7af59b SN |
93 | .memplanes = 1, |
94 | .colplanes = 1, | |
95 | .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, | |
96 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 97 | }, { |
ef7af59b SN |
98 | .name = "YUV 4:2:2 packed, CrYCbY", |
99 | .fourcc = V4L2_PIX_FMT_VYUY, | |
100 | .depth = { 16 }, | |
3d112d9a | 101 | .color = FIMC_FMT_CRYCBY422, |
ef7af59b SN |
102 | .memplanes = 1, |
103 | .colplanes = 1, | |
104 | .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, | |
105 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 106 | }, { |
ef7af59b SN |
107 | .name = "YUV 4:2:2 packed, YCrYCb", |
108 | .fourcc = V4L2_PIX_FMT_YVYU, | |
109 | .depth = { 16 }, | |
3d112d9a | 110 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
111 | .memplanes = 1, |
112 | .colplanes = 1, | |
113 | .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, | |
114 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 115 | }, { |
ef7af59b SN |
116 | .name = "YUV 4:2:2 planar, Y/Cb/Cr", |
117 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
118 | .depth = { 12 }, | |
3d112d9a | 119 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
120 | .memplanes = 1, |
121 | .colplanes = 3, | |
122 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 123 | }, { |
ef7af59b SN |
124 | .name = "YUV 4:2:2 planar, Y/CbCr", |
125 | .fourcc = V4L2_PIX_FMT_NV16, | |
126 | .depth = { 16 }, | |
3d112d9a | 127 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
128 | .memplanes = 1, |
129 | .colplanes = 2, | |
130 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 131 | }, { |
ef7af59b SN |
132 | .name = "YUV 4:2:2 planar, Y/CrCb", |
133 | .fourcc = V4L2_PIX_FMT_NV61, | |
134 | .depth = { 16 }, | |
3d112d9a | 135 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
136 | .memplanes = 1, |
137 | .colplanes = 2, | |
138 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 139 | }, { |
ef7af59b SN |
140 | .name = "YUV 4:2:0 planar, YCbCr", |
141 | .fourcc = V4L2_PIX_FMT_YUV420, | |
142 | .depth = { 12 }, | |
3d112d9a | 143 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
144 | .memplanes = 1, |
145 | .colplanes = 3, | |
146 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 147 | }, { |
ef7af59b SN |
148 | .name = "YUV 4:2:0 planar, Y/CbCr", |
149 | .fourcc = V4L2_PIX_FMT_NV12, | |
150 | .depth = { 12 }, | |
3d112d9a | 151 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
152 | .memplanes = 1, |
153 | .colplanes = 2, | |
154 | .flags = FMT_FLAGS_M2M, | |
155 | }, { | |
0a198bcd | 156 | .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr", |
ef7af59b | 157 | .fourcc = V4L2_PIX_FMT_NV12M, |
3d112d9a | 158 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
159 | .depth = { 8, 4 }, |
160 | .memplanes = 2, | |
161 | .colplanes = 2, | |
162 | .flags = FMT_FLAGS_M2M, | |
163 | }, { | |
0a198bcd | 164 | .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr", |
ef7af59b | 165 | .fourcc = V4L2_PIX_FMT_YUV420M, |
3d112d9a | 166 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
167 | .depth = { 8, 2, 2 }, |
168 | .memplanes = 3, | |
169 | .colplanes = 3, | |
170 | .flags = FMT_FLAGS_M2M, | |
171 | }, { | |
0a198bcd | 172 | .name = "YUV 4:2:0 non-contig. 2p, tiled", |
ef7af59b | 173 | .fourcc = V4L2_PIX_FMT_NV12MT, |
3d112d9a | 174 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
175 | .depth = { 8, 4 }, |
176 | .memplanes = 2, | |
177 | .colplanes = 2, | |
178 | .flags = FMT_FLAGS_M2M, | |
ee7160e5 SN |
179 | }, { |
180 | .name = "JPEG encoded data", | |
181 | .fourcc = V4L2_PIX_FMT_JPEG, | |
3d112d9a | 182 | .color = FIMC_FMT_JPEG, |
ee7160e5 SN |
183 | .depth = { 8 }, |
184 | .memplanes = 1, | |
185 | .colplanes = 1, | |
186 | .mbus_code = V4L2_MBUS_FMT_JPEG_1X8, | |
14783d25 SN |
187 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, |
188 | }, { | |
189 | .name = "S5C73MX interleaved UYVY/JPEG", | |
190 | .fourcc = V4L2_PIX_FMT_S5C_UYVY_JPG, | |
191 | .color = FIMC_FMT_YUYV_JPEG, | |
192 | .depth = { 8 }, | |
193 | .memplanes = 2, | |
194 | .colplanes = 1, | |
195 | .mdataplanes = 0x2, /* plane 1 holds frame meta data */ | |
196 | .mbus_code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
197 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, | |
5f3cc447 | 198 | }, |
548aafcd | 199 | }; |
5fd8f738 | 200 | |
bb7c276e | 201 | struct fimc_fmt *fimc_get_format(unsigned int index) |
dafb9c70 | 202 | { |
97d97422 SN |
203 | if (index >= ARRAY_SIZE(fimc_formats)) |
204 | return NULL; | |
205 | ||
206 | return &fimc_formats[index]; | |
dafb9c70 SN |
207 | } |
208 | ||
ee7160e5 SN |
209 | int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh, |
210 | int dw, int dh, int rotation) | |
5fd8f738 | 211 | { |
ee7160e5 SN |
212 | if (rotation == 90 || rotation == 270) |
213 | swap(dw, dh); | |
5fd8f738 | 214 | |
ee7160e5 SN |
215 | if (!ctx->scaler.enabled) |
216 | return (sw == dw && sh == dh) ? 0 : -EINVAL; | |
5fd8f738 | 217 | |
ee7160e5 | 218 | if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh)) |
1b09f292 HK |
219 | return -EINVAL; |
220 | ||
5fd8f738 SN |
221 | return 0; |
222 | } | |
223 | ||
224 | static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) | |
225 | { | |
548aafcd SN |
226 | u32 sh = 6; |
227 | ||
228 | if (src >= 64 * tar) | |
5fd8f738 | 229 | return -EINVAL; |
548aafcd SN |
230 | |
231 | while (sh--) { | |
232 | u32 tmp = 1 << sh; | |
233 | if (src >= tar * tmp) { | |
234 | *shift = sh, *ratio = tmp; | |
235 | return 0; | |
236 | } | |
5fd8f738 | 237 | } |
548aafcd | 238 | *shift = 0, *ratio = 1; |
5fd8f738 SN |
239 | return 0; |
240 | } | |
241 | ||
5f3cc447 | 242 | int fimc_set_scaler_info(struct fimc_ctx *ctx) |
5fd8f738 | 243 | { |
405f230c | 244 | const struct fimc_variant *variant = ctx->fimc_dev->variant; |
30c9939d | 245 | struct device *dev = &ctx->fimc_dev->pdev->dev; |
5fd8f738 SN |
246 | struct fimc_scaler *sc = &ctx->scaler; |
247 | struct fimc_frame *s_frame = &ctx->s_frame; | |
248 | struct fimc_frame *d_frame = &ctx->d_frame; | |
249 | int tx, ty, sx, sy; | |
250 | int ret; | |
251 | ||
47654df8 SN |
252 | if (ctx->rotation == 90 || ctx->rotation == 270) { |
253 | ty = d_frame->width; | |
254 | tx = d_frame->height; | |
255 | } else { | |
256 | tx = d_frame->width; | |
257 | ty = d_frame->height; | |
258 | } | |
5fd8f738 | 259 | if (tx <= 0 || ty <= 0) { |
30c9939d | 260 | dev_err(dev, "Invalid target size: %dx%d", tx, ty); |
5fd8f738 SN |
261 | return -EINVAL; |
262 | } | |
263 | ||
264 | sx = s_frame->width; | |
265 | sy = s_frame->height; | |
266 | if (sx <= 0 || sy <= 0) { | |
30c9939d | 267 | dev_err(dev, "Invalid source size: %dx%d", sx, sy); |
5fd8f738 SN |
268 | return -EINVAL; |
269 | } | |
5fd8f738 SN |
270 | sc->real_width = sx; |
271 | sc->real_height = sy; | |
5fd8f738 SN |
272 | |
273 | ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); | |
274 | if (ret) | |
275 | return ret; | |
276 | ||
277 | ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); | |
278 | if (ret) | |
279 | return ret; | |
280 | ||
281 | sc->pre_dst_width = sx / sc->pre_hratio; | |
282 | sc->pre_dst_height = sy / sc->pre_vratio; | |
283 | ||
b241c6d6 HK |
284 | if (variant->has_mainscaler_ext) { |
285 | sc->main_hratio = (sx << 14) / (tx << sc->hfactor); | |
286 | sc->main_vratio = (sy << 14) / (ty << sc->vfactor); | |
287 | } else { | |
288 | sc->main_hratio = (sx << 8) / (tx << sc->hfactor); | |
289 | sc->main_vratio = (sy << 8) / (ty << sc->vfactor); | |
290 | ||
291 | } | |
5fd8f738 SN |
292 | |
293 | sc->scaleup_h = (tx >= sx) ? 1 : 0; | |
294 | sc->scaleup_v = (ty >= sy) ? 1 : 0; | |
295 | ||
296 | /* check to see if input and output size/format differ */ | |
297 | if (s_frame->fmt->color == d_frame->fmt->color | |
298 | && s_frame->width == d_frame->width | |
299 | && s_frame->height == d_frame->height) | |
300 | sc->copy_mode = 1; | |
301 | else | |
302 | sc->copy_mode = 0; | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
e9e21083 | 307 | static irqreturn_t fimc_irq_handler(int irq, void *priv) |
5fd8f738 | 308 | { |
548aafcd | 309 | struct fimc_dev *fimc = priv; |
4ecbf5d1 | 310 | struct fimc_ctx *ctx; |
5fd8f738 | 311 | |
5fd8f738 SN |
312 | fimc_hw_clear_irq(fimc); |
313 | ||
e9e21083 SN |
314 | spin_lock(&fimc->slock); |
315 | ||
4ecbf5d1 | 316 | if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) { |
e9e21083 SN |
317 | if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) { |
318 | set_bit(ST_M2M_SUSPENDED, &fimc->state); | |
319 | wake_up(&fimc->irq_queue); | |
320 | goto out; | |
321 | } | |
4ecbf5d1 SN |
322 | ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev); |
323 | if (ctx != NULL) { | |
e9e21083 | 324 | spin_unlock(&fimc->slock); |
4ecbf5d1 | 325 | fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE); |
5fd8f738 | 326 | |
4ecbf5d1 SN |
327 | if (ctx->state & FIMC_CTX_SHUT) { |
328 | ctx->state &= ~FIMC_CTX_SHUT; | |
329 | wake_up(&fimc->irq_queue); | |
330 | } | |
efb13c3d | 331 | return IRQ_HANDLED; |
5fd8f738 | 332 | } |
ee7160e5 | 333 | } else if (test_bit(ST_CAPT_PEND, &fimc->state)) { |
97d97422 SN |
334 | int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) && |
335 | fimc->vid_cap.reqbufs_count == 1; | |
336 | fimc_capture_irq_handler(fimc, !last_buf); | |
5fd8f738 | 337 | } |
e9e21083 | 338 | out: |
5fd8f738 SN |
339 | spin_unlock(&fimc->slock); |
340 | return IRQ_HANDLED; | |
341 | } | |
342 | ||
ef7af59b | 343 | /* The color format (colplanes, memplanes) must be already configured. */ |
2dab38e2 | 344 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
548aafcd | 345 | struct fimc_frame *frame, struct fimc_addr *paddr) |
5fd8f738 | 346 | { |
5fd8f738 | 347 | int ret = 0; |
548aafcd | 348 | u32 pix_size; |
5fd8f738 | 349 | |
2dab38e2 | 350 | if (vb == NULL || frame == NULL) |
5fd8f738 SN |
351 | return -EINVAL; |
352 | ||
353 | pix_size = frame->width * frame->height; | |
354 | ||
ef7af59b SN |
355 | dbg("memplanes= %d, colplanes= %d, pix_size= %d", |
356 | frame->fmt->memplanes, frame->fmt->colplanes, pix_size); | |
357 | ||
ba7fcb0c | 358 | paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0); |
5fd8f738 | 359 | |
ef7af59b SN |
360 | if (frame->fmt->memplanes == 1) { |
361 | switch (frame->fmt->colplanes) { | |
5fd8f738 SN |
362 | case 1: |
363 | paddr->cb = 0; | |
364 | paddr->cr = 0; | |
365 | break; | |
366 | case 2: | |
367 | /* decompose Y into Y/Cb */ | |
368 | paddr->cb = (u32)(paddr->y + pix_size); | |
369 | paddr->cr = 0; | |
370 | break; | |
371 | case 3: | |
372 | paddr->cb = (u32)(paddr->y + pix_size); | |
373 | /* decompose Y into Y/Cb/Cr */ | |
3d112d9a | 374 | if (FIMC_FMT_YCBCR420 == frame->fmt->color) |
5fd8f738 SN |
375 | paddr->cr = (u32)(paddr->cb |
376 | + (pix_size >> 2)); | |
377 | else /* 422 */ | |
378 | paddr->cr = (u32)(paddr->cb | |
379 | + (pix_size >> 1)); | |
380 | break; | |
381 | default: | |
382 | return -EINVAL; | |
383 | } | |
14783d25 | 384 | } else if (!frame->fmt->mdataplanes) { |
ef7af59b | 385 | if (frame->fmt->memplanes >= 2) |
ba7fcb0c | 386 | paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1); |
ef7af59b SN |
387 | |
388 | if (frame->fmt->memplanes == 3) | |
ba7fcb0c | 389 | paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2); |
5fd8f738 SN |
390 | } |
391 | ||
548aafcd SN |
392 | dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d", |
393 | paddr->y, paddr->cb, paddr->cr, ret); | |
5fd8f738 SN |
394 | |
395 | return ret; | |
396 | } | |
397 | ||
398 | /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */ | |
9e803a04 | 399 | void fimc_set_yuv_order(struct fimc_ctx *ctx) |
5fd8f738 SN |
400 | { |
401 | /* The one only mode supported in SoC. */ | |
c83a1ff0 SN |
402 | ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
403 | ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; | |
5fd8f738 SN |
404 | |
405 | /* Set order for 1 plane input formats. */ | |
406 | switch (ctx->s_frame.fmt->color) { | |
3d112d9a | 407 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 408 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; |
5fd8f738 | 409 | break; |
3d112d9a | 410 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 411 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; |
5fd8f738 | 412 | break; |
3d112d9a | 413 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 414 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; |
5fd8f738 | 415 | break; |
3d112d9a | 416 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 417 | default: |
c83a1ff0 | 418 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
419 | break; |
420 | } | |
421 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); | |
422 | ||
423 | switch (ctx->d_frame.fmt->color) { | |
3d112d9a | 424 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 425 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; |
5fd8f738 | 426 | break; |
3d112d9a | 427 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 428 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; |
5fd8f738 | 429 | break; |
3d112d9a | 430 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 431 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; |
5fd8f738 | 432 | break; |
3d112d9a | 433 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 434 | default: |
c83a1ff0 | 435 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
436 | break; |
437 | } | |
438 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); | |
439 | } | |
440 | ||
9e803a04 | 441 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f) |
ddc79e0f | 442 | { |
405f230c | 443 | const struct fimc_variant *variant = ctx->fimc_dev->variant; |
ef7af59b SN |
444 | u32 i, depth = 0; |
445 | ||
446 | for (i = 0; i < f->fmt->colplanes; i++) | |
447 | depth += f->fmt->depth[i]; | |
ddc79e0f SN |
448 | |
449 | f->dma_offset.y_h = f->offs_h; | |
450 | if (!variant->pix_hoff) | |
ef7af59b | 451 | f->dma_offset.y_h *= (depth >> 3); |
ddc79e0f SN |
452 | |
453 | f->dma_offset.y_v = f->offs_v; | |
454 | ||
455 | f->dma_offset.cb_h = f->offs_h; | |
456 | f->dma_offset.cb_v = f->offs_v; | |
457 | ||
458 | f->dma_offset.cr_h = f->offs_h; | |
459 | f->dma_offset.cr_v = f->offs_v; | |
460 | ||
461 | if (!variant->pix_hoff) { | |
ef7af59b | 462 | if (f->fmt->colplanes == 3) { |
ddc79e0f SN |
463 | f->dma_offset.cb_h >>= 1; |
464 | f->dma_offset.cr_h >>= 1; | |
465 | } | |
3d112d9a | 466 | if (f->fmt->color == FIMC_FMT_YCBCR420) { |
ddc79e0f SN |
467 | f->dma_offset.cb_v >>= 1; |
468 | f->dma_offset.cr_v >>= 1; | |
469 | } | |
470 | } | |
471 | ||
472 | dbg("in_offset: color= %d, y_h= %d, y_v= %d", | |
473 | f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v); | |
474 | } | |
475 | ||
7e566be2 | 476 | static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx) |
9448ab7d SN |
477 | { |
478 | struct fimc_effect *effect = &ctx->effect; | |
479 | ||
480 | switch (colorfx) { | |
481 | case V4L2_COLORFX_NONE: | |
482 | effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS; | |
483 | break; | |
484 | case V4L2_COLORFX_BW: | |
485 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
486 | effect->pat_cb = 128; | |
487 | effect->pat_cr = 128; | |
488 | break; | |
489 | case V4L2_COLORFX_SEPIA: | |
490 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
491 | effect->pat_cb = 115; | |
492 | effect->pat_cr = 145; | |
493 | break; | |
494 | case V4L2_COLORFX_NEGATIVE: | |
495 | effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE; | |
496 | break; | |
497 | case V4L2_COLORFX_EMBOSS: | |
498 | effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING; | |
499 | break; | |
500 | case V4L2_COLORFX_ART_FREEZE: | |
501 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE; | |
502 | break; | |
503 | case V4L2_COLORFX_SILHOUETTE: | |
504 | effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE; | |
505 | break; | |
506 | case V4L2_COLORFX_SET_CBCR: | |
507 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
508 | effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8; | |
509 | effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff; | |
510 | break; | |
511 | default: | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
131b6c61 SN |
518 | /* |
519 | * V4L2 controls handling | |
520 | */ | |
521 | #define ctrl_to_ctx(__ctrl) \ | |
9448ab7d | 522 | container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler) |
131b6c61 | 523 | |
dafb9c70 | 524 | static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl) |
131b6c61 | 525 | { |
131b6c61 | 526 | struct fimc_dev *fimc = ctx->fimc_dev; |
405f230c | 527 | const struct fimc_variant *variant = fimc->variant; |
dafb9c70 | 528 | unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT; |
131b6c61 SN |
529 | int ret = 0; |
530 | ||
531 | if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) | |
532 | return 0; | |
533 | ||
534 | switch (ctrl->id) { | |
535 | case V4L2_CID_HFLIP: | |
131b6c61 SN |
536 | ctx->hflip = ctrl->val; |
537 | break; | |
538 | ||
539 | case V4L2_CID_VFLIP: | |
131b6c61 SN |
540 | ctx->vflip = ctrl->val; |
541 | break; | |
542 | ||
543 | case V4L2_CID_ROTATE: | |
544 | if (fimc_capture_pending(fimc) || | |
dafb9c70 | 545 | (ctx->state & flags) == flags) { |
ee7160e5 | 546 | ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width, |
131b6c61 SN |
547 | ctx->s_frame.height, ctx->d_frame.width, |
548 | ctx->d_frame.height, ctrl->val); | |
dafb9c70 SN |
549 | if (ret) |
550 | return -EINVAL; | |
131b6c61 SN |
551 | } |
552 | if ((ctrl->val == 90 || ctrl->val == 270) && | |
553 | !variant->has_out_rot) | |
554 | return -EINVAL; | |
dafb9c70 | 555 | |
131b6c61 SN |
556 | ctx->rotation = ctrl->val; |
557 | break; | |
558 | ||
dafb9c70 SN |
559 | case V4L2_CID_ALPHA_COMPONENT: |
560 | ctx->d_frame.alpha = ctrl->val; | |
561 | break; | |
9448ab7d SN |
562 | |
563 | case V4L2_CID_COLORFX: | |
564 | ret = fimc_set_color_effect(ctx, ctrl->val); | |
565 | if (ret) | |
566 | return ret; | |
567 | break; | |
131b6c61 | 568 | } |
9448ab7d | 569 | |
131b6c61 SN |
570 | ctx->state |= FIMC_PARAMS; |
571 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
131b6c61 SN |
572 | return 0; |
573 | } | |
574 | ||
dafb9c70 SN |
575 | static int fimc_s_ctrl(struct v4l2_ctrl *ctrl) |
576 | { | |
577 | struct fimc_ctx *ctx = ctrl_to_ctx(ctrl); | |
578 | unsigned long flags; | |
579 | int ret; | |
580 | ||
efb13c3d | 581 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
dafb9c70 | 582 | ret = __fimc_s_ctrl(ctx, ctrl); |
efb13c3d | 583 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
dafb9c70 SN |
584 | |
585 | return ret; | |
586 | } | |
587 | ||
131b6c61 SN |
588 | static const struct v4l2_ctrl_ops fimc_ctrl_ops = { |
589 | .s_ctrl = fimc_s_ctrl, | |
590 | }; | |
591 | ||
592 | int fimc_ctrls_create(struct fimc_ctx *ctx) | |
593 | { | |
405f230c | 594 | const struct fimc_variant *variant = ctx->fimc_dev->variant; |
dafb9c70 | 595 | unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt); |
9448ab7d SN |
596 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
597 | struct v4l2_ctrl_handler *handler = &ctrls->handler; | |
dafb9c70 | 598 | |
9448ab7d | 599 | if (ctx->ctrls.ready) |
131b6c61 | 600 | return 0; |
131b6c61 | 601 | |
9448ab7d SN |
602 | v4l2_ctrl_handler_init(handler, 6); |
603 | ||
604 | ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
53e5ab94 | 605 | V4L2_CID_ROTATE, 0, 270, 90, 0); |
9448ab7d | 606 | ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 607 | V4L2_CID_HFLIP, 0, 1, 1, 0); |
9448ab7d | 608 | ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 609 | V4L2_CID_VFLIP, 0, 1, 1, 0); |
9448ab7d | 610 | |
dafb9c70 | 611 | if (variant->has_alpha) |
9448ab7d SN |
612 | ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
613 | V4L2_CID_ALPHA_COMPONENT, | |
614 | 0, max_alpha, 1, 0); | |
dafb9c70 | 615 | else |
9448ab7d SN |
616 | ctrls->alpha = NULL; |
617 | ||
618 | ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops, | |
619 | V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, | |
620 | ~0x983f, V4L2_COLORFX_NONE); | |
621 | ||
622 | ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
623 | V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); | |
dafb9c70 | 624 | |
9448ab7d | 625 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 | 626 | |
9448ab7d | 627 | if (!handler->error) { |
4c4ed226 | 628 | v4l2_ctrl_cluster(2, &ctrls->colorfx); |
9448ab7d SN |
629 | ctrls->ready = true; |
630 | } | |
631 | ||
632 | return handler->error; | |
131b6c61 SN |
633 | } |
634 | ||
635 | void fimc_ctrls_delete(struct fimc_ctx *ctx) | |
636 | { | |
9448ab7d SN |
637 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
638 | ||
639 | if (ctrls->ready) { | |
640 | v4l2_ctrl_handler_free(&ctrls->handler); | |
641 | ctrls->ready = false; | |
642 | ctrls->alpha = NULL; | |
131b6c61 SN |
643 | } |
644 | } | |
645 | ||
646 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active) | |
647 | { | |
dafb9c70 | 648 | unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA; |
9448ab7d | 649 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
dafb9c70 | 650 | |
9448ab7d | 651 | if (!ctrls->ready) |
131b6c61 SN |
652 | return; |
653 | ||
8183e7a7 | 654 | mutex_lock(ctrls->handler.lock); |
9448ab7d SN |
655 | v4l2_ctrl_activate(ctrls->rotate, active); |
656 | v4l2_ctrl_activate(ctrls->hflip, active); | |
657 | v4l2_ctrl_activate(ctrls->vflip, active); | |
658 | v4l2_ctrl_activate(ctrls->colorfx, active); | |
659 | if (ctrls->alpha) | |
660 | v4l2_ctrl_activate(ctrls->alpha, active && has_alpha); | |
131b6c61 SN |
661 | |
662 | if (active) { | |
9448ab7d SN |
663 | fimc_set_color_effect(ctx, ctrls->colorfx->cur.val); |
664 | ctx->rotation = ctrls->rotate->val; | |
665 | ctx->hflip = ctrls->hflip->val; | |
666 | ctx->vflip = ctrls->vflip->val; | |
131b6c61 | 667 | } else { |
9448ab7d | 668 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 SN |
669 | ctx->rotation = 0; |
670 | ctx->hflip = 0; | |
671 | ctx->vflip = 0; | |
672 | } | |
8183e7a7 | 673 | mutex_unlock(ctrls->handler.lock); |
131b6c61 SN |
674 | } |
675 | ||
dafb9c70 SN |
676 | /* Update maximum value of the alpha color control */ |
677 | void fimc_alpha_ctrl_update(struct fimc_ctx *ctx) | |
678 | { | |
679 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9448ab7d | 680 | struct v4l2_ctrl *ctrl = ctx->ctrls.alpha; |
dafb9c70 SN |
681 | |
682 | if (ctrl == NULL || !fimc->variant->has_alpha) | |
683 | return; | |
684 | ||
685 | v4l2_ctrl_lock(ctrl); | |
686 | ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt); | |
687 | ||
688 | if (ctrl->cur.val > ctrl->maximum) | |
689 | ctrl->cur.val = ctrl->maximum; | |
690 | ||
691 | v4l2_ctrl_unlock(ctrl); | |
692 | } | |
693 | ||
fa8880be | 694 | void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f) |
5fd8f738 | 695 | { |
e578588e | 696 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; |
91707b8b | 697 | int i; |
5fd8f738 | 698 | |
e578588e SN |
699 | pixm->width = frame->o_width; |
700 | pixm->height = frame->o_height; | |
701 | pixm->field = V4L2_FIELD_NONE; | |
702 | pixm->pixelformat = frame->fmt->fourcc; | |
703 | pixm->colorspace = V4L2_COLORSPACE_JPEG; | |
704 | pixm->num_planes = frame->fmt->memplanes; | |
91707b8b SN |
705 | |
706 | for (i = 0; i < pixm->num_planes; ++i) { | |
fa8880be SN |
707 | pixm->plane_fmt[i].bytesperline = frame->bytesperline[i]; |
708 | pixm->plane_fmt[i].sizeimage = frame->payload[i]; | |
91707b8b | 709 | } |
5fd8f738 SN |
710 | } |
711 | ||
4db5e27e SN |
712 | void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f) |
713 | { | |
714 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; | |
715 | ||
716 | frame->f_width = pixm->plane_fmt[0].bytesperline; | |
717 | if (frame->fmt->colplanes == 1) | |
718 | frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0]; | |
719 | frame->f_height = pixm->height; | |
720 | frame->width = pixm->width; | |
721 | frame->height = pixm->height; | |
722 | frame->o_width = pixm->width; | |
723 | frame->o_height = pixm->height; | |
724 | frame->offs_h = 0; | |
725 | frame->offs_v = 0; | |
726 | } | |
727 | ||
728 | /** | |
729 | * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane | |
730 | * @fmt: fimc pixel format description (input) | |
731 | * @width: requested pixel width | |
732 | * @height: requested pixel height | |
733 | * @pix: multi-plane format to adjust | |
734 | */ | |
735 | void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height, | |
736 | struct v4l2_pix_format_mplane *pix) | |
737 | { | |
738 | u32 bytesperline = 0; | |
739 | int i; | |
740 | ||
741 | pix->colorspace = V4L2_COLORSPACE_JPEG; | |
742 | pix->field = V4L2_FIELD_NONE; | |
743 | pix->num_planes = fmt->memplanes; | |
dafb9c70 | 744 | pix->pixelformat = fmt->fourcc; |
4db5e27e SN |
745 | pix->height = height; |
746 | pix->width = width; | |
747 | ||
748 | for (i = 0; i < pix->num_planes; ++i) { | |
d547ab66 SN |
749 | struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i]; |
750 | u32 bpl = plane_fmt->bytesperline; | |
4db5e27e SN |
751 | |
752 | if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width)) | |
753 | bpl = pix->width; /* Planar */ | |
754 | ||
755 | if (fmt->colplanes == 1 && /* Packed */ | |
756 | (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width)) | |
757 | bpl = (pix->width * fmt->depth[0]) / 8; | |
fa8880be SN |
758 | /* |
759 | * Currently bytesperline for each plane is same, except | |
760 | * V4L2_PIX_FMT_YUV420M format. This calculation may need | |
761 | * to be changed when other multi-planar formats are added | |
762 | * to the fimc_formats[] array. | |
763 | */ | |
764 | if (i == 0) | |
4db5e27e | 765 | bytesperline = bpl; |
fa8880be SN |
766 | else if (i == 1 && fmt->memplanes == 3) |
767 | bytesperline /= 2; | |
4db5e27e | 768 | |
d547ab66 SN |
769 | plane_fmt->bytesperline = bytesperline; |
770 | plane_fmt->sizeimage = max((pix->width * pix->height * | |
771 | fmt->depth[i]) / 8, plane_fmt->sizeimage); | |
4db5e27e SN |
772 | } |
773 | } | |
774 | ||
cf52df8a SN |
775 | /** |
776 | * fimc_find_format - lookup fimc color format by fourcc or media bus format | |
777 | * @pixelformat: fourcc to match, ignored if null | |
778 | * @mbus_code: media bus code to match, ignored if null | |
779 | * @mask: the color flags to match | |
780 | * @index: offset in the fimc_formats array, ignored if negative | |
781 | */ | |
63746be5 | 782 | struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code, |
cf52df8a | 783 | unsigned int mask, int index) |
5fd8f738 | 784 | { |
cf52df8a | 785 | struct fimc_fmt *fmt, *def_fmt = NULL; |
5fd8f738 | 786 | unsigned int i; |
cf52df8a | 787 | int id = 0; |
5fd8f738 | 788 | |
63746be5 | 789 | if (index >= (int)ARRAY_SIZE(fimc_formats)) |
cf52df8a | 790 | return NULL; |
5f3cc447 SN |
791 | |
792 | for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) { | |
793 | fmt = &fimc_formats[i]; | |
cf52df8a SN |
794 | if (!(fmt->flags & mask)) |
795 | continue; | |
796 | if (pixelformat && fmt->fourcc == *pixelformat) | |
797 | return fmt; | |
798 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
799 | return fmt; | |
800 | if (index == id) | |
801 | def_fmt = fmt; | |
802 | id++; | |
5f3cc447 | 803 | } |
cf52df8a | 804 | return def_fmt; |
5f3cc447 SN |
805 | } |
806 | ||
e9e21083 | 807 | static void fimc_clk_put(struct fimc_dev *fimc) |
5fd8f738 SN |
808 | { |
809 | int i; | |
6ec0163b | 810 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
bd7d8888 SN |
811 | if (IS_ERR_OR_NULL(fimc->clock[i])) |
812 | continue; | |
813 | clk_unprepare(fimc->clock[i]); | |
814 | clk_put(fimc->clock[i]); | |
815 | fimc->clock[i] = NULL; | |
5fd8f738 SN |
816 | } |
817 | } | |
818 | ||
819 | static int fimc_clk_get(struct fimc_dev *fimc) | |
820 | { | |
bd7d8888 SN |
821 | int i, ret; |
822 | ||
6ec0163b | 823 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
a25be18d | 824 | fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]); |
bd7d8888 SN |
825 | if (IS_ERR(fimc->clock[i])) |
826 | goto err; | |
827 | ret = clk_prepare(fimc->clock[i]); | |
828 | if (ret < 0) { | |
829 | clk_put(fimc->clock[i]); | |
830 | fimc->clock[i] = NULL; | |
831 | goto err; | |
832 | } | |
5fd8f738 | 833 | } |
e9e21083 | 834 | return 0; |
bd7d8888 SN |
835 | err: |
836 | fimc_clk_put(fimc); | |
837 | dev_err(&fimc->pdev->dev, "failed to get clock: %s\n", | |
838 | fimc_clocks[i]); | |
839 | return -ENXIO; | |
e9e21083 SN |
840 | } |
841 | ||
842 | static int fimc_m2m_suspend(struct fimc_dev *fimc) | |
843 | { | |
844 | unsigned long flags; | |
845 | int timeout; | |
846 | ||
847 | spin_lock_irqsave(&fimc->slock, flags); | |
848 | if (!fimc_m2m_pending(fimc)) { | |
849 | spin_unlock_irqrestore(&fimc->slock, flags); | |
850 | return 0; | |
851 | } | |
852 | clear_bit(ST_M2M_SUSPENDED, &fimc->state); | |
853 | set_bit(ST_M2M_SUSPENDING, &fimc->state); | |
854 | spin_unlock_irqrestore(&fimc->slock, flags); | |
855 | ||
856 | timeout = wait_event_timeout(fimc->irq_queue, | |
857 | test_bit(ST_M2M_SUSPENDED, &fimc->state), | |
858 | FIMC_SHUTDOWN_TIMEOUT); | |
859 | ||
860 | clear_bit(ST_M2M_SUSPENDING, &fimc->state); | |
861 | return timeout == 0 ? -EAGAIN : 0; | |
862 | } | |
863 | ||
864 | static int fimc_m2m_resume(struct fimc_dev *fimc) | |
865 | { | |
866 | unsigned long flags; | |
867 | ||
868 | spin_lock_irqsave(&fimc->slock, flags); | |
869 | /* Clear for full H/W setup in first run after resume */ | |
870 | fimc->m2m.ctx = NULL; | |
871 | spin_unlock_irqrestore(&fimc->slock, flags); | |
872 | ||
873 | if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state)) | |
874 | fimc_m2m_job_finish(fimc->m2m.ctx, | |
875 | VB2_BUF_STATE_ERROR); | |
5fd8f738 SN |
876 | return 0; |
877 | } | |
878 | ||
879 | static int fimc_probe(struct platform_device *pdev) | |
880 | { | |
405f230c | 881 | const struct fimc_drvdata *drv_data = fimc_get_drvdata(pdev); |
bb7c276e | 882 | struct s5p_platform_fimc *pdata; |
5fd8f738 SN |
883 | struct fimc_dev *fimc; |
884 | struct resource *res; | |
5fd8f738 SN |
885 | int ret = 0; |
886 | ||
a7d5bbcf | 887 | if (pdev->id >= drv_data->num_entities) { |
5fd8f738 SN |
888 | dev_err(&pdev->dev, "Invalid platform device id: %d\n", |
889 | pdev->id); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
6d91a51a | 893 | fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL); |
5fd8f738 SN |
894 | if (!fimc) |
895 | return -ENOMEM; | |
896 | ||
897 | fimc->id = pdev->id; | |
e9e21083 | 898 | |
5fd8f738 SN |
899 | fimc->variant = drv_data->variant[fimc->id]; |
900 | fimc->pdev = pdev; | |
117182d1 SN |
901 | pdata = pdev->dev.platform_data; |
902 | fimc->pdata = pdata; | |
e9e21083 | 903 | |
5f3cc447 | 904 | init_waitqueue_head(&fimc->irq_queue); |
5fd8f738 | 905 | spin_lock_init(&fimc->slock); |
5fd8f738 SN |
906 | mutex_init(&fimc->lock); |
907 | ||
908 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6d91a51a SN |
909 | fimc->regs = devm_request_and_ioremap(&pdev->dev, res); |
910 | if (fimc->regs == NULL) { | |
911 | dev_err(&pdev->dev, "Failed to obtain io memory\n"); | |
912 | return -ENOENT; | |
5fd8f738 SN |
913 | } |
914 | ||
5fd8f738 | 915 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
6d91a51a SN |
916 | if (res == NULL) { |
917 | dev_err(&pdev->dev, "Failed to get IRQ resource\n"); | |
918 | return -ENXIO; | |
5fd8f738 | 919 | } |
5fd8f738 | 920 | |
e9e21083 SN |
921 | ret = fimc_clk_get(fimc); |
922 | if (ret) | |
6d91a51a | 923 | return ret; |
e9e21083 SN |
924 | clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency); |
925 | clk_enable(fimc->clock[CLK_BUS]); | |
926 | ||
6ec0163b | 927 | ret = devm_request_irq(&pdev->dev, res->start, fimc_irq_handler, |
5af86c26 | 928 | 0, dev_name(&pdev->dev), fimc); |
5fd8f738 SN |
929 | if (ret) { |
930 | dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); | |
931 | goto err_clk; | |
932 | } | |
933 | ||
693f5c40 SN |
934 | ret = fimc_initialize_capture_subdev(fimc); |
935 | if (ret) | |
936 | goto err_clk; | |
937 | ||
938 | platform_set_drvdata(pdev, fimc); | |
e9e21083 SN |
939 | pm_runtime_enable(&pdev->dev); |
940 | ret = pm_runtime_get_sync(&pdev->dev); | |
941 | if (ret < 0) | |
693f5c40 | 942 | goto err_sd; |
2dab38e2 | 943 | /* Initialize contiguous memory allocator */ |
e9e21083 | 944 | fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
2dab38e2 SN |
945 | if (IS_ERR(fimc->alloc_ctx)) { |
946 | ret = PTR_ERR(fimc->alloc_ctx); | |
e9e21083 | 947 | goto err_pm; |
2dab38e2 SN |
948 | } |
949 | ||
96a85742 | 950 | dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id); |
5fd8f738 | 951 | |
e9e21083 | 952 | pm_runtime_put(&pdev->dev); |
5fd8f738 | 953 | return 0; |
e9e21083 SN |
954 | err_pm: |
955 | pm_runtime_put(&pdev->dev); | |
693f5c40 SN |
956 | err_sd: |
957 | fimc_unregister_capture_subdev(fimc); | |
5fd8f738 | 958 | err_clk: |
e9e21083 | 959 | fimc_clk_put(fimc); |
5fd8f738 SN |
960 | return ret; |
961 | } | |
962 | ||
e9e21083 | 963 | static int fimc_runtime_resume(struct device *dev) |
5fd8f738 | 964 | { |
e9e21083 | 965 | struct fimc_dev *fimc = dev_get_drvdata(dev); |
5fd8f738 | 966 | |
e9e21083 SN |
967 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); |
968 | ||
969 | /* Enable clocks and perform basic initalization */ | |
970 | clk_enable(fimc->clock[CLK_GATE]); | |
5fd8f738 | 971 | fimc_hw_reset(fimc); |
e9e21083 SN |
972 | |
973 | /* Resume the capture or mem-to-mem device */ | |
974 | if (fimc_capture_busy(fimc)) | |
975 | return fimc_capture_resume(fimc); | |
f664684a SN |
976 | |
977 | return fimc_m2m_resume(fimc); | |
e9e21083 SN |
978 | } |
979 | ||
980 | static int fimc_runtime_suspend(struct device *dev) | |
981 | { | |
982 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
983 | int ret = 0; | |
984 | ||
985 | if (fimc_capture_busy(fimc)) | |
986 | ret = fimc_capture_suspend(fimc); | |
987 | else | |
988 | ret = fimc_m2m_suspend(fimc); | |
989 | if (!ret) | |
990 | clk_disable(fimc->clock[CLK_GATE]); | |
991 | ||
992 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
993 | return ret; | |
994 | } | |
995 | ||
996 | #ifdef CONFIG_PM_SLEEP | |
997 | static int fimc_resume(struct device *dev) | |
998 | { | |
999 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1000 | unsigned long flags; | |
1001 | ||
1002 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1003 | ||
1004 | /* Do not resume if the device was idle before system suspend */ | |
1005 | spin_lock_irqsave(&fimc->slock, flags); | |
1006 | if (!test_and_clear_bit(ST_LPM, &fimc->state) || | |
1007 | (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) { | |
1008 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1009 | return 0; | |
1010 | } | |
1011 | fimc_hw_reset(fimc); | |
e9e21083 SN |
1012 | spin_unlock_irqrestore(&fimc->slock, flags); |
1013 | ||
1014 | if (fimc_capture_busy(fimc)) | |
1015 | return fimc_capture_resume(fimc); | |
1016 | ||
1017 | return fimc_m2m_resume(fimc); | |
1018 | } | |
1019 | ||
1020 | static int fimc_suspend(struct device *dev) | |
1021 | { | |
1022 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1023 | ||
1024 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1025 | ||
1026 | if (test_and_set_bit(ST_LPM, &fimc->state)) | |
1027 | return 0; | |
1028 | if (fimc_capture_busy(fimc)) | |
1029 | return fimc_capture_suspend(fimc); | |
1030 | ||
1031 | return fimc_m2m_suspend(fimc); | |
1032 | } | |
1033 | #endif /* CONFIG_PM_SLEEP */ | |
1034 | ||
4c62e976 | 1035 | static int fimc_remove(struct platform_device *pdev) |
e9e21083 SN |
1036 | { |
1037 | struct fimc_dev *fimc = platform_get_drvdata(pdev); | |
1038 | ||
1039 | pm_runtime_disable(&pdev->dev); | |
e9e21083 | 1040 | pm_runtime_set_suspended(&pdev->dev); |
5fd8f738 | 1041 | |
693f5c40 | 1042 | fimc_unregister_capture_subdev(fimc); |
2dab38e2 SN |
1043 | vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx); |
1044 | ||
e9e21083 SN |
1045 | clk_disable(fimc->clock[CLK_BUS]); |
1046 | fimc_clk_put(fimc); | |
548aafcd | 1047 | |
e9e21083 | 1048 | dev_info(&pdev->dev, "driver unloaded\n"); |
5fd8f738 SN |
1049 | return 0; |
1050 | } | |
1051 | ||
a7d5bbcf | 1052 | /* Image pixel limits, similar across several FIMC HW revisions. */ |
405f230c | 1053 | static const struct fimc_pix_limit s5p_pix_limit[4] = { |
a7d5bbcf SN |
1054 | [0] = { |
1055 | .scaler_en_w = 3264, | |
1056 | .scaler_dis_w = 8192, | |
1057 | .in_rot_en_h = 1920, | |
1058 | .in_rot_dis_w = 8192, | |
1059 | .out_rot_en_w = 1920, | |
1060 | .out_rot_dis_w = 4224, | |
1061 | }, | |
1062 | [1] = { | |
1063 | .scaler_en_w = 4224, | |
1064 | .scaler_dis_w = 8192, | |
1065 | .in_rot_en_h = 1920, | |
1066 | .in_rot_dis_w = 8192, | |
1067 | .out_rot_en_w = 1920, | |
1068 | .out_rot_dis_w = 4224, | |
1069 | }, | |
1070 | [2] = { | |
1071 | .scaler_en_w = 1920, | |
1072 | .scaler_dis_w = 8192, | |
1073 | .in_rot_en_h = 1280, | |
1074 | .in_rot_dis_w = 8192, | |
1075 | .out_rot_en_w = 1280, | |
1076 | .out_rot_dis_w = 1920, | |
1077 | }, | |
25b9875f SN |
1078 | [3] = { |
1079 | .scaler_en_w = 1920, | |
1080 | .scaler_dis_w = 8192, | |
1081 | .in_rot_en_h = 1366, | |
1082 | .in_rot_dis_w = 8192, | |
1083 | .out_rot_en_w = 1366, | |
1084 | .out_rot_dis_w = 1920, | |
1085 | }, | |
a7d5bbcf SN |
1086 | }; |
1087 | ||
405f230c | 1088 | static const struct fimc_variant fimc0_variant_s5p = { |
a7d5bbcf SN |
1089 | .has_inp_rot = 1, |
1090 | .has_out_rot = 1, | |
d3953223 | 1091 | .has_cam_if = 1, |
5fd8f738 SN |
1092 | .min_inp_pixsize = 16, |
1093 | .min_out_pixsize = 16, | |
a7d5bbcf | 1094 | .hor_offs_align = 8, |
9c63afcb | 1095 | .min_vsize_align = 16, |
a7d5bbcf SN |
1096 | .out_buf_count = 4, |
1097 | .pix_limit = &s5p_pix_limit[0], | |
5fd8f738 SN |
1098 | }; |
1099 | ||
405f230c | 1100 | static const struct fimc_variant fimc2_variant_s5p = { |
d3953223 | 1101 | .has_cam_if = 1, |
5fd8f738 SN |
1102 | .min_inp_pixsize = 16, |
1103 | .min_out_pixsize = 16, | |
a7d5bbcf | 1104 | .hor_offs_align = 8, |
9c63afcb | 1105 | .min_vsize_align = 16, |
a7d5bbcf | 1106 | .out_buf_count = 4, |
bb7c276e | 1107 | .pix_limit = &s5p_pix_limit[1], |
5fd8f738 SN |
1108 | }; |
1109 | ||
405f230c | 1110 | static const struct fimc_variant fimc0_variant_s5pv210 = { |
a7d5bbcf SN |
1111 | .pix_hoff = 1, |
1112 | .has_inp_rot = 1, | |
1113 | .has_out_rot = 1, | |
d3953223 | 1114 | .has_cam_if = 1, |
5fd8f738 | 1115 | .min_inp_pixsize = 16, |
548aafcd | 1116 | .min_out_pixsize = 16, |
a7d5bbcf | 1117 | .hor_offs_align = 8, |
9c63afcb | 1118 | .min_vsize_align = 16, |
a7d5bbcf SN |
1119 | .out_buf_count = 4, |
1120 | .pix_limit = &s5p_pix_limit[1], | |
1121 | }; | |
5fd8f738 | 1122 | |
405f230c | 1123 | static const struct fimc_variant fimc1_variant_s5pv210 = { |
a7d5bbcf SN |
1124 | .pix_hoff = 1, |
1125 | .has_inp_rot = 1, | |
1126 | .has_out_rot = 1, | |
d3953223 | 1127 | .has_cam_if = 1, |
b241c6d6 | 1128 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1129 | .min_inp_pixsize = 16, |
1130 | .min_out_pixsize = 16, | |
1131 | .hor_offs_align = 1, | |
9c63afcb | 1132 | .min_vsize_align = 1, |
a7d5bbcf SN |
1133 | .out_buf_count = 4, |
1134 | .pix_limit = &s5p_pix_limit[2], | |
5fd8f738 SN |
1135 | }; |
1136 | ||
405f230c | 1137 | static const struct fimc_variant fimc2_variant_s5pv210 = { |
d3953223 | 1138 | .has_cam_if = 1, |
ddc79e0f | 1139 | .pix_hoff = 1, |
5fd8f738 | 1140 | .min_inp_pixsize = 16, |
548aafcd | 1141 | .min_out_pixsize = 16, |
a7d5bbcf | 1142 | .hor_offs_align = 8, |
9c63afcb | 1143 | .min_vsize_align = 16, |
a7d5bbcf SN |
1144 | .out_buf_count = 4, |
1145 | .pix_limit = &s5p_pix_limit[2], | |
1146 | }; | |
5fd8f738 | 1147 | |
405f230c | 1148 | static const struct fimc_variant fimc0_variant_exynos4210 = { |
a7d5bbcf SN |
1149 | .pix_hoff = 1, |
1150 | .has_inp_rot = 1, | |
1151 | .has_out_rot = 1, | |
d3953223 | 1152 | .has_cam_if = 1, |
798174ab | 1153 | .has_cistatus2 = 1, |
b241c6d6 | 1154 | .has_mainscaler_ext = 1, |
dafb9c70 | 1155 | .has_alpha = 1, |
a7d5bbcf SN |
1156 | .min_inp_pixsize = 16, |
1157 | .min_out_pixsize = 16, | |
566afaac | 1158 | .hor_offs_align = 2, |
9c63afcb | 1159 | .min_vsize_align = 1, |
a7d5bbcf SN |
1160 | .out_buf_count = 32, |
1161 | .pix_limit = &s5p_pix_limit[1], | |
1162 | }; | |
1163 | ||
405f230c | 1164 | static const struct fimc_variant fimc3_variant_exynos4210 = { |
a7d5bbcf | 1165 | .pix_hoff = 1, |
798174ab | 1166 | .has_cistatus2 = 1, |
b241c6d6 | 1167 | .has_mainscaler_ext = 1, |
dafb9c70 | 1168 | .has_alpha = 1, |
a7d5bbcf SN |
1169 | .min_inp_pixsize = 16, |
1170 | .min_out_pixsize = 16, | |
566afaac | 1171 | .hor_offs_align = 2, |
9c63afcb | 1172 | .min_vsize_align = 1, |
a7d5bbcf | 1173 | .out_buf_count = 32, |
25b9875f | 1174 | .pix_limit = &s5p_pix_limit[3], |
5fd8f738 SN |
1175 | }; |
1176 | ||
405f230c SN |
1177 | static const struct fimc_variant fimc0_variant_exynos4x12 = { |
1178 | .pix_hoff = 1, | |
1179 | .has_inp_rot = 1, | |
1180 | .has_out_rot = 1, | |
1181 | .has_cam_if = 1, | |
1182 | .has_isp_wb = 1, | |
1183 | .has_cistatus2 = 1, | |
1184 | .has_mainscaler_ext = 1, | |
1185 | .has_alpha = 1, | |
1186 | .min_inp_pixsize = 16, | |
1187 | .min_out_pixsize = 16, | |
1188 | .hor_offs_align = 2, | |
1189 | .min_vsize_align = 1, | |
1190 | .out_buf_count = 32, | |
1191 | .pix_limit = &s5p_pix_limit[1], | |
1192 | }; | |
1193 | ||
1194 | static const struct fimc_variant fimc3_variant_exynos4x12 = { | |
1195 | .pix_hoff = 1, | |
1196 | .has_cistatus2 = 1, | |
1197 | .has_mainscaler_ext = 1, | |
1198 | .has_alpha = 1, | |
1199 | .min_inp_pixsize = 16, | |
1200 | .min_out_pixsize = 16, | |
1201 | .hor_offs_align = 2, | |
1202 | .min_vsize_align = 1, | |
1203 | .out_buf_count = 32, | |
1204 | .pix_limit = &s5p_pix_limit[3], | |
1205 | }; | |
1206 | ||
a7d5bbcf | 1207 | /* S5PC100 */ |
405f230c | 1208 | static const struct fimc_drvdata fimc_drvdata_s5p = { |
5fd8f738 | 1209 | .variant = { |
a7d5bbcf SN |
1210 | [0] = &fimc0_variant_s5p, |
1211 | [1] = &fimc0_variant_s5p, | |
5fd8f738 SN |
1212 | [2] = &fimc2_variant_s5p, |
1213 | }, | |
a7d5bbcf SN |
1214 | .num_entities = 3, |
1215 | .lclk_frequency = 133000000UL, | |
5fd8f738 SN |
1216 | }; |
1217 | ||
a7d5bbcf | 1218 | /* S5PV210, S5PC110 */ |
405f230c | 1219 | static const struct fimc_drvdata fimc_drvdata_s5pv210 = { |
5fd8f738 | 1220 | .variant = { |
a7d5bbcf SN |
1221 | [0] = &fimc0_variant_s5pv210, |
1222 | [1] = &fimc1_variant_s5pv210, | |
5fd8f738 SN |
1223 | [2] = &fimc2_variant_s5pv210, |
1224 | }, | |
a7d5bbcf SN |
1225 | .num_entities = 3, |
1226 | .lclk_frequency = 166000000UL, | |
1227 | }; | |
1228 | ||
bb7c276e | 1229 | /* EXYNOS4210, S5PV310, S5PC210 */ |
405f230c SN |
1230 | static const struct fimc_drvdata fimc_drvdata_exynos4210 = { |
1231 | .variant = { | |
1232 | [0] = &fimc0_variant_exynos4210, | |
1233 | [1] = &fimc0_variant_exynos4210, | |
1234 | [2] = &fimc0_variant_exynos4210, | |
1235 | [3] = &fimc3_variant_exynos4210, | |
1236 | }, | |
1237 | .num_entities = 4, | |
1238 | .lclk_frequency = 166000000UL, | |
1239 | }; | |
1240 | ||
1241 | /* EXYNOS4212, EXYNOS4412 */ | |
1242 | static const struct fimc_drvdata fimc_drvdata_exynos4x12 = { | |
a7d5bbcf | 1243 | .variant = { |
405f230c SN |
1244 | [0] = &fimc0_variant_exynos4x12, |
1245 | [1] = &fimc0_variant_exynos4x12, | |
1246 | [2] = &fimc0_variant_exynos4x12, | |
1247 | [3] = &fimc3_variant_exynos4x12, | |
a7d5bbcf SN |
1248 | }, |
1249 | .num_entities = 4, | |
1250 | .lclk_frequency = 166000000UL, | |
5fd8f738 SN |
1251 | }; |
1252 | ||
405f230c | 1253 | static const struct platform_device_id fimc_driver_ids[] = { |
5fd8f738 SN |
1254 | { |
1255 | .name = "s5p-fimc", | |
1256 | .driver_data = (unsigned long)&fimc_drvdata_s5p, | |
1257 | }, { | |
1258 | .name = "s5pv210-fimc", | |
1259 | .driver_data = (unsigned long)&fimc_drvdata_s5pv210, | |
a7d5bbcf | 1260 | }, { |
25b9875f | 1261 | .name = "exynos4-fimc", |
405f230c SN |
1262 | .driver_data = (unsigned long)&fimc_drvdata_exynos4210, |
1263 | }, { | |
1264 | .name = "exynos4x12-fimc", | |
1265 | .driver_data = (unsigned long)&fimc_drvdata_exynos4x12, | |
5fd8f738 SN |
1266 | }, |
1267 | {}, | |
1268 | }; | |
1269 | MODULE_DEVICE_TABLE(platform, fimc_driver_ids); | |
1270 | ||
e9e21083 SN |
1271 | static const struct dev_pm_ops fimc_pm_ops = { |
1272 | SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) | |
1273 | SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) | |
1274 | }; | |
1275 | ||
5fd8f738 SN |
1276 | static struct platform_driver fimc_driver = { |
1277 | .probe = fimc_probe, | |
4c62e976 | 1278 | .remove = fimc_remove, |
5fd8f738 SN |
1279 | .id_table = fimc_driver_ids, |
1280 | .driver = { | |
d3953223 | 1281 | .name = FIMC_MODULE_NAME, |
5fd8f738 | 1282 | .owner = THIS_MODULE, |
e9e21083 | 1283 | .pm = &fimc_pm_ops, |
5fd8f738 SN |
1284 | } |
1285 | }; | |
1286 | ||
d3953223 | 1287 | int __init fimc_register_driver(void) |
5fd8f738 | 1288 | { |
ecd9acbf | 1289 | return platform_driver_register(&fimc_driver); |
5fd8f738 SN |
1290 | } |
1291 | ||
d3953223 | 1292 | void __exit fimc_unregister_driver(void) |
5fd8f738 SN |
1293 | { |
1294 | platform_driver_unregister(&fimc_driver); | |
1295 | } |