Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
0c9204d3 | 2 | * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd. |
5fd8f738 SN |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FIMC_CORE_H_ | |
10 | #define FIMC_CORE_H_ | |
11 | ||
5f3cc447 SN |
12 | /*#define DEBUG*/ |
13 | ||
2319c539 | 14 | #include <linux/platform_device.h> |
aee7126c | 15 | #include <linux/sched.h> |
4ecbf5d1 | 16 | #include <linux/spinlock.h> |
5fd8f738 | 17 | #include <linux/types.h> |
aee7126c | 18 | #include <linux/videodev2.h> |
2dab38e2 | 19 | #include <linux/io.h> |
25422781 | 20 | #include <linux/sizes.h> |
574e1717 SN |
21 | |
22 | #include <media/media-entity.h> | |
2dab38e2 | 23 | #include <media/videobuf2-core.h> |
131b6c61 | 24 | #include <media/v4l2-ctrls.h> |
5fd8f738 SN |
25 | #include <media/v4l2-device.h> |
26 | #include <media/v4l2-mem2mem.h> | |
5f3cc447 | 27 | #include <media/v4l2-mediabus.h> |
df7e09a3 | 28 | #include <media/s5p_fimc.h> |
aee7126c | 29 | |
5fd8f738 | 30 | #define dbg(fmt, args...) \ |
1e004695 | 31 | pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args) |
5fd8f738 | 32 | |
5f3cc447 SN |
33 | /* Time to wait for next frame VSYNC interrupt while stopping operation. */ |
34 | #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000) | |
ebdfea81 | 35 | #define MAX_FIMC_CLOCKS 2 |
d3953223 | 36 | #define FIMC_MODULE_NAME "s5p-fimc" |
a7d5bbcf | 37 | #define FIMC_MAX_DEVS 4 |
5fd8f738 SN |
38 | #define FIMC_MAX_OUT_BUFS 4 |
39 | #define SCALER_MAX_HRATIO 64 | |
40 | #define SCALER_MAX_VRATIO 64 | |
548aafcd | 41 | #define DMA_MIN_SIZE 8 |
237e0265 | 42 | #define FIMC_CAMIF_MAX_HEIGHT 0x2000 |
5fd8f738 | 43 | |
a25be18d SN |
44 | /* indices to the clocks array */ |
45 | enum { | |
46 | CLK_BUS, | |
47 | CLK_GATE, | |
a25be18d SN |
48 | }; |
49 | ||
5f3cc447 | 50 | enum fimc_dev_flags { |
e9e21083 SN |
51 | ST_LPM, |
52 | /* m2m node */ | |
53 | ST_M2M_RUN, | |
5fd8f738 | 54 | ST_M2M_PEND, |
e9e21083 SN |
55 | ST_M2M_SUSPENDING, |
56 | ST_M2M_SUSPENDED, | |
57 | /* capture node */ | |
5f3cc447 SN |
58 | ST_CAPT_PEND, |
59 | ST_CAPT_RUN, | |
60 | ST_CAPT_STREAM, | |
4db5e27e | 61 | ST_CAPT_ISP_STREAM, |
3e4748d8 | 62 | ST_CAPT_SUSPENDED, |
5f3cc447 | 63 | ST_CAPT_SHUT, |
e9e21083 | 64 | ST_CAPT_BUSY, |
131b6c61 | 65 | ST_CAPT_APPLY_CFG, |
ee7160e5 | 66 | ST_CAPT_JPEG, |
5fd8f738 SN |
67 | }; |
68 | ||
e9e21083 | 69 | #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state) |
5fd8f738 SN |
70 | #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state) |
71 | ||
5f3cc447 SN |
72 | #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state) |
73 | #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state) | |
e9e21083 | 74 | #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state) |
5f3cc447 | 75 | |
5fd8f738 | 76 | enum fimc_datapath { |
3d112d9a SN |
77 | FIMC_IO_NONE, |
78 | FIMC_IO_CAMERA, | |
79 | FIMC_IO_DMA, | |
80 | FIMC_IO_LCDFIFO, | |
81 | FIMC_IO_WRITEBACK, | |
82 | FIMC_IO_ISP, | |
5fd8f738 SN |
83 | }; |
84 | ||
85 | enum fimc_color_fmt { | |
3d112d9a SN |
86 | FIMC_FMT_RGB444 = 0x10, |
87 | FIMC_FMT_RGB555, | |
88 | FIMC_FMT_RGB565, | |
89 | FIMC_FMT_RGB666, | |
90 | FIMC_FMT_RGB888, | |
91 | FIMC_FMT_RGB30_LOCAL, | |
92 | FIMC_FMT_YCBCR420 = 0x20, | |
93 | FIMC_FMT_YCBYCR422, | |
94 | FIMC_FMT_YCRYCB422, | |
95 | FIMC_FMT_CBYCRY422, | |
96 | FIMC_FMT_CRYCBY422, | |
97 | FIMC_FMT_YCBCR444_LOCAL, | |
98 | FIMC_FMT_JPEG = 0x40, | |
99 | FIMC_FMT_RAW8 = 0x80, | |
100 | FIMC_FMT_RAW10, | |
101 | FIMC_FMT_RAW12, | |
5fd8f738 SN |
102 | }; |
103 | ||
237e0265 SN |
104 | #define fimc_fmt_is_rgb(x) (!!((x) & 0x10)) |
105 | #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40)) | |
548aafcd | 106 | |
4db5e27e SN |
107 | #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \ |
108 | __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) | |
109 | ||
5fd8f738 | 110 | /* The hardware context state. */ |
548aafcd | 111 | #define FIMC_PARAMS (1 << 0) |
548aafcd SN |
112 | #define FIMC_SRC_FMT (1 << 3) |
113 | #define FIMC_DST_FMT (1 << 4) | |
fed07f84 | 114 | #define FIMC_COMPOSE (1 << 5) |
237e0265 SN |
115 | #define FIMC_CTX_M2M (1 << 16) |
116 | #define FIMC_CTX_CAP (1 << 17) | |
117 | #define FIMC_CTX_SHUT (1 << 18) | |
5fd8f738 SN |
118 | |
119 | /* Image conversion flags */ | |
120 | #define FIMC_IN_DMA_ACCESS_TILED (1 << 0) | |
121 | #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0) | |
122 | #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1) | |
123 | #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1) | |
124 | #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2) | |
125 | #define FIMC_SCAN_MODE_INTERLACED (1 << 2) | |
548aafcd SN |
126 | /* |
127 | * YCbCr data dynamic range for RGB-YUV color conversion. | |
128 | * Y/Cb/Cr: (0 ~ 255) */ | |
5fd8f738 SN |
129 | #define FIMC_COLOR_RANGE_WIDE (0 << 3) |
130 | /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */ | |
131 | #define FIMC_COLOR_RANGE_NARROW (1 << 3) | |
132 | ||
5fd8f738 SN |
133 | /** |
134 | * struct fimc_fmt - the driver's internal color format data | |
5f3cc447 | 135 | * @mbus_code: Media Bus pixel code, -1 if not applicable |
5fd8f738 | 136 | * @name: format description |
5f3cc447 | 137 | * @fourcc: the fourcc code for this format, 0 if not applicable |
5fd8f738 | 138 | * @color: the corresponding fimc_color_fmt |
ef7af59b SN |
139 | * @memplanes: number of physically non-contiguous data planes |
140 | * @colplanes: number of physically contiguous data planes | |
3495dcef SN |
141 | * @depth: per plane driver's private 'number of bits per pixel' |
142 | * @flags: flags indicating which operation mode format applies to | |
5fd8f738 SN |
143 | */ |
144 | struct fimc_fmt { | |
5f3cc447 | 145 | enum v4l2_mbus_pixelcode mbus_code; |
5fd8f738 SN |
146 | char *name; |
147 | u32 fourcc; | |
148 | u32 color; | |
ef7af59b SN |
149 | u16 memplanes; |
150 | u16 colplanes; | |
151 | u8 depth[VIDEO_MAX_PLANES]; | |
5f3cc447 | 152 | u16 flags; |
dafb9c70 SN |
153 | #define FMT_FLAGS_CAM (1 << 0) |
154 | #define FMT_FLAGS_M2M_IN (1 << 1) | |
155 | #define FMT_FLAGS_M2M_OUT (1 << 2) | |
156 | #define FMT_FLAGS_M2M (1 << 1 | 1 << 2) | |
157 | #define FMT_HAS_ALPHA (1 << 3) | |
5fd8f738 SN |
158 | }; |
159 | ||
160 | /** | |
161 | * struct fimc_dma_offset - pixel offset information for DMA | |
162 | * @y_h: y value horizontal offset | |
163 | * @y_v: y value vertical offset | |
164 | * @cb_h: cb value horizontal offset | |
165 | * @cb_v: cb value vertical offset | |
166 | * @cr_h: cr value horizontal offset | |
167 | * @cr_v: cr value vertical offset | |
168 | */ | |
169 | struct fimc_dma_offset { | |
170 | int y_h; | |
171 | int y_v; | |
172 | int cb_h; | |
173 | int cb_v; | |
174 | int cr_h; | |
175 | int cr_v; | |
176 | }; | |
177 | ||
178 | /** | |
3495dcef | 179 | * struct fimc_effect - color effect information |
5fd8f738 SN |
180 | * @type: effect type |
181 | * @pat_cb: cr value when type is "arbitrary" | |
182 | * @pat_cr: cr value when type is "arbitrary" | |
183 | */ | |
184 | struct fimc_effect { | |
185 | u32 type; | |
186 | u8 pat_cb; | |
187 | u8 pat_cr; | |
188 | }; | |
189 | ||
190 | /** | |
191 | * struct fimc_scaler - the configuration data for FIMC inetrnal scaler | |
548aafcd SN |
192 | * @scaleup_h: flag indicating scaling up horizontally |
193 | * @scaleup_v: flag indicating scaling up vertically | |
194 | * @copy_mode: flag indicating transparent DMA transfer (no scaling | |
195 | * and color format conversion) | |
196 | * @enabled: flag indicating if the scaler is used | |
5fd8f738 SN |
197 | * @hfactor: horizontal shift factor |
198 | * @vfactor: vertical shift factor | |
199 | * @pre_hratio: horizontal ratio of the prescaler | |
200 | * @pre_vratio: vertical ratio of the prescaler | |
201 | * @pre_dst_width: the prescaler's destination width | |
202 | * @pre_dst_height: the prescaler's destination height | |
5fd8f738 SN |
203 | * @main_hratio: the main scaler's horizontal ratio |
204 | * @main_vratio: the main scaler's vertical ratio | |
548aafcd SN |
205 | * @real_width: source pixel (width - offset) |
206 | * @real_height: source pixel (height - offset) | |
5fd8f738 SN |
207 | */ |
208 | struct fimc_scaler { | |
dda7ae78 SN |
209 | unsigned int scaleup_h:1; |
210 | unsigned int scaleup_v:1; | |
211 | unsigned int copy_mode:1; | |
212 | unsigned int enabled:1; | |
5fd8f738 SN |
213 | u32 hfactor; |
214 | u32 vfactor; | |
215 | u32 pre_hratio; | |
216 | u32 pre_vratio; | |
217 | u32 pre_dst_width; | |
218 | u32 pre_dst_height; | |
5fd8f738 SN |
219 | u32 main_hratio; |
220 | u32 main_vratio; | |
221 | u32 real_width; | |
222 | u32 real_height; | |
5fd8f738 SN |
223 | }; |
224 | ||
225 | /** | |
226 | * struct fimc_addr - the FIMC physical address set for DMA | |
5fd8f738 SN |
227 | * @y: luminance plane physical address |
228 | * @cb: Cb plane physical address | |
229 | * @cr: Cr plane physical address | |
230 | */ | |
231 | struct fimc_addr { | |
232 | u32 y; | |
233 | u32 cb; | |
234 | u32 cr; | |
235 | }; | |
236 | ||
237 | /** | |
238 | * struct fimc_vid_buffer - the driver's video buffer | |
5f3cc447 | 239 | * @vb: v4l videobuf buffer |
3495dcef | 240 | * @list: linked list structure for buffer queue |
5f3cc447 SN |
241 | * @paddr: precalculated physical address set |
242 | * @index: buffer index for the output DMA engine | |
5fd8f738 SN |
243 | */ |
244 | struct fimc_vid_buffer { | |
2dab38e2 SN |
245 | struct vb2_buffer vb; |
246 | struct list_head list; | |
5f3cc447 SN |
247 | struct fimc_addr paddr; |
248 | int index; | |
5fd8f738 SN |
249 | }; |
250 | ||
251 | /** | |
548aafcd | 252 | * struct fimc_frame - source/target frame properties |
5fd8f738 SN |
253 | * @f_width: image full width (virtual screen size) |
254 | * @f_height: image full height (virtual screen size) | |
255 | * @o_width: original image width as set by S_FMT | |
256 | * @o_height: original image height as set by S_FMT | |
257 | * @offs_h: image horizontal pixel offset | |
258 | * @offs_v: image vertical pixel offset | |
259 | * @width: image pixel width | |
260 | * @height: image pixel weight | |
ef7af59b | 261 | * @payload: image size in bytes (w x h x bpp) |
3495dcef | 262 | * @paddr: image frame buffer physical addresses |
5fd8f738 | 263 | * @dma_offset: DMA offset in bytes |
3495dcef | 264 | * @fmt: fimc color format pointer |
5fd8f738 SN |
265 | */ |
266 | struct fimc_frame { | |
267 | u32 f_width; | |
268 | u32 f_height; | |
269 | u32 o_width; | |
270 | u32 o_height; | |
271 | u32 offs_h; | |
272 | u32 offs_v; | |
273 | u32 width; | |
274 | u32 height; | |
ef7af59b | 275 | unsigned long payload[VIDEO_MAX_PLANES]; |
5fd8f738 SN |
276 | struct fimc_addr paddr; |
277 | struct fimc_dma_offset dma_offset; | |
278 | struct fimc_fmt *fmt; | |
dafb9c70 | 279 | u8 alpha; |
5fd8f738 SN |
280 | }; |
281 | ||
282 | /** | |
283 | * struct fimc_m2m_device - v4l2 memory-to-memory device data | |
284 | * @vfd: the video device node for v4l2 m2m mode | |
5fd8f738 SN |
285 | * @m2m_dev: v4l2 memory-to-memory device data |
286 | * @ctx: hardware context data | |
287 | * @refcnt: the reference counter | |
288 | */ | |
289 | struct fimc_m2m_device { | |
bbc5296f | 290 | struct video_device vfd; |
5fd8f738 SN |
291 | struct v4l2_m2m_dev *m2m_dev; |
292 | struct fimc_ctx *ctx; | |
293 | int refcnt; | |
294 | }; | |
295 | ||
237e0265 SN |
296 | #define FIMC_SD_PAD_SINK 0 |
297 | #define FIMC_SD_PAD_SOURCE 1 | |
298 | #define FIMC_SD_PADS_NUM 2 | |
299 | ||
5f3cc447 SN |
300 | /** |
301 | * struct fimc_vid_cap - camera capture device information | |
302 | * @ctx: hardware context data | |
303 | * @vfd: video device node for camera capture mode | |
237e0265 | 304 | * @subdev: subdev exposing the FIMC processing block |
574e1717 | 305 | * @vd_pad: fimc video capture node pad |
237e0265 SN |
306 | * @sd_pads: fimc video processing block pads |
307 | * @mf: media bus format at the FIMC camera input (and the scaler output) pad | |
5f3cc447 SN |
308 | * @pending_buf_q: the pending buffer queue head |
309 | * @active_buf_q: the queue head of buffers scheduled in hardware | |
310 | * @vbq: the capture am video buffer queue | |
311 | * @active_buf_cnt: number of video buffers scheduled in hardware | |
312 | * @buf_index: index for managing the output DMA buffers | |
313 | * @frame_count: the frame counter for statistics | |
314 | * @reqbufs_count: the number of buffers requested in REQBUFS ioctl | |
315 | * @input_index: input (camera sensor) index | |
316 | * @refcnt: driver's private reference counter | |
d09a7dc8 | 317 | * @input: capture input type, grp_id of the attached subdev |
d3953223 | 318 | * @user_subdev_api: true if subdevs are not configured by the host driver |
5f3cc447 SN |
319 | */ |
320 | struct fimc_vid_cap { | |
321 | struct fimc_ctx *ctx; | |
2dab38e2 | 322 | struct vb2_alloc_ctx *alloc_ctx; |
31d34d9b | 323 | struct video_device vfd; |
693f5c40 | 324 | struct v4l2_subdev subdev; |
574e1717 | 325 | struct media_pad vd_pad; |
237e0265 SN |
326 | struct v4l2_mbus_framefmt mf; |
327 | struct media_pad sd_pads[FIMC_SD_PADS_NUM]; | |
5f3cc447 SN |
328 | struct list_head pending_buf_q; |
329 | struct list_head active_buf_q; | |
2dab38e2 | 330 | struct vb2_queue vbq; |
5f3cc447 SN |
331 | int active_buf_cnt; |
332 | int buf_index; | |
333 | unsigned int frame_count; | |
334 | unsigned int reqbufs_count; | |
335 | int input_index; | |
336 | int refcnt; | |
d09a7dc8 | 337 | u32 input; |
d3953223 | 338 | bool user_subdev_api; |
5f3cc447 SN |
339 | }; |
340 | ||
a7d5bbcf SN |
341 | /** |
342 | * struct fimc_pix_limit - image pixel size limits in various IP configurations | |
343 | * | |
344 | * @scaler_en_w: max input pixel width when the scaler is enabled | |
345 | * @scaler_dis_w: max input pixel width when the scaler is disabled | |
346 | * @in_rot_en_h: max input width with the input rotator is on | |
347 | * @in_rot_dis_w: max input width with the input rotator is off | |
348 | * @out_rot_en_w: max output width with the output rotator on | |
349 | * @out_rot_dis_w: max output width with the output rotator off | |
350 | */ | |
351 | struct fimc_pix_limit { | |
352 | u16 scaler_en_w; | |
353 | u16 scaler_dis_w; | |
354 | u16 in_rot_en_h; | |
355 | u16 in_rot_dis_w; | |
356 | u16 out_rot_en_w; | |
357 | u16 out_rot_dis_w; | |
358 | }; | |
359 | ||
5fd8f738 | 360 | /** |
bb7c276e | 361 | * struct fimc_variant - FIMC device variant information |
5fd8f738 SN |
362 | * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes |
363 | * @has_inp_rot: set if has input rotator | |
364 | * @has_out_rot: set if has output rotator | |
798174ab | 365 | * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision |
b241c6d6 HK |
366 | * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register |
367 | * are present in this IP revision | |
d3953223 | 368 | * @has_cam_if: set if this instance has a camera input interface |
a7d5bbcf | 369 | * @pix_limit: pixel size constraints for the scaler |
5fd8f738 SN |
370 | * @min_inp_pixsize: minimum input pixel size |
371 | * @min_out_pixsize: minimum output pixel size | |
a7d5bbcf | 372 | * @hor_offs_align: horizontal pixel offset aligment |
9c63afcb | 373 | * @min_vsize_align: minimum vertical pixel size alignment |
a7d5bbcf | 374 | * @out_buf_count: the number of buffers in output DMA sequence |
5fd8f738 | 375 | */ |
bb7c276e | 376 | struct fimc_variant { |
5fd8f738 SN |
377 | unsigned int pix_hoff:1; |
378 | unsigned int has_inp_rot:1; | |
379 | unsigned int has_out_rot:1; | |
798174ab | 380 | unsigned int has_cistatus2:1; |
b241c6d6 | 381 | unsigned int has_mainscaler_ext:1; |
d3953223 | 382 | unsigned int has_cam_if:1; |
dafb9c70 | 383 | unsigned int has_alpha:1; |
a7d5bbcf | 384 | struct fimc_pix_limit *pix_limit; |
5fd8f738 SN |
385 | u16 min_inp_pixsize; |
386 | u16 min_out_pixsize; | |
a7d5bbcf | 387 | u16 hor_offs_align; |
9c63afcb | 388 | u16 min_vsize_align; |
a7d5bbcf | 389 | u16 out_buf_count; |
5fd8f738 SN |
390 | }; |
391 | ||
392 | /** | |
bb7c276e SN |
393 | * struct fimc_drvdata - per device type driver data |
394 | * @variant: variant information for this device | |
395 | * @num_entities: number of fimc instances available in a SoC | |
396 | * @lclk_frequency: local bus clock frequency | |
5fd8f738 | 397 | */ |
bb7c276e SN |
398 | struct fimc_drvdata { |
399 | struct fimc_variant *variant[FIMC_MAX_DEVS]; | |
400 | int num_entities; | |
401 | unsigned long lclk_frequency; | |
5fd8f738 SN |
402 | }; |
403 | ||
bb7c276e SN |
404 | #define fimc_get_drvdata(_pdev) \ |
405 | ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data) | |
d3953223 | 406 | |
5fd8f738 SN |
407 | struct fimc_ctx; |
408 | ||
409 | /** | |
548aafcd | 410 | * struct fimc_dev - abstraction for FIMC entity |
5fd8f738 SN |
411 | * @slock: the spinlock protecting this data structure |
412 | * @lock: the mutex protecting this data structure | |
413 | * @pdev: pointer to the FIMC platform device | |
5f3cc447 | 414 | * @pdata: pointer to the device platform data |
3495dcef | 415 | * @variant: the IP variant information |
a25be18d | 416 | * @id: FIMC device index (0..FIMC_MAX_DEVS) |
3495dcef | 417 | * @clock: clocks required for FIMC operation |
5fd8f738 | 418 | * @regs: the mapped hardware registers |
3495dcef | 419 | * @irq_queue: interrupt handler waitqueue |
30c9939d | 420 | * @v4l2_dev: root v4l2_device |
5fd8f738 | 421 | * @m2m: memory-to-memory V4L2 device information |
5f3cc447 SN |
422 | * @vid_cap: camera capture device information |
423 | * @state: flags used to synchronize m2m and capture mode operation | |
3495dcef | 424 | * @alloc_ctx: videobuf2 memory allocator context |
d3953223 | 425 | * @pipeline: fimc video capture pipeline data structure |
5fd8f738 SN |
426 | */ |
427 | struct fimc_dev { | |
428 | spinlock_t slock; | |
429 | struct mutex lock; | |
430 | struct platform_device *pdev; | |
df7e09a3 | 431 | struct s5p_platform_fimc *pdata; |
bb7c276e | 432 | struct fimc_variant *variant; |
a25be18d | 433 | u16 id; |
a25be18d | 434 | struct clk *clock[MAX_FIMC_CLOCKS]; |
5fd8f738 | 435 | void __iomem *regs; |
5f3cc447 | 436 | wait_queue_head_t irq_queue; |
30c9939d | 437 | struct v4l2_device *v4l2_dev; |
5fd8f738 | 438 | struct fimc_m2m_device m2m; |
5f3cc447 | 439 | struct fimc_vid_cap vid_cap; |
5fd8f738 | 440 | unsigned long state; |
2dab38e2 | 441 | struct vb2_alloc_ctx *alloc_ctx; |
d3953223 | 442 | struct fimc_pipeline pipeline; |
b9ee31e6 | 443 | const struct fimc_pipeline_ops *pipeline_ops; |
5fd8f738 SN |
444 | }; |
445 | ||
9448ab7d SN |
446 | /** |
447 | * struct fimc_ctrls - v4l2 controls structure | |
448 | * @handler: the control handler | |
449 | * @colorfx: image effect control | |
450 | * @colorfx_cbcr: Cb/Cr coefficients control | |
451 | * @rotate: image rotation control | |
452 | * @hflip: horizontal flip control | |
453 | * @vflip: vertical flip control | |
454 | * @alpha: RGB alpha control | |
455 | * @ready: true if @handler is initialized | |
456 | */ | |
457 | struct fimc_ctrls { | |
458 | struct v4l2_ctrl_handler handler; | |
459 | struct { | |
460 | struct v4l2_ctrl *colorfx; | |
461 | struct v4l2_ctrl *colorfx_cbcr; | |
462 | }; | |
463 | struct v4l2_ctrl *rotate; | |
464 | struct v4l2_ctrl *hflip; | |
465 | struct v4l2_ctrl *vflip; | |
466 | struct v4l2_ctrl *alpha; | |
467 | bool ready; | |
468 | }; | |
469 | ||
5fd8f738 SN |
470 | /** |
471 | * fimc_ctx - the device context data | |
5fd8f738 SN |
472 | * @s_frame: source frame properties |
473 | * @d_frame: destination frame properties | |
474 | * @out_order_1p: output 1-plane YCBCR order | |
475 | * @out_order_2p: output 2-plane YCBCR order | |
476 | * @in_order_1p input 1-plane YCBCR order | |
477 | * @in_order_2p: input 2-plane YCBCR order | |
478 | * @in_path: input mode (DMA or camera) | |
479 | * @out_path: output mode (DMA or FIFO) | |
480 | * @scaler: image scaler properties | |
481 | * @effect: image effect | |
482 | * @rotation: image clockwise rotation in degrees | |
131b6c61 SN |
483 | * @hflip: indicates image horizontal flip if set |
484 | * @vflip: indicates image vertical flip if set | |
548aafcd | 485 | * @flags: additional flags for image conversion |
5fd8f738 SN |
486 | * @state: flags to keep track of user configuration |
487 | * @fimc_dev: the FIMC device this context applies to | |
488 | * @m2m_ctx: memory-to-memory device context | |
e578588e | 489 | * @fh: v4l2 file handle |
9448ab7d | 490 | * @ctrls: v4l2 controls structure |
5fd8f738 SN |
491 | */ |
492 | struct fimc_ctx { | |
5fd8f738 SN |
493 | struct fimc_frame s_frame; |
494 | struct fimc_frame d_frame; | |
495 | u32 out_order_1p; | |
496 | u32 out_order_2p; | |
497 | u32 in_order_1p; | |
498 | u32 in_order_2p; | |
499 | enum fimc_datapath in_path; | |
500 | enum fimc_datapath out_path; | |
501 | struct fimc_scaler scaler; | |
502 | struct fimc_effect effect; | |
503 | int rotation; | |
131b6c61 SN |
504 | unsigned int hflip:1; |
505 | unsigned int vflip:1; | |
5fd8f738 SN |
506 | u32 flags; |
507 | u32 state; | |
508 | struct fimc_dev *fimc_dev; | |
509 | struct v4l2_m2m_ctx *m2m_ctx; | |
e578588e | 510 | struct v4l2_fh fh; |
9448ab7d | 511 | struct fimc_ctrls ctrls; |
5fd8f738 SN |
512 | }; |
513 | ||
e578588e SN |
514 | #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh) |
515 | ||
237e0265 SN |
516 | static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height) |
517 | { | |
518 | f->o_width = width; | |
519 | f->o_height = height; | |
520 | f->f_width = width; | |
521 | f->f_height = height; | |
522 | } | |
523 | ||
524 | static inline void set_frame_crop(struct fimc_frame *f, | |
525 | u32 left, u32 top, u32 width, u32 height) | |
526 | { | |
527 | f->offs_h = left; | |
528 | f->offs_v = top; | |
529 | f->width = width; | |
530 | f->height = height; | |
531 | } | |
532 | ||
533 | static inline u32 fimc_get_format_depth(struct fimc_fmt *ff) | |
534 | { | |
535 | u32 i, depth = 0; | |
536 | ||
537 | if (ff != NULL) | |
538 | for (i = 0; i < ff->colplanes; i++) | |
539 | depth += ff->depth[i]; | |
540 | return depth; | |
541 | } | |
542 | ||
4ecbf5d1 SN |
543 | static inline bool fimc_capture_active(struct fimc_dev *fimc) |
544 | { | |
545 | unsigned long flags; | |
546 | bool ret; | |
547 | ||
548 | spin_lock_irqsave(&fimc->slock, flags); | |
549 | ret = !!(fimc->state & (1 << ST_CAPT_RUN) || | |
550 | fimc->state & (1 << ST_CAPT_PEND)); | |
551 | spin_unlock_irqrestore(&fimc->slock, flags); | |
552 | return ret; | |
553 | } | |
554 | ||
efb13c3d | 555 | static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx) |
4ecbf5d1 SN |
556 | { |
557 | unsigned long flags; | |
558 | ||
efb13c3d | 559 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
4ecbf5d1 | 560 | ctx->state |= state; |
efb13c3d | 561 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
4ecbf5d1 SN |
562 | } |
563 | ||
564 | static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx) | |
565 | { | |
566 | unsigned long flags; | |
567 | bool ret; | |
568 | ||
efb13c3d | 569 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
4ecbf5d1 | 570 | ret = (ctx->state & mask) == mask; |
efb13c3d | 571 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
4ecbf5d1 SN |
572 | return ret; |
573 | } | |
574 | ||
5fd8f738 SN |
575 | static inline int tiled_fmt(struct fimc_fmt *fmt) |
576 | { | |
ef7af59b | 577 | return fmt->fourcc == V4L2_PIX_FMT_NV12MT; |
5fd8f738 SN |
578 | } |
579 | ||
dafb9c70 SN |
580 | /* Return the alpha component bit mask */ |
581 | static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt) | |
582 | { | |
583 | switch (fmt->color) { | |
3d112d9a SN |
584 | case FIMC_FMT_RGB444: return 0x0f; |
585 | case FIMC_FMT_RGB555: return 0x01; | |
586 | case FIMC_FMT_RGB888: return 0xff; | |
dafb9c70 SN |
587 | default: return 0; |
588 | }; | |
589 | } | |
590 | ||
548aafcd SN |
591 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, |
592 | enum v4l2_buf_type type) | |
03e30ca5 PO |
593 | { |
594 | struct fimc_frame *frame; | |
595 | ||
ef7af59b | 596 | if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { |
4ecbf5d1 | 597 | if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx)) |
5f3cc447 SN |
598 | frame = &ctx->s_frame; |
599 | else | |
600 | return ERR_PTR(-EINVAL); | |
ef7af59b | 601 | } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { |
03e30ca5 PO |
602 | frame = &ctx->d_frame; |
603 | } else { | |
30c9939d | 604 | v4l2_err(ctx->fimc_dev->v4l2_dev, |
03e30ca5 PO |
605 | "Wrong buffer/video queue type (%d)\n", type); |
606 | return ERR_PTR(-EINVAL); | |
607 | } | |
608 | ||
609 | return frame; | |
610 | } | |
611 | ||
5f3cc447 SN |
612 | /* -----------------------------------------------------*/ |
613 | /* fimc-core.c */ | |
ef7af59b SN |
614 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, |
615 | struct v4l2_fmtdesc *f); | |
131b6c61 SN |
616 | int fimc_ctrls_create(struct fimc_ctx *ctx); |
617 | void fimc_ctrls_delete(struct fimc_ctx *ctx); | |
618 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active); | |
dafb9c70 | 619 | void fimc_alpha_ctrl_update(struct fimc_ctx *ctx); |
e578588e | 620 | int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f); |
4db5e27e SN |
621 | void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height, |
622 | struct v4l2_pix_format_mplane *pix); | |
63746be5 | 623 | struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code, |
cf52df8a | 624 | unsigned int mask, int index); |
97d97422 | 625 | struct fimc_fmt *fimc_get_format(unsigned int index); |
5f3cc447 | 626 | |
ee7160e5 SN |
627 | int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh, |
628 | int dw, int dh, int rotation); | |
5f3cc447 SN |
629 | int fimc_set_scaler_info(struct fimc_ctx *ctx); |
630 | int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags); | |
2dab38e2 | 631 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
5f3cc447 | 632 | struct fimc_frame *frame, struct fimc_addr *paddr); |
9e803a04 SN |
633 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f); |
634 | void fimc_set_yuv_order(struct fimc_ctx *ctx); | |
4db5e27e | 635 | void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f); |
97d97422 | 636 | void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf); |
9e803a04 | 637 | |
30c9939d SN |
638 | int fimc_register_m2m_device(struct fimc_dev *fimc, |
639 | struct v4l2_device *v4l2_dev); | |
640 | void fimc_unregister_m2m_device(struct fimc_dev *fimc); | |
d3953223 SN |
641 | int fimc_register_driver(void); |
642 | void fimc_unregister_driver(void); | |
5f3cc447 | 643 | |
97d97422 SN |
644 | /* -----------------------------------------------------*/ |
645 | /* fimc-m2m.c */ | |
646 | void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state); | |
647 | ||
5f3cc447 SN |
648 | /* -----------------------------------------------------*/ |
649 | /* fimc-capture.c */ | |
693f5c40 SN |
650 | int fimc_initialize_capture_subdev(struct fimc_dev *fimc); |
651 | void fimc_unregister_capture_subdev(struct fimc_dev *fimc); | |
131b6c61 | 652 | int fimc_capture_ctrls_create(struct fimc_dev *fimc); |
e1d72f4d SN |
653 | void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification, |
654 | void *arg); | |
e9e21083 SN |
655 | int fimc_capture_suspend(struct fimc_dev *fimc); |
656 | int fimc_capture_resume(struct fimc_dev *fimc); | |
548aafcd | 657 | |
5f3cc447 | 658 | /* |
0295202c | 659 | * Buffer list manipulation functions. Must be called with fimc.slock held. |
5f3cc447 | 660 | */ |
0295202c SN |
661 | |
662 | /** | |
663 | * fimc_active_queue_add - add buffer to the capture active buffers queue | |
664 | * @buf: buffer to add to the active buffers list | |
665 | */ | |
666 | static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap, | |
667 | struct fimc_vid_buffer *buf) | |
5f3cc447 | 668 | { |
2dab38e2 | 669 | list_add_tail(&buf->list, &vid_cap->active_buf_q); |
5f3cc447 SN |
670 | vid_cap->active_buf_cnt++; |
671 | } | |
672 | ||
0295202c SN |
673 | /** |
674 | * fimc_active_queue_pop - pop buffer from the capture active buffers queue | |
675 | * | |
676 | * The caller must assure the active_buf_q list is not empty. | |
5f3cc447 | 677 | */ |
0295202c SN |
678 | static inline struct fimc_vid_buffer *fimc_active_queue_pop( |
679 | struct fimc_vid_cap *vid_cap) | |
5f3cc447 SN |
680 | { |
681 | struct fimc_vid_buffer *buf; | |
682 | buf = list_entry(vid_cap->active_buf_q.next, | |
2dab38e2 SN |
683 | struct fimc_vid_buffer, list); |
684 | list_del(&buf->list); | |
5f3cc447 SN |
685 | vid_cap->active_buf_cnt--; |
686 | return buf; | |
687 | } | |
688 | ||
0295202c SN |
689 | /** |
690 | * fimc_pending_queue_add - add buffer to the capture pending buffers queue | |
691 | * @buf: buffer to add to the pending buffers list | |
692 | */ | |
5f3cc447 SN |
693 | static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap, |
694 | struct fimc_vid_buffer *buf) | |
695 | { | |
2dab38e2 | 696 | list_add_tail(&buf->list, &vid_cap->pending_buf_q); |
5f3cc447 SN |
697 | } |
698 | ||
0295202c SN |
699 | /** |
700 | * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue | |
701 | * | |
702 | * The caller must assure the pending_buf_q list is not empty. | |
703 | */ | |
704 | static inline struct fimc_vid_buffer *fimc_pending_queue_pop( | |
705 | struct fimc_vid_cap *vid_cap) | |
5f3cc447 SN |
706 | { |
707 | struct fimc_vid_buffer *buf; | |
708 | buf = list_entry(vid_cap->pending_buf_q.next, | |
2dab38e2 SN |
709 | struct fimc_vid_buffer, list); |
710 | list_del(&buf->list); | |
5f3cc447 SN |
711 | return buf; |
712 | } | |
713 | ||
5fd8f738 | 714 | #endif /* FIMC_CORE_H_ */ |