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[media] MAINTAINERS: Add s5c73m3 driver entry
[deliverable/linux.git] / drivers / media / platform / s5p-fimc / fimc-reg.c
CommitLineData
5fd8f738
SN		 1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
0c9204d3
SN		 4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
5fd8f738
SN		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/io.h>
13#include <linux/delay.h>
df7e09a3 14#include <media/s5p_fimc.h>
5fd8f738 15
c83a1ff0 16#include "fimc-reg.h"
5fd8f738
SN		 17#include "fimc-core.h"
18
19
20void fimc_hw_reset(struct fimc_dev *dev)
21{
22 u32 cfg;
23
c83a1ff0
SN		 24 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
25 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
26 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
5fd8f738
SN		 27
28 /* Software reset. */
c83a1ff0
SN		 29 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
30 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
31 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
e9e21083 32 udelay(10);
5fd8f738 33
c83a1ff0
SN		 34 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
35 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
36 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
2c1bb62e
SN		 37
38 if (dev->variant->out_buf_count > 4)
39 fimc_hw_set_dma_seq(dev, 0xF);
5fd8f738
SN		 40}
41
ac75934c 42static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
5fd8f738 43{
c83a1ff0 44 u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL;
5fd8f738 45
131b6c61 46 if (ctx->hflip)
c83a1ff0 47 flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR;
1bc05e77
SN		 48 if (ctx->vflip)
49 flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR;
131b6c61 50
ac75934c
SN		 51 if (ctx->rotation <= 90)
52 return flip;
5fd8f738 53
c83a1ff0 54 return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180;
5fd8f738
SN		 55}
56
ac75934c 57static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
5fd8f738 58{
c83a1ff0 59 u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL;
5fd8f738 60
131b6c61 61 if (ctx->hflip)
c83a1ff0 62 flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR;
1bc05e77
SN		 63 if (ctx->vflip)
64 flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR;
131b6c61 65
ac75934c
SN		 66 if (ctx->rotation <= 90)
67 return flip;
68
c83a1ff0 69 return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180;
5fd8f738
SN		 70}
71
47654df8
SN		 72void fimc_hw_set_rotation(struct fimc_ctx *ctx)
73{
74 u32 cfg, flip;
75 struct fimc_dev *dev = ctx->fimc_dev;
76
c83a1ff0
SN		 77 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
78 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
79 FIMC_REG_CITRGFMT_FLIP_180);
47654df8
SN		 80
81 /*
82 * The input and output rotator cannot work simultaneously.
83 * Use the output rotator in output DMA mode or the input rotator
84 * in direct fifo output mode.
85 */
86 if (ctx->rotation == 90 || ctx->rotation == 270) {
3d112d9a 87 if (ctx->out_path == FIMC_IO_LCDFIFO)
c83a1ff0 88 cfg |= FIMC_REG_CITRGFMT_INROT90;
47654df8 89 else
c83a1ff0 90 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
47654df8 91 }
47654df8 92
3d112d9a 93 if (ctx->out_path == FIMC_IO_DMA) {
ac75934c 94 cfg |= fimc_hw_get_target_flip(ctx);
c83a1ff0 95 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
ac75934c
SN		 96 } else {
97 /* LCD FIFO path */
c83a1ff0
SN		 98 flip = readl(dev->regs + FIMC_REG_MSCTRL);
99 flip &= ~FIMC_REG_MSCTRL_FLIP_MASK;
ac75934c 100 flip |= fimc_hw_get_in_flip(ctx);
c83a1ff0 101 writel(flip, dev->regs + FIMC_REG_MSCTRL);
ac75934c 102 }
47654df8
SN		 103}
104
5fd8f738
SN		 105void fimc_hw_set_target_format(struct fimc_ctx *ctx)
106{
107 u32 cfg;
108 struct fimc_dev *dev = ctx->fimc_dev;
109 struct fimc_frame *frame = &ctx->d_frame;
110
111 dbg("w= %d, h= %d color: %d", frame->width,
c83a1ff0 112 frame->height, frame->fmt->color);
5fd8f738 113
c83a1ff0
SN		 114 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
115 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
116 FIMC_REG_CITRGFMT_VSIZE_MASK);
5fd8f738
SN		 117
118 switch (frame->fmt->color) {
3d112d9a 119 case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
c83a1ff0 120 cfg |= FIMC_REG_CITRGFMT_RGB;
5fd8f738 121 break;
3d112d9a 122 case FIMC_FMT_YCBCR420:
c83a1ff0 123 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
5fd8f738 124 break;
3d112d9a 125 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
ef7af59b 126 if (frame->fmt->colplanes == 1)
c83a1ff0 127 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
5fd8f738 128 else
c83a1ff0 129 cfg |= FIMC_REG_CITRGFMT_YCBCR422;
5fd8f738
SN		 130 break;
131 default:
132 break;
133 }
134
c83a1ff0
SN		 135 if (ctx->rotation == 90 || ctx->rotation == 270)
136 cfg |= (frame->height << 16) | frame->width;
137 else
138 cfg |= (frame->width << 16) | frame->height;
47654df8 139
c83a1ff0 140 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
5fd8f738 141
c83a1ff0
SN		 142 cfg = readl(dev->regs + FIMC_REG_CITAREA);
143 cfg &= ~FIMC_REG_CITAREA_MASK;
5fd8f738 144 cfg |= (frame->width * frame->height);
c83a1ff0 145 writel(cfg, dev->regs + FIMC_REG_CITAREA);
5fd8f738
SN		 146}
147
148static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
149{
150 struct fimc_dev *dev = ctx->fimc_dev;
151 struct fimc_frame *frame = &ctx->d_frame;
47654df8 152 u32 cfg;
5fd8f738 153
c83a1ff0
SN		 154 cfg = (frame->f_height << 16) | frame->f_width;
155 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
5f3cc447
SN		 156
157 /* Select color space conversion equation (HD/SD size).*/
c83a1ff0 158 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
5f3cc447 159 if (frame->f_width >= 1280) /* HD */
c83a1ff0 160 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
5f3cc447 161 else /* SD */
c83a1ff0
SN		 162 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
163 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
5f3cc447 164
5fd8f738
SN		 165}
166
167void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
168{
5fd8f738
SN		 169 struct fimc_dev *dev = ctx->fimc_dev;
170 struct fimc_frame *frame = &ctx->d_frame;
171 struct fimc_dma_offset *offset = &frame->dma_offset;
dafb9c70 172 struct fimc_fmt *fmt = frame->fmt;
c83a1ff0 173 u32 cfg;
5fd8f738
SN		 174
175 /* Set the input dma offsets. */
c83a1ff0
SN		 176 cfg = (offset->y_v << 16) | offset->y_h;
177 writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
5fd8f738 178
c83a1ff0
SN		 179 cfg = (offset->cb_v << 16) | offset->cb_h;
180 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
5fd8f738 181
c83a1ff0
SN		 182 cfg = (offset->cr_v << 16) | offset->cr_h;
183 writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
5fd8f738
SN		 184
185 fimc_hw_set_out_dma_size(ctx);
186
187 /* Configure chroma components order. */
c83a1ff0 188 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
5fd8f738 189
c83a1ff0
SN		 190 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
191 FIMC_REG_CIOCTRL_ORDER422_MASK |
192 FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK |
193 FIMC_REG_CIOCTRL_RGB16FMT_MASK);
5fd8f738 194
dafb9c70 195 if (fmt->colplanes == 1)
5fd8f738 196 cfg |= ctx->out_order_1p;
dafb9c70 197 else if (fmt->colplanes == 2)
c83a1ff0 198 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
dafb9c70 199 else if (fmt->colplanes == 3)
c83a1ff0 200 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
5fd8f738 201
3d112d9a 202 if (fmt->color == FIMC_FMT_RGB565)
c83a1ff0 203 cfg |= FIMC_REG_CIOCTRL_RGB565;
3d112d9a 204 else if (fmt->color == FIMC_FMT_RGB555)
c83a1ff0 205 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
3d112d9a 206 else if (fmt->color == FIMC_FMT_RGB444)
c83a1ff0 207 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
dafb9c70 208
c83a1ff0 209 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
5fd8f738
SN		 210}
211
212static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
213{
c83a1ff0 214 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
5fd8f738 215 if (enable)
c83a1ff0 216 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738 217 else
c83a1ff0
SN		 218 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
219 writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
5fd8f738
SN		 220}
221
222void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
223{
c83a1ff0 224 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
5fd8f738 225 if (enable)
c83a1ff0 226 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
5fd8f738 227 else
c83a1ff0
SN		 228 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
229 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
5fd8f738
SN		 230}
231
b241c6d6 232void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
5fd8f738
SN		 233{
234 struct fimc_dev *dev = ctx->fimc_dev;
235 struct fimc_scaler *sc = &ctx->scaler;
548aafcd 236 u32 cfg, shfactor;
5fd8f738
SN		 237
238 shfactor = 10 - (sc->hfactor + sc->vfactor);
c83a1ff0 239 cfg = shfactor << 28;
5fd8f738 240
c83a1ff0
SN		 241 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
242 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
5fd8f738 243
c83a1ff0
SN		 244 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
245 writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
5fd8f738
SN		 246}
247
b241c6d6 248static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
5fd8f738
SN		 249{
250 struct fimc_dev *dev = ctx->fimc_dev;
251 struct fimc_scaler *sc = &ctx->scaler;
252 struct fimc_frame *src_frame = &ctx->s_frame;
253 struct fimc_frame *dst_frame = &ctx->d_frame;
2c1bb62e 254
c83a1ff0 255 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
2c1bb62e 256
c83a1ff0
SN		 257 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
258 FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V |
259 FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE |
260 FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK |
261 FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT);
5fd8f738
SN		 262
263 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
c83a1ff0
SN		 264 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
265 FIMC_REG_CISCCTRL_CSCY2R_WIDE);
5fd8f738
SN		 266
267 if (!sc->enabled)
c83a1ff0 268 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
5fd8f738
SN		 269
270 if (sc->scaleup_h)
c83a1ff0 271 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
5fd8f738
SN		 272
273 if (sc->scaleup_v)
c83a1ff0 274 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
5fd8f738
SN		 275
276 if (sc->copy_mode)
c83a1ff0 277 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
5fd8f738 278
3d112d9a 279 if (ctx->in_path == FIMC_IO_DMA) {
dafb9c70 280 switch (src_frame->fmt->color) {
3d112d9a 281 case FIMC_FMT_RGB565:
c83a1ff0 282 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
dafb9c70 283 break;
3d112d9a 284 case FIMC_FMT_RGB666:
c83a1ff0 285 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
dafb9c70 286 break;
3d112d9a 287 case FIMC_FMT_RGB888:
c83a1ff0 288 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
dafb9c70
SN		 289 break;
290 }
5fd8f738
SN		 291 }
292
3d112d9a 293 if (ctx->out_path == FIMC_IO_DMA) {
dafb9c70
SN		 294 u32 color = dst_frame->fmt->color;
295
3d112d9a 296 if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
c83a1ff0 297 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
3d112d9a 298 else if (color == FIMC_FMT_RGB666)
c83a1ff0 299 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
3d112d9a 300 else if (color == FIMC_FMT_RGB888)
c83a1ff0 301 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
5fd8f738 302 } else {
c83a1ff0 303 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
5fd8f738
SN		 304
305 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
c83a1ff0 306 cfg |= FIMC_REG_CISCCTRL_INTERLACE;
5fd8f738
SN		 307 }
308
c83a1ff0 309 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
b241c6d6
HK		 310}
311
312void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
313{
314 struct fimc_dev *dev = ctx->fimc_dev;
405f230c 315 const struct fimc_variant *variant = dev->variant;
b241c6d6
HK		 316 struct fimc_scaler *sc = &ctx->scaler;
317 u32 cfg;
318
319 dbg("main_hratio= 0x%X main_vratio= 0x%X",
c83a1ff0 320 sc->main_hratio, sc->main_vratio);
b241c6d6
HK		 321
322 fimc_hw_set_scaler(ctx);
323
c83a1ff0
SN		 324 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
325 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
326 FIMC_REG_CISCCTRL_MVRATIO_MASK);
b241c6d6 327
70f66ea2 328 if (variant->has_mainscaler_ext) {
c83a1ff0
SN		 329 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
330 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
331 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
b241c6d6 332
c83a1ff0 333 cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
b241c6d6 334
c83a1ff0
SN		 335 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
336 FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK);
337 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
338 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
339 writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
70f66ea2 340 } else {
c83a1ff0
SN		 341 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
342 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
343 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
70f66ea2 344 }
5fd8f738
SN		 345}
346
35f29248 347void fimc_hw_enable_capture(struct fimc_ctx *ctx)
5fd8f738
SN		 348{
349 struct fimc_dev *dev = ctx->fimc_dev;
35f29248 350 u32 cfg;
5fd8f738 351
35f29248
SN		 352 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
353 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE;
5fd8f738
SN		 354
355 if (ctx->scaler.enabled)
c83a1ff0 356 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
35f29248
SN		 357 else
358 cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
5fd8f738 359
c83a1ff0
SN		 360 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
361 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
5fd8f738
SN		 362}
363
35f29248
SN		 364void fimc_hw_disable_capture(struct fimc_dev *dev)
365{
366 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
367 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN |
368 FIMC_REG_CIIMGCPT_IMGCPTEN_SC);
369 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
370}
371
9448ab7d 372void fimc_hw_set_effect(struct fimc_ctx *ctx)
5fd8f738
SN		 373{
374 struct fimc_dev *dev = ctx->fimc_dev;
375 struct fimc_effect *effect = &ctx->effect;
ee7160e5 376 u32 cfg = 0;
5fd8f738 377
9448ab7d 378 if (effect->type != FIMC_REG_CIIMGEFF_FIN_BYPASS) {
c83a1ff0
SN		 379 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
380 FIMC_REG_CIIMGEFF_IE_ENABLE;
ee7160e5 381 cfg |= effect->type;
c83a1ff0
SN		 382 if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY)
383 cfg |= (effect->pat_cb << 13) | effect->pat_cr;
5fd8f738
SN		 384 }
385
c83a1ff0 386 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
5fd8f738
SN		 387}
388
dafb9c70
SN		 389void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
390{
391 struct fimc_dev *dev = ctx->fimc_dev;
392 struct fimc_frame *frame = &ctx->d_frame;
393 u32 cfg;
394
395 if (!(frame->fmt->flags & FMT_HAS_ALPHA))
396 return;
397
c83a1ff0
SN		 398 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
399 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
dafb9c70 400 cfg |= (frame->alpha << 4);
c83a1ff0 401 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
dafb9c70
SN		 402}
403
5fd8f738
SN		 404static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
405{
406 struct fimc_dev *dev = ctx->fimc_dev;
407 struct fimc_frame *frame = &ctx->s_frame;
408 u32 cfg_o = 0;
409 u32 cfg_r = 0;
410
3d112d9a 411 if (FIMC_IO_LCDFIFO == ctx->out_path)
c83a1ff0 412 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738 413
c83a1ff0
SN		 414 cfg_o |= (frame->f_height << 16) | frame->f_width;
415 cfg_r |= (frame->height << 16) | frame->width;
5fd8f738 416
c83a1ff0
SN		 417 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
418 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738
SN		 419}
420
421void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
422{
423 struct fimc_dev *dev = ctx->fimc_dev;
424 struct fimc_frame *frame = &ctx->s_frame;
425 struct fimc_dma_offset *offset = &frame->dma_offset;
548aafcd 426 u32 cfg;
5fd8f738
SN		 427
428 /* Set the pixel offsets. */
c83a1ff0
SN		 429 cfg = (offset->y_v << 16) | offset->y_h;
430 writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
5fd8f738 431
c83a1ff0
SN		 432 cfg = (offset->cb_v << 16) | offset->cb_h;
433 writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
5fd8f738 434
c83a1ff0
SN		 435 cfg = (offset->cr_v << 16) | offset->cr_h;
436 writel(cfg, dev->regs + FIMC_REG_CIICROFF);
5fd8f738
SN		 437
438 /* Input original and real size. */
439 fimc_hw_set_in_dma_size(ctx);
440
548aafcd 441 /* Use DMA autoload only in FIFO mode. */
3d112d9a 442 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
5fd8f738
SN		 443
444 /* Set the input DMA to process single frame only. */
c83a1ff0
SN		 445 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
446 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
447 | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
448 | FIMC_REG_MSCTRL_INPUT_MASK
449 | FIMC_REG_MSCTRL_C_INT_IN_MASK
450 | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK);
5fd8f738 451
c83a1ff0
SN		 452 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
453 | FIMC_REG_MSCTRL_INPUT_MEMORY
454 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
5fd8f738
SN		 455
456 switch (frame->fmt->color) {
3d112d9a 457 case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
c83a1ff0 458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
5fd8f738 459 break;
3d112d9a 460 case FIMC_FMT_YCBCR420:
c83a1ff0 461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
5fd8f738 462
ef7af59b 463 if (frame->fmt->colplanes == 2)
c83a1ff0 464 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
5fd8f738 465 else
c83a1ff0 466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
5fd8f738
SN		 467
468 break;
3d112d9a 469 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
ef7af59b 470 if (frame->fmt->colplanes == 1) {
5fd8f738 471 cfg |= ctx->in_order_1p
c83a1ff0 472 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
5fd8f738 473 } else {
c83a1ff0 474 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
5fd8f738 475
ef7af59b 476 if (frame->fmt->colplanes == 2)
5fd8f738 477 cfg |= ctx->in_order_2p
c83a1ff0 478 | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
5fd8f738 479 else
c83a1ff0 480 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
5fd8f738
SN		 481 }
482 break;
483 default:
484 break;
485 }
486
c83a1ff0 487 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
5fd8f738
SN		 488
489 /* Input/output DMA linear/tiled mode. */
c83a1ff0
SN		 490 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
491 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
5fd8f738
SN		 492
493 if (tiled_fmt(ctx->s_frame.fmt))
c83a1ff0 494 cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
5fd8f738
SN		 495
496 if (tiled_fmt(ctx->d_frame.fmt))
c83a1ff0 497 cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
5fd8f738 498
c83a1ff0 499 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
5fd8f738
SN		 500}
501
502
503void fimc_hw_set_input_path(struct fimc_ctx *ctx)
504{
505 struct fimc_dev *dev = ctx->fimc_dev;
506
c83a1ff0
SN		 507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
5fd8f738 509
3d112d9a 510 if (ctx->in_path == FIMC_IO_DMA)
c83a1ff0 511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
5fd8f738 512 else
c83a1ff0 513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
5fd8f738 514
c83a1ff0 515 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
5fd8f738
SN		 516}
517
518void fimc_hw_set_output_path(struct fimc_ctx *ctx)
519{
520 struct fimc_dev *dev = ctx->fimc_dev;
521
c83a1ff0
SN		 522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
3d112d9a 524 if (ctx->out_path == FIMC_IO_LCDFIFO)
c83a1ff0
SN		 525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
5fd8f738
SN		 527}
528
529void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
530{
c83a1ff0
SN		 531 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
532 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
533 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738 534
c83a1ff0
SN		 535 writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
536 writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
537 writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
5fd8f738 538
c83a1ff0
SN		 539 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
540 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738
SN		 541}
542
548aafcd
SN		 543void fimc_hw_set_output_addr(struct fimc_dev *dev,
544 struct fimc_addr *paddr, int index)
5fd8f738 545{
548aafcd
SN		 546 int i = (index == -1) ? 0 : index;
547 do {
c83a1ff0
SN		 548 writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
549 writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
550 writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
548aafcd
SN		 551 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
552 i, paddr->y, paddr->cb, paddr->cr);
553 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
5fd8f738 554}
5f3cc447
SN		 555
556int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
df7e09a3 557 struct s5p_fimc_isp_info *cam)
5f3cc447 558{
c83a1ff0 559 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447 560
c83a1ff0
SN		 561 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
562 FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC |
563 FIMC_REG_CIGCTRL_INVPOLFIELD);
5f3cc447 564
12ecf56d 565 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
c83a1ff0 566 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
5f3cc447 567
12ecf56d 568 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
c83a1ff0 569 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
5f3cc447 570
12ecf56d 571 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
c83a1ff0 572 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
5f3cc447 573
12ecf56d 574 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
c83a1ff0 575 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
5f3cc447 576
12ecf56d 577 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
c83a1ff0 578 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
12ecf56d 579
c83a1ff0 580 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 581
582 return 0;
583}
584
c83a1ff0
SN		 585struct mbus_pixfmt_desc {
586 u32 pixelcode;
587 u32 cisrcfmt;
588 u16 bus_width;
589};
590
591static const struct mbus_pixfmt_desc pix_desc[] = {
592 { V4L2_MBUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 },
593 { V4L2_MBUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 },
594 { V4L2_MBUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 },
595 { V4L2_MBUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 },
596};
597
5f3cc447 598int fimc_hw_set_camera_source(struct fimc_dev *fimc,
df7e09a3 599 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 600{
601 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
602 u32 cfg = 0;
3d0ce7ed
SN		 603 u32 bus_width;
604 int i;
605
5f3cc447 606 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
3d0ce7ed 607 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
237e0265 608 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
3d0ce7ed
SN		 609 cfg = pix_desc[i].cisrcfmt;
610 bus_width = pix_desc[i].bus_width;
611 break;
612 }
613 }
5f3cc447 614
3d0ce7ed 615 if (i == ARRAY_SIZE(pix_desc)) {
31d34d9b 616 v4l2_err(&fimc->vid_cap.vfd,
3d0ce7ed 617 "Camera color format not supported: %d\n",
237e0265 618 fimc->vid_cap.mf.code);
5f3cc447
SN		 619 return -EINVAL;
620 }
621
622 if (cam->bus_type == FIMC_ITU_601) {
3d0ce7ed 623 if (bus_width == 8)
c83a1ff0 624 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
3d0ce7ed 625 else if (bus_width == 16)
c83a1ff0 626 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
5f3cc447 627 } /* else defaults to ITU-R BT.656 8-bit */
ee7160e5 628 } else if (cam->bus_type == FIMC_MIPI_CSI2) {
14783d25 629 if (fimc_fmt_is_user_defined(f->fmt->color))
c83a1ff0 630 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
5f3cc447
SN		 631 }
632
c83a1ff0
SN		 633 cfg |= (f->o_width << 16) | f->o_height;
634 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
5f3cc447
SN		 635 return 0;
636}
637
c83a1ff0 638void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
5f3cc447
SN		 639{
640 u32 hoff2, voff2;
641
c83a1ff0 642 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
5f3cc447 643
c83a1ff0
SN		 644 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
645 cfg |= FIMC_REG_CIWDOFST_OFF_EN |
646 (f->offs_h << 16) | f->offs_v;
5f3cc447 647
c83a1ff0 648 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
5f3cc447
SN		 649
650 /* See CIWDOFSTn register description in the datasheet for details. */
651 hoff2 = f->o_width - f->width - f->offs_h;
652 voff2 = f->o_height - f->height - f->offs_v;
c83a1ff0
SN		 653 cfg = (hoff2 << 16) | voff2;
654 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
5f3cc447
SN		 655}
656
657int fimc_hw_set_camera_type(struct fimc_dev *fimc,
df7e09a3 658 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 659{
660 u32 cfg, tmp;
661 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
20676a4c 662 u32 csis_data_alignment = 32;
5f3cc447 663
c83a1ff0 664 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 665
666 /* Select ITU B interface, disable Writeback path and test pattern. */
c83a1ff0
SN		 667 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
668 FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB |
669 FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG);
5f3cc447 670
31ce54f6
SN		 671 switch (cam->bus_type) {
672 case FIMC_MIPI_CSI2:
c83a1ff0 673 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
5f3cc447
SN		 674
675 if (cam->mux_id == 0)
c83a1ff0 676 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
5f3cc447
SN		 677
678 /* TODO: add remaining supported formats. */
ee7160e5
SN		 679 switch (vid_cap->mf.code) {
680 case V4L2_MBUS_FMT_VYUY8_2X8:
c83a1ff0 681 tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
ee7160e5
SN		 682 break;
683 case V4L2_MBUS_FMT_JPEG_1X8:
14783d25 684 case V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8:
c83a1ff0
SN		 685 tmp = FIMC_REG_CSIIMGFMT_USER(1);
686 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
ee7160e5
SN		 687 break;
688 default:
31d34d9b 689 v4l2_err(&vid_cap->vfd,
a516d08f 690 "Not supported camera pixel format: %#x\n",
237e0265 691 vid_cap->mf.code);
5f3cc447
SN		 692 return -EINVAL;
693 }
20676a4c 694 tmp |= (csis_data_alignment == 32) << 8;
e0eec9af 695
c83a1ff0 696 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
31ce54f6
SN		 697 break;
698 case FIMC_ITU_601...FIMC_ITU_656:
5f3cc447 699 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
c83a1ff0 700 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
31ce54f6
SN		 701 break;
702 case FIMC_LCD_WB:
c83a1ff0 703 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
31ce54f6
SN		 704 break;
705 default:
31d34d9b 706 v4l2_err(&vid_cap->vfd, "Invalid camera bus type selected\n");
5f3cc447
SN		 707 return -EINVAL;
708 }
c83a1ff0 709 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 710
711 return 0;
712}
c83a1ff0
SN		 713
714void fimc_hw_clear_irq(struct fimc_dev *dev)
715{
716 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
717 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
718 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
719}
720
721void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
722{
723 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
724 if (on)
725 cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
726 else
727 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
728 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
729}
730
731void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
732{
733 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
734 if (on)
735 cfg |= FIMC_REG_MSCTRL_ENVID;
736 else
737 cfg &= ~FIMC_REG_MSCTRL_ENVID;
738 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
739}
740
c83a1ff0 741/* Return an index to the buffer actually being written. */
14783d25 742s32 fimc_hw_get_frame_index(struct fimc_dev *dev)
c83a1ff0 743{
14783d25 744 s32 reg;
c83a1ff0
SN		 745
746 if (dev->variant->has_cistatus2) {
14783d25
SN		 747 reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f;
748 return reg - 1;
c83a1ff0
SN		 749 }
750
751 reg = readl(dev->regs + FIMC_REG_CISTATUS);
752
753 return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >>
754 FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
755}
756
14783d25
SN		 757/* Return an index to the buffer being written previously. */
758s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev)
759{
760 s32 reg;
761
762 if (!dev->variant->has_cistatus2)
763 return -1;
764
765 reg = readl(dev->regs + FIMC_REG_CISTATUS2);
766 return ((reg >> 7) & 0x3f) - 1;
767}
768
c83a1ff0
SN		 769/* Locking: the caller holds fimc->slock */
770void fimc_activate_capture(struct fimc_ctx *ctx)
771{
772 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
35f29248 773 fimc_hw_enable_capture(ctx);
c83a1ff0
SN		 774}
775
776void fimc_deactivate_capture(struct fimc_dev *fimc)
777{
778 fimc_hw_en_lastirq(fimc, true);
35f29248 779 fimc_hw_disable_capture(fimc);
c83a1ff0
SN		 780 fimc_hw_enable_scaler(fimc, false);
781 fimc_hw_en_lastirq(fimc, false);
782}
Linux kernel - Deliverables
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