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b5f1220d SN |
1 | /* |
2 | * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver | |
3 | * | |
a1212162 | 4 | * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd. |
29de2337 | 5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> |
b5f1220d SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/memory.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <media/v4l2-subdev.h> | |
436d42c6 | 29 | #include <linux/platform_data/mipi-csis.h> |
b5f1220d SN |
30 | #include "mipi-csis.h" |
31 | ||
32 | static int debug; | |
33 | module_param(debug, int, 0644); | |
99c6902c | 34 | MODULE_PARM_DESC(debug, "Debug level (0-2)"); |
b5f1220d SN |
35 | |
36 | /* Register map definition */ | |
37 | ||
38 | /* CSIS global control */ | |
39 | #define S5PCSIS_CTRL 0x00 | |
40 | #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31) | |
41 | #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31) | |
42 | #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20) | |
43 | #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16) | |
44 | #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8) | |
45 | #define S5PCSIS_CTRL_RESET (1 << 4) | |
46 | #define S5PCSIS_CTRL_ENABLE (1 << 0) | |
47 | ||
48 | /* D-PHY control */ | |
49 | #define S5PCSIS_DPHYCTRL 0x04 | |
50 | #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27) | |
51 | #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0) | |
52 | ||
53 | #define S5PCSIS_CONFIG 0x08 | |
54 | #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2) | |
55 | #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2) | |
56 | #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2) | |
57 | #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2) | |
58 | /* User defined formats, x = 1...4 */ | |
59 | #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2) | |
60 | #define S5PCSIS_CFG_FMT_MASK (0x3f << 2) | |
61 | #define S5PCSIS_CFG_NR_LANE_MASK 3 | |
62 | ||
99c6902c | 63 | /* Interrupt mask */ |
b5f1220d | 64 | #define S5PCSIS_INTMSK 0x10 |
99c6902c SN |
65 | #define S5PCSIS_INTMSK_EN_ALL 0xf000103f |
66 | #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31) | |
67 | #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30) | |
68 | #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29) | |
69 | #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28) | |
70 | #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12) | |
71 | #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5) | |
72 | #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4) | |
73 | #define S5PCSIS_INTMSK_ERR_OVER (1 << 3) | |
74 | #define S5PCSIS_INTMSK_ERR_ECC (1 << 2) | |
75 | #define S5PCSIS_INTMSK_ERR_CRC (1 << 1) | |
76 | #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0) | |
77 | ||
78 | /* Interrupt source */ | |
b5f1220d | 79 | #define S5PCSIS_INTSRC 0x14 |
99c6902c SN |
80 | #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31) |
81 | #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30) | |
82 | #define S5PCSIS_INTSRC_EVEN (0x3 << 30) | |
83 | #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29) | |
84 | #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28) | |
85 | #define S5PCSIS_INTSRC_ODD (0x3 << 28) | |
86 | #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28) | |
87 | #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12) | |
88 | #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5) | |
89 | #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4) | |
90 | #define S5PCSIS_INTSRC_ERR_OVER (1 << 3) | |
91 | #define S5PCSIS_INTSRC_ERR_ECC (1 << 2) | |
92 | #define S5PCSIS_INTSRC_ERR_CRC (1 << 1) | |
93 | #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0) | |
94 | #define S5PCSIS_INTSRC_ERRORS 0xf03f | |
b5f1220d SN |
95 | |
96 | /* Pixel resolution */ | |
97 | #define S5PCSIS_RESOL 0x2c | |
98 | #define CSIS_MAX_PIX_WIDTH 0xffff | |
99 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
100 | ||
36fa8092 SN |
101 | /* Non-image packet data buffers */ |
102 | #define S5PCSIS_PKTDATA_ODD 0x2000 | |
103 | #define S5PCSIS_PKTDATA_EVEN 0x3000 | |
104 | #define S5PCSIS_PKTDATA_SIZE SZ_4K | |
105 | ||
b5f1220d SN |
106 | enum { |
107 | CSIS_CLK_MUX, | |
108 | CSIS_CLK_GATE, | |
109 | }; | |
110 | ||
111 | static char *csi_clock_name[] = { | |
112 | [CSIS_CLK_MUX] = "sclk_csis", | |
113 | [CSIS_CLK_GATE] = "csis", | |
114 | }; | |
115 | #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name) | |
116 | ||
438df3eb | 117 | static const char * const csis_supply_name[] = { |
29de2337 SN |
118 | "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */ |
119 | "vddio", /* CSIS I/O and PLL (1.8V) supply */ | |
438df3eb SN |
120 | }; |
121 | #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name) | |
122 | ||
b5f1220d SN |
123 | enum { |
124 | ST_POWERED = 1, | |
125 | ST_STREAMING = 2, | |
126 | ST_SUSPENDED = 4, | |
127 | }; | |
128 | ||
99c6902c SN |
129 | struct s5pcsis_event { |
130 | u32 mask; | |
131 | const char * const name; | |
132 | unsigned int counter; | |
133 | }; | |
134 | ||
135 | static const struct s5pcsis_event s5pcsis_events[] = { | |
136 | /* Errors */ | |
137 | { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" }, | |
138 | { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" }, | |
139 | { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" }, | |
140 | { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" }, | |
141 | { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" }, | |
142 | { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" }, | |
143 | { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" }, | |
144 | /* Non-image data receive events */ | |
145 | { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" }, | |
146 | { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" }, | |
147 | { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" }, | |
148 | { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" }, | |
149 | }; | |
150 | #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events) | |
151 | ||
36fa8092 SN |
152 | struct csis_pktbuf { |
153 | u32 *data; | |
154 | unsigned int len; | |
155 | }; | |
156 | ||
b5f1220d SN |
157 | /** |
158 | * struct csis_state - the driver's internal state data structure | |
159 | * @lock: mutex serializing the subdev and power management operations, | |
160 | * protecting @format and @flags members | |
161 | * @pads: CSIS pads array | |
162 | * @sd: v4l2_subdev associated with CSIS device instance | |
ccbfd1d4 | 163 | * @index: the hardware instance index |
b5f1220d | 164 | * @pdev: CSIS platform device |
b5f1220d | 165 | * @regs: mmaped I/O registers memory |
99c6902c | 166 | * @supplies: CSIS regulator supplies |
b5f1220d SN |
167 | * @clock: CSIS clocks |
168 | * @irq: requested s5p-mipi-csis irq number | |
169 | * @flags: the state variable for power and streaming control | |
170 | * @csis_fmt: current CSIS pixel format | |
171 | * @format: common media bus format for the source and sink pad | |
99c6902c | 172 | * @slock: spinlock protecting structure members below |
36fa8092 | 173 | * @pkt_buf: the frame embedded (non-image) data buffer |
99c6902c | 174 | * @events: MIPI-CSIS event (error) counters |
b5f1220d SN |
175 | */ |
176 | struct csis_state { | |
177 | struct mutex lock; | |
178 | struct media_pad pads[CSIS_PADS_NUM]; | |
179 | struct v4l2_subdev sd; | |
ccbfd1d4 | 180 | u8 index; |
b5f1220d | 181 | struct platform_device *pdev; |
b5f1220d | 182 | void __iomem *regs; |
438df3eb | 183 | struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES]; |
b5f1220d SN |
184 | struct clk *clock[NUM_CSIS_CLOCKS]; |
185 | int irq; | |
b5f1220d SN |
186 | u32 flags; |
187 | const struct csis_pix_format *csis_fmt; | |
188 | struct v4l2_mbus_framefmt format; | |
99c6902c SN |
189 | |
190 | struct spinlock slock; | |
36fa8092 | 191 | struct csis_pktbuf pkt_buf; |
99c6902c | 192 | struct s5pcsis_event events[S5PCSIS_NUM_EVENTS]; |
b5f1220d SN |
193 | }; |
194 | ||
195 | /** | |
196 | * struct csis_pix_format - CSIS pixel format description | |
197 | * @pix_width_alignment: horizontal pixel alignment, width will be | |
198 | * multiple of 2^pix_width_alignment | |
199 | * @code: corresponding media bus code | |
200 | * @fmt_reg: S5PCSIS_CONFIG register value | |
20676a4c | 201 | * @data_alignment: MIPI-CSI data alignment in bits |
b5f1220d SN |
202 | */ |
203 | struct csis_pix_format { | |
204 | unsigned int pix_width_alignment; | |
205 | enum v4l2_mbus_pixelcode code; | |
206 | u32 fmt_reg; | |
20676a4c | 207 | u8 data_alignment; |
b5f1220d SN |
208 | }; |
209 | ||
210 | static const struct csis_pix_format s5pcsis_formats[] = { | |
211 | { | |
212 | .code = V4L2_MBUS_FMT_VYUY8_2X8, | |
213 | .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT, | |
20676a4c | 214 | .data_alignment = 32, |
b5f1220d SN |
215 | }, { |
216 | .code = V4L2_MBUS_FMT_JPEG_1X8, | |
217 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
20676a4c | 218 | .data_alignment = 32, |
14783d25 SN |
219 | }, { |
220 | .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
221 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
222 | .data_alignment = 32, | |
e26991b4 SN |
223 | }, { |
224 | .code = V4L2_MBUS_FMT_SGRBG8_1X8, | |
225 | .fmt_reg = S5PCSIS_CFG_FMT_RAW8, | |
226 | .data_alignment = 24, | |
227 | }, { | |
228 | .code = V4L2_MBUS_FMT_SGRBG10_1X10, | |
229 | .fmt_reg = S5PCSIS_CFG_FMT_RAW10, | |
230 | .data_alignment = 24, | |
231 | }, { | |
232 | .code = V4L2_MBUS_FMT_SGRBG12_1X12, | |
233 | .fmt_reg = S5PCSIS_CFG_FMT_RAW12, | |
234 | .data_alignment = 24, | |
14783d25 | 235 | } |
b5f1220d SN |
236 | }; |
237 | ||
238 | #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) | |
239 | #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r) | |
240 | ||
241 | static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev) | |
242 | { | |
243 | return container_of(sdev, struct csis_state, sd); | |
244 | } | |
245 | ||
246 | static const struct csis_pix_format *find_csis_format( | |
247 | struct v4l2_mbus_framefmt *mf) | |
248 | { | |
249 | int i; | |
250 | ||
251 | for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++) | |
252 | if (mf->code == s5pcsis_formats[i].code) | |
253 | return &s5pcsis_formats[i]; | |
254 | return NULL; | |
255 | } | |
256 | ||
257 | static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) | |
258 | { | |
259 | u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); | |
260 | ||
261 | val = on ? val | S5PCSIS_INTMSK_EN_ALL : | |
262 | val & ~S5PCSIS_INTMSK_EN_ALL; | |
263 | s5pcsis_write(state, S5PCSIS_INTMSK, val); | |
264 | } | |
265 | ||
266 | static void s5pcsis_reset(struct csis_state *state) | |
267 | { | |
268 | u32 val = s5pcsis_read(state, S5PCSIS_CTRL); | |
269 | ||
270 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); | |
271 | udelay(10); | |
272 | } | |
273 | ||
274 | static void s5pcsis_system_enable(struct csis_state *state, int on) | |
275 | { | |
cd65a645 SN |
276 | struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data; |
277 | u32 val, mask; | |
b5f1220d SN |
278 | |
279 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
280 | if (on) | |
281 | val |= S5PCSIS_CTRL_ENABLE; | |
282 | else | |
283 | val &= ~S5PCSIS_CTRL_ENABLE; | |
284 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
285 | ||
286 | val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
cd65a645 SN |
287 | val &= ~S5PCSIS_DPHYCTRL_ENABLE; |
288 | if (on) { | |
289 | mask = (1 << (pdata->lanes + 1)) - 1; | |
290 | val |= (mask & S5PCSIS_DPHYCTRL_ENABLE); | |
291 | } | |
b5f1220d SN |
292 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); |
293 | } | |
294 | ||
295 | /* Called with the state.lock mutex held */ | |
296 | static void __s5pcsis_set_format(struct csis_state *state) | |
297 | { | |
298 | struct v4l2_mbus_framefmt *mf = &state->format; | |
299 | u32 val; | |
300 | ||
14783d25 | 301 | v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", |
b5f1220d SN |
302 | mf->code, mf->width, mf->height); |
303 | ||
304 | /* Color format */ | |
305 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
306 | val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; | |
307 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
308 | ||
309 | /* Pixel resolution */ | |
310 | val = (mf->width << 16) | mf->height; | |
311 | s5pcsis_write(state, S5PCSIS_RESOL, val); | |
312 | } | |
313 | ||
314 | static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) | |
315 | { | |
316 | u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
317 | ||
318 | val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); | |
319 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
320 | } | |
321 | ||
322 | static void s5pcsis_set_params(struct csis_state *state) | |
323 | { | |
324 | struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data; | |
325 | u32 val; | |
326 | ||
327 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
328 | val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1); | |
329 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
330 | ||
331 | __s5pcsis_set_format(state); | |
332 | s5pcsis_set_hsync_settle(state, pdata->hs_settle); | |
333 | ||
334 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
20676a4c | 335 | if (state->csis_fmt->data_alignment == 32) |
b5f1220d SN |
336 | val |= S5PCSIS_CTRL_ALIGN_32BIT; |
337 | else /* 24-bits */ | |
338 | val &= ~S5PCSIS_CTRL_ALIGN_32BIT; | |
65214a86 | 339 | |
b5f1220d | 340 | val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; |
65214a86 SN |
341 | if (pdata->wclk_source) |
342 | val |= S5PCSIS_CTRL_WCLK_EXTCLK; | |
b5f1220d SN |
343 | s5pcsis_write(state, S5PCSIS_CTRL, val); |
344 | ||
345 | /* Update the shadow register. */ | |
346 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
347 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); | |
348 | } | |
349 | ||
350 | static void s5pcsis_clk_put(struct csis_state *state) | |
351 | { | |
352 | int i; | |
353 | ||
bd7d8888 SN |
354 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { |
355 | if (IS_ERR_OR_NULL(state->clock[i])) | |
356 | continue; | |
357 | clk_unprepare(state->clock[i]); | |
358 | clk_put(state->clock[i]); | |
359 | state->clock[i] = NULL; | |
360 | } | |
b5f1220d SN |
361 | } |
362 | ||
363 | static int s5pcsis_clk_get(struct csis_state *state) | |
364 | { | |
365 | struct device *dev = &state->pdev->dev; | |
bd7d8888 | 366 | int i, ret; |
b5f1220d SN |
367 | |
368 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { | |
369 | state->clock[i] = clk_get(dev, csi_clock_name[i]); | |
bd7d8888 SN |
370 | if (IS_ERR(state->clock[i])) |
371 | goto err; | |
372 | ret = clk_prepare(state->clock[i]); | |
373 | if (ret < 0) { | |
374 | clk_put(state->clock[i]); | |
375 | state->clock[i] = NULL; | |
376 | goto err; | |
b5f1220d SN |
377 | } |
378 | } | |
379 | return 0; | |
bd7d8888 SN |
380 | err: |
381 | s5pcsis_clk_put(state); | |
382 | dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]); | |
383 | return -ENXIO; | |
b5f1220d SN |
384 | } |
385 | ||
a2fea0df SN |
386 | static void dump_regs(struct csis_state *state, const char *label) |
387 | { | |
388 | struct { | |
389 | u32 offset; | |
390 | const char * const name; | |
391 | } registers[] = { | |
392 | { 0x00, "CTRL" }, | |
393 | { 0x04, "DPHYCTRL" }, | |
394 | { 0x08, "CONFIG" }, | |
395 | { 0x0c, "DPHYSTS" }, | |
396 | { 0x10, "INTMSK" }, | |
397 | { 0x2c, "RESOL" }, | |
398 | { 0x38, "SDW_CONFIG" }, | |
399 | }; | |
400 | u32 i; | |
401 | ||
402 | v4l2_info(&state->sd, "--- %s ---\n", label); | |
403 | ||
404 | for (i = 0; i < ARRAY_SIZE(registers); i++) { | |
405 | u32 cfg = s5pcsis_read(state, registers[i].offset); | |
406 | v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg); | |
407 | } | |
408 | } | |
409 | ||
b5f1220d SN |
410 | static void s5pcsis_start_stream(struct csis_state *state) |
411 | { | |
412 | s5pcsis_reset(state); | |
413 | s5pcsis_set_params(state); | |
414 | s5pcsis_system_enable(state, true); | |
415 | s5pcsis_enable_interrupts(state, true); | |
416 | } | |
417 | ||
418 | static void s5pcsis_stop_stream(struct csis_state *state) | |
419 | { | |
420 | s5pcsis_enable_interrupts(state, false); | |
421 | s5pcsis_system_enable(state, false); | |
422 | } | |
423 | ||
99c6902c SN |
424 | static void s5pcsis_clear_counters(struct csis_state *state) |
425 | { | |
426 | unsigned long flags; | |
427 | int i; | |
428 | ||
429 | spin_lock_irqsave(&state->slock, flags); | |
430 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) | |
431 | state->events[i].counter = 0; | |
432 | spin_unlock_irqrestore(&state->slock, flags); | |
433 | } | |
434 | ||
435 | static void s5pcsis_log_counters(struct csis_state *state, bool non_errors) | |
436 | { | |
437 | int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4; | |
438 | unsigned long flags; | |
439 | ||
440 | spin_lock_irqsave(&state->slock, flags); | |
441 | ||
ef2c8326 SN |
442 | for (i--; i >= 0; i--) { |
443 | if (state->events[i].counter > 0 || debug) | |
99c6902c SN |
444 | v4l2_info(&state->sd, "%s events: %d\n", |
445 | state->events[i].name, | |
446 | state->events[i].counter); | |
ef2c8326 | 447 | } |
99c6902c SN |
448 | spin_unlock_irqrestore(&state->slock, flags); |
449 | } | |
450 | ||
451 | /* | |
452 | * V4L2 subdev operations | |
453 | */ | |
454 | static int s5pcsis_s_power(struct v4l2_subdev *sd, int on) | |
455 | { | |
456 | struct csis_state *state = sd_to_csis_state(sd); | |
457 | struct device *dev = &state->pdev->dev; | |
458 | ||
459 | if (on) | |
460 | return pm_runtime_get_sync(dev); | |
461 | ||
462 | return pm_runtime_put_sync(dev); | |
463 | } | |
464 | ||
b5f1220d SN |
465 | static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable) |
466 | { | |
467 | struct csis_state *state = sd_to_csis_state(sd); | |
468 | int ret = 0; | |
469 | ||
470 | v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", | |
471 | __func__, enable, state->flags); | |
472 | ||
473 | if (enable) { | |
99c6902c | 474 | s5pcsis_clear_counters(state); |
b5f1220d SN |
475 | ret = pm_runtime_get_sync(&state->pdev->dev); |
476 | if (ret && ret != 1) | |
477 | return ret; | |
478 | } | |
99c6902c | 479 | |
b5f1220d SN |
480 | mutex_lock(&state->lock); |
481 | if (enable) { | |
482 | if (state->flags & ST_SUSPENDED) { | |
483 | ret = -EBUSY; | |
484 | goto unlock; | |
485 | } | |
486 | s5pcsis_start_stream(state); | |
487 | state->flags |= ST_STREAMING; | |
488 | } else { | |
489 | s5pcsis_stop_stream(state); | |
490 | state->flags &= ~ST_STREAMING; | |
99c6902c SN |
491 | if (debug > 0) |
492 | s5pcsis_log_counters(state, true); | |
b5f1220d SN |
493 | } |
494 | unlock: | |
495 | mutex_unlock(&state->lock); | |
496 | if (!enable) | |
497 | pm_runtime_put(&state->pdev->dev); | |
498 | ||
499 | return ret == 1 ? 0 : ret; | |
500 | } | |
501 | ||
502 | static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd, | |
503 | struct v4l2_subdev_fh *fh, | |
504 | struct v4l2_subdev_mbus_code_enum *code) | |
505 | { | |
506 | if (code->index >= ARRAY_SIZE(s5pcsis_formats)) | |
507 | return -EINVAL; | |
508 | ||
509 | code->code = s5pcsis_formats[code->index].code; | |
510 | return 0; | |
511 | } | |
512 | ||
513 | static struct csis_pix_format const *s5pcsis_try_format( | |
514 | struct v4l2_mbus_framefmt *mf) | |
515 | { | |
516 | struct csis_pix_format const *csis_fmt; | |
517 | ||
518 | csis_fmt = find_csis_format(mf); | |
519 | if (csis_fmt == NULL) | |
520 | csis_fmt = &s5pcsis_formats[0]; | |
521 | ||
522 | mf->code = csis_fmt->code; | |
523 | v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH, | |
524 | csis_fmt->pix_width_alignment, | |
525 | &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1, | |
526 | 0); | |
527 | return csis_fmt; | |
528 | } | |
529 | ||
530 | static struct v4l2_mbus_framefmt *__s5pcsis_get_format( | |
531 | struct csis_state *state, struct v4l2_subdev_fh *fh, | |
532 | u32 pad, enum v4l2_subdev_format_whence which) | |
533 | { | |
534 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
535 | return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL; | |
536 | ||
537 | return &state->format; | |
538 | } | |
539 | ||
540 | static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
541 | struct v4l2_subdev_format *fmt) | |
542 | { | |
543 | struct csis_state *state = sd_to_csis_state(sd); | |
544 | struct csis_pix_format const *csis_fmt; | |
545 | struct v4l2_mbus_framefmt *mf; | |
546 | ||
547 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
548 | return -EINVAL; | |
549 | ||
550 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
551 | ||
552 | if (fmt->pad == CSIS_PAD_SOURCE) { | |
553 | if (mf) { | |
554 | mutex_lock(&state->lock); | |
555 | fmt->format = *mf; | |
556 | mutex_unlock(&state->lock); | |
557 | } | |
558 | return 0; | |
559 | } | |
560 | csis_fmt = s5pcsis_try_format(&fmt->format); | |
561 | if (mf) { | |
562 | mutex_lock(&state->lock); | |
563 | *mf = fmt->format; | |
564 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
565 | state->csis_fmt = csis_fmt; | |
566 | mutex_unlock(&state->lock); | |
567 | } | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
572 | struct v4l2_subdev_format *fmt) | |
573 | { | |
574 | struct csis_state *state = sd_to_csis_state(sd); | |
575 | struct v4l2_mbus_framefmt *mf; | |
576 | ||
577 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
578 | return -EINVAL; | |
579 | ||
580 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
581 | if (!mf) | |
582 | return -EINVAL; | |
583 | ||
584 | mutex_lock(&state->lock); | |
585 | fmt->format = *mf; | |
586 | mutex_unlock(&state->lock); | |
587 | return 0; | |
588 | } | |
589 | ||
36fa8092 SN |
590 | static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf, |
591 | unsigned int *size) | |
592 | { | |
593 | struct csis_state *state = sd_to_csis_state(sd); | |
594 | unsigned long flags; | |
595 | ||
596 | *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE); | |
597 | ||
598 | spin_lock_irqsave(&state->slock, flags); | |
599 | state->pkt_buf.data = buf; | |
600 | state->pkt_buf.len = *size; | |
601 | spin_unlock_irqrestore(&state->slock, flags); | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
99c6902c SN |
606 | static int s5pcsis_log_status(struct v4l2_subdev *sd) |
607 | { | |
608 | struct csis_state *state = sd_to_csis_state(sd); | |
609 | ||
a2fea0df | 610 | mutex_lock(&state->lock); |
99c6902c | 611 | s5pcsis_log_counters(state, true); |
a2fea0df SN |
612 | if (debug && (state->flags & ST_POWERED)) |
613 | dump_regs(state, __func__); | |
614 | mutex_unlock(&state->lock); | |
99c6902c SN |
615 | return 0; |
616 | } | |
617 | ||
6cf1056f SN |
618 | static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
619 | { | |
620 | struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0); | |
621 | ||
622 | format->colorspace = V4L2_COLORSPACE_JPEG; | |
623 | format->code = s5pcsis_formats[0].code; | |
624 | format->width = S5PCSIS_DEF_PIX_WIDTH; | |
625 | format->height = S5PCSIS_DEF_PIX_HEIGHT; | |
626 | format->field = V4L2_FIELD_NONE; | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = { | |
632 | .open = s5pcsis_open, | |
633 | }; | |
634 | ||
b5f1220d SN |
635 | static struct v4l2_subdev_core_ops s5pcsis_core_ops = { |
636 | .s_power = s5pcsis_s_power, | |
99c6902c | 637 | .log_status = s5pcsis_log_status, |
b5f1220d SN |
638 | }; |
639 | ||
640 | static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = { | |
641 | .enum_mbus_code = s5pcsis_enum_mbus_code, | |
642 | .get_fmt = s5pcsis_get_fmt, | |
643 | .set_fmt = s5pcsis_set_fmt, | |
644 | }; | |
645 | ||
646 | static struct v4l2_subdev_video_ops s5pcsis_video_ops = { | |
36fa8092 | 647 | .s_rx_buffer = s5pcsis_s_rx_buffer, |
b5f1220d SN |
648 | .s_stream = s5pcsis_s_stream, |
649 | }; | |
650 | ||
651 | static struct v4l2_subdev_ops s5pcsis_subdev_ops = { | |
652 | .core = &s5pcsis_core_ops, | |
653 | .pad = &s5pcsis_pad_ops, | |
654 | .video = &s5pcsis_video_ops, | |
655 | }; | |
656 | ||
657 | static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id) | |
658 | { | |
659 | struct csis_state *state = dev_id; | |
36fa8092 | 660 | struct csis_pktbuf *pktbuf = &state->pkt_buf; |
99c6902c SN |
661 | unsigned long flags; |
662 | u32 status; | |
663 | ||
664 | status = s5pcsis_read(state, S5PCSIS_INTSRC); | |
99c6902c SN |
665 | spin_lock_irqsave(&state->slock, flags); |
666 | ||
36fa8092 SN |
667 | if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) { |
668 | u32 offset; | |
669 | ||
670 | if (status & S5PCSIS_INTSRC_EVEN) | |
671 | offset = S5PCSIS_PKTDATA_EVEN; | |
672 | else | |
673 | offset = S5PCSIS_PKTDATA_ODD; | |
674 | ||
675 | memcpy(pktbuf->data, state->regs + offset, pktbuf->len); | |
676 | pktbuf->data = NULL; | |
677 | rmb(); | |
678 | } | |
679 | ||
99c6902c SN |
680 | /* Update the event/error counters */ |
681 | if ((status & S5PCSIS_INTSRC_ERRORS) || debug) { | |
682 | int i; | |
683 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) { | |
684 | if (!(status & state->events[i].mask)) | |
685 | continue; | |
686 | state->events[i].counter++; | |
687 | v4l2_dbg(2, debug, &state->sd, "%s: %d\n", | |
688 | state->events[i].name, | |
689 | state->events[i].counter); | |
690 | } | |
691 | v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); | |
692 | } | |
693 | spin_unlock_irqrestore(&state->slock, flags); | |
b5f1220d | 694 | |
99c6902c | 695 | s5pcsis_write(state, S5PCSIS_INTSRC, status); |
b5f1220d SN |
696 | return IRQ_HANDLED; |
697 | } | |
698 | ||
699 | static int __devinit s5pcsis_probe(struct platform_device *pdev) | |
700 | { | |
701 | struct s5p_platform_mipi_csis *pdata; | |
702 | struct resource *mem_res; | |
b5f1220d SN |
703 | struct csis_state *state; |
704 | int ret = -ENOMEM; | |
438df3eb | 705 | int i; |
b5f1220d | 706 | |
a1212162 | 707 | state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL); |
b5f1220d SN |
708 | if (!state) |
709 | return -ENOMEM; | |
710 | ||
711 | mutex_init(&state->lock); | |
99c6902c SN |
712 | spin_lock_init(&state->slock); |
713 | ||
b5f1220d | 714 | state->pdev = pdev; |
ccbfd1d4 | 715 | state->index = max(0, pdev->id); |
b5f1220d SN |
716 | |
717 | pdata = pdev->dev.platform_data; | |
ccbfd1d4 | 718 | if (pdata == NULL) { |
b5f1220d | 719 | dev_err(&pdev->dev, "Platform data not fully specified\n"); |
a1212162 | 720 | return -EINVAL; |
b5f1220d SN |
721 | } |
722 | ||
ccbfd1d4 | 723 | if ((state->index == 1 && pdata->lanes > CSIS1_MAX_LANES) || |
b5f1220d | 724 | pdata->lanes > CSIS0_MAX_LANES) { |
b5f1220d SN |
725 | dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n", |
726 | pdata->lanes); | |
a1212162 | 727 | return -EINVAL; |
b5f1220d SN |
728 | } |
729 | ||
730 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a1212162 SN |
731 | state->regs = devm_request_and_ioremap(&pdev->dev, mem_res); |
732 | if (state->regs == NULL) { | |
733 | dev_err(&pdev->dev, "Failed to request and remap io memory\n"); | |
734 | return -ENXIO; | |
b5f1220d | 735 | } |
b5f1220d SN |
736 | |
737 | state->irq = platform_get_irq(pdev, 0); | |
738 | if (state->irq < 0) { | |
b5f1220d | 739 | dev_err(&pdev->dev, "Failed to get irq\n"); |
a1212162 | 740 | return state->irq; |
b5f1220d SN |
741 | } |
742 | ||
438df3eb SN |
743 | for (i = 0; i < CSIS_NUM_SUPPLIES; i++) |
744 | state->supplies[i].supply = csis_supply_name[i]; | |
745 | ||
746 | ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES, | |
747 | state->supplies); | |
a1212162 SN |
748 | if (ret) |
749 | return ret; | |
750 | ||
751 | ret = s5pcsis_clk_get(state); | |
438df3eb SN |
752 | if (ret) |
753 | goto e_clkput; | |
b5f1220d | 754 | |
a1212162 SN |
755 | clk_enable(state->clock[CSIS_CLK_MUX]); |
756 | if (pdata->clk_rate) | |
757 | clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate); | |
758 | else | |
759 | dev_WARN(&pdev->dev, "No clock frequency specified!\n"); | |
760 | ||
761 | ret = devm_request_irq(&pdev->dev, state->irq, s5pcsis_irq_handler, | |
762 | 0, dev_name(&pdev->dev), state); | |
b5f1220d | 763 | if (ret) { |
a1212162 | 764 | dev_err(&pdev->dev, "Interrupt request failed\n"); |
b5f1220d SN |
765 | goto e_regput; |
766 | } | |
767 | ||
768 | v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); | |
769 | state->sd.owner = THIS_MODULE; | |
770 | strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name)); | |
6cf1056f | 771 | state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
b5f1220d SN |
772 | state->csis_fmt = &s5pcsis_formats[0]; |
773 | ||
6cf1056f SN |
774 | state->format.code = s5pcsis_formats[0].code; |
775 | state->format.width = S5PCSIS_DEF_PIX_WIDTH; | |
776 | state->format.height = S5PCSIS_DEF_PIX_HEIGHT; | |
777 | ||
b5f1220d SN |
778 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
779 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
780 | ret = media_entity_init(&state->sd.entity, | |
781 | CSIS_PADS_NUM, state->pads, 0); | |
782 | if (ret < 0) | |
a1212162 | 783 | goto e_clkput; |
b5f1220d SN |
784 | |
785 | /* This allows to retrieve the platform device id by the host driver */ | |
786 | v4l2_set_subdevdata(&state->sd, pdev); | |
787 | ||
788 | /* .. and a pointer to the subdev. */ | |
789 | platform_set_drvdata(pdev, &state->sd); | |
790 | ||
99c6902c SN |
791 | memcpy(state->events, s5pcsis_events, sizeof(state->events)); |
792 | ||
b5f1220d | 793 | pm_runtime_enable(&pdev->dev); |
b5f1220d SN |
794 | return 0; |
795 | ||
b5f1220d | 796 | e_regput: |
438df3eb | 797 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
798 | e_clkput: |
799 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
800 | s5pcsis_clk_put(state); | |
b5f1220d SN |
801 | return ret; |
802 | } | |
803 | ||
d4d4e3c9 | 804 | static int s5pcsis_pm_suspend(struct device *dev, bool runtime) |
b5f1220d | 805 | { |
b5f1220d SN |
806 | struct platform_device *pdev = to_platform_device(dev); |
807 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
808 | struct csis_state *state = sd_to_csis_state(sd); | |
c68956c1 | 809 | int ret = 0; |
b5f1220d SN |
810 | |
811 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
812 | __func__, state->flags); | |
813 | ||
814 | mutex_lock(&state->lock); | |
815 | if (state->flags & ST_POWERED) { | |
816 | s5pcsis_stop_stream(state); | |
ccbfd1d4 | 817 | ret = s5p_csis_phy_enable(state->index, false); |
b5f1220d SN |
818 | if (ret) |
819 | goto unlock; | |
438df3eb SN |
820 | ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES, |
821 | state->supplies); | |
822 | if (ret) | |
823 | goto unlock; | |
b5f1220d SN |
824 | clk_disable(state->clock[CSIS_CLK_GATE]); |
825 | state->flags &= ~ST_POWERED; | |
d4d4e3c9 SN |
826 | if (!runtime) |
827 | state->flags |= ST_SUSPENDED; | |
b5f1220d | 828 | } |
b5f1220d SN |
829 | unlock: |
830 | mutex_unlock(&state->lock); | |
831 | return ret ? -EAGAIN : 0; | |
832 | } | |
833 | ||
d4d4e3c9 | 834 | static int s5pcsis_pm_resume(struct device *dev, bool runtime) |
b5f1220d | 835 | { |
b5f1220d SN |
836 | struct platform_device *pdev = to_platform_device(dev); |
837 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
838 | struct csis_state *state = sd_to_csis_state(sd); | |
839 | int ret = 0; | |
840 | ||
841 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
842 | __func__, state->flags); | |
843 | ||
844 | mutex_lock(&state->lock); | |
d4d4e3c9 | 845 | if (!runtime && !(state->flags & ST_SUSPENDED)) |
b5f1220d SN |
846 | goto unlock; |
847 | ||
848 | if (!(state->flags & ST_POWERED)) { | |
438df3eb SN |
849 | ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES, |
850 | state->supplies); | |
b5f1220d SN |
851 | if (ret) |
852 | goto unlock; | |
ccbfd1d4 | 853 | ret = s5p_csis_phy_enable(state->index, true); |
b5f1220d SN |
854 | if (!ret) { |
855 | state->flags |= ST_POWERED; | |
438df3eb SN |
856 | } else { |
857 | regulator_bulk_disable(CSIS_NUM_SUPPLIES, | |
858 | state->supplies); | |
b5f1220d SN |
859 | goto unlock; |
860 | } | |
861 | clk_enable(state->clock[CSIS_CLK_GATE]); | |
862 | } | |
863 | if (state->flags & ST_STREAMING) | |
864 | s5pcsis_start_stream(state); | |
865 | ||
866 | state->flags &= ~ST_SUSPENDED; | |
867 | unlock: | |
868 | mutex_unlock(&state->lock); | |
869 | return ret ? -EAGAIN : 0; | |
870 | } | |
871 | ||
872 | #ifdef CONFIG_PM_SLEEP | |
d4d4e3c9 | 873 | static int s5pcsis_suspend(struct device *dev) |
b5f1220d | 874 | { |
d4d4e3c9 | 875 | return s5pcsis_pm_suspend(dev, false); |
b5f1220d SN |
876 | } |
877 | ||
d4d4e3c9 | 878 | static int s5pcsis_resume(struct device *dev) |
b5f1220d | 879 | { |
d4d4e3c9 SN |
880 | return s5pcsis_pm_resume(dev, false); |
881 | } | |
882 | #endif | |
b5f1220d | 883 | |
d4d4e3c9 SN |
884 | #ifdef CONFIG_PM_RUNTIME |
885 | static int s5pcsis_runtime_suspend(struct device *dev) | |
886 | { | |
887 | return s5pcsis_pm_suspend(dev, true); | |
888 | } | |
b5f1220d | 889 | |
d4d4e3c9 SN |
890 | static int s5pcsis_runtime_resume(struct device *dev) |
891 | { | |
892 | return s5pcsis_pm_resume(dev, true); | |
b5f1220d SN |
893 | } |
894 | #endif | |
895 | ||
896 | static int __devexit s5pcsis_remove(struct platform_device *pdev) | |
897 | { | |
898 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
899 | struct csis_state *state = sd_to_csis_state(sd); | |
b5f1220d SN |
900 | |
901 | pm_runtime_disable(&pdev->dev); | |
68a6bb54 | 902 | s5pcsis_pm_suspend(&pdev->dev, false); |
b5f1220d SN |
903 | clk_disable(state->clock[CSIS_CLK_MUX]); |
904 | pm_runtime_set_suspended(&pdev->dev); | |
b5f1220d | 905 | s5pcsis_clk_put(state); |
438df3eb | 906 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
907 | |
908 | media_entity_cleanup(&state->sd.entity); | |
b5f1220d SN |
909 | |
910 | return 0; | |
911 | } | |
912 | ||
913 | static const struct dev_pm_ops s5pcsis_pm_ops = { | |
d4d4e3c9 SN |
914 | SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume, |
915 | NULL) | |
916 | SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume) | |
b5f1220d SN |
917 | }; |
918 | ||
919 | static struct platform_driver s5pcsis_driver = { | |
920 | .probe = s5pcsis_probe, | |
921 | .remove = __devexit_p(s5pcsis_remove), | |
922 | .driver = { | |
923 | .name = CSIS_DRIVER_NAME, | |
924 | .owner = THIS_MODULE, | |
925 | .pm = &s5pcsis_pm_ops, | |
926 | }, | |
927 | }; | |
928 | ||
ecd9acbf | 929 | module_platform_driver(s5pcsis_driver); |
b5f1220d SN |
930 | |
931 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
ecd9acbf | 932 | MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver"); |
b5f1220d | 933 | MODULE_LICENSE("GPL"); |