[media] s5p-mfc: use one implementation of s5p_mfc_get_new_ctx
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
CommitLineData
af935746
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1/*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
af935746 21#include <linux/videodev2.h>
f9f715a9 22#include <media/v4l2-event.h>
af935746 23#include <linux/workqueue.h>
b27a23be 24#include <linux/of.h>
c139990e 25#include <media/videobuf2-v4l2.h>
43a1ea1f 26#include "s5p_mfc_common.h"
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27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
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AK
32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
af935746 34#include "s5p_mfc_pm.h"
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35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
139adba6
MCC
40int mfc_debug_level;
41module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
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42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44/* Helper functions for interrupt processing */
7fb89eca 45
af935746 46/* Remove from hw execution round robin */
7fb89eca 47void clear_work_bit(struct s5p_mfc_ctx *ctx)
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KD
48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
7fb89eca 52 __clear_bit(ctx->num, &dev->ctx_work_bits);
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53 spin_unlock(&dev->condlock);
54}
55
7fb89eca
AH
56/* Add to hw execution round robin */
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66/* Remove from hw execution round robin */
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77/* Add to hw execution round robin */
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
05d1d0f0
AH
88int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
89{
90 unsigned long flags;
91 int ctx;
92
93 spin_lock_irqsave(&dev->condlock, flags);
94 ctx = dev->curr_ctx;
95 do {
96 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
97 if (ctx == dev->curr_ctx) {
98 if (!test_bit(ctx, &dev->ctx_work_bits))
99 ctx = -EAGAIN;
100 break;
101 }
102 } while (!test_bit(ctx, &dev->ctx_work_bits));
103 spin_unlock_irqrestore(&dev->condlock, flags);
104
105 return ctx;
106}
107
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108/* Wake up context wait_queue */
109static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
110 unsigned int err)
111{
112 ctx->int_cond = 1;
113 ctx->int_type = reason;
114 ctx->int_err = err;
115 wake_up(&ctx->queue);
116}
117
118/* Wake up device wait_queue */
119static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
120 unsigned int err)
121{
122 dev->int_cond = 1;
123 dev->int_type = reason;
124 dev->int_err = err;
125 wake_up(&dev->queue);
126}
127
a13bba4f 128static void s5p_mfc_watchdog(unsigned long arg)
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129{
130 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
131
132 if (test_bit(0, &dev->hw_lock))
133 atomic_inc(&dev->watchdog_cnt);
134 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
135 /* This means that hw is busy and no interrupts were
136 * generated by hw for the Nth time of running this
137 * watchdog timer. This usually means a serious hw
138 * error. Now it is time to kill all instances and
139 * reset the MFC. */
140 mfc_err("Time out during waiting for HW\n");
141 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
142 }
143 dev->watchdog_timer.expires = jiffies +
144 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
145 add_timer(&dev->watchdog_timer);
146}
147
148static void s5p_mfc_watchdog_worker(struct work_struct *work)
149{
150 struct s5p_mfc_dev *dev;
151 struct s5p_mfc_ctx *ctx;
152 unsigned long flags;
153 int mutex_locked;
154 int i, ret;
155
156 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
157
158 mfc_err("Driver timeout error handling\n");
159 /* Lock the mutex that protects open and release.
160 * This is necessary as they may load and unload firmware. */
161 mutex_locked = mutex_trylock(&dev->mfc_mutex);
162 if (!mutex_locked)
163 mfc_err("Error: some instance may be closing/opening\n");
164 spin_lock_irqsave(&dev->irqlock, flags);
165
166 s5p_mfc_clock_off();
167
168 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
169 ctx = dev->ctx[i];
170 if (!ctx)
171 continue;
172 ctx->state = MFCINST_ERROR;
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173 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
174 &ctx->dst_queue, &ctx->vq_dst);
175 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
176 &ctx->src_queue, &ctx->vq_src);
af935746 177 clear_work_bit(ctx);
43a1ea1f 178 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
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179 }
180 clear_bit(0, &dev->hw_lock);
181 spin_unlock_irqrestore(&dev->irqlock, flags);
b16e6448
AM
182
183 /* De-init MFC */
184 s5p_mfc_deinit_hw(dev);
185
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186 /* Double check if there is at least one instance running.
187 * If no instance is in memory than no firmware should be present */
188 if (dev->num_inst > 0) {
46075006 189 ret = s5p_mfc_load_firmware(dev);
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190 if (ret) {
191 mfc_err("Failed to reload FW\n");
192 goto unlock;
193 }
194 s5p_mfc_clock_on();
195 ret = s5p_mfc_init_hw(dev);
196 if (ret)
197 mfc_err("Failed to reinit FW\n");
198 }
199unlock:
200 if (mutex_locked)
201 mutex_unlock(&dev->mfc_mutex);
202}
203
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204static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
205{
206 struct s5p_mfc_buf *dst_buf;
43a1ea1f 207 struct s5p_mfc_dev *dev = ctx->dev;
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208
209 ctx->state = MFCINST_FINISHED;
210 ctx->sequence++;
211 while (!list_empty(&ctx->dst_queue)) {
212 dst_buf = list_entry(ctx->dst_queue.next,
213 struct s5p_mfc_buf, list);
214 mfc_debug(2, "Cleaning up buffer: %d\n",
2d700715
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215 dst_buf->b->vb2_buf.index);
216 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
217 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
af935746 218 list_del(&dst_buf->list);
4d0b0ed6 219 dst_buf->flags |= MFC_BUF_FLAG_EOS;
af935746 220 ctx->dst_queue_cnt--;
2d700715 221 dst_buf->b->sequence = (ctx->sequence++);
af935746 222
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AK
223 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
224 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
2d700715 225 dst_buf->b->field = V4L2_FIELD_NONE;
af935746 226 else
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227 dst_buf->b->field = V4L2_FIELD_INTERLACED;
228 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
af935746 229
2d700715
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230 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
231 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
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232 }
233}
234
235static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
236{
237 struct s5p_mfc_dev *dev = ctx->dev;
238 struct s5p_mfc_buf *dst_buf, *src_buf;
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AK
239 size_t dec_y_addr;
240 unsigned int frame_type;
241
bb21c54a 242 /* Make sure we actually have a new frame before continuing. */
43a1ea1f 243 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
bb21c54a
IF
244 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
245 return;
246 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
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247
248 /* Copy timestamp / timecode from decoded src to dst and set
bb21c54a 249 appropriate flags. */
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250 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
251 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
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252 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
253 == dec_y_addr) {
254 dst_buf->b->timecode =
255 src_buf->b->timecode;
d6dd645e
JS
256 dst_buf->b->vb2_buf.timestamp =
257 src_buf->b->vb2_buf.timestamp;
2d700715 258 dst_buf->b->flags &=
309f4d62 259 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
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260 dst_buf->b->flags |=
261 src_buf->b->flags
309f4d62 262 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
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263 switch (frame_type) {
264 case S5P_FIMV_DECODE_FRAME_I_FRAME:
2d700715 265 dst_buf->b->flags |=
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KD
266 V4L2_BUF_FLAG_KEYFRAME;
267 break;
268 case S5P_FIMV_DECODE_FRAME_P_FRAME:
2d700715 269 dst_buf->b->flags |=
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270 V4L2_BUF_FLAG_PFRAME;
271 break;
272 case S5P_FIMV_DECODE_FRAME_B_FRAME:
2d700715 273 dst_buf->b->flags |=
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274 V4L2_BUF_FLAG_BFRAME;
275 break;
bb21c54a
IF
276 default:
277 /* Don't know how to handle
278 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
279 mfc_debug(2, "Unexpected frame type: %d\n",
280 frame_type);
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281 }
282 break;
283 }
284 }
285}
286
287static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
288{
289 struct s5p_mfc_dev *dev = ctx->dev;
290 struct s5p_mfc_buf *dst_buf;
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AK
291 size_t dspl_y_addr;
292 unsigned int frame_type;
af935746 293
43a1ea1f 294 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
7c672812
SS
295 if (IS_MFCV6_PLUS(dev))
296 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
297 get_disp_frame_type, ctx);
298 else
299 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
300 get_dec_frame_type, dev);
43a1ea1f 301
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302 /* If frame is same as previous then skip and do not dequeue */
303 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
304 if (!ctx->after_packed_pb)
305 ctx->sequence++;
306 ctx->after_packed_pb = 0;
307 return;
308 }
309 ctx->sequence++;
310 /* The MFC returns address of the buffer, now we have to
311 * check which videobuf does it correspond to */
312 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
313 /* Check if this is the buffer we're looking for */
2d700715
JS
314 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
315 == dspl_y_addr) {
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316 list_del(&dst_buf->list);
317 ctx->dst_queue_cnt--;
2d700715 318 dst_buf->b->sequence = ctx->sequence;
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AK
319 if (s5p_mfc_hw_call(dev->mfc_ops,
320 get_pic_type_top, ctx) ==
321 s5p_mfc_hw_call(dev->mfc_ops,
322 get_pic_type_bot, ctx))
2d700715 323 dst_buf->b->field = V4L2_FIELD_NONE;
af935746 324 else
2d700715 325 dst_buf->b->field =
af935746 326 V4L2_FIELD_INTERLACED;
2d700715
JS
327 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
328 ctx->luma_size);
329 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
330 ctx->chroma_size);
331 clear_bit(dst_buf->b->vb2_buf.index,
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KD
332 &ctx->dec_dst_flag);
333
2d700715
JS
334 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
335 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
af935746 336
af935746
KD
337 break;
338 }
339 }
340}
341
342/* Handle frame decoding interrupt */
343static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
344 unsigned int reason, unsigned int err)
345{
346 struct s5p_mfc_dev *dev = ctx->dev;
347 unsigned int dst_frame_status;
a0517f5d 348 unsigned int dec_frame_status;
af935746
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349 struct s5p_mfc_buf *src_buf;
350 unsigned long flags;
351 unsigned int res_change;
352
43a1ea1f 353 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
af935746 354 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
a0517f5d
PO
355 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
356 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
f96f3cfa
JP
357 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
358 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
359 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
af935746
KD
360 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
361 if (ctx->state == MFCINST_RES_CHANGE_INIT)
362 ctx->state = MFCINST_RES_CHANGE_FLUSH;
f96f3cfa
JP
363 if (res_change == S5P_FIMV_RES_INCREASE ||
364 res_change == S5P_FIMV_RES_DECREASE) {
af935746 365 ctx->state = MFCINST_RES_CHANGE_INIT;
e2c3be2a 366 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 367 wake_up_ctx(ctx, reason, err);
9a7bc6b0 368 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 369 s5p_mfc_clock_off();
e2c3be2a 370 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD
371 return;
372 }
373 if (ctx->dpb_flush_flag)
374 ctx->dpb_flush_flag = 0;
375
376 spin_lock_irqsave(&dev->irqlock, flags);
377 /* All frames remaining in the buffer have been extracted */
378 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
379 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
0520e4cc
PO
380 static const struct v4l2_event ev_src_ch = {
381 .type = V4L2_EVENT_SOURCE_CHANGE,
382 .u.src_change.changes =
383 V4L2_EVENT_SRC_CH_RESOLUTION,
384 };
385
af935746
KD
386 s5p_mfc_handle_frame_all_extracted(ctx);
387 ctx->state = MFCINST_RES_CHANGE_END;
0520e4cc
PO
388 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
389
af935746
KD
390 goto leave_handle_frame;
391 } else {
392 s5p_mfc_handle_frame_all_extracted(ctx);
393 }
394 }
395
a0517f5d 396 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
af935746
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397 s5p_mfc_handle_frame_copy_time(ctx);
398
399 /* A frame has been decoded and is in the buffer */
400 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
401 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
402 s5p_mfc_handle_frame_new(ctx, err);
403 } else {
404 mfc_debug(2, "No frame decode\n");
405 }
406 /* Mark source buffer as complete */
407 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
408 && !list_empty(&ctx->src_queue)) {
409 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
410 list);
43a1ea1f
AK
411 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
412 get_consumed_stream, dev);
413 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
f49f3ed5 414 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
d2a0db1e 415 ctx->consumed_stream + STUFF_BYTE <
2d700715 416 src_buf->b->vb2_buf.planes[0].bytesused) {
af935746
KD
417 /* Run MFC again on the same buffer */
418 mfc_debug(2, "Running again the same buffer\n");
419 ctx->after_packed_pb = 1;
420 } else {
af935746
KD
421 mfc_debug(2, "MFC needs next buffer\n");
422 ctx->consumed_stream = 0;
a34026e7
KD
423 if (src_buf->flags & MFC_BUF_FLAG_EOS)
424 ctx->state = MFCINST_FINISHING;
af935746
KD
425 list_del(&src_buf->list);
426 ctx->src_queue_cnt--;
43a1ea1f 427 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
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JS
428 vb2_buffer_done(&src_buf->b->vb2_buf,
429 VB2_BUF_STATE_ERROR);
af935746 430 else
2d700715
JS
431 vb2_buffer_done(&src_buf->b->vb2_buf,
432 VB2_BUF_STATE_DONE);
af935746
KD
433 }
434 }
435leave_handle_frame:
436 spin_unlock_irqrestore(&dev->irqlock, flags);
437 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
e9d98ddc 438 || ctx->dst_queue_cnt < ctx->pb_count)
af935746 439 clear_work_bit(ctx);
e2c3be2a 440 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 441 wake_up_ctx(ctx, reason, err);
9a7bc6b0 442 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 443 s5p_mfc_clock_off();
76a4ddbd
P
444 /* if suspending, wake up device and do not try_run again*/
445 if (test_bit(0, &dev->enter_suspend))
446 wake_up_dev(dev, reason, err);
447 else
e2c3be2a 448 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD
449}
450
451/* Error handling for interrupt */
7296e25f
KD
452static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
453 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
af935746 454{
af935746
KD
455 unsigned long flags;
456
af935746 457 mfc_err("Interrupt Error: %08x\n", err);
af935746 458
7296e25f
KD
459 if (ctx != NULL) {
460 /* Error recovery is dependent on the state of context */
461 switch (ctx->state) {
462 case MFCINST_RES_CHANGE_INIT:
463 case MFCINST_RES_CHANGE_FLUSH:
464 case MFCINST_RES_CHANGE_END:
465 case MFCINST_FINISHING:
466 case MFCINST_FINISHED:
467 case MFCINST_RUNNING:
39c1cb2b 468 /* It is highly probable that an error occurred
7296e25f
KD
469 * while decoding a frame */
470 clear_work_bit(ctx);
471 ctx->state = MFCINST_ERROR;
472 /* Mark all dst buffers as having an error */
473 spin_lock_irqsave(&dev->irqlock, flags);
e2c3be2a 474 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
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KD
475 &ctx->dst_queue, &ctx->vq_dst);
476 /* Mark all src buffers as having an error */
e2c3be2a 477 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
7296e25f
KD
478 &ctx->src_queue, &ctx->vq_src);
479 spin_unlock_irqrestore(&dev->irqlock, flags);
480 wake_up_ctx(ctx, reason, err);
481 break;
482 default:
483 clear_work_bit(ctx);
484 ctx->state = MFCINST_ERROR;
485 wake_up_ctx(ctx, reason, err);
486 break;
487 }
af935746 488 }
9a7bc6b0 489 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
e2c3be2a 490 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
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KD
491 s5p_mfc_clock_off();
492 wake_up_dev(dev, reason, err);
af935746
KD
493 return;
494}
495
496/* Header parsing interrupt handling */
497static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
498 unsigned int reason, unsigned int err)
499{
500 struct s5p_mfc_dev *dev;
af935746 501
1259762f 502 if (ctx == NULL)
af935746
KD
503 return;
504 dev = ctx->dev;
505 if (ctx->c_ops->post_seq_start) {
506 if (ctx->c_ops->post_seq_start(ctx))
507 mfc_err("post_seq_start() failed\n");
508 } else {
43a1ea1f
AK
509 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
510 dev);
511 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
512 dev);
af935746 513
e2c3be2a 514 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
8f532a7f 515
e9d98ddc 516 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
43a1ea1f 517 dev);
f96f3cfa
JP
518 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
519 dev);
bb869368 520 if (ctx->img_width == 0 || ctx->img_height == 0)
af935746
KD
521 ctx->state = MFCINST_ERROR;
522 else
523 ctx->state = MFCINST_HEAD_PARSED;
f96f3cfa
JP
524
525 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
526 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
527 !list_empty(&ctx->src_queue)) {
528 struct s5p_mfc_buf *src_buf;
529 src_buf = list_entry(ctx->src_queue.next,
530 struct s5p_mfc_buf, list);
531 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
532 dev) <
2d700715 533 src_buf->b->vb2_buf.planes[0].bytesused)
f96f3cfa
JP
534 ctx->head_processed = 0;
535 else
536 ctx->head_processed = 1;
537 } else {
538 ctx->head_processed = 1;
539 }
af935746 540 }
e2c3be2a 541 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 542 clear_work_bit(ctx);
9a7bc6b0 543 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 544 s5p_mfc_clock_off();
e2c3be2a 545 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD
546 wake_up_ctx(ctx, reason, err);
547}
548
549/* Header parsing interrupt handling */
550static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
551 unsigned int reason, unsigned int err)
552{
553 struct s5p_mfc_buf *src_buf;
554 struct s5p_mfc_dev *dev;
555 unsigned long flags;
556
1259762f 557 if (ctx == NULL)
af935746
KD
558 return;
559 dev = ctx->dev;
e2c3be2a 560 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD
561 ctx->int_type = reason;
562 ctx->int_err = err;
563 ctx->int_cond = 1;
7fb89eca 564 clear_work_bit(ctx);
af935746
KD
565 if (err == 0) {
566 ctx->state = MFCINST_RUNNING;
f96f3cfa 567 if (!ctx->dpb_flush_flag && ctx->head_processed) {
af935746
KD
568 spin_lock_irqsave(&dev->irqlock, flags);
569 if (!list_empty(&ctx->src_queue)) {
570 src_buf = list_entry(ctx->src_queue.next,
571 struct s5p_mfc_buf, list);
572 list_del(&src_buf->list);
573 ctx->src_queue_cnt--;
2d700715 574 vb2_buffer_done(&src_buf->b->vb2_buf,
af935746
KD
575 VB2_BUF_STATE_DONE);
576 }
577 spin_unlock_irqrestore(&dev->irqlock, flags);
578 } else {
579 ctx->dpb_flush_flag = 0;
580 }
9a7bc6b0 581 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746
KD
582
583 s5p_mfc_clock_off();
584
585 wake_up(&ctx->queue);
e2c3be2a 586 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746 587 } else {
9a7bc6b0 588 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746
KD
589
590 s5p_mfc_clock_off();
591
592 wake_up(&ctx->queue);
593 }
594}
595
96c57776 596static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
f9f715a9
AH
597{
598 struct s5p_mfc_dev *dev = ctx->dev;
599 struct s5p_mfc_buf *mb_entry;
600
4130eabc 601 mfc_debug(2, "Stream completed\n");
f9f715a9 602
f9f715a9
AH
603 ctx->state = MFCINST_FINISHED;
604
605 spin_lock(&dev->irqlock);
606 if (!list_empty(&ctx->dst_queue)) {
607 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
608 list);
609 list_del(&mb_entry->list);
610 ctx->dst_queue_cnt--;
2d700715
JS
611 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
612 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
f9f715a9
AH
613 }
614 spin_unlock(&dev->irqlock);
615
616 clear_work_bit(ctx);
617
e8256447 618 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
f9f715a9
AH
619
620 s5p_mfc_clock_off();
621 wake_up(&ctx->queue);
e2c3be2a 622 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
f9f715a9
AH
623}
624
af935746
KD
625/* Interrupt processing */
626static irqreturn_t s5p_mfc_irq(int irq, void *priv)
627{
628 struct s5p_mfc_dev *dev = priv;
629 struct s5p_mfc_ctx *ctx;
630 unsigned int reason;
631 unsigned int err;
632
633 mfc_debug_enter();
634 /* Reset the timeout watchdog */
635 atomic_set(&dev->watchdog_cnt, 0);
636 ctx = dev->ctx[dev->curr_ctx];
637 /* Get the reason of interrupt and the error code */
43a1ea1f
AK
638 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
639 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
af935746
KD
640 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
641 switch (reason) {
43a1ea1f 642 case S5P_MFC_R2H_CMD_ERR_RET:
39c1cb2b 643 /* An error has occurred */
af935746 644 if (ctx->state == MFCINST_RUNNING &&
43a1ea1f
AK
645 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
646 dev->warn_start)
af935746
KD
647 s5p_mfc_handle_frame(ctx, reason, err);
648 else
7296e25f 649 s5p_mfc_handle_error(dev, ctx, reason, err);
af935746
KD
650 clear_bit(0, &dev->enter_suspend);
651 break;
652
43a1ea1f
AK
653 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
654 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
655 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
af935746
KD
656 if (ctx->c_ops->post_frame_start) {
657 if (ctx->c_ops->post_frame_start(ctx))
658 mfc_err("post_frame_start() failed\n");
96c57776
AH
659
660 if (ctx->state == MFCINST_FINISHING &&
661 list_empty(&ctx->ref_queue)) {
662 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
663 s5p_mfc_handle_stream_complete(ctx);
664 break;
665 }
e2c3be2a 666 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 667 wake_up_ctx(ctx, reason, err);
9a7bc6b0 668 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 669 s5p_mfc_clock_off();
e2c3be2a 670 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD
671 } else {
672 s5p_mfc_handle_frame(ctx, reason, err);
673 }
674 break;
675
43a1ea1f 676 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
af935746
KD
677 s5p_mfc_handle_seq_done(ctx, reason, err);
678 break;
679
43a1ea1f
AK
680 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
681 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
af935746
KD
682 ctx->state = MFCINST_GOT_INST;
683 clear_work_bit(ctx);
684 wake_up(&ctx->queue);
685 goto irq_cleanup_hw;
686
43a1ea1f 687 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
af935746 688 clear_work_bit(ctx);
9d87e837 689 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD
690 ctx->state = MFCINST_FREE;
691 wake_up(&ctx->queue);
692 goto irq_cleanup_hw;
693
43a1ea1f
AK
694 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
695 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
696 case S5P_MFC_R2H_CMD_SLEEP_RET:
697 case S5P_MFC_R2H_CMD_WAKEUP_RET:
af935746
KD
698 if (ctx)
699 clear_work_bit(ctx);
e2c3be2a 700 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD
701 wake_up_dev(dev, reason, err);
702 clear_bit(0, &dev->hw_lock);
703 clear_bit(0, &dev->enter_suspend);
704 break;
705
43a1ea1f 706 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
af935746
KD
707 s5p_mfc_handle_init_buffers(ctx, reason, err);
708 break;
f9f715a9 709
43a1ea1f 710 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
96c57776
AH
711 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
712 ctx->int_type = reason;
713 ctx->int_err = err;
714 s5p_mfc_handle_stream_complete(ctx);
f9f715a9
AH
715 break;
716
8f23cc02
AK
717 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
718 clear_work_bit(ctx);
719 ctx->state = MFCINST_RUNNING;
720 wake_up(&ctx->queue);
721 goto irq_cleanup_hw;
722
af935746
KD
723 default:
724 mfc_debug(2, "Unknown int reason\n");
e2c3be2a 725 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD
726 }
727 mfc_debug_leave();
728 return IRQ_HANDLED;
729irq_cleanup_hw:
e2c3be2a 730 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD
731 ctx->int_type = reason;
732 ctx->int_err = err;
733 ctx->int_cond = 1;
734 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
735 mfc_err("Failed to unlock hw\n");
736
737 s5p_mfc_clock_off();
738
e2c3be2a 739 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD
740 mfc_debug(2, "Exit via irq_cleanup_hw\n");
741 return IRQ_HANDLED;
742}
743
744/* Open an MFC node */
745static int s5p_mfc_open(struct file *file)
746{
b80cb8dc 747 struct video_device *vdev = video_devdata(file);
af935746
KD
748 struct s5p_mfc_dev *dev = video_drvdata(file);
749 struct s5p_mfc_ctx *ctx = NULL;
750 struct vb2_queue *q;
af935746
KD
751 int ret = 0;
752
753 mfc_debug_enter();
bc738301
HV
754 if (mutex_lock_interruptible(&dev->mfc_mutex))
755 return -ERESTARTSYS;
af935746
KD
756 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
757 /* Allocate memory for context */
bae061b4 758 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
af935746
KD
759 if (!ctx) {
760 mfc_err("Not enough memory\n");
761 ret = -ENOMEM;
762 goto err_alloc;
763 }
55647a99 764 v4l2_fh_init(&ctx->fh, vdev);
af935746
KD
765 file->private_data = &ctx->fh;
766 v4l2_fh_add(&ctx->fh);
767 ctx->dev = dev;
768 INIT_LIST_HEAD(&ctx->src_queue);
769 INIT_LIST_HEAD(&ctx->dst_queue);
770 ctx->src_queue_cnt = 0;
771 ctx->dst_queue_cnt = 0;
772 /* Get context number */
773 ctx->num = 0;
774 while (dev->ctx[ctx->num]) {
775 ctx->num++;
776 if (ctx->num >= MFC_NUM_CONTEXTS) {
777 mfc_err("Too many open contexts\n");
778 ret = -EBUSY;
779 goto err_no_ctx;
780 }
781 }
782 /* Mark context as idle */
7fb89eca 783 clear_work_bit_irqsave(ctx);
af935746 784 dev->ctx[ctx->num] = ctx;
b80cb8dc 785 if (vdev == dev->vfd_dec) {
af935746
KD
786 ctx->type = MFCINST_DECODER;
787 ctx->c_ops = get_dec_codec_ops();
43a1ea1f 788 s5p_mfc_dec_init(ctx);
af935746
KD
789 /* Setup ctrl handler */
790 ret = s5p_mfc_dec_ctrls_setup(ctx);
791 if (ret) {
792 mfc_err("Failed to setup mfc controls\n");
793 goto err_ctrls_setup;
794 }
b80cb8dc 795 } else if (vdev == dev->vfd_enc) {
af935746
KD
796 ctx->type = MFCINST_ENCODER;
797 ctx->c_ops = get_enc_codec_ops();
798 /* only for encoder */
799 INIT_LIST_HEAD(&ctx->ref_queue);
800 ctx->ref_queue_cnt = 0;
43a1ea1f 801 s5p_mfc_enc_init(ctx);
af935746
KD
802 /* Setup ctrl handler */
803 ret = s5p_mfc_enc_ctrls_setup(ctx);
804 if (ret) {
805 mfc_err("Failed to setup mfc controls\n");
806 goto err_ctrls_setup;
807 }
808 } else {
809 ret = -ENOENT;
810 goto err_bad_node;
811 }
812 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
9d87e837 813 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD
814 /* Load firmware if this is the first instance */
815 if (dev->num_inst == 1) {
816 dev->watchdog_timer.expires = jiffies +
817 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
818 add_timer(&dev->watchdog_timer);
819 ret = s5p_mfc_power_on();
820 if (ret < 0) {
821 mfc_err("power on failed\n");
822 goto err_pwr_enable;
823 }
824 s5p_mfc_clock_on();
2e731e44
KD
825 ret = s5p_mfc_load_firmware(dev);
826 if (ret) {
827 s5p_mfc_clock_off();
828 goto err_load_fw;
829 }
af935746
KD
830 /* Init the FW */
831 ret = s5p_mfc_init_hw(dev);
2e731e44 832 s5p_mfc_clock_off();
af935746
KD
833 if (ret)
834 goto err_init_hw;
af935746
KD
835 }
836 /* Init videobuf2 queue for CAPTURE */
837 q = &ctx->vq_dst;
838 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
839 q->drv_priv = &ctx->fh;
654a731b 840 q->lock = &dev->mfc_mutex;
b80cb8dc 841 if (vdev == dev->vfd_dec) {
af935746
KD
842 q->io_modes = VB2_MMAP;
843 q->ops = get_dec_queue_ops();
b80cb8dc 844 } else if (vdev == dev->vfd_enc) {
af935746
KD
845 q->io_modes = VB2_MMAP | VB2_USERPTR;
846 q->ops = get_enc_queue_ops();
847 } else {
848 ret = -ENOENT;
849 goto err_queue_init;
850 }
749ae716 851 q->mem_ops = &vb2_dma_contig_memops;
ade48681 852 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD
853 ret = vb2_queue_init(q);
854 if (ret) {
855 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
856 goto err_queue_init;
857 }
858 /* Init videobuf2 queue for OUTPUT */
859 q = &ctx->vq_src;
860 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
861 q->io_modes = VB2_MMAP;
862 q->drv_priv = &ctx->fh;
41f03a00 863 q->lock = &dev->mfc_mutex;
b80cb8dc 864 if (vdev == dev->vfd_dec) {
af935746
KD
865 q->io_modes = VB2_MMAP;
866 q->ops = get_dec_queue_ops();
b80cb8dc 867 } else if (vdev == dev->vfd_enc) {
af935746
KD
868 q->io_modes = VB2_MMAP | VB2_USERPTR;
869 q->ops = get_enc_queue_ops();
870 } else {
871 ret = -ENOENT;
872 goto err_queue_init;
873 }
e6c9dec3
KD
874 /* One way to indicate end-of-stream for MFC is to set the
875 * bytesused == 0. However by default videobuf2 handles bytesused
876 * equal to 0 as a special case and changes its value to the size
877 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
878 * will keep the value of bytesused intact.
879 */
880 q->allow_zero_bytesused = 1;
749ae716 881 q->mem_ops = &vb2_dma_contig_memops;
ade48681 882 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD
883 ret = vb2_queue_init(q);
884 if (ret) {
885 mfc_err("Failed to initialize videobuf2 queue(output)\n");
886 goto err_queue_init;
887 }
888 init_waitqueue_head(&ctx->queue);
bc738301 889 mutex_unlock(&dev->mfc_mutex);
af935746
KD
890 mfc_debug_leave();
891 return ret;
39c1cb2b 892 /* Deinit when failure occurred */
af935746 893err_queue_init:
2e731e44
KD
894 if (dev->num_inst == 1)
895 s5p_mfc_deinit_hw(dev);
af935746 896err_init_hw:
2e731e44 897err_load_fw:
af935746
KD
898err_pwr_enable:
899 if (dev->num_inst == 1) {
900 if (s5p_mfc_power_off() < 0)
901 mfc_err("power off failed\n");
1b73ba0b 902 del_timer_sync(&dev->watchdog_timer);
af935746
KD
903 }
904err_ctrls_setup:
905 s5p_mfc_dec_ctrls_delete(ctx);
906err_bad_node:
1b73ba0b 907 dev->ctx[ctx->num] = NULL;
af935746
KD
908err_no_ctx:
909 v4l2_fh_del(&ctx->fh);
910 v4l2_fh_exit(&ctx->fh);
911 kfree(ctx);
912err_alloc:
913 dev->num_inst--;
bc738301 914 mutex_unlock(&dev->mfc_mutex);
af935746
KD
915 mfc_debug_leave();
916 return ret;
917}
918
919/* Release MFC context */
920static int s5p_mfc_release(struct file *file)
921{
922 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
923 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD
924
925 mfc_debug_enter();
bc738301 926 mutex_lock(&dev->mfc_mutex);
af935746
KD
927 s5p_mfc_clock_on();
928 vb2_queue_release(&ctx->vq_src);
929 vb2_queue_release(&ctx->vq_dst);
930 /* Mark context as idle */
7fb89eca 931 clear_work_bit_irqsave(ctx);
9d87e837 932 /* If instance was initialised and not yet freed,
39c1cb2b 933 * return instance and free resources */
9d87e837 934 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
af935746 935 mfc_debug(2, "Has to free instance\n");
818cd91a 936 s5p_mfc_close_mfc_inst(dev, ctx);
af935746
KD
937 }
938 /* hardware locking scheme */
939 if (dev->curr_ctx == ctx->num)
940 clear_bit(0, &dev->hw_lock);
941 dev->num_inst--;
942 if (dev->num_inst == 0) {
2e731e44 943 mfc_debug(2, "Last instance\n");
43a1ea1f 944 s5p_mfc_deinit_hw(dev);
af935746
KD
945 del_timer_sync(&dev->watchdog_timer);
946 if (s5p_mfc_power_off() < 0)
947 mfc_err("Power off failed\n");
948 }
949 mfc_debug(2, "Shutting down clock\n");
950 s5p_mfc_clock_off();
1259762f 951 dev->ctx[ctx->num] = NULL;
af935746
KD
952 s5p_mfc_dec_ctrls_delete(ctx);
953 v4l2_fh_del(&ctx->fh);
954 v4l2_fh_exit(&ctx->fh);
955 kfree(ctx);
956 mfc_debug_leave();
bc738301 957 mutex_unlock(&dev->mfc_mutex);
af935746
KD
958 return 0;
959}
960
961/* Poll */
962static unsigned int s5p_mfc_poll(struct file *file,
963 struct poll_table_struct *wait)
964{
965 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
966 struct s5p_mfc_dev *dev = ctx->dev;
967 struct vb2_queue *src_q, *dst_q;
968 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
969 unsigned int rc = 0;
970 unsigned long flags;
971
bc738301 972 mutex_lock(&dev->mfc_mutex);
af935746
KD
973 src_q = &ctx->vq_src;
974 dst_q = &ctx->vq_dst;
975 /*
976 * There has to be at least one buffer queued on each queued_list, which
977 * means either in driver already or waiting for driver to claim it
978 * and start processing.
979 */
980 if ((!src_q->streaming || list_empty(&src_q->queued_list))
981 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
982 rc = POLLERR;
983 goto end;
984 }
985 mutex_unlock(&dev->mfc_mutex);
f9f715a9 986 poll_wait(file, &ctx->fh.wait, wait);
af935746
KD
987 poll_wait(file, &src_q->done_wq, wait);
988 poll_wait(file, &dst_q->done_wq, wait);
989 mutex_lock(&dev->mfc_mutex);
f9f715a9
AH
990 if (v4l2_event_pending(&ctx->fh))
991 rc |= POLLPRI;
af935746
KD
992 spin_lock_irqsave(&src_q->done_lock, flags);
993 if (!list_empty(&src_q->done_list))
994 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
995 done_entry);
996 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
997 || src_vb->state == VB2_BUF_STATE_ERROR))
998 rc |= POLLOUT | POLLWRNORM;
999 spin_unlock_irqrestore(&src_q->done_lock, flags);
1000 spin_lock_irqsave(&dst_q->done_lock, flags);
1001 if (!list_empty(&dst_q->done_list))
1002 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1003 done_entry);
1004 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1005 || dst_vb->state == VB2_BUF_STATE_ERROR))
1006 rc |= POLLIN | POLLRDNORM;
1007 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1008end:
bc738301 1009 mutex_unlock(&dev->mfc_mutex);
af935746
KD
1010 return rc;
1011}
1012
1013/* Mmap */
1014static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1015{
1016 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
bc738301 1017 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD
1018 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1019 int ret;
bc738301
HV
1020
1021 if (mutex_lock_interruptible(&dev->mfc_mutex))
1022 return -ERESTARTSYS;
af935746
KD
1023 if (offset < DST_QUEUE_OFF_BASE) {
1024 mfc_debug(2, "mmaping source\n");
1025 ret = vb2_mmap(&ctx->vq_src, vma);
1026 } else { /* capture */
1027 mfc_debug(2, "mmaping destination\n");
1028 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1029 ret = vb2_mmap(&ctx->vq_dst, vma);
1030 }
bc738301 1031 mutex_unlock(&dev->mfc_mutex);
af935746
KD
1032 return ret;
1033}
1034
1035/* v4l2 ops */
1036static const struct v4l2_file_operations s5p_mfc_fops = {
1037 .owner = THIS_MODULE,
1038 .open = s5p_mfc_open,
1039 .release = s5p_mfc_release,
1040 .poll = s5p_mfc_poll,
1041 .unlocked_ioctl = video_ioctl2,
1042 .mmap = s5p_mfc_mmap,
1043};
1044
1045static int match_child(struct device *dev, void *data)
1046{
1047 if (!dev_name(dev))
1048 return 0;
1049 return !strcmp(dev_name(dev), (char *)data);
1050}
1051
b27a23be
AK
1052static void *mfc_get_drv_data(struct platform_device *pdev);
1053
6e83e6e2
AK
1054static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1055{
65fccab5 1056 unsigned int mem_info[2] = { };
6e83e6e2
AK
1057
1058 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1059 sizeof(struct device), GFP_KERNEL);
1060 if (!dev->mem_dev_l) {
1061 mfc_err("Not enough memory\n");
1062 return -ENOMEM;
1063 }
1064 device_initialize(dev->mem_dev_l);
1065 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1066 "samsung,mfc-l", mem_info, 2);
1067 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1068 mem_info[0], mem_info[1],
1069 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1070 mfc_err("Failed to declare coherent memory for\n"
1071 "MFC device\n");
1072 return -ENOMEM;
1073 }
1074
1075 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1076 sizeof(struct device), GFP_KERNEL);
1077 if (!dev->mem_dev_r) {
1078 mfc_err("Not enough memory\n");
1079 return -ENOMEM;
1080 }
1081 device_initialize(dev->mem_dev_r);
1082 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1083 "samsung,mfc-r", mem_info, 2);
1084 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1085 mem_info[0], mem_info[1],
1086 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1087 pr_err("Failed to declare coherent memory for\n"
1088 "MFC device\n");
1089 return -ENOMEM;
1090 }
1091 return 0;
1092}
1093
af935746 1094/* MFC probe function */
1e393e90 1095static int s5p_mfc_probe(struct platform_device *pdev)
af935746
KD
1096{
1097 struct s5p_mfc_dev *dev;
1098 struct video_device *vfd;
1099 struct resource *res;
1100 int ret;
1101
1102 pr_debug("%s++\n", __func__);
bae061b4 1103 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
af935746
KD
1104 if (!dev) {
1105 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1106 return -ENOMEM;
1107 }
1108
1109 spin_lock_init(&dev->irqlock);
1110 spin_lock_init(&dev->condlock);
1111 dev->plat_dev = pdev;
1112 if (!dev->plat_dev) {
1113 dev_err(&pdev->dev, "No platform data specified\n");
d310f478 1114 return -ENODEV;
af935746
KD
1115 }
1116
b27a23be 1117 dev->variant = mfc_get_drv_data(pdev);
8f532a7f 1118
af935746
KD
1119 ret = s5p_mfc_init_pm(dev);
1120 if (ret < 0) {
1121 dev_err(&pdev->dev, "failed to get mfc clock source\n");
d310f478 1122 return ret;
af935746
KD
1123 }
1124
1125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af935746 1126
f23999ec
TR
1127 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1128 if (IS_ERR(dev->regs_base))
1129 return PTR_ERR(dev->regs_base);
af935746
KD
1130
1131 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1132 if (res == NULL) {
1133 dev_err(&pdev->dev, "failed to get irq resource\n");
1134 ret = -ENOENT;
d310f478 1135 goto err_res;
af935746
KD
1136 }
1137 dev->irq = res->start;
d310f478 1138 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1957f0d7 1139 0, pdev->name, dev);
af935746
KD
1140 if (ret) {
1141 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
d310f478 1142 goto err_res;
af935746
KD
1143 }
1144
b27a23be 1145 if (pdev->dev.of_node) {
d68b44e0
WY
1146 ret = s5p_mfc_alloc_memdevs(dev);
1147 if (ret < 0)
b27a23be 1148 goto err_res;
b27a23be
AK
1149 } else {
1150 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1151 "s5p-mfc-l", match_child);
1152 if (!dev->mem_dev_l) {
1153 mfc_err("Mem child (L) device get failed\n");
1154 ret = -ENODEV;
1155 goto err_res;
1156 }
1157 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1158 "s5p-mfc-r", match_child);
1159 if (!dev->mem_dev_r) {
1160 mfc_err("Mem child (R) device get failed\n");
1161 ret = -ENODEV;
1162 goto err_res;
1163 }
af935746
KD
1164 }
1165
1166 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
ef89fff8 1167 if (IS_ERR(dev->alloc_ctx[0])) {
af935746 1168 ret = PTR_ERR(dev->alloc_ctx[0]);
d310f478 1169 goto err_res;
af935746
KD
1170 }
1171 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
ef89fff8 1172 if (IS_ERR(dev->alloc_ctx[1])) {
af935746
KD
1173 ret = PTR_ERR(dev->alloc_ctx[1]);
1174 goto err_mem_init_ctx_1;
1175 }
1176
1177 mutex_init(&dev->mfc_mutex);
1178
2e731e44
KD
1179 ret = s5p_mfc_alloc_firmware(dev);
1180 if (ret)
1181 goto err_alloc_fw;
1182
af935746
KD
1183 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1184 if (ret)
1185 goto err_v4l2_dev_reg;
1186 init_waitqueue_head(&dev->queue);
1187
1188 /* decoder */
1189 vfd = video_device_alloc();
1190 if (!vfd) {
1191 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1192 ret = -ENOMEM;
1193 goto err_dec_alloc;
1194 }
d0ce898c 1195 vfd->fops = &s5p_mfc_fops;
af935746 1196 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
d0ce898c 1197 vfd->release = video_device_release;
af935746
KD
1198 vfd->lock = &dev->mfc_mutex;
1199 vfd->v4l2_dev = &dev->v4l2_dev;
954f340f 1200 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD
1201 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1202 dev->vfd_dec = vfd;
1203 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1204 if (ret) {
1205 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1206 video_device_release(vfd);
1207 goto err_dec_reg;
1208 }
1209 v4l2_info(&dev->v4l2_dev,
1210 "decoder registered as /dev/video%d\n", vfd->num);
1211 video_set_drvdata(vfd, dev);
1212
1213 /* encoder */
1214 vfd = video_device_alloc();
1215 if (!vfd) {
1216 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1217 ret = -ENOMEM;
1218 goto err_enc_alloc;
1219 }
d0ce898c 1220 vfd->fops = &s5p_mfc_fops;
af935746 1221 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
d0ce898c 1222 vfd->release = video_device_release;
af935746
KD
1223 vfd->lock = &dev->mfc_mutex;
1224 vfd->v4l2_dev = &dev->v4l2_dev;
cdcf45e7 1225 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD
1226 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1227 dev->vfd_enc = vfd;
1228 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1229 if (ret) {
1230 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1231 video_device_release(vfd);
1232 goto err_enc_reg;
1233 }
1234 v4l2_info(&dev->v4l2_dev,
1235 "encoder registered as /dev/video%d\n", vfd->num);
1236 video_set_drvdata(vfd, dev);
1237 platform_set_drvdata(pdev, dev);
1238
1239 dev->hw_lock = 0;
1240 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1241 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1242 atomic_set(&dev->watchdog_cnt, 0);
1243 init_timer(&dev->watchdog_timer);
1244 dev->watchdog_timer.data = (unsigned long)dev;
1245 dev->watchdog_timer.function = s5p_mfc_watchdog;
1246
43a1ea1f
AK
1247 /* Initialize HW ops and commands based on MFC version */
1248 s5p_mfc_init_hw_ops(dev);
1249 s5p_mfc_init_hw_cmds(dev);
6a9c6f68 1250 s5p_mfc_init_regs(dev);
43a1ea1f 1251
af935746
KD
1252 pr_debug("%s--\n", __func__);
1253 return 0;
1254
1255/* Deinit MFC if probe had failed */
1256err_enc_reg:
1257 video_device_release(dev->vfd_enc);
1258err_enc_alloc:
1259 video_unregister_device(dev->vfd_dec);
1260err_dec_reg:
1261 video_device_release(dev->vfd_dec);
1262err_dec_alloc:
1263 v4l2_device_unregister(&dev->v4l2_dev);
1264err_v4l2_dev_reg:
2e731e44
KD
1265 s5p_mfc_release_firmware(dev);
1266err_alloc_fw:
af935746
KD
1267 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1268err_mem_init_ctx_1:
1269 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
af935746
KD
1270err_res:
1271 s5p_mfc_final_pm(dev);
d310f478 1272
af935746
KD
1273 pr_debug("%s-- with error\n", __func__);
1274 return ret;
1275
1276}
1277
1278/* Remove the driver */
4c62e976 1279static int s5p_mfc_remove(struct platform_device *pdev)
af935746
KD
1280{
1281 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1282
1283 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1284
1285 del_timer_sync(&dev->watchdog_timer);
1286 flush_workqueue(dev->watchdog_workqueue);
1287 destroy_workqueue(dev->watchdog_workqueue);
1288
1289 video_unregister_device(dev->vfd_enc);
1290 video_unregister_device(dev->vfd_dec);
1291 v4l2_device_unregister(&dev->v4l2_dev);
2e731e44 1292 s5p_mfc_release_firmware(dev);
af935746
KD
1293 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1294 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
6e83e6e2
AK
1295 if (pdev->dev.of_node) {
1296 put_device(dev->mem_dev_l);
1297 put_device(dev->mem_dev_r);
1298 }
af935746 1299
af935746 1300 s5p_mfc_final_pm(dev);
af935746
KD
1301 return 0;
1302}
1303
1304#ifdef CONFIG_PM_SLEEP
1305
1306static int s5p_mfc_suspend(struct device *dev)
1307{
1308 struct platform_device *pdev = to_platform_device(dev);
1309 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1310 int ret;
1311
1312 if (m_dev->num_inst == 0)
1313 return 0;
81c9bcfb 1314
af935746
KD
1315 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1316 mfc_err("Error: going to suspend for a second time\n");
1317 return -EIO;
1318 }
1319
1320 /* Check if we're processing then wait if it necessary. */
1321 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1322 /* Try and lock the HW */
1323 /* Wait on the interrupt waitqueue */
1324 ret = wait_event_interruptible_timeout(m_dev->queue,
76a4ddbd 1325 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
af935746
KD
1326 if (ret == 0) {
1327 mfc_err("Waiting for hardware to finish timed out\n");
64370994 1328 clear_bit(0, &m_dev->enter_suspend);
af935746
KD
1329 return -EIO;
1330 }
1331 }
81c9bcfb 1332
64370994
P
1333 ret = s5p_mfc_sleep(m_dev);
1334 if (ret) {
1335 clear_bit(0, &m_dev->enter_suspend);
1336 clear_bit(0, &m_dev->hw_lock);
1337 }
1338 return ret;
af935746
KD
1339}
1340
1341static int s5p_mfc_resume(struct device *dev)
1342{
1343 struct platform_device *pdev = to_platform_device(dev);
1344 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1345
1346 if (m_dev->num_inst == 0)
1347 return 0;
1348 return s5p_mfc_wakeup(m_dev);
1349}
1350#endif
1351
e243c7c1 1352#ifdef CONFIG_PM
af935746
KD
1353static int s5p_mfc_runtime_suspend(struct device *dev)
1354{
1355 struct platform_device *pdev = to_platform_device(dev);
1356 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1357
1358 atomic_set(&m_dev->pm.power, 0);
1359 return 0;
1360}
1361
1362static int s5p_mfc_runtime_resume(struct device *dev)
1363{
1364 struct platform_device *pdev = to_platform_device(dev);
1365 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
af935746 1366
af935746
KD
1367 atomic_set(&m_dev->pm.power, 1);
1368 return 0;
1369}
1370#endif
1371
1372/* Power management */
1373static const struct dev_pm_ops s5p_mfc_pm_ops = {
1374 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1375 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1376 NULL)
1377};
1378
ca5ea0c5 1379static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
8f532a7f
AK
1380 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1381 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1382 .dsc = DESC_BUF_SIZE,
1383 .shm = SHARED_BUF_SIZE,
1384};
1385
ca5ea0c5 1386static struct s5p_mfc_buf_size buf_size_v5 = {
8f532a7f
AK
1387 .fw = MAX_FW_SIZE,
1388 .cpb = MAX_CPB_SIZE,
1389 .priv = &mfc_buf_size_v5,
1390};
1391
ca5ea0c5 1392static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
8f532a7f
AK
1393 .base = MFC_BASE_ALIGN_ORDER,
1394};
1395
1396static struct s5p_mfc_variant mfc_drvdata_v5 = {
1397 .version = MFC_VERSION,
9aa5f008 1398 .version_bit = MFC_V5_BIT,
8f532a7f
AK
1399 .port_num = MFC_NUM_PORTS,
1400 .buf_size = &buf_size_v5,
1401 .buf_align = &mfc_buf_align_v5,
77ba6b73 1402 .fw_name[0] = "s5p-mfc.fw",
f96f3cfa
JP
1403};
1404
ca5ea0c5 1405static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
f96f3cfa
JP
1406 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1407 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1408 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1409 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1410 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1411};
1412
ca5ea0c5 1413static struct s5p_mfc_buf_size buf_size_v6 = {
f96f3cfa
JP
1414 .fw = MAX_FW_SIZE_V6,
1415 .cpb = MAX_CPB_SIZE_V6,
1416 .priv = &mfc_buf_size_v6,
1417};
1418
ca5ea0c5 1419static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
f96f3cfa
JP
1420 .base = 0,
1421};
1422
1423static struct s5p_mfc_variant mfc_drvdata_v6 = {
1424 .version = MFC_VERSION_V6,
9aa5f008 1425 .version_bit = MFC_V6_BIT,
f96f3cfa
JP
1426 .port_num = MFC_NUM_PORTS_V6,
1427 .buf_size = &buf_size_v6,
1428 .buf_align = &mfc_buf_align_v6,
77ba6b73
AK
1429 .fw_name[0] = "s5p-mfc-v6.fw",
1430 /*
1431 * v6-v2 firmware contains bug fixes and interface change
1432 * for init buffer command
1433 */
1434 .fw_name[1] = "s5p-mfc-v6-v2.fw",
8f532a7f
AK
1435};
1436
ca5ea0c5 1437static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
5441e9da
AK
1438 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1439 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1440 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1441 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1442 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1443};
1444
ca5ea0c5 1445static struct s5p_mfc_buf_size buf_size_v7 = {
5441e9da
AK
1446 .fw = MAX_FW_SIZE_V7,
1447 .cpb = MAX_CPB_SIZE_V7,
1448 .priv = &mfc_buf_size_v7,
1449};
1450
ca5ea0c5 1451static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
5441e9da
AK
1452 .base = 0,
1453};
1454
1455static struct s5p_mfc_variant mfc_drvdata_v7 = {
1456 .version = MFC_VERSION_V7,
9aa5f008 1457 .version_bit = MFC_V7_BIT,
5441e9da
AK
1458 .port_num = MFC_NUM_PORTS_V7,
1459 .buf_size = &buf_size_v7,
1460 .buf_align = &mfc_buf_align_v7,
77ba6b73 1461 .fw_name[0] = "s5p-mfc-v7.fw",
5441e9da
AK
1462};
1463
ca5ea0c5 1464static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
e2b9deb2
KA
1465 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1466 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1467 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
3e594ce7
KA
1468 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1469 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
e2b9deb2
KA
1470};
1471
ca5ea0c5 1472static struct s5p_mfc_buf_size buf_size_v8 = {
e2b9deb2
KA
1473 .fw = MAX_FW_SIZE_V8,
1474 .cpb = MAX_CPB_SIZE_V8,
1475 .priv = &mfc_buf_size_v8,
1476};
1477
ca5ea0c5 1478static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
e2b9deb2
KA
1479 .base = 0,
1480};
1481
1482static struct s5p_mfc_variant mfc_drvdata_v8 = {
1483 .version = MFC_VERSION_V8,
1484 .version_bit = MFC_V8_BIT,
1485 .port_num = MFC_NUM_PORTS_V8,
1486 .buf_size = &buf_size_v8,
1487 .buf_align = &mfc_buf_align_v8,
77ba6b73 1488 .fw_name[0] = "s5p-mfc-v8.fw",
e2b9deb2
KA
1489};
1490
6425f646 1491static const struct platform_device_id mfc_driver_ids[] = {
8f532a7f
AK
1492 {
1493 .name = "s5p-mfc",
1494 .driver_data = (unsigned long)&mfc_drvdata_v5,
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1495 }, {
1496 .name = "s5p-mfc-v5",
1497 .driver_data = (unsigned long)&mfc_drvdata_v5,
1498 }, {
1499 .name = "s5p-mfc-v6",
1500 .driver_data = (unsigned long)&mfc_drvdata_v6,
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1501 }, {
1502 .name = "s5p-mfc-v7",
1503 .driver_data = (unsigned long)&mfc_drvdata_v7,
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1504 }, {
1505 .name = "s5p-mfc-v8",
1506 .driver_data = (unsigned long)&mfc_drvdata_v8,
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1507 },
1508 {},
1509};
1510MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1511
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1512static const struct of_device_id exynos_mfc_match[] = {
1513 {
1514 .compatible = "samsung,mfc-v5",
1515 .data = &mfc_drvdata_v5,
1516 }, {
1517 .compatible = "samsung,mfc-v6",
1518 .data = &mfc_drvdata_v6,
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1519 }, {
1520 .compatible = "samsung,mfc-v7",
1521 .data = &mfc_drvdata_v7,
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1522 }, {
1523 .compatible = "samsung,mfc-v8",
1524 .data = &mfc_drvdata_v8,
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1525 },
1526 {},
1527};
1528MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1529
1530static void *mfc_get_drv_data(struct platform_device *pdev)
1531{
1532 struct s5p_mfc_variant *driver_data = NULL;
1533
1534 if (pdev->dev.of_node) {
1535 const struct of_device_id *match;
a40a1382 1536 match = of_match_node(exynos_mfc_match,
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1537 pdev->dev.of_node);
1538 if (match)
1539 driver_data = (struct s5p_mfc_variant *)match->data;
1540 } else {
1541 driver_data = (struct s5p_mfc_variant *)
1542 platform_get_device_id(pdev)->driver_data;
1543 }
1544 return driver_data;
1545}
1546
1e393e90 1547static struct platform_driver s5p_mfc_driver = {
8f532a7f 1548 .probe = s5p_mfc_probe,
4c62e976 1549 .remove = s5p_mfc_remove,
8f532a7f 1550 .id_table = mfc_driver_ids,
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1551 .driver = {
1552 .name = S5P_MFC_NAME,
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1553 .pm = &s5p_mfc_pm_ops,
1554 .of_match_table = exynos_mfc_match,
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1555 },
1556};
1557
1d6629b1 1558module_platform_driver(s5p_mfc_driver);
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1559
1560MODULE_LICENSE("GPL");
1561MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1562MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1563
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