Commit | Line | Data |
---|---|---|
af935746 KD |
1 | /* |
2 | * Samsung S5P Multi Format Codec v 5.1 | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Kamil Debski, <k.debski@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
af935746 | 21 | #include <linux/videodev2.h> |
f9f715a9 | 22 | #include <media/v4l2-event.h> |
af935746 | 23 | #include <linux/workqueue.h> |
b27a23be | 24 | #include <linux/of.h> |
c139990e | 25 | #include <media/videobuf2-v4l2.h> |
43a1ea1f | 26 | #include "s5p_mfc_common.h" |
af935746 KD |
27 | #include "s5p_mfc_ctrl.h" |
28 | #include "s5p_mfc_debug.h" | |
29 | #include "s5p_mfc_dec.h" | |
30 | #include "s5p_mfc_enc.h" | |
31 | #include "s5p_mfc_intr.h" | |
43a1ea1f AK |
32 | #include "s5p_mfc_opr.h" |
33 | #include "s5p_mfc_cmd.h" | |
af935746 | 34 | #include "s5p_mfc_pm.h" |
af935746 KD |
35 | |
36 | #define S5P_MFC_NAME "s5p-mfc" | |
37 | #define S5P_MFC_DEC_NAME "s5p-mfc-dec" | |
38 | #define S5P_MFC_ENC_NAME "s5p-mfc-enc" | |
39 | ||
139adba6 MCC |
40 | int mfc_debug_level; |
41 | module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR); | |
af935746 KD |
42 | MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); |
43 | ||
44 | /* Helper functions for interrupt processing */ | |
7fb89eca | 45 | |
af935746 | 46 | /* Remove from hw execution round robin */ |
7fb89eca | 47 | void clear_work_bit(struct s5p_mfc_ctx *ctx) |
af935746 KD |
48 | { |
49 | struct s5p_mfc_dev *dev = ctx->dev; | |
50 | ||
51 | spin_lock(&dev->condlock); | |
7fb89eca | 52 | __clear_bit(ctx->num, &dev->ctx_work_bits); |
af935746 KD |
53 | spin_unlock(&dev->condlock); |
54 | } | |
55 | ||
7fb89eca AH |
56 | /* Add to hw execution round robin */ |
57 | void set_work_bit(struct s5p_mfc_ctx *ctx) | |
58 | { | |
59 | struct s5p_mfc_dev *dev = ctx->dev; | |
60 | ||
61 | spin_lock(&dev->condlock); | |
62 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
63 | spin_unlock(&dev->condlock); | |
64 | } | |
65 | ||
66 | /* Remove from hw execution round robin */ | |
67 | void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
68 | { | |
69 | struct s5p_mfc_dev *dev = ctx->dev; | |
70 | unsigned long flags; | |
71 | ||
72 | spin_lock_irqsave(&dev->condlock, flags); | |
73 | __clear_bit(ctx->num, &dev->ctx_work_bits); | |
74 | spin_unlock_irqrestore(&dev->condlock, flags); | |
75 | } | |
76 | ||
77 | /* Add to hw execution round robin */ | |
78 | void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
79 | { | |
80 | struct s5p_mfc_dev *dev = ctx->dev; | |
81 | unsigned long flags; | |
82 | ||
83 | spin_lock_irqsave(&dev->condlock, flags); | |
84 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
85 | spin_unlock_irqrestore(&dev->condlock, flags); | |
86 | } | |
87 | ||
af935746 KD |
88 | /* Wake up context wait_queue */ |
89 | static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, | |
90 | unsigned int err) | |
91 | { | |
92 | ctx->int_cond = 1; | |
93 | ctx->int_type = reason; | |
94 | ctx->int_err = err; | |
95 | wake_up(&ctx->queue); | |
96 | } | |
97 | ||
98 | /* Wake up device wait_queue */ | |
99 | static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, | |
100 | unsigned int err) | |
101 | { | |
102 | dev->int_cond = 1; | |
103 | dev->int_type = reason; | |
104 | dev->int_err = err; | |
105 | wake_up(&dev->queue); | |
106 | } | |
107 | ||
a13bba4f | 108 | static void s5p_mfc_watchdog(unsigned long arg) |
af935746 KD |
109 | { |
110 | struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; | |
111 | ||
112 | if (test_bit(0, &dev->hw_lock)) | |
113 | atomic_inc(&dev->watchdog_cnt); | |
114 | if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { | |
115 | /* This means that hw is busy and no interrupts were | |
116 | * generated by hw for the Nth time of running this | |
117 | * watchdog timer. This usually means a serious hw | |
118 | * error. Now it is time to kill all instances and | |
119 | * reset the MFC. */ | |
120 | mfc_err("Time out during waiting for HW\n"); | |
121 | queue_work(dev->watchdog_workqueue, &dev->watchdog_work); | |
122 | } | |
123 | dev->watchdog_timer.expires = jiffies + | |
124 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
125 | add_timer(&dev->watchdog_timer); | |
126 | } | |
127 | ||
128 | static void s5p_mfc_watchdog_worker(struct work_struct *work) | |
129 | { | |
130 | struct s5p_mfc_dev *dev; | |
131 | struct s5p_mfc_ctx *ctx; | |
132 | unsigned long flags; | |
133 | int mutex_locked; | |
134 | int i, ret; | |
135 | ||
136 | dev = container_of(work, struct s5p_mfc_dev, watchdog_work); | |
137 | ||
138 | mfc_err("Driver timeout error handling\n"); | |
139 | /* Lock the mutex that protects open and release. | |
140 | * This is necessary as they may load and unload firmware. */ | |
141 | mutex_locked = mutex_trylock(&dev->mfc_mutex); | |
142 | if (!mutex_locked) | |
143 | mfc_err("Error: some instance may be closing/opening\n"); | |
144 | spin_lock_irqsave(&dev->irqlock, flags); | |
145 | ||
146 | s5p_mfc_clock_off(); | |
147 | ||
148 | for (i = 0; i < MFC_NUM_CONTEXTS; i++) { | |
149 | ctx = dev->ctx[i]; | |
150 | if (!ctx) | |
151 | continue; | |
152 | ctx->state = MFCINST_ERROR; | |
e2c3be2a KD |
153 | s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, |
154 | &ctx->dst_queue, &ctx->vq_dst); | |
155 | s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, | |
156 | &ctx->src_queue, &ctx->vq_src); | |
af935746 | 157 | clear_work_bit(ctx); |
43a1ea1f | 158 | wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); |
af935746 KD |
159 | } |
160 | clear_bit(0, &dev->hw_lock); | |
161 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
b16e6448 AM |
162 | |
163 | /* De-init MFC */ | |
164 | s5p_mfc_deinit_hw(dev); | |
165 | ||
af935746 KD |
166 | /* Double check if there is at least one instance running. |
167 | * If no instance is in memory than no firmware should be present */ | |
168 | if (dev->num_inst > 0) { | |
46075006 | 169 | ret = s5p_mfc_load_firmware(dev); |
af935746 KD |
170 | if (ret) { |
171 | mfc_err("Failed to reload FW\n"); | |
172 | goto unlock; | |
173 | } | |
174 | s5p_mfc_clock_on(); | |
175 | ret = s5p_mfc_init_hw(dev); | |
176 | if (ret) | |
177 | mfc_err("Failed to reinit FW\n"); | |
178 | } | |
179 | unlock: | |
180 | if (mutex_locked) | |
181 | mutex_unlock(&dev->mfc_mutex); | |
182 | } | |
183 | ||
af935746 KD |
184 | static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) |
185 | { | |
186 | mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); | |
187 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); | |
188 | mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); | |
189 | } | |
190 | ||
191 | static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) | |
192 | { | |
193 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f | 194 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
195 | |
196 | ctx->state = MFCINST_FINISHED; | |
197 | ctx->sequence++; | |
198 | while (!list_empty(&ctx->dst_queue)) { | |
199 | dst_buf = list_entry(ctx->dst_queue.next, | |
200 | struct s5p_mfc_buf, list); | |
201 | mfc_debug(2, "Cleaning up buffer: %d\n", | |
2d700715 JS |
202 | dst_buf->b->vb2_buf.index); |
203 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0); | |
204 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0); | |
af935746 KD |
205 | list_del(&dst_buf->list); |
206 | ctx->dst_queue_cnt--; | |
2d700715 | 207 | dst_buf->b->sequence = (ctx->sequence++); |
af935746 | 208 | |
43a1ea1f AK |
209 | if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == |
210 | s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) | |
2d700715 | 211 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 212 | else |
2d700715 JS |
213 | dst_buf->b->field = V4L2_FIELD_INTERLACED; |
214 | dst_buf->b->flags |= V4L2_BUF_FLAG_LAST; | |
af935746 | 215 | |
2d700715 JS |
216 | ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index); |
217 | vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE); | |
af935746 KD |
218 | } |
219 | } | |
220 | ||
221 | static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) | |
222 | { | |
223 | struct s5p_mfc_dev *dev = ctx->dev; | |
224 | struct s5p_mfc_buf *dst_buf, *src_buf; | |
43a1ea1f AK |
225 | size_t dec_y_addr; |
226 | unsigned int frame_type; | |
227 | ||
bb21c54a | 228 | /* Make sure we actually have a new frame before continuing. */ |
43a1ea1f | 229 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); |
bb21c54a IF |
230 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) |
231 | return; | |
232 | dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); | |
af935746 KD |
233 | |
234 | /* Copy timestamp / timecode from decoded src to dst and set | |
bb21c54a | 235 | appropriate flags. */ |
af935746 KD |
236 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
237 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
2d700715 JS |
238 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
239 | == dec_y_addr) { | |
240 | dst_buf->b->timecode = | |
241 | src_buf->b->timecode; | |
242 | dst_buf->b->timestamp = | |
243 | src_buf->b->timestamp; | |
244 | dst_buf->b->flags &= | |
309f4d62 | 245 | ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
2d700715 JS |
246 | dst_buf->b->flags |= |
247 | src_buf->b->flags | |
309f4d62 | 248 | & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
af935746 KD |
249 | switch (frame_type) { |
250 | case S5P_FIMV_DECODE_FRAME_I_FRAME: | |
2d700715 | 251 | dst_buf->b->flags |= |
af935746 KD |
252 | V4L2_BUF_FLAG_KEYFRAME; |
253 | break; | |
254 | case S5P_FIMV_DECODE_FRAME_P_FRAME: | |
2d700715 | 255 | dst_buf->b->flags |= |
af935746 KD |
256 | V4L2_BUF_FLAG_PFRAME; |
257 | break; | |
258 | case S5P_FIMV_DECODE_FRAME_B_FRAME: | |
2d700715 | 259 | dst_buf->b->flags |= |
af935746 KD |
260 | V4L2_BUF_FLAG_BFRAME; |
261 | break; | |
bb21c54a IF |
262 | default: |
263 | /* Don't know how to handle | |
264 | S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */ | |
265 | mfc_debug(2, "Unexpected frame type: %d\n", | |
266 | frame_type); | |
af935746 KD |
267 | } |
268 | break; | |
269 | } | |
270 | } | |
271 | } | |
272 | ||
273 | static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) | |
274 | { | |
275 | struct s5p_mfc_dev *dev = ctx->dev; | |
276 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f AK |
277 | size_t dspl_y_addr; |
278 | unsigned int frame_type; | |
af935746 | 279 | |
43a1ea1f | 280 | dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); |
7c672812 SS |
281 | if (IS_MFCV6_PLUS(dev)) |
282 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
283 | get_disp_frame_type, ctx); | |
284 | else | |
285 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
286 | get_dec_frame_type, dev); | |
43a1ea1f | 287 | |
af935746 KD |
288 | /* If frame is same as previous then skip and do not dequeue */ |
289 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { | |
290 | if (!ctx->after_packed_pb) | |
291 | ctx->sequence++; | |
292 | ctx->after_packed_pb = 0; | |
293 | return; | |
294 | } | |
295 | ctx->sequence++; | |
296 | /* The MFC returns address of the buffer, now we have to | |
297 | * check which videobuf does it correspond to */ | |
298 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
299 | /* Check if this is the buffer we're looking for */ | |
2d700715 JS |
300 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
301 | == dspl_y_addr) { | |
af935746 KD |
302 | list_del(&dst_buf->list); |
303 | ctx->dst_queue_cnt--; | |
2d700715 | 304 | dst_buf->b->sequence = ctx->sequence; |
43a1ea1f AK |
305 | if (s5p_mfc_hw_call(dev->mfc_ops, |
306 | get_pic_type_top, ctx) == | |
307 | s5p_mfc_hw_call(dev->mfc_ops, | |
308 | get_pic_type_bot, ctx)) | |
2d700715 | 309 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 310 | else |
2d700715 | 311 | dst_buf->b->field = |
af935746 | 312 | V4L2_FIELD_INTERLACED; |
2d700715 JS |
313 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, |
314 | ctx->luma_size); | |
315 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, | |
316 | ctx->chroma_size); | |
317 | clear_bit(dst_buf->b->vb2_buf.index, | |
af935746 KD |
318 | &ctx->dec_dst_flag); |
319 | ||
2d700715 JS |
320 | vb2_buffer_done(&dst_buf->b->vb2_buf, err ? |
321 | VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); | |
af935746 | 322 | |
af935746 KD |
323 | break; |
324 | } | |
325 | } | |
326 | } | |
327 | ||
328 | /* Handle frame decoding interrupt */ | |
329 | static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, | |
330 | unsigned int reason, unsigned int err) | |
331 | { | |
332 | struct s5p_mfc_dev *dev = ctx->dev; | |
333 | unsigned int dst_frame_status; | |
a0517f5d | 334 | unsigned int dec_frame_status; |
af935746 KD |
335 | struct s5p_mfc_buf *src_buf; |
336 | unsigned long flags; | |
337 | unsigned int res_change; | |
338 | ||
43a1ea1f | 339 | dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
af935746 | 340 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; |
a0517f5d PO |
341 | dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev) |
342 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; | |
f96f3cfa JP |
343 | res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
344 | & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) | |
345 | >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; | |
af935746 KD |
346 | mfc_debug(2, "Frame Status: %x\n", dst_frame_status); |
347 | if (ctx->state == MFCINST_RES_CHANGE_INIT) | |
348 | ctx->state = MFCINST_RES_CHANGE_FLUSH; | |
f96f3cfa JP |
349 | if (res_change == S5P_FIMV_RES_INCREASE || |
350 | res_change == S5P_FIMV_RES_DECREASE) { | |
af935746 | 351 | ctx->state = MFCINST_RES_CHANGE_INIT; |
e2c3be2a | 352 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 353 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 354 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 355 | s5p_mfc_clock_off(); |
e2c3be2a | 356 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
357 | return; |
358 | } | |
359 | if (ctx->dpb_flush_flag) | |
360 | ctx->dpb_flush_flag = 0; | |
361 | ||
362 | spin_lock_irqsave(&dev->irqlock, flags); | |
363 | /* All frames remaining in the buffer have been extracted */ | |
364 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { | |
365 | if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { | |
0520e4cc PO |
366 | static const struct v4l2_event ev_src_ch = { |
367 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
368 | .u.src_change.changes = | |
369 | V4L2_EVENT_SRC_CH_RESOLUTION, | |
370 | }; | |
371 | ||
af935746 KD |
372 | s5p_mfc_handle_frame_all_extracted(ctx); |
373 | ctx->state = MFCINST_RES_CHANGE_END; | |
0520e4cc PO |
374 | v4l2_event_queue_fh(&ctx->fh, &ev_src_ch); |
375 | ||
af935746 KD |
376 | goto leave_handle_frame; |
377 | } else { | |
378 | s5p_mfc_handle_frame_all_extracted(ctx); | |
379 | } | |
380 | } | |
381 | ||
a0517f5d | 382 | if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) |
af935746 KD |
383 | s5p_mfc_handle_frame_copy_time(ctx); |
384 | ||
385 | /* A frame has been decoded and is in the buffer */ | |
386 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || | |
387 | dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { | |
388 | s5p_mfc_handle_frame_new(ctx, err); | |
389 | } else { | |
390 | mfc_debug(2, "No frame decode\n"); | |
391 | } | |
392 | /* Mark source buffer as complete */ | |
393 | if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY | |
394 | && !list_empty(&ctx->src_queue)) { | |
395 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, | |
396 | list); | |
43a1ea1f AK |
397 | ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, |
398 | get_consumed_stream, dev); | |
399 | if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && | |
f49f3ed5 | 400 | ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC && |
d2a0db1e | 401 | ctx->consumed_stream + STUFF_BYTE < |
2d700715 | 402 | src_buf->b->vb2_buf.planes[0].bytesused) { |
af935746 KD |
403 | /* Run MFC again on the same buffer */ |
404 | mfc_debug(2, "Running again the same buffer\n"); | |
405 | ctx->after_packed_pb = 1; | |
406 | } else { | |
af935746 KD |
407 | mfc_debug(2, "MFC needs next buffer\n"); |
408 | ctx->consumed_stream = 0; | |
a34026e7 KD |
409 | if (src_buf->flags & MFC_BUF_FLAG_EOS) |
410 | ctx->state = MFCINST_FINISHING; | |
af935746 KD |
411 | list_del(&src_buf->list); |
412 | ctx->src_queue_cnt--; | |
43a1ea1f | 413 | if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) |
2d700715 JS |
414 | vb2_buffer_done(&src_buf->b->vb2_buf, |
415 | VB2_BUF_STATE_ERROR); | |
af935746 | 416 | else |
2d700715 JS |
417 | vb2_buffer_done(&src_buf->b->vb2_buf, |
418 | VB2_BUF_STATE_DONE); | |
af935746 KD |
419 | } |
420 | } | |
421 | leave_handle_frame: | |
422 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
423 | if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) | |
e9d98ddc | 424 | || ctx->dst_queue_cnt < ctx->pb_count) |
af935746 | 425 | clear_work_bit(ctx); |
e2c3be2a | 426 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 427 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 428 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 429 | s5p_mfc_clock_off(); |
76a4ddbd P |
430 | /* if suspending, wake up device and do not try_run again*/ |
431 | if (test_bit(0, &dev->enter_suspend)) | |
432 | wake_up_dev(dev, reason, err); | |
433 | else | |
e2c3be2a | 434 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
435 | } |
436 | ||
437 | /* Error handling for interrupt */ | |
7296e25f KD |
438 | static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, |
439 | struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) | |
af935746 | 440 | { |
af935746 KD |
441 | unsigned long flags; |
442 | ||
af935746 | 443 | mfc_err("Interrupt Error: %08x\n", err); |
af935746 | 444 | |
7296e25f KD |
445 | if (ctx != NULL) { |
446 | /* Error recovery is dependent on the state of context */ | |
447 | switch (ctx->state) { | |
448 | case MFCINST_RES_CHANGE_INIT: | |
449 | case MFCINST_RES_CHANGE_FLUSH: | |
450 | case MFCINST_RES_CHANGE_END: | |
451 | case MFCINST_FINISHING: | |
452 | case MFCINST_FINISHED: | |
453 | case MFCINST_RUNNING: | |
39c1cb2b | 454 | /* It is highly probable that an error occurred |
7296e25f KD |
455 | * while decoding a frame */ |
456 | clear_work_bit(ctx); | |
457 | ctx->state = MFCINST_ERROR; | |
458 | /* Mark all dst buffers as having an error */ | |
459 | spin_lock_irqsave(&dev->irqlock, flags); | |
e2c3be2a | 460 | s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, |
7296e25f KD |
461 | &ctx->dst_queue, &ctx->vq_dst); |
462 | /* Mark all src buffers as having an error */ | |
e2c3be2a | 463 | s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, |
7296e25f KD |
464 | &ctx->src_queue, &ctx->vq_src); |
465 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
466 | wake_up_ctx(ctx, reason, err); | |
467 | break; | |
468 | default: | |
469 | clear_work_bit(ctx); | |
470 | ctx->state = MFCINST_ERROR; | |
471 | wake_up_ctx(ctx, reason, err); | |
472 | break; | |
473 | } | |
af935746 | 474 | } |
9a7bc6b0 | 475 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
e2c3be2a | 476 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
7296e25f KD |
477 | s5p_mfc_clock_off(); |
478 | wake_up_dev(dev, reason, err); | |
af935746 KD |
479 | return; |
480 | } | |
481 | ||
482 | /* Header parsing interrupt handling */ | |
483 | static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, | |
484 | unsigned int reason, unsigned int err) | |
485 | { | |
486 | struct s5p_mfc_dev *dev; | |
af935746 | 487 | |
1259762f | 488 | if (ctx == NULL) |
af935746 KD |
489 | return; |
490 | dev = ctx->dev; | |
491 | if (ctx->c_ops->post_seq_start) { | |
492 | if (ctx->c_ops->post_seq_start(ctx)) | |
493 | mfc_err("post_seq_start() failed\n"); | |
494 | } else { | |
43a1ea1f AK |
495 | ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, |
496 | dev); | |
497 | ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, | |
498 | dev); | |
af935746 | 499 | |
e2c3be2a | 500 | s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx); |
8f532a7f | 501 | |
e9d98ddc | 502 | ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, |
43a1ea1f | 503 | dev); |
f96f3cfa JP |
504 | ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, |
505 | dev); | |
bb869368 | 506 | if (ctx->img_width == 0 || ctx->img_height == 0) |
af935746 KD |
507 | ctx->state = MFCINST_ERROR; |
508 | else | |
509 | ctx->state = MFCINST_HEAD_PARSED; | |
f96f3cfa JP |
510 | |
511 | if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
512 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && | |
513 | !list_empty(&ctx->src_queue)) { | |
514 | struct s5p_mfc_buf *src_buf; | |
515 | src_buf = list_entry(ctx->src_queue.next, | |
516 | struct s5p_mfc_buf, list); | |
517 | if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, | |
518 | dev) < | |
2d700715 | 519 | src_buf->b->vb2_buf.planes[0].bytesused) |
f96f3cfa JP |
520 | ctx->head_processed = 0; |
521 | else | |
522 | ctx->head_processed = 1; | |
523 | } else { | |
524 | ctx->head_processed = 1; | |
525 | } | |
af935746 | 526 | } |
e2c3be2a | 527 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 528 | clear_work_bit(ctx); |
9a7bc6b0 | 529 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 530 | s5p_mfc_clock_off(); |
e2c3be2a | 531 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
532 | wake_up_ctx(ctx, reason, err); |
533 | } | |
534 | ||
535 | /* Header parsing interrupt handling */ | |
536 | static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, | |
537 | unsigned int reason, unsigned int err) | |
538 | { | |
539 | struct s5p_mfc_buf *src_buf; | |
540 | struct s5p_mfc_dev *dev; | |
541 | unsigned long flags; | |
542 | ||
1259762f | 543 | if (ctx == NULL) |
af935746 KD |
544 | return; |
545 | dev = ctx->dev; | |
e2c3be2a | 546 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
547 | ctx->int_type = reason; |
548 | ctx->int_err = err; | |
549 | ctx->int_cond = 1; | |
7fb89eca | 550 | clear_work_bit(ctx); |
af935746 KD |
551 | if (err == 0) { |
552 | ctx->state = MFCINST_RUNNING; | |
f96f3cfa | 553 | if (!ctx->dpb_flush_flag && ctx->head_processed) { |
af935746 KD |
554 | spin_lock_irqsave(&dev->irqlock, flags); |
555 | if (!list_empty(&ctx->src_queue)) { | |
556 | src_buf = list_entry(ctx->src_queue.next, | |
557 | struct s5p_mfc_buf, list); | |
558 | list_del(&src_buf->list); | |
559 | ctx->src_queue_cnt--; | |
2d700715 | 560 | vb2_buffer_done(&src_buf->b->vb2_buf, |
af935746 KD |
561 | VB2_BUF_STATE_DONE); |
562 | } | |
563 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
564 | } else { | |
565 | ctx->dpb_flush_flag = 0; | |
566 | } | |
9a7bc6b0 | 567 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
568 | |
569 | s5p_mfc_clock_off(); | |
570 | ||
571 | wake_up(&ctx->queue); | |
e2c3be2a | 572 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 | 573 | } else { |
9a7bc6b0 | 574 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
575 | |
576 | s5p_mfc_clock_off(); | |
577 | ||
578 | wake_up(&ctx->queue); | |
579 | } | |
580 | } | |
581 | ||
f9f715a9 AH |
582 | static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, |
583 | unsigned int reason, unsigned int err) | |
584 | { | |
585 | struct s5p_mfc_dev *dev = ctx->dev; | |
586 | struct s5p_mfc_buf *mb_entry; | |
587 | ||
4130eabc | 588 | mfc_debug(2, "Stream completed\n"); |
f9f715a9 AH |
589 | |
590 | s5p_mfc_clear_int_flags(dev); | |
591 | ctx->int_type = reason; | |
592 | ctx->int_err = err; | |
593 | ctx->state = MFCINST_FINISHED; | |
594 | ||
595 | spin_lock(&dev->irqlock); | |
596 | if (!list_empty(&ctx->dst_queue)) { | |
597 | mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, | |
598 | list); | |
599 | list_del(&mb_entry->list); | |
600 | ctx->dst_queue_cnt--; | |
2d700715 JS |
601 | vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0); |
602 | vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE); | |
f9f715a9 AH |
603 | } |
604 | spin_unlock(&dev->irqlock); | |
605 | ||
606 | clear_work_bit(ctx); | |
607 | ||
e8256447 | 608 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
f9f715a9 AH |
609 | |
610 | s5p_mfc_clock_off(); | |
611 | wake_up(&ctx->queue); | |
e2c3be2a | 612 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
f9f715a9 AH |
613 | } |
614 | ||
af935746 KD |
615 | /* Interrupt processing */ |
616 | static irqreturn_t s5p_mfc_irq(int irq, void *priv) | |
617 | { | |
618 | struct s5p_mfc_dev *dev = priv; | |
619 | struct s5p_mfc_ctx *ctx; | |
620 | unsigned int reason; | |
621 | unsigned int err; | |
622 | ||
623 | mfc_debug_enter(); | |
624 | /* Reset the timeout watchdog */ | |
625 | atomic_set(&dev->watchdog_cnt, 0); | |
626 | ctx = dev->ctx[dev->curr_ctx]; | |
627 | /* Get the reason of interrupt and the error code */ | |
43a1ea1f AK |
628 | reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); |
629 | err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); | |
af935746 KD |
630 | mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); |
631 | switch (reason) { | |
43a1ea1f | 632 | case S5P_MFC_R2H_CMD_ERR_RET: |
39c1cb2b | 633 | /* An error has occurred */ |
af935746 | 634 | if (ctx->state == MFCINST_RUNNING && |
43a1ea1f AK |
635 | s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= |
636 | dev->warn_start) | |
af935746 KD |
637 | s5p_mfc_handle_frame(ctx, reason, err); |
638 | else | |
7296e25f | 639 | s5p_mfc_handle_error(dev, ctx, reason, err); |
af935746 KD |
640 | clear_bit(0, &dev->enter_suspend); |
641 | break; | |
642 | ||
43a1ea1f AK |
643 | case S5P_MFC_R2H_CMD_SLICE_DONE_RET: |
644 | case S5P_MFC_R2H_CMD_FIELD_DONE_RET: | |
645 | case S5P_MFC_R2H_CMD_FRAME_DONE_RET: | |
af935746 KD |
646 | if (ctx->c_ops->post_frame_start) { |
647 | if (ctx->c_ops->post_frame_start(ctx)) | |
648 | mfc_err("post_frame_start() failed\n"); | |
e2c3be2a | 649 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 650 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 651 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 652 | s5p_mfc_clock_off(); |
e2c3be2a | 653 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
654 | } else { |
655 | s5p_mfc_handle_frame(ctx, reason, err); | |
656 | } | |
657 | break; | |
658 | ||
43a1ea1f | 659 | case S5P_MFC_R2H_CMD_SEQ_DONE_RET: |
af935746 KD |
660 | s5p_mfc_handle_seq_done(ctx, reason, err); |
661 | break; | |
662 | ||
43a1ea1f AK |
663 | case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: |
664 | ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); | |
af935746 KD |
665 | ctx->state = MFCINST_GOT_INST; |
666 | clear_work_bit(ctx); | |
667 | wake_up(&ctx->queue); | |
668 | goto irq_cleanup_hw; | |
669 | ||
43a1ea1f | 670 | case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: |
af935746 | 671 | clear_work_bit(ctx); |
9d87e837 | 672 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 KD |
673 | ctx->state = MFCINST_FREE; |
674 | wake_up(&ctx->queue); | |
675 | goto irq_cleanup_hw; | |
676 | ||
43a1ea1f AK |
677 | case S5P_MFC_R2H_CMD_SYS_INIT_RET: |
678 | case S5P_MFC_R2H_CMD_FW_STATUS_RET: | |
679 | case S5P_MFC_R2H_CMD_SLEEP_RET: | |
680 | case S5P_MFC_R2H_CMD_WAKEUP_RET: | |
af935746 KD |
681 | if (ctx) |
682 | clear_work_bit(ctx); | |
e2c3be2a | 683 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
684 | wake_up_dev(dev, reason, err); |
685 | clear_bit(0, &dev->hw_lock); | |
686 | clear_bit(0, &dev->enter_suspend); | |
687 | break; | |
688 | ||
43a1ea1f | 689 | case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: |
af935746 KD |
690 | s5p_mfc_handle_init_buffers(ctx, reason, err); |
691 | break; | |
f9f715a9 | 692 | |
43a1ea1f | 693 | case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: |
f9f715a9 AH |
694 | s5p_mfc_handle_stream_complete(ctx, reason, err); |
695 | break; | |
696 | ||
8f23cc02 AK |
697 | case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: |
698 | clear_work_bit(ctx); | |
699 | ctx->state = MFCINST_RUNNING; | |
700 | wake_up(&ctx->queue); | |
701 | goto irq_cleanup_hw; | |
702 | ||
af935746 KD |
703 | default: |
704 | mfc_debug(2, "Unknown int reason\n"); | |
e2c3be2a | 705 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
706 | } |
707 | mfc_debug_leave(); | |
708 | return IRQ_HANDLED; | |
709 | irq_cleanup_hw: | |
e2c3be2a | 710 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
711 | ctx->int_type = reason; |
712 | ctx->int_err = err; | |
713 | ctx->int_cond = 1; | |
714 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
715 | mfc_err("Failed to unlock hw\n"); | |
716 | ||
717 | s5p_mfc_clock_off(); | |
718 | ||
e2c3be2a | 719 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
720 | mfc_debug(2, "Exit via irq_cleanup_hw\n"); |
721 | return IRQ_HANDLED; | |
722 | } | |
723 | ||
724 | /* Open an MFC node */ | |
725 | static int s5p_mfc_open(struct file *file) | |
726 | { | |
b80cb8dc | 727 | struct video_device *vdev = video_devdata(file); |
af935746 KD |
728 | struct s5p_mfc_dev *dev = video_drvdata(file); |
729 | struct s5p_mfc_ctx *ctx = NULL; | |
730 | struct vb2_queue *q; | |
af935746 KD |
731 | int ret = 0; |
732 | ||
733 | mfc_debug_enter(); | |
bc738301 HV |
734 | if (mutex_lock_interruptible(&dev->mfc_mutex)) |
735 | return -ERESTARTSYS; | |
af935746 KD |
736 | dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ |
737 | /* Allocate memory for context */ | |
bae061b4 | 738 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
af935746 KD |
739 | if (!ctx) { |
740 | mfc_err("Not enough memory\n"); | |
741 | ret = -ENOMEM; | |
742 | goto err_alloc; | |
743 | } | |
55647a99 | 744 | v4l2_fh_init(&ctx->fh, vdev); |
af935746 KD |
745 | file->private_data = &ctx->fh; |
746 | v4l2_fh_add(&ctx->fh); | |
747 | ctx->dev = dev; | |
748 | INIT_LIST_HEAD(&ctx->src_queue); | |
749 | INIT_LIST_HEAD(&ctx->dst_queue); | |
750 | ctx->src_queue_cnt = 0; | |
751 | ctx->dst_queue_cnt = 0; | |
752 | /* Get context number */ | |
753 | ctx->num = 0; | |
754 | while (dev->ctx[ctx->num]) { | |
755 | ctx->num++; | |
756 | if (ctx->num >= MFC_NUM_CONTEXTS) { | |
757 | mfc_err("Too many open contexts\n"); | |
758 | ret = -EBUSY; | |
759 | goto err_no_ctx; | |
760 | } | |
761 | } | |
762 | /* Mark context as idle */ | |
7fb89eca | 763 | clear_work_bit_irqsave(ctx); |
af935746 | 764 | dev->ctx[ctx->num] = ctx; |
b80cb8dc | 765 | if (vdev == dev->vfd_dec) { |
af935746 KD |
766 | ctx->type = MFCINST_DECODER; |
767 | ctx->c_ops = get_dec_codec_ops(); | |
43a1ea1f | 768 | s5p_mfc_dec_init(ctx); |
af935746 KD |
769 | /* Setup ctrl handler */ |
770 | ret = s5p_mfc_dec_ctrls_setup(ctx); | |
771 | if (ret) { | |
772 | mfc_err("Failed to setup mfc controls\n"); | |
773 | goto err_ctrls_setup; | |
774 | } | |
b80cb8dc | 775 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
776 | ctx->type = MFCINST_ENCODER; |
777 | ctx->c_ops = get_enc_codec_ops(); | |
778 | /* only for encoder */ | |
779 | INIT_LIST_HEAD(&ctx->ref_queue); | |
780 | ctx->ref_queue_cnt = 0; | |
43a1ea1f | 781 | s5p_mfc_enc_init(ctx); |
af935746 KD |
782 | /* Setup ctrl handler */ |
783 | ret = s5p_mfc_enc_ctrls_setup(ctx); | |
784 | if (ret) { | |
785 | mfc_err("Failed to setup mfc controls\n"); | |
786 | goto err_ctrls_setup; | |
787 | } | |
788 | } else { | |
789 | ret = -ENOENT; | |
790 | goto err_bad_node; | |
791 | } | |
792 | ctx->fh.ctrl_handler = &ctx->ctrl_handler; | |
9d87e837 | 793 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 KD |
794 | /* Load firmware if this is the first instance */ |
795 | if (dev->num_inst == 1) { | |
796 | dev->watchdog_timer.expires = jiffies + | |
797 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
798 | add_timer(&dev->watchdog_timer); | |
799 | ret = s5p_mfc_power_on(); | |
800 | if (ret < 0) { | |
801 | mfc_err("power on failed\n"); | |
802 | goto err_pwr_enable; | |
803 | } | |
804 | s5p_mfc_clock_on(); | |
2e731e44 KD |
805 | ret = s5p_mfc_load_firmware(dev); |
806 | if (ret) { | |
807 | s5p_mfc_clock_off(); | |
808 | goto err_load_fw; | |
809 | } | |
af935746 KD |
810 | /* Init the FW */ |
811 | ret = s5p_mfc_init_hw(dev); | |
2e731e44 | 812 | s5p_mfc_clock_off(); |
af935746 KD |
813 | if (ret) |
814 | goto err_init_hw; | |
af935746 KD |
815 | } |
816 | /* Init videobuf2 queue for CAPTURE */ | |
817 | q = &ctx->vq_dst; | |
818 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
819 | q->drv_priv = &ctx->fh; | |
654a731b | 820 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 821 | if (vdev == dev->vfd_dec) { |
af935746 KD |
822 | q->io_modes = VB2_MMAP; |
823 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 824 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
825 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
826 | q->ops = get_enc_queue_ops(); | |
827 | } else { | |
828 | ret = -ENOENT; | |
829 | goto err_queue_init; | |
830 | } | |
749ae716 | 831 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 832 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
833 | ret = vb2_queue_init(q); |
834 | if (ret) { | |
835 | mfc_err("Failed to initialize videobuf2 queue(capture)\n"); | |
836 | goto err_queue_init; | |
837 | } | |
838 | /* Init videobuf2 queue for OUTPUT */ | |
839 | q = &ctx->vq_src; | |
840 | q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
841 | q->io_modes = VB2_MMAP; | |
842 | q->drv_priv = &ctx->fh; | |
41f03a00 | 843 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 844 | if (vdev == dev->vfd_dec) { |
af935746 KD |
845 | q->io_modes = VB2_MMAP; |
846 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 847 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
848 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
849 | q->ops = get_enc_queue_ops(); | |
850 | } else { | |
851 | ret = -ENOENT; | |
852 | goto err_queue_init; | |
853 | } | |
e6c9dec3 KD |
854 | /* One way to indicate end-of-stream for MFC is to set the |
855 | * bytesused == 0. However by default videobuf2 handles bytesused | |
856 | * equal to 0 as a special case and changes its value to the size | |
857 | * of the buffer. Set the allow_zero_bytesused flag so that videobuf2 | |
858 | * will keep the value of bytesused intact. | |
859 | */ | |
860 | q->allow_zero_bytesused = 1; | |
749ae716 | 861 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 862 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
863 | ret = vb2_queue_init(q); |
864 | if (ret) { | |
865 | mfc_err("Failed to initialize videobuf2 queue(output)\n"); | |
866 | goto err_queue_init; | |
867 | } | |
868 | init_waitqueue_head(&ctx->queue); | |
bc738301 | 869 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
870 | mfc_debug_leave(); |
871 | return ret; | |
39c1cb2b | 872 | /* Deinit when failure occurred */ |
af935746 | 873 | err_queue_init: |
2e731e44 KD |
874 | if (dev->num_inst == 1) |
875 | s5p_mfc_deinit_hw(dev); | |
af935746 | 876 | err_init_hw: |
2e731e44 | 877 | err_load_fw: |
af935746 KD |
878 | err_pwr_enable: |
879 | if (dev->num_inst == 1) { | |
880 | if (s5p_mfc_power_off() < 0) | |
881 | mfc_err("power off failed\n"); | |
1b73ba0b | 882 | del_timer_sync(&dev->watchdog_timer); |
af935746 KD |
883 | } |
884 | err_ctrls_setup: | |
885 | s5p_mfc_dec_ctrls_delete(ctx); | |
886 | err_bad_node: | |
1b73ba0b | 887 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
888 | err_no_ctx: |
889 | v4l2_fh_del(&ctx->fh); | |
890 | v4l2_fh_exit(&ctx->fh); | |
891 | kfree(ctx); | |
892 | err_alloc: | |
893 | dev->num_inst--; | |
bc738301 | 894 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
895 | mfc_debug_leave(); |
896 | return ret; | |
897 | } | |
898 | ||
899 | /* Release MFC context */ | |
900 | static int s5p_mfc_release(struct file *file) | |
901 | { | |
902 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
903 | struct s5p_mfc_dev *dev = ctx->dev; | |
af935746 KD |
904 | |
905 | mfc_debug_enter(); | |
bc738301 | 906 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
907 | s5p_mfc_clock_on(); |
908 | vb2_queue_release(&ctx->vq_src); | |
909 | vb2_queue_release(&ctx->vq_dst); | |
910 | /* Mark context as idle */ | |
7fb89eca | 911 | clear_work_bit_irqsave(ctx); |
9d87e837 | 912 | /* If instance was initialised and not yet freed, |
39c1cb2b | 913 | * return instance and free resources */ |
9d87e837 | 914 | if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) { |
af935746 | 915 | mfc_debug(2, "Has to free instance\n"); |
818cd91a | 916 | s5p_mfc_close_mfc_inst(dev, ctx); |
af935746 KD |
917 | } |
918 | /* hardware locking scheme */ | |
919 | if (dev->curr_ctx == ctx->num) | |
920 | clear_bit(0, &dev->hw_lock); | |
921 | dev->num_inst--; | |
922 | if (dev->num_inst == 0) { | |
2e731e44 | 923 | mfc_debug(2, "Last instance\n"); |
43a1ea1f | 924 | s5p_mfc_deinit_hw(dev); |
af935746 KD |
925 | del_timer_sync(&dev->watchdog_timer); |
926 | if (s5p_mfc_power_off() < 0) | |
927 | mfc_err("Power off failed\n"); | |
928 | } | |
929 | mfc_debug(2, "Shutting down clock\n"); | |
930 | s5p_mfc_clock_off(); | |
1259762f | 931 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
932 | s5p_mfc_dec_ctrls_delete(ctx); |
933 | v4l2_fh_del(&ctx->fh); | |
934 | v4l2_fh_exit(&ctx->fh); | |
935 | kfree(ctx); | |
936 | mfc_debug_leave(); | |
bc738301 | 937 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
938 | return 0; |
939 | } | |
940 | ||
941 | /* Poll */ | |
942 | static unsigned int s5p_mfc_poll(struct file *file, | |
943 | struct poll_table_struct *wait) | |
944 | { | |
945 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
946 | struct s5p_mfc_dev *dev = ctx->dev; | |
947 | struct vb2_queue *src_q, *dst_q; | |
948 | struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; | |
949 | unsigned int rc = 0; | |
950 | unsigned long flags; | |
951 | ||
bc738301 | 952 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
953 | src_q = &ctx->vq_src; |
954 | dst_q = &ctx->vq_dst; | |
955 | /* | |
956 | * There has to be at least one buffer queued on each queued_list, which | |
957 | * means either in driver already or waiting for driver to claim it | |
958 | * and start processing. | |
959 | */ | |
960 | if ((!src_q->streaming || list_empty(&src_q->queued_list)) | |
961 | && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { | |
962 | rc = POLLERR; | |
963 | goto end; | |
964 | } | |
965 | mutex_unlock(&dev->mfc_mutex); | |
f9f715a9 | 966 | poll_wait(file, &ctx->fh.wait, wait); |
af935746 KD |
967 | poll_wait(file, &src_q->done_wq, wait); |
968 | poll_wait(file, &dst_q->done_wq, wait); | |
969 | mutex_lock(&dev->mfc_mutex); | |
f9f715a9 AH |
970 | if (v4l2_event_pending(&ctx->fh)) |
971 | rc |= POLLPRI; | |
af935746 KD |
972 | spin_lock_irqsave(&src_q->done_lock, flags); |
973 | if (!list_empty(&src_q->done_list)) | |
974 | src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, | |
975 | done_entry); | |
976 | if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE | |
977 | || src_vb->state == VB2_BUF_STATE_ERROR)) | |
978 | rc |= POLLOUT | POLLWRNORM; | |
979 | spin_unlock_irqrestore(&src_q->done_lock, flags); | |
980 | spin_lock_irqsave(&dst_q->done_lock, flags); | |
981 | if (!list_empty(&dst_q->done_list)) | |
982 | dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, | |
983 | done_entry); | |
984 | if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE | |
985 | || dst_vb->state == VB2_BUF_STATE_ERROR)) | |
986 | rc |= POLLIN | POLLRDNORM; | |
987 | spin_unlock_irqrestore(&dst_q->done_lock, flags); | |
988 | end: | |
bc738301 | 989 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
990 | return rc; |
991 | } | |
992 | ||
993 | /* Mmap */ | |
994 | static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) | |
995 | { | |
996 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
bc738301 | 997 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
998 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
999 | int ret; | |
bc738301 HV |
1000 | |
1001 | if (mutex_lock_interruptible(&dev->mfc_mutex)) | |
1002 | return -ERESTARTSYS; | |
af935746 KD |
1003 | if (offset < DST_QUEUE_OFF_BASE) { |
1004 | mfc_debug(2, "mmaping source\n"); | |
1005 | ret = vb2_mmap(&ctx->vq_src, vma); | |
1006 | } else { /* capture */ | |
1007 | mfc_debug(2, "mmaping destination\n"); | |
1008 | vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); | |
1009 | ret = vb2_mmap(&ctx->vq_dst, vma); | |
1010 | } | |
bc738301 | 1011 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
1012 | return ret; |
1013 | } | |
1014 | ||
1015 | /* v4l2 ops */ | |
1016 | static const struct v4l2_file_operations s5p_mfc_fops = { | |
1017 | .owner = THIS_MODULE, | |
1018 | .open = s5p_mfc_open, | |
1019 | .release = s5p_mfc_release, | |
1020 | .poll = s5p_mfc_poll, | |
1021 | .unlocked_ioctl = video_ioctl2, | |
1022 | .mmap = s5p_mfc_mmap, | |
1023 | }; | |
1024 | ||
1025 | static int match_child(struct device *dev, void *data) | |
1026 | { | |
1027 | if (!dev_name(dev)) | |
1028 | return 0; | |
1029 | return !strcmp(dev_name(dev), (char *)data); | |
1030 | } | |
1031 | ||
b27a23be AK |
1032 | static void *mfc_get_drv_data(struct platform_device *pdev); |
1033 | ||
6e83e6e2 AK |
1034 | static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) |
1035 | { | |
65fccab5 | 1036 | unsigned int mem_info[2] = { }; |
6e83e6e2 AK |
1037 | |
1038 | dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, | |
1039 | sizeof(struct device), GFP_KERNEL); | |
1040 | if (!dev->mem_dev_l) { | |
1041 | mfc_err("Not enough memory\n"); | |
1042 | return -ENOMEM; | |
1043 | } | |
1044 | device_initialize(dev->mem_dev_l); | |
1045 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1046 | "samsung,mfc-l", mem_info, 2); | |
1047 | if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], | |
1048 | mem_info[0], mem_info[1], | |
1049 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1050 | mfc_err("Failed to declare coherent memory for\n" | |
1051 | "MFC device\n"); | |
1052 | return -ENOMEM; | |
1053 | } | |
1054 | ||
1055 | dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, | |
1056 | sizeof(struct device), GFP_KERNEL); | |
1057 | if (!dev->mem_dev_r) { | |
1058 | mfc_err("Not enough memory\n"); | |
1059 | return -ENOMEM; | |
1060 | } | |
1061 | device_initialize(dev->mem_dev_r); | |
1062 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1063 | "samsung,mfc-r", mem_info, 2); | |
1064 | if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], | |
1065 | mem_info[0], mem_info[1], | |
1066 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1067 | pr_err("Failed to declare coherent memory for\n" | |
1068 | "MFC device\n"); | |
1069 | return -ENOMEM; | |
1070 | } | |
1071 | return 0; | |
1072 | } | |
1073 | ||
af935746 | 1074 | /* MFC probe function */ |
1e393e90 | 1075 | static int s5p_mfc_probe(struct platform_device *pdev) |
af935746 KD |
1076 | { |
1077 | struct s5p_mfc_dev *dev; | |
1078 | struct video_device *vfd; | |
1079 | struct resource *res; | |
1080 | int ret; | |
1081 | ||
1082 | pr_debug("%s++\n", __func__); | |
bae061b4 | 1083 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
af935746 KD |
1084 | if (!dev) { |
1085 | dev_err(&pdev->dev, "Not enough memory for MFC device\n"); | |
1086 | return -ENOMEM; | |
1087 | } | |
1088 | ||
1089 | spin_lock_init(&dev->irqlock); | |
1090 | spin_lock_init(&dev->condlock); | |
1091 | dev->plat_dev = pdev; | |
1092 | if (!dev->plat_dev) { | |
1093 | dev_err(&pdev->dev, "No platform data specified\n"); | |
d310f478 | 1094 | return -ENODEV; |
af935746 KD |
1095 | } |
1096 | ||
b27a23be | 1097 | dev->variant = mfc_get_drv_data(pdev); |
8f532a7f | 1098 | |
af935746 KD |
1099 | ret = s5p_mfc_init_pm(dev); |
1100 | if (ret < 0) { | |
1101 | dev_err(&pdev->dev, "failed to get mfc clock source\n"); | |
d310f478 | 1102 | return ret; |
af935746 KD |
1103 | } |
1104 | ||
1105 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
af935746 | 1106 | |
f23999ec TR |
1107 | dev->regs_base = devm_ioremap_resource(&pdev->dev, res); |
1108 | if (IS_ERR(dev->regs_base)) | |
1109 | return PTR_ERR(dev->regs_base); | |
af935746 KD |
1110 | |
1111 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1112 | if (res == NULL) { | |
1113 | dev_err(&pdev->dev, "failed to get irq resource\n"); | |
1114 | ret = -ENOENT; | |
d310f478 | 1115 | goto err_res; |
af935746 KD |
1116 | } |
1117 | dev->irq = res->start; | |
d310f478 | 1118 | ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, |
1957f0d7 | 1119 | 0, pdev->name, dev); |
af935746 KD |
1120 | if (ret) { |
1121 | dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); | |
d310f478 | 1122 | goto err_res; |
af935746 KD |
1123 | } |
1124 | ||
b27a23be | 1125 | if (pdev->dev.of_node) { |
d68b44e0 WY |
1126 | ret = s5p_mfc_alloc_memdevs(dev); |
1127 | if (ret < 0) | |
b27a23be | 1128 | goto err_res; |
b27a23be AK |
1129 | } else { |
1130 | dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, | |
1131 | "s5p-mfc-l", match_child); | |
1132 | if (!dev->mem_dev_l) { | |
1133 | mfc_err("Mem child (L) device get failed\n"); | |
1134 | ret = -ENODEV; | |
1135 | goto err_res; | |
1136 | } | |
1137 | dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, | |
1138 | "s5p-mfc-r", match_child); | |
1139 | if (!dev->mem_dev_r) { | |
1140 | mfc_err("Mem child (R) device get failed\n"); | |
1141 | ret = -ENODEV; | |
1142 | goto err_res; | |
1143 | } | |
af935746 KD |
1144 | } |
1145 | ||
1146 | dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); | |
ef89fff8 | 1147 | if (IS_ERR(dev->alloc_ctx[0])) { |
af935746 | 1148 | ret = PTR_ERR(dev->alloc_ctx[0]); |
d310f478 | 1149 | goto err_res; |
af935746 KD |
1150 | } |
1151 | dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); | |
ef89fff8 | 1152 | if (IS_ERR(dev->alloc_ctx[1])) { |
af935746 KD |
1153 | ret = PTR_ERR(dev->alloc_ctx[1]); |
1154 | goto err_mem_init_ctx_1; | |
1155 | } | |
1156 | ||
1157 | mutex_init(&dev->mfc_mutex); | |
1158 | ||
2e731e44 KD |
1159 | ret = s5p_mfc_alloc_firmware(dev); |
1160 | if (ret) | |
1161 | goto err_alloc_fw; | |
1162 | ||
af935746 KD |
1163 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); |
1164 | if (ret) | |
1165 | goto err_v4l2_dev_reg; | |
1166 | init_waitqueue_head(&dev->queue); | |
1167 | ||
1168 | /* decoder */ | |
1169 | vfd = video_device_alloc(); | |
1170 | if (!vfd) { | |
1171 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1172 | ret = -ENOMEM; | |
1173 | goto err_dec_alloc; | |
1174 | } | |
d0ce898c | 1175 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1176 | vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); |
d0ce898c | 1177 | vfd->release = video_device_release; |
af935746 KD |
1178 | vfd->lock = &dev->mfc_mutex; |
1179 | vfd->v4l2_dev = &dev->v4l2_dev; | |
954f340f | 1180 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1181 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); |
1182 | dev->vfd_dec = vfd; | |
1183 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1184 | if (ret) { | |
1185 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1186 | video_device_release(vfd); | |
1187 | goto err_dec_reg; | |
1188 | } | |
1189 | v4l2_info(&dev->v4l2_dev, | |
1190 | "decoder registered as /dev/video%d\n", vfd->num); | |
1191 | video_set_drvdata(vfd, dev); | |
1192 | ||
1193 | /* encoder */ | |
1194 | vfd = video_device_alloc(); | |
1195 | if (!vfd) { | |
1196 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1197 | ret = -ENOMEM; | |
1198 | goto err_enc_alloc; | |
1199 | } | |
d0ce898c | 1200 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1201 | vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); |
d0ce898c | 1202 | vfd->release = video_device_release; |
af935746 KD |
1203 | vfd->lock = &dev->mfc_mutex; |
1204 | vfd->v4l2_dev = &dev->v4l2_dev; | |
cdcf45e7 | 1205 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1206 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); |
1207 | dev->vfd_enc = vfd; | |
1208 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1209 | if (ret) { | |
1210 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1211 | video_device_release(vfd); | |
1212 | goto err_enc_reg; | |
1213 | } | |
1214 | v4l2_info(&dev->v4l2_dev, | |
1215 | "encoder registered as /dev/video%d\n", vfd->num); | |
1216 | video_set_drvdata(vfd, dev); | |
1217 | platform_set_drvdata(pdev, dev); | |
1218 | ||
1219 | dev->hw_lock = 0; | |
1220 | dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); | |
1221 | INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); | |
1222 | atomic_set(&dev->watchdog_cnt, 0); | |
1223 | init_timer(&dev->watchdog_timer); | |
1224 | dev->watchdog_timer.data = (unsigned long)dev; | |
1225 | dev->watchdog_timer.function = s5p_mfc_watchdog; | |
1226 | ||
43a1ea1f AK |
1227 | /* Initialize HW ops and commands based on MFC version */ |
1228 | s5p_mfc_init_hw_ops(dev); | |
1229 | s5p_mfc_init_hw_cmds(dev); | |
6a9c6f68 | 1230 | s5p_mfc_init_regs(dev); |
43a1ea1f | 1231 | |
af935746 KD |
1232 | pr_debug("%s--\n", __func__); |
1233 | return 0; | |
1234 | ||
1235 | /* Deinit MFC if probe had failed */ | |
1236 | err_enc_reg: | |
1237 | video_device_release(dev->vfd_enc); | |
1238 | err_enc_alloc: | |
1239 | video_unregister_device(dev->vfd_dec); | |
1240 | err_dec_reg: | |
1241 | video_device_release(dev->vfd_dec); | |
1242 | err_dec_alloc: | |
1243 | v4l2_device_unregister(&dev->v4l2_dev); | |
1244 | err_v4l2_dev_reg: | |
2e731e44 KD |
1245 | s5p_mfc_release_firmware(dev); |
1246 | err_alloc_fw: | |
af935746 KD |
1247 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); |
1248 | err_mem_init_ctx_1: | |
1249 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); | |
af935746 KD |
1250 | err_res: |
1251 | s5p_mfc_final_pm(dev); | |
d310f478 | 1252 | |
af935746 KD |
1253 | pr_debug("%s-- with error\n", __func__); |
1254 | return ret; | |
1255 | ||
1256 | } | |
1257 | ||
1258 | /* Remove the driver */ | |
4c62e976 | 1259 | static int s5p_mfc_remove(struct platform_device *pdev) |
af935746 KD |
1260 | { |
1261 | struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); | |
1262 | ||
1263 | v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); | |
1264 | ||
1265 | del_timer_sync(&dev->watchdog_timer); | |
1266 | flush_workqueue(dev->watchdog_workqueue); | |
1267 | destroy_workqueue(dev->watchdog_workqueue); | |
1268 | ||
1269 | video_unregister_device(dev->vfd_enc); | |
1270 | video_unregister_device(dev->vfd_dec); | |
1271 | v4l2_device_unregister(&dev->v4l2_dev); | |
2e731e44 | 1272 | s5p_mfc_release_firmware(dev); |
af935746 KD |
1273 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); |
1274 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); | |
6e83e6e2 AK |
1275 | if (pdev->dev.of_node) { |
1276 | put_device(dev->mem_dev_l); | |
1277 | put_device(dev->mem_dev_r); | |
1278 | } | |
af935746 | 1279 | |
af935746 | 1280 | s5p_mfc_final_pm(dev); |
af935746 KD |
1281 | return 0; |
1282 | } | |
1283 | ||
1284 | #ifdef CONFIG_PM_SLEEP | |
1285 | ||
1286 | static int s5p_mfc_suspend(struct device *dev) | |
1287 | { | |
1288 | struct platform_device *pdev = to_platform_device(dev); | |
1289 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1290 | int ret; | |
1291 | ||
1292 | if (m_dev->num_inst == 0) | |
1293 | return 0; | |
81c9bcfb | 1294 | |
af935746 KD |
1295 | if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { |
1296 | mfc_err("Error: going to suspend for a second time\n"); | |
1297 | return -EIO; | |
1298 | } | |
1299 | ||
1300 | /* Check if we're processing then wait if it necessary. */ | |
1301 | while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { | |
1302 | /* Try and lock the HW */ | |
1303 | /* Wait on the interrupt waitqueue */ | |
1304 | ret = wait_event_interruptible_timeout(m_dev->queue, | |
76a4ddbd | 1305 | m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); |
af935746 KD |
1306 | if (ret == 0) { |
1307 | mfc_err("Waiting for hardware to finish timed out\n"); | |
64370994 | 1308 | clear_bit(0, &m_dev->enter_suspend); |
af935746 KD |
1309 | return -EIO; |
1310 | } | |
1311 | } | |
81c9bcfb | 1312 | |
64370994 P |
1313 | ret = s5p_mfc_sleep(m_dev); |
1314 | if (ret) { | |
1315 | clear_bit(0, &m_dev->enter_suspend); | |
1316 | clear_bit(0, &m_dev->hw_lock); | |
1317 | } | |
1318 | return ret; | |
af935746 KD |
1319 | } |
1320 | ||
1321 | static int s5p_mfc_resume(struct device *dev) | |
1322 | { | |
1323 | struct platform_device *pdev = to_platform_device(dev); | |
1324 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1325 | ||
1326 | if (m_dev->num_inst == 0) | |
1327 | return 0; | |
1328 | return s5p_mfc_wakeup(m_dev); | |
1329 | } | |
1330 | #endif | |
1331 | ||
e243c7c1 | 1332 | #ifdef CONFIG_PM |
af935746 KD |
1333 | static int s5p_mfc_runtime_suspend(struct device *dev) |
1334 | { | |
1335 | struct platform_device *pdev = to_platform_device(dev); | |
1336 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1337 | ||
1338 | atomic_set(&m_dev->pm.power, 0); | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int s5p_mfc_runtime_resume(struct device *dev) | |
1343 | { | |
1344 | struct platform_device *pdev = to_platform_device(dev); | |
1345 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
af935746 | 1346 | |
af935746 KD |
1347 | atomic_set(&m_dev->pm.power, 1); |
1348 | return 0; | |
1349 | } | |
1350 | #endif | |
1351 | ||
1352 | /* Power management */ | |
1353 | static const struct dev_pm_ops s5p_mfc_pm_ops = { | |
1354 | SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) | |
1355 | SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, | |
1356 | NULL) | |
1357 | }; | |
1358 | ||
ca5ea0c5 | 1359 | static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { |
8f532a7f AK |
1360 | .h264_ctx = MFC_H264_CTX_BUF_SIZE, |
1361 | .non_h264_ctx = MFC_CTX_BUF_SIZE, | |
1362 | .dsc = DESC_BUF_SIZE, | |
1363 | .shm = SHARED_BUF_SIZE, | |
1364 | }; | |
1365 | ||
ca5ea0c5 | 1366 | static struct s5p_mfc_buf_size buf_size_v5 = { |
8f532a7f AK |
1367 | .fw = MAX_FW_SIZE, |
1368 | .cpb = MAX_CPB_SIZE, | |
1369 | .priv = &mfc_buf_size_v5, | |
1370 | }; | |
1371 | ||
ca5ea0c5 | 1372 | static struct s5p_mfc_buf_align mfc_buf_align_v5 = { |
8f532a7f AK |
1373 | .base = MFC_BASE_ALIGN_ORDER, |
1374 | }; | |
1375 | ||
1376 | static struct s5p_mfc_variant mfc_drvdata_v5 = { | |
1377 | .version = MFC_VERSION, | |
9aa5f008 | 1378 | .version_bit = MFC_V5_BIT, |
8f532a7f AK |
1379 | .port_num = MFC_NUM_PORTS, |
1380 | .buf_size = &buf_size_v5, | |
1381 | .buf_align = &mfc_buf_align_v5, | |
77ba6b73 | 1382 | .fw_name[0] = "s5p-mfc.fw", |
f96f3cfa JP |
1383 | }; |
1384 | ||
ca5ea0c5 | 1385 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { |
f96f3cfa JP |
1386 | .dev_ctx = MFC_CTX_BUF_SIZE_V6, |
1387 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, | |
1388 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, | |
1389 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, | |
1390 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, | |
1391 | }; | |
1392 | ||
ca5ea0c5 | 1393 | static struct s5p_mfc_buf_size buf_size_v6 = { |
f96f3cfa JP |
1394 | .fw = MAX_FW_SIZE_V6, |
1395 | .cpb = MAX_CPB_SIZE_V6, | |
1396 | .priv = &mfc_buf_size_v6, | |
1397 | }; | |
1398 | ||
ca5ea0c5 | 1399 | static struct s5p_mfc_buf_align mfc_buf_align_v6 = { |
f96f3cfa JP |
1400 | .base = 0, |
1401 | }; | |
1402 | ||
1403 | static struct s5p_mfc_variant mfc_drvdata_v6 = { | |
1404 | .version = MFC_VERSION_V6, | |
9aa5f008 | 1405 | .version_bit = MFC_V6_BIT, |
f96f3cfa JP |
1406 | .port_num = MFC_NUM_PORTS_V6, |
1407 | .buf_size = &buf_size_v6, | |
1408 | .buf_align = &mfc_buf_align_v6, | |
77ba6b73 AK |
1409 | .fw_name[0] = "s5p-mfc-v6.fw", |
1410 | /* | |
1411 | * v6-v2 firmware contains bug fixes and interface change | |
1412 | * for init buffer command | |
1413 | */ | |
1414 | .fw_name[1] = "s5p-mfc-v6-v2.fw", | |
8f532a7f AK |
1415 | }; |
1416 | ||
ca5ea0c5 | 1417 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { |
5441e9da AK |
1418 | .dev_ctx = MFC_CTX_BUF_SIZE_V7, |
1419 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, | |
1420 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, | |
1421 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, | |
1422 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, | |
1423 | }; | |
1424 | ||
ca5ea0c5 | 1425 | static struct s5p_mfc_buf_size buf_size_v7 = { |
5441e9da AK |
1426 | .fw = MAX_FW_SIZE_V7, |
1427 | .cpb = MAX_CPB_SIZE_V7, | |
1428 | .priv = &mfc_buf_size_v7, | |
1429 | }; | |
1430 | ||
ca5ea0c5 | 1431 | static struct s5p_mfc_buf_align mfc_buf_align_v7 = { |
5441e9da AK |
1432 | .base = 0, |
1433 | }; | |
1434 | ||
1435 | static struct s5p_mfc_variant mfc_drvdata_v7 = { | |
1436 | .version = MFC_VERSION_V7, | |
9aa5f008 | 1437 | .version_bit = MFC_V7_BIT, |
5441e9da AK |
1438 | .port_num = MFC_NUM_PORTS_V7, |
1439 | .buf_size = &buf_size_v7, | |
1440 | .buf_align = &mfc_buf_align_v7, | |
77ba6b73 | 1441 | .fw_name[0] = "s5p-mfc-v7.fw", |
5441e9da AK |
1442 | }; |
1443 | ||
ca5ea0c5 | 1444 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { |
e2b9deb2 KA |
1445 | .dev_ctx = MFC_CTX_BUF_SIZE_V8, |
1446 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8, | |
1447 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8, | |
3e594ce7 KA |
1448 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8, |
1449 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8, | |
e2b9deb2 KA |
1450 | }; |
1451 | ||
ca5ea0c5 | 1452 | static struct s5p_mfc_buf_size buf_size_v8 = { |
e2b9deb2 KA |
1453 | .fw = MAX_FW_SIZE_V8, |
1454 | .cpb = MAX_CPB_SIZE_V8, | |
1455 | .priv = &mfc_buf_size_v8, | |
1456 | }; | |
1457 | ||
ca5ea0c5 | 1458 | static struct s5p_mfc_buf_align mfc_buf_align_v8 = { |
e2b9deb2 KA |
1459 | .base = 0, |
1460 | }; | |
1461 | ||
1462 | static struct s5p_mfc_variant mfc_drvdata_v8 = { | |
1463 | .version = MFC_VERSION_V8, | |
1464 | .version_bit = MFC_V8_BIT, | |
1465 | .port_num = MFC_NUM_PORTS_V8, | |
1466 | .buf_size = &buf_size_v8, | |
1467 | .buf_align = &mfc_buf_align_v8, | |
77ba6b73 | 1468 | .fw_name[0] = "s5p-mfc-v8.fw", |
e2b9deb2 KA |
1469 | }; |
1470 | ||
6425f646 | 1471 | static const struct platform_device_id mfc_driver_ids[] = { |
8f532a7f AK |
1472 | { |
1473 | .name = "s5p-mfc", | |
1474 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
f96f3cfa JP |
1475 | }, { |
1476 | .name = "s5p-mfc-v5", | |
1477 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
1478 | }, { | |
1479 | .name = "s5p-mfc-v6", | |
1480 | .driver_data = (unsigned long)&mfc_drvdata_v6, | |
5441e9da AK |
1481 | }, { |
1482 | .name = "s5p-mfc-v7", | |
1483 | .driver_data = (unsigned long)&mfc_drvdata_v7, | |
e2b9deb2 KA |
1484 | }, { |
1485 | .name = "s5p-mfc-v8", | |
1486 | .driver_data = (unsigned long)&mfc_drvdata_v8, | |
8f532a7f AK |
1487 | }, |
1488 | {}, | |
1489 | }; | |
1490 | MODULE_DEVICE_TABLE(platform, mfc_driver_ids); | |
1491 | ||
b27a23be AK |
1492 | static const struct of_device_id exynos_mfc_match[] = { |
1493 | { | |
1494 | .compatible = "samsung,mfc-v5", | |
1495 | .data = &mfc_drvdata_v5, | |
1496 | }, { | |
1497 | .compatible = "samsung,mfc-v6", | |
1498 | .data = &mfc_drvdata_v6, | |
5441e9da AK |
1499 | }, { |
1500 | .compatible = "samsung,mfc-v7", | |
1501 | .data = &mfc_drvdata_v7, | |
e2b9deb2 KA |
1502 | }, { |
1503 | .compatible = "samsung,mfc-v8", | |
1504 | .data = &mfc_drvdata_v8, | |
b27a23be AK |
1505 | }, |
1506 | {}, | |
1507 | }; | |
1508 | MODULE_DEVICE_TABLE(of, exynos_mfc_match); | |
1509 | ||
1510 | static void *mfc_get_drv_data(struct platform_device *pdev) | |
1511 | { | |
1512 | struct s5p_mfc_variant *driver_data = NULL; | |
1513 | ||
1514 | if (pdev->dev.of_node) { | |
1515 | const struct of_device_id *match; | |
a40a1382 | 1516 | match = of_match_node(exynos_mfc_match, |
b27a23be AK |
1517 | pdev->dev.of_node); |
1518 | if (match) | |
1519 | driver_data = (struct s5p_mfc_variant *)match->data; | |
1520 | } else { | |
1521 | driver_data = (struct s5p_mfc_variant *) | |
1522 | platform_get_device_id(pdev)->driver_data; | |
1523 | } | |
1524 | return driver_data; | |
1525 | } | |
1526 | ||
1e393e90 | 1527 | static struct platform_driver s5p_mfc_driver = { |
8f532a7f | 1528 | .probe = s5p_mfc_probe, |
4c62e976 | 1529 | .remove = s5p_mfc_remove, |
8f532a7f | 1530 | .id_table = mfc_driver_ids, |
af935746 KD |
1531 | .driver = { |
1532 | .name = S5P_MFC_NAME, | |
b27a23be AK |
1533 | .pm = &s5p_mfc_pm_ops, |
1534 | .of_match_table = exynos_mfc_match, | |
af935746 KD |
1535 | }, |
1536 | }; | |
1537 | ||
1d6629b1 | 1538 | module_platform_driver(s5p_mfc_driver); |
af935746 KD |
1539 | |
1540 | MODULE_LICENSE("GPL"); | |
1541 | MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); | |
1542 | MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); | |
1543 |