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[media] s5p-mfc: Move firmware allocation point to avoid allocation problems
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
af935746 21#include <linux/videodev2.h>
f9f715a9 22#include <media/v4l2-event.h>
af935746 23#include <linux/workqueue.h>
b27a23be 24#include <linux/of.h>
af935746 25#include <media/videobuf2-core.h>
43a1ea1f 26#include "s5p_mfc_common.h"
af935746
KD		 27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
af935746 34#include "s5p_mfc_pm.h"
af935746
KD		 35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40int debug;
41module_param(debug, int, S_IRUGO | S_IWUSR);
42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44/* Helper functions for interrupt processing */
7fb89eca 45
af935746 46/* Remove from hw execution round robin */
7fb89eca 47void clear_work_bit(struct s5p_mfc_ctx *ctx)
af935746
KD		 48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
7fb89eca 52 __clear_bit(ctx->num, &dev->ctx_work_bits);
af935746
KD		 53 spin_unlock(&dev->condlock);
54}
55
7fb89eca
AH		 56/* Add to hw execution round robin */
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66/* Remove from hw execution round robin */
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77/* Add to hw execution round robin */
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
af935746
KD		 88/* Wake up context wait_queue */
89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91{
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96}
97
98/* Wake up device wait_queue */
99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101{
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106}
107
a13bba4f 108static void s5p_mfc_watchdog(unsigned long arg)
af935746
KD		 109{
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126}
127
128static void s5p_mfc_watchdog_worker(struct work_struct *work)
129{
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
43a1ea1f
AK		 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
154 &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
156 &ctx->vq_src);
af935746 157 clear_work_bit(ctx);
43a1ea1f 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
af935746
KD		 159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_reload_firmware(dev);
166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 if (ret)
173 mfc_err("Failed to reinit FW\n");
174 }
175unlock:
176 if (mutex_locked)
177 mutex_unlock(&dev->mfc_mutex);
178}
179
180static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
181{
182 struct video_device *vdev = video_devdata(file);
183
184 if (!vdev) {
185 mfc_err("failed to get video_device");
186 return MFCNODE_INVALID;
187 }
188 if (vdev->index == 0)
189 return MFCNODE_DECODER;
190 else if (vdev->index == 1)
191 return MFCNODE_ENCODER;
192 return MFCNODE_INVALID;
193}
194
195static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
196{
197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
200}
201
202static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
203{
204 struct s5p_mfc_buf *dst_buf;
43a1ea1f 205 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 206
207 ctx->state = MFCINST_FINISHED;
208 ctx->sequence++;
209 while (!list_empty(&ctx->dst_queue)) {
210 dst_buf = list_entry(ctx->dst_queue.next,
211 struct s5p_mfc_buf, list);
212 mfc_debug(2, "Cleaning up buffer: %d\n",
213 dst_buf->b->v4l2_buf.index);
214 vb2_set_plane_payload(dst_buf->b, 0, 0);
215 vb2_set_plane_payload(dst_buf->b, 1, 0);
216 list_del(&dst_buf->list);
217 ctx->dst_queue_cnt--;
218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
219
43a1ea1f
AK		 220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
af935746
KD		 222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
223 else
224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
225
226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
228 }
229}
230
231static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
232{
233 struct s5p_mfc_dev *dev = ctx->dev;
234 struct s5p_mfc_buf *dst_buf, *src_buf;
43a1ea1f
AK		 235 size_t dec_y_addr;
236 unsigned int frame_type;
237
238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
af935746
KD		 240
241 /* Copy timestamp / timecode from decoded src to dst and set
242 appropraite flags */
243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
ba7fcb0c 245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
af935746
KD		 246 memcpy(&dst_buf->b->v4l2_buf.timecode,
247 &src_buf->b->v4l2_buf.timecode,
248 sizeof(struct v4l2_timecode));
249 memcpy(&dst_buf->b->v4l2_buf.timestamp,
250 &src_buf->b->v4l2_buf.timestamp,
251 sizeof(struct timeval));
252 switch (frame_type) {
253 case S5P_FIMV_DECODE_FRAME_I_FRAME:
254 dst_buf->b->v4l2_buf.flags |=
255 V4L2_BUF_FLAG_KEYFRAME;
256 break;
257 case S5P_FIMV_DECODE_FRAME_P_FRAME:
258 dst_buf->b->v4l2_buf.flags |=
259 V4L2_BUF_FLAG_PFRAME;
260 break;
261 case S5P_FIMV_DECODE_FRAME_B_FRAME:
262 dst_buf->b->v4l2_buf.flags |=
263 V4L2_BUF_FLAG_BFRAME;
264 break;
265 }
266 break;
267 }
268 }
269}
270
271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
272{
273 struct s5p_mfc_dev *dev = ctx->dev;
274 struct s5p_mfc_buf *dst_buf;
43a1ea1f
AK		 275 size_t dspl_y_addr;
276 unsigned int frame_type;
af935746 277
43a1ea1f
AK		 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
280
af935746
KD		 281 /* If frame is same as previous then skip and do not dequeue */
282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
283 if (!ctx->after_packed_pb)
284 ctx->sequence++;
285 ctx->after_packed_pb = 0;
286 return;
287 }
288 ctx->sequence++;
289 /* The MFC returns address of the buffer, now we have to
290 * check which videobuf does it correspond to */
291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
292 /* Check if this is the buffer we're looking for */
ba7fcb0c 293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
af935746
KD		 294 list_del(&dst_buf->list);
295 ctx->dst_queue_cnt--;
296 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
43a1ea1f
AK		 297 if (s5p_mfc_hw_call(dev->mfc_ops,
298 get_pic_type_top, ctx) ==
299 s5p_mfc_hw_call(dev->mfc_ops,
300 get_pic_type_bot, ctx))
af935746
KD		 301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
302 else
303 dst_buf->b->v4l2_buf.field =
304 V4L2_FIELD_INTERLACED;
305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
307 clear_bit(dst_buf->b->v4l2_buf.index,
308 &ctx->dec_dst_flag);
309
310 vb2_buffer_done(dst_buf->b,
311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
312
af935746
KD		 313 break;
314 }
315 }
316}
317
318/* Handle frame decoding interrupt */
319static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
320 unsigned int reason, unsigned int err)
321{
322 struct s5p_mfc_dev *dev = ctx->dev;
323 unsigned int dst_frame_status;
324 struct s5p_mfc_buf *src_buf;
325 unsigned long flags;
326 unsigned int res_change;
327
43a1ea1f 328 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
af935746 329 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
f96f3cfa
JP		 330 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
331 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
332 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
af935746
KD		 333 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
334 if (ctx->state == MFCINST_RES_CHANGE_INIT)
335 ctx->state = MFCINST_RES_CHANGE_FLUSH;
f96f3cfa
JP		 336 if (res_change == S5P_FIMV_RES_INCREASE ||
337 res_change == S5P_FIMV_RES_DECREASE) {
af935746 338 ctx->state = MFCINST_RES_CHANGE_INIT;
43a1ea1f 339 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 340 wake_up_ctx(ctx, reason, err);
341 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
342 BUG();
343 s5p_mfc_clock_off();
43a1ea1f 344 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 345 return;
346 }
347 if (ctx->dpb_flush_flag)
348 ctx->dpb_flush_flag = 0;
349
350 spin_lock_irqsave(&dev->irqlock, flags);
351 /* All frames remaining in the buffer have been extracted */
352 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
353 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
354 s5p_mfc_handle_frame_all_extracted(ctx);
355 ctx->state = MFCINST_RES_CHANGE_END;
356 goto leave_handle_frame;
357 } else {
358 s5p_mfc_handle_frame_all_extracted(ctx);
359 }
360 }
361
362 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
363 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
364 s5p_mfc_handle_frame_copy_time(ctx);
365
366 /* A frame has been decoded and is in the buffer */
367 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
368 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
369 s5p_mfc_handle_frame_new(ctx, err);
370 } else {
371 mfc_debug(2, "No frame decode\n");
372 }
373 /* Mark source buffer as complete */
374 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
375 && !list_empty(&ctx->src_queue)) {
376 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
377 list);
43a1ea1f
AK		 378 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
379 get_consumed_stream, dev);
380 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
d2a0db1e
AK		 381 ctx->consumed_stream + STUFF_BYTE <
382 src_buf->b->v4l2_planes[0].bytesused) {
af935746
KD		 383 /* Run MFC again on the same buffer */
384 mfc_debug(2, "Running again the same buffer\n");
385 ctx->after_packed_pb = 1;
386 } else {
af935746
KD		 387 mfc_debug(2, "MFC needs next buffer\n");
388 ctx->consumed_stream = 0;
389 list_del(&src_buf->list);
390 ctx->src_queue_cnt--;
43a1ea1f 391 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
af935746
KD		 392 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
393 else
394 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
395 }
396 }
397leave_handle_frame:
398 spin_unlock_irqrestore(&dev->irqlock, flags);
399 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
400 || ctx->dst_queue_cnt < ctx->dpb_count)
401 clear_work_bit(ctx);
43a1ea1f 402 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 403 wake_up_ctx(ctx, reason, err);
404 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
405 BUG();
406 s5p_mfc_clock_off();
43a1ea1f 407 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 408}
409
410/* Error handling for interrupt */
411static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
412 unsigned int reason, unsigned int err)
413{
414 struct s5p_mfc_dev *dev;
415 unsigned long flags;
416
417 /* If no context is available then all necessary
418 * processing has been done. */
1259762f 419 if (ctx == NULL)
af935746
KD		 420 return;
421
422 dev = ctx->dev;
423 mfc_err("Interrupt Error: %08x\n", err);
43a1ea1f 424 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 425 wake_up_dev(dev, reason, err);
426
427 /* Error recovery is dependent on the state of context */
428 switch (ctx->state) {
429 case MFCINST_INIT:
430 /* This error had to happen while acquireing instance */
431 case MFCINST_GOT_INST:
432 /* This error had to happen while parsing the header */
433 case MFCINST_HEAD_PARSED:
434 /* This error had to happen while setting dst buffers */
435 case MFCINST_RETURN_INST:
436 /* This error had to happen while releasing instance */
437 clear_work_bit(ctx);
438 wake_up_ctx(ctx, reason, err);
439 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
440 BUG();
441 s5p_mfc_clock_off();
442 ctx->state = MFCINST_ERROR;
443 break;
444 case MFCINST_FINISHING:
445 case MFCINST_FINISHED:
446 case MFCINST_RUNNING:
447 /* It is higly probable that an error occured
448 * while decoding a frame */
449 clear_work_bit(ctx);
450 ctx->state = MFCINST_ERROR;
451 /* Mark all dst buffers as having an error */
452 spin_lock_irqsave(&dev->irqlock, flags);
43a1ea1f
AK		 453 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
454 &ctx->vq_dst);
af935746 455 /* Mark all src buffers as having an error */
43a1ea1f
AK		 456 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
457 &ctx->vq_src);
af935746
KD		 458 spin_unlock_irqrestore(&dev->irqlock, flags);
459 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
460 BUG();
461 s5p_mfc_clock_off();
462 break;
463 default:
464 mfc_err("Encountered an error interrupt which had not been handled\n");
465 break;
466 }
467 return;
468}
469
470/* Header parsing interrupt handling */
471static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
472 unsigned int reason, unsigned int err)
473{
474 struct s5p_mfc_dev *dev;
af935746 475
1259762f 476 if (ctx == NULL)
af935746
KD		 477 return;
478 dev = ctx->dev;
479 if (ctx->c_ops->post_seq_start) {
480 if (ctx->c_ops->post_seq_start(ctx))
481 mfc_err("post_seq_start() failed\n");
482 } else {
43a1ea1f
AK		 483 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
484 dev);
485 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
486 dev);
af935746 487
8f532a7f
AK		 488 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
489
43a1ea1f
AK		 490 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
491 dev);
f96f3cfa
JP		 492 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
493 dev);
bb869368 494 if (ctx->img_width == 0 || ctx->img_height == 0)
af935746
KD		 495 ctx->state = MFCINST_ERROR;
496 else
497 ctx->state = MFCINST_HEAD_PARSED;
f96f3cfa
JP		 498
499 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
500 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
501 !list_empty(&ctx->src_queue)) {
502 struct s5p_mfc_buf *src_buf;
503 src_buf = list_entry(ctx->src_queue.next,
504 struct s5p_mfc_buf, list);
505 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
506 dev) <
507 src_buf->b->v4l2_planes[0].bytesused)
508 ctx->head_processed = 0;
509 else
510 ctx->head_processed = 1;
511 } else {
512 ctx->head_processed = 1;
513 }
af935746 514 }
43a1ea1f 515 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 516 clear_work_bit(ctx);
517 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
518 BUG();
519 s5p_mfc_clock_off();
43a1ea1f 520 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 521 wake_up_ctx(ctx, reason, err);
522}
523
524/* Header parsing interrupt handling */
525static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
526 unsigned int reason, unsigned int err)
527{
528 struct s5p_mfc_buf *src_buf;
529 struct s5p_mfc_dev *dev;
530 unsigned long flags;
531
1259762f 532 if (ctx == NULL)
af935746
KD		 533 return;
534 dev = ctx->dev;
43a1ea1f 535 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 536 ctx->int_type = reason;
537 ctx->int_err = err;
538 ctx->int_cond = 1;
7fb89eca 539 clear_work_bit(ctx);
af935746
KD		 540 if (err == 0) {
541 ctx->state = MFCINST_RUNNING;
f96f3cfa 542 if (!ctx->dpb_flush_flag && ctx->head_processed) {
af935746
KD		 543 spin_lock_irqsave(&dev->irqlock, flags);
544 if (!list_empty(&ctx->src_queue)) {
545 src_buf = list_entry(ctx->src_queue.next,
546 struct s5p_mfc_buf, list);
547 list_del(&src_buf->list);
548 ctx->src_queue_cnt--;
549 vb2_buffer_done(src_buf->b,
550 VB2_BUF_STATE_DONE);
551 }
552 spin_unlock_irqrestore(&dev->irqlock, flags);
553 } else {
554 ctx->dpb_flush_flag = 0;
555 }
556 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
557 BUG();
558
559 s5p_mfc_clock_off();
560
561 wake_up(&ctx->queue);
43a1ea1f 562 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 563 } else {
564 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
565 BUG();
566
567 s5p_mfc_clock_off();
568
569 wake_up(&ctx->queue);
570 }
571}
572
f9f715a9
AH		 573static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
574 unsigned int reason, unsigned int err)
575{
576 struct s5p_mfc_dev *dev = ctx->dev;
577 struct s5p_mfc_buf *mb_entry;
578
579 mfc_debug(2, "Stream completed");
580
581 s5p_mfc_clear_int_flags(dev);
582 ctx->int_type = reason;
583 ctx->int_err = err;
584 ctx->state = MFCINST_FINISHED;
585
586 spin_lock(&dev->irqlock);
587 if (!list_empty(&ctx->dst_queue)) {
588 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
589 list);
590 list_del(&mb_entry->list);
591 ctx->dst_queue_cnt--;
592 vb2_set_plane_payload(mb_entry->b, 0, 0);
593 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
594 }
595 spin_unlock(&dev->irqlock);
596
597 clear_work_bit(ctx);
598
599 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
600 WARN_ON(1);
601
602 s5p_mfc_clock_off();
603 wake_up(&ctx->queue);
43a1ea1f 604 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
f9f715a9
AH		 605}
606
af935746
KD		 607/* Interrupt processing */
608static irqreturn_t s5p_mfc_irq(int irq, void *priv)
609{
610 struct s5p_mfc_dev *dev = priv;
611 struct s5p_mfc_ctx *ctx;
612 unsigned int reason;
613 unsigned int err;
614
615 mfc_debug_enter();
616 /* Reset the timeout watchdog */
617 atomic_set(&dev->watchdog_cnt, 0);
618 ctx = dev->ctx[dev->curr_ctx];
619 /* Get the reason of interrupt and the error code */
43a1ea1f
AK		 620 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
621 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
af935746
KD		 622 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
623 switch (reason) {
43a1ea1f 624 case S5P_MFC_R2H_CMD_ERR_RET:
af935746
KD		 625 /* An error has occured */
626 if (ctx->state == MFCINST_RUNNING &&
43a1ea1f
AK		 627 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
628 dev->warn_start)
af935746
KD		 629 s5p_mfc_handle_frame(ctx, reason, err);
630 else
631 s5p_mfc_handle_error(ctx, reason, err);
632 clear_bit(0, &dev->enter_suspend);
633 break;
634
43a1ea1f
AK		 635 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
636 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
637 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
af935746
KD		 638 if (ctx->c_ops->post_frame_start) {
639 if (ctx->c_ops->post_frame_start(ctx))
640 mfc_err("post_frame_start() failed\n");
43a1ea1f 641 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 642 wake_up_ctx(ctx, reason, err);
643 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
644 BUG();
645 s5p_mfc_clock_off();
43a1ea1f 646 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 647 } else {
648 s5p_mfc_handle_frame(ctx, reason, err);
649 }
650 break;
651
43a1ea1f 652 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
af935746
KD		 653 s5p_mfc_handle_seq_done(ctx, reason, err);
654 break;
655
43a1ea1f
AK		 656 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
657 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
af935746
KD		 658 ctx->state = MFCINST_GOT_INST;
659 clear_work_bit(ctx);
660 wake_up(&ctx->queue);
661 goto irq_cleanup_hw;
662
43a1ea1f 663 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
af935746
KD		 664 clear_work_bit(ctx);
665 ctx->state = MFCINST_FREE;
666 wake_up(&ctx->queue);
667 goto irq_cleanup_hw;
668
43a1ea1f
AK		 669 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
670 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
671 case S5P_MFC_R2H_CMD_SLEEP_RET:
672 case S5P_MFC_R2H_CMD_WAKEUP_RET:
af935746
KD		 673 if (ctx)
674 clear_work_bit(ctx);
43a1ea1f 675 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 676 wake_up_dev(dev, reason, err);
677 clear_bit(0, &dev->hw_lock);
678 clear_bit(0, &dev->enter_suspend);
679 break;
680
43a1ea1f 681 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
af935746
KD		 682 s5p_mfc_handle_init_buffers(ctx, reason, err);
683 break;
f9f715a9 684
43a1ea1f 685 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
f9f715a9
AH		 686 s5p_mfc_handle_stream_complete(ctx, reason, err);
687 break;
688
8f23cc02
AK		 689 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
690 clear_work_bit(ctx);
691 ctx->state = MFCINST_RUNNING;
692 wake_up(&ctx->queue);
693 goto irq_cleanup_hw;
694
af935746
KD		 695 default:
696 mfc_debug(2, "Unknown int reason\n");
43a1ea1f 697 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 698 }
699 mfc_debug_leave();
700 return IRQ_HANDLED;
701irq_cleanup_hw:
43a1ea1f 702 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 703 ctx->int_type = reason;
704 ctx->int_err = err;
705 ctx->int_cond = 1;
706 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
707 mfc_err("Failed to unlock hw\n");
708
709 s5p_mfc_clock_off();
710
43a1ea1f 711 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 712 mfc_debug(2, "Exit via irq_cleanup_hw\n");
713 return IRQ_HANDLED;
714}
715
716/* Open an MFC node */
717static int s5p_mfc_open(struct file *file)
718{
719 struct s5p_mfc_dev *dev = video_drvdata(file);
720 struct s5p_mfc_ctx *ctx = NULL;
721 struct vb2_queue *q;
af935746
KD		 722 int ret = 0;
723
724 mfc_debug_enter();
bc738301
HV		 725 if (mutex_lock_interruptible(&dev->mfc_mutex))
726 return -ERESTARTSYS;
af935746
KD		 727 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
728 /* Allocate memory for context */
bae061b4 729 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
af935746
KD		 730 if (!ctx) {
731 mfc_err("Not enough memory\n");
732 ret = -ENOMEM;
733 goto err_alloc;
734 }
735 v4l2_fh_init(&ctx->fh, video_devdata(file));
736 file->private_data = &ctx->fh;
737 v4l2_fh_add(&ctx->fh);
738 ctx->dev = dev;
739 INIT_LIST_HEAD(&ctx->src_queue);
740 INIT_LIST_HEAD(&ctx->dst_queue);
741 ctx->src_queue_cnt = 0;
742 ctx->dst_queue_cnt = 0;
743 /* Get context number */
744 ctx->num = 0;
745 while (dev->ctx[ctx->num]) {
746 ctx->num++;
747 if (ctx->num >= MFC_NUM_CONTEXTS) {
748 mfc_err("Too many open contexts\n");
749 ret = -EBUSY;
750 goto err_no_ctx;
751 }
752 }
753 /* Mark context as idle */
7fb89eca 754 clear_work_bit_irqsave(ctx);
af935746
KD		 755 dev->ctx[ctx->num] = ctx;
756 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
757 ctx->type = MFCINST_DECODER;
758 ctx->c_ops = get_dec_codec_ops();
43a1ea1f 759 s5p_mfc_dec_init(ctx);
af935746
KD		 760 /* Setup ctrl handler */
761 ret = s5p_mfc_dec_ctrls_setup(ctx);
762 if (ret) {
763 mfc_err("Failed to setup mfc controls\n");
764 goto err_ctrls_setup;
765 }
766 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
767 ctx->type = MFCINST_ENCODER;
768 ctx->c_ops = get_enc_codec_ops();
769 /* only for encoder */
770 INIT_LIST_HEAD(&ctx->ref_queue);
771 ctx->ref_queue_cnt = 0;
43a1ea1f 772 s5p_mfc_enc_init(ctx);
af935746
KD		 773 /* Setup ctrl handler */
774 ret = s5p_mfc_enc_ctrls_setup(ctx);
775 if (ret) {
776 mfc_err("Failed to setup mfc controls\n");
777 goto err_ctrls_setup;
778 }
779 } else {
780 ret = -ENOENT;
781 goto err_bad_node;
782 }
783 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
784 ctx->inst_no = -1;
785 /* Load firmware if this is the first instance */
786 if (dev->num_inst == 1) {
787 dev->watchdog_timer.expires = jiffies +
788 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
789 add_timer(&dev->watchdog_timer);
790 ret = s5p_mfc_power_on();
791 if (ret < 0) {
792 mfc_err("power on failed\n");
793 goto err_pwr_enable;
794 }
795 s5p_mfc_clock_on();
2e731e44
KD		 796 ret = s5p_mfc_load_firmware(dev);
797 if (ret) {
798 s5p_mfc_clock_off();
799 goto err_load_fw;
800 }
af935746
KD		 801 /* Init the FW */
802 ret = s5p_mfc_init_hw(dev);
2e731e44 803 s5p_mfc_clock_off();
af935746
KD		 804 if (ret)
805 goto err_init_hw;
af935746
KD		 806 }
807 /* Init videobuf2 queue for CAPTURE */
808 q = &ctx->vq_dst;
809 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
810 q->drv_priv = &ctx->fh;
811 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
812 q->io_modes = VB2_MMAP;
813 q->ops = get_dec_queue_ops();
814 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
815 q->io_modes = VB2_MMAP | VB2_USERPTR;
816 q->ops = get_enc_queue_ops();
817 } else {
818 ret = -ENOENT;
819 goto err_queue_init;
820 }
821 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
822 ret = vb2_queue_init(q);
823 if (ret) {
824 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
825 goto err_queue_init;
826 }
827 /* Init videobuf2 queue for OUTPUT */
828 q = &ctx->vq_src;
829 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
830 q->io_modes = VB2_MMAP;
831 q->drv_priv = &ctx->fh;
832 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
833 q->io_modes = VB2_MMAP;
834 q->ops = get_dec_queue_ops();
835 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
836 q->io_modes = VB2_MMAP | VB2_USERPTR;
837 q->ops = get_enc_queue_ops();
838 } else {
839 ret = -ENOENT;
840 goto err_queue_init;
841 }
842 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
843 ret = vb2_queue_init(q);
844 if (ret) {
845 mfc_err("Failed to initialize videobuf2 queue(output)\n");
846 goto err_queue_init;
847 }
848 init_waitqueue_head(&ctx->queue);
bc738301 849 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 850 mfc_debug_leave();
851 return ret;
852 /* Deinit when failure occured */
853err_queue_init:
2e731e44
KD		 854 if (dev->num_inst == 1)
855 s5p_mfc_deinit_hw(dev);
af935746 856err_init_hw:
2e731e44 857err_load_fw:
1259762f 858 dev->ctx[ctx->num] = NULL;
af935746 859 del_timer_sync(&dev->watchdog_timer);
af935746
KD		 860err_pwr_enable:
861 if (dev->num_inst == 1) {
862 if (s5p_mfc_power_off() < 0)
863 mfc_err("power off failed\n");
af935746
KD		 864 }
865err_ctrls_setup:
866 s5p_mfc_dec_ctrls_delete(ctx);
867err_bad_node:
868err_no_ctx:
869 v4l2_fh_del(&ctx->fh);
870 v4l2_fh_exit(&ctx->fh);
871 kfree(ctx);
872err_alloc:
873 dev->num_inst--;
bc738301 874 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 875 mfc_debug_leave();
876 return ret;
877}
878
879/* Release MFC context */
880static int s5p_mfc_release(struct file *file)
881{
882 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
883 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 884
885 mfc_debug_enter();
bc738301 886 mutex_lock(&dev->mfc_mutex);
af935746
KD		 887 s5p_mfc_clock_on();
888 vb2_queue_release(&ctx->vq_src);
889 vb2_queue_release(&ctx->vq_dst);
890 /* Mark context as idle */
7fb89eca 891 clear_work_bit_irqsave(ctx);
af935746
KD		 892 /* If instance was initialised then
893 * return instance and free reosurces */
894 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
895 mfc_debug(2, "Has to free instance\n");
896 ctx->state = MFCINST_RETURN_INST;
7fb89eca 897 set_work_bit_irqsave(ctx);
af935746 898 s5p_mfc_clean_ctx_int_flags(ctx);
43a1ea1f 899 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 900 /* Wait until instance is returned or timeout occured */
901 if (s5p_mfc_wait_for_done_ctx
43a1ea1f 902 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
af935746
KD		 903 s5p_mfc_clock_off();
904 mfc_err("Err returning instance\n");
905 }
906 mfc_debug(2, "After free instance\n");
907 /* Free resources */
43a1ea1f
AK		 908 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
909 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
af935746 910 if (ctx->type == MFCINST_DECODER)
43a1ea1f
AK		 911 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
912 ctx);
af935746
KD		 913
914 ctx->inst_no = MFC_NO_INSTANCE_SET;
915 }
916 /* hardware locking scheme */
917 if (dev->curr_ctx == ctx->num)
918 clear_bit(0, &dev->hw_lock);
919 dev->num_inst--;
920 if (dev->num_inst == 0) {
2e731e44 921 mfc_debug(2, "Last instance\n");
43a1ea1f 922 s5p_mfc_deinit_hw(dev);
af935746
KD		 923 del_timer_sync(&dev->watchdog_timer);
924 if (s5p_mfc_power_off() < 0)
925 mfc_err("Power off failed\n");
926 }
927 mfc_debug(2, "Shutting down clock\n");
928 s5p_mfc_clock_off();
1259762f 929 dev->ctx[ctx->num] = NULL;
af935746
KD		 930 s5p_mfc_dec_ctrls_delete(ctx);
931 v4l2_fh_del(&ctx->fh);
932 v4l2_fh_exit(&ctx->fh);
933 kfree(ctx);
934 mfc_debug_leave();
bc738301 935 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 936 return 0;
937}
938
939/* Poll */
940static unsigned int s5p_mfc_poll(struct file *file,
941 struct poll_table_struct *wait)
942{
943 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
944 struct s5p_mfc_dev *dev = ctx->dev;
945 struct vb2_queue *src_q, *dst_q;
946 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
947 unsigned int rc = 0;
948 unsigned long flags;
949
bc738301 950 mutex_lock(&dev->mfc_mutex);
af935746
KD		 951 src_q = &ctx->vq_src;
952 dst_q = &ctx->vq_dst;
953 /*
954 * There has to be at least one buffer queued on each queued_list, which
955 * means either in driver already or waiting for driver to claim it
956 * and start processing.
957 */
958 if ((!src_q->streaming || list_empty(&src_q->queued_list))
959 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
960 rc = POLLERR;
961 goto end;
962 }
963 mutex_unlock(&dev->mfc_mutex);
f9f715a9 964 poll_wait(file, &ctx->fh.wait, wait);
af935746
KD		 965 poll_wait(file, &src_q->done_wq, wait);
966 poll_wait(file, &dst_q->done_wq, wait);
967 mutex_lock(&dev->mfc_mutex);
f9f715a9
AH		 968 if (v4l2_event_pending(&ctx->fh))
969 rc |= POLLPRI;
af935746
KD		 970 spin_lock_irqsave(&src_q->done_lock, flags);
971 if (!list_empty(&src_q->done_list))
972 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
973 done_entry);
974 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
975 || src_vb->state == VB2_BUF_STATE_ERROR))
976 rc |= POLLOUT | POLLWRNORM;
977 spin_unlock_irqrestore(&src_q->done_lock, flags);
978 spin_lock_irqsave(&dst_q->done_lock, flags);
979 if (!list_empty(&dst_q->done_list))
980 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
981 done_entry);
982 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
983 || dst_vb->state == VB2_BUF_STATE_ERROR))
984 rc |= POLLIN | POLLRDNORM;
985 spin_unlock_irqrestore(&dst_q->done_lock, flags);
986end:
bc738301 987 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 988 return rc;
989}
990
991/* Mmap */
992static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
993{
994 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
bc738301 995 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 996 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
997 int ret;
bc738301
HV		 998
999 if (mutex_lock_interruptible(&dev->mfc_mutex))
1000 return -ERESTARTSYS;
af935746
KD		 1001 if (offset < DST_QUEUE_OFF_BASE) {
1002 mfc_debug(2, "mmaping source\n");
1003 ret = vb2_mmap(&ctx->vq_src, vma);
1004 } else { /* capture */
1005 mfc_debug(2, "mmaping destination\n");
1006 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1007 ret = vb2_mmap(&ctx->vq_dst, vma);
1008 }
bc738301 1009 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 1010 return ret;
1011}
1012
1013/* v4l2 ops */
1014static const struct v4l2_file_operations s5p_mfc_fops = {
1015 .owner = THIS_MODULE,
1016 .open = s5p_mfc_open,
1017 .release = s5p_mfc_release,
1018 .poll = s5p_mfc_poll,
1019 .unlocked_ioctl = video_ioctl2,
1020 .mmap = s5p_mfc_mmap,
1021};
1022
1023static int match_child(struct device *dev, void *data)
1024{
1025 if (!dev_name(dev))
1026 return 0;
1027 return !strcmp(dev_name(dev), (char *)data);
1028}
1029
b27a23be
AK		 1030static void *mfc_get_drv_data(struct platform_device *pdev);
1031
af935746 1032/* MFC probe function */
1e393e90 1033static int s5p_mfc_probe(struct platform_device *pdev)
af935746
KD		 1034{
1035 struct s5p_mfc_dev *dev;
1036 struct video_device *vfd;
1037 struct resource *res;
1038 int ret;
b27a23be 1039 unsigned int mem_info[2];
af935746
KD		 1040
1041 pr_debug("%s++\n", __func__);
bae061b4 1042 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
af935746
KD		 1043 if (!dev) {
1044 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1045 return -ENOMEM;
1046 }
1047
1048 spin_lock_init(&dev->irqlock);
1049 spin_lock_init(&dev->condlock);
1050 dev->plat_dev = pdev;
1051 if (!dev->plat_dev) {
1052 dev_err(&pdev->dev, "No platform data specified\n");
d310f478 1053 return -ENODEV;
af935746
KD		 1054 }
1055
b27a23be 1056 dev->variant = mfc_get_drv_data(pdev);
8f532a7f 1057
af935746
KD		 1058 ret = s5p_mfc_init_pm(dev);
1059 if (ret < 0) {
1060 dev_err(&pdev->dev, "failed to get mfc clock source\n");
d310f478 1061 return ret;
af935746
KD		 1062 }
1063
1064 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af935746 1065
d310f478 1066 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res);
af935746 1067 if (dev->regs_base == NULL) {
d310f478
SK		 1068 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1069 return -ENOENT;
af935746
KD		 1070 }
1071
1072 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1073 if (res == NULL) {
1074 dev_err(&pdev->dev, "failed to get irq resource\n");
1075 ret = -ENOENT;
d310f478 1076 goto err_res;
af935746
KD		 1077 }
1078 dev->irq = res->start;
d310f478
SK		 1079 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1080 IRQF_DISABLED, pdev->name, dev);
af935746
KD		 1081 if (ret) {
1082 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
d310f478 1083 goto err_res;
af935746
KD		 1084 }
1085
b27a23be
AK		 1086 if (pdev->dev.of_node) {
1087 dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL);
1088 if (!dev->mem_dev_l) {
1089 mfc_err("Not enough memory\n");
1090 ret = -ENOMEM;
1091 goto err_res;
1092 }
1093 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-l",
1094 mem_info, 2);
1095 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1096 mem_info[0], mem_info[1],
1097 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1098 mfc_err("Failed to declare coherent memory for\n"
1099 "MFC device\n");
1100 ret = -ENOMEM;
1101 goto err_res;
1102 }
f96f3cfa 1103
b27a23be
AK		 1104 dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL);
1105 if (!dev->mem_dev_r) {
1106 mfc_err("Not enough memory\n");
1107 ret = -ENOMEM;
1108 goto err_res;
1109 }
1110 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-r",
1111 mem_info, 2);
1112 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1113 mem_info[0], mem_info[1],
1114 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1115 pr_err("Failed to declare coherent memory for\n"
1116 "MFC device\n");
1117 ret = -ENOMEM;
1118 goto err_res;
1119 }
1120 } else {
1121 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1122 "s5p-mfc-l", match_child);
1123 if (!dev->mem_dev_l) {
1124 mfc_err("Mem child (L) device get failed\n");
1125 ret = -ENODEV;
1126 goto err_res;
1127 }
1128 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1129 "s5p-mfc-r", match_child);
1130 if (!dev->mem_dev_r) {
1131 mfc_err("Mem child (R) device get failed\n");
1132 ret = -ENODEV;
1133 goto err_res;
1134 }
af935746
KD		 1135 }
1136
1137 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1138 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
1139 ret = PTR_ERR(dev->alloc_ctx[0]);
d310f478 1140 goto err_res;
af935746
KD		 1141 }
1142 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1143 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
1144 ret = PTR_ERR(dev->alloc_ctx[1]);
1145 goto err_mem_init_ctx_1;
1146 }
1147
1148 mutex_init(&dev->mfc_mutex);
1149
2e731e44
KD		 1150 ret = s5p_mfc_alloc_firmware(dev);
1151 if (ret)
1152 goto err_alloc_fw;
1153
af935746
KD		 1154 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1155 if (ret)
1156 goto err_v4l2_dev_reg;
1157 init_waitqueue_head(&dev->queue);
1158
1159 /* decoder */
1160 vfd = video_device_alloc();
1161 if (!vfd) {
1162 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1163 ret = -ENOMEM;
1164 goto err_dec_alloc;
1165 }
1166 vfd->fops = &s5p_mfc_fops,
1167 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1168 vfd->release = video_device_release,
1169 vfd->lock = &dev->mfc_mutex;
1170 vfd->v4l2_dev = &dev->v4l2_dev;
954f340f 1171 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1172 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1173 dev->vfd_dec = vfd;
1174 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1175 if (ret) {
1176 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1177 video_device_release(vfd);
1178 goto err_dec_reg;
1179 }
1180 v4l2_info(&dev->v4l2_dev,
1181 "decoder registered as /dev/video%d\n", vfd->num);
1182 video_set_drvdata(vfd, dev);
1183
1184 /* encoder */
1185 vfd = video_device_alloc();
1186 if (!vfd) {
1187 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1188 ret = -ENOMEM;
1189 goto err_enc_alloc;
1190 }
1191 vfd->fops = &s5p_mfc_fops,
1192 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1193 vfd->release = video_device_release,
1194 vfd->lock = &dev->mfc_mutex;
1195 vfd->v4l2_dev = &dev->v4l2_dev;
cdcf45e7 1196 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1197 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1198 dev->vfd_enc = vfd;
1199 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1200 if (ret) {
1201 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1202 video_device_release(vfd);
1203 goto err_enc_reg;
1204 }
1205 v4l2_info(&dev->v4l2_dev,
1206 "encoder registered as /dev/video%d\n", vfd->num);
1207 video_set_drvdata(vfd, dev);
1208 platform_set_drvdata(pdev, dev);
1209
1210 dev->hw_lock = 0;
1211 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1212 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1213 atomic_set(&dev->watchdog_cnt, 0);
1214 init_timer(&dev->watchdog_timer);
1215 dev->watchdog_timer.data = (unsigned long)dev;
1216 dev->watchdog_timer.function = s5p_mfc_watchdog;
1217
43a1ea1f
AK		 1218 /* Initialize HW ops and commands based on MFC version */
1219 s5p_mfc_init_hw_ops(dev);
1220 s5p_mfc_init_hw_cmds(dev);
1221
af935746
KD		 1222 pr_debug("%s--\n", __func__);
1223 return 0;
1224
1225/* Deinit MFC if probe had failed */
1226err_enc_reg:
1227 video_device_release(dev->vfd_enc);
1228err_enc_alloc:
1229 video_unregister_device(dev->vfd_dec);
1230err_dec_reg:
1231 video_device_release(dev->vfd_dec);
1232err_dec_alloc:
1233 v4l2_device_unregister(&dev->v4l2_dev);
1234err_v4l2_dev_reg:
2e731e44
KD		 1235 s5p_mfc_release_firmware(dev);
1236err_alloc_fw:
af935746
KD		 1237 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1238err_mem_init_ctx_1:
1239 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
af935746
KD		 1240err_res:
1241 s5p_mfc_final_pm(dev);
d310f478 1242
af935746
KD		 1243 pr_debug("%s-- with error\n", __func__);
1244 return ret;
1245
1246}
1247
1248/* Remove the driver */
1249static int __devexit s5p_mfc_remove(struct platform_device *pdev)
1250{
1251 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1252
1253 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1254
1255 del_timer_sync(&dev->watchdog_timer);
1256 flush_workqueue(dev->watchdog_workqueue);
1257 destroy_workqueue(dev->watchdog_workqueue);
1258
1259 video_unregister_device(dev->vfd_enc);
1260 video_unregister_device(dev->vfd_dec);
1261 v4l2_device_unregister(&dev->v4l2_dev);
2e731e44 1262 s5p_mfc_release_firmware(dev);
af935746
KD		 1263 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1264 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1265
af935746 1266 s5p_mfc_final_pm(dev);
af935746
KD		 1267 return 0;
1268}
1269
1270#ifdef CONFIG_PM_SLEEP
1271
1272static int s5p_mfc_suspend(struct device *dev)
1273{
1274 struct platform_device *pdev = to_platform_device(dev);
1275 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1276 int ret;
1277
1278 if (m_dev->num_inst == 0)
1279 return 0;
81c9bcfb 1280
af935746
KD		 1281 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1282 mfc_err("Error: going to suspend for a second time\n");
1283 return -EIO;
1284 }
1285
1286 /* Check if we're processing then wait if it necessary. */
1287 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1288 /* Try and lock the HW */
1289 /* Wait on the interrupt waitqueue */
1290 ret = wait_event_interruptible_timeout(m_dev->queue,
1291 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
1292 msecs_to_jiffies(MFC_INT_TIMEOUT));
1293
1294 if (ret == 0) {
1295 mfc_err("Waiting for hardware to finish timed out\n");
1296 return -EIO;
1297 }
1298 }
81c9bcfb
SK		 1299
1300 return s5p_mfc_sleep(m_dev);
af935746
KD		 1301}
1302
1303static int s5p_mfc_resume(struct device *dev)
1304{
1305 struct platform_device *pdev = to_platform_device(dev);
1306 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1307
1308 if (m_dev->num_inst == 0)
1309 return 0;
1310 return s5p_mfc_wakeup(m_dev);
1311}
1312#endif
1313
1314#ifdef CONFIG_PM_RUNTIME
1315static int s5p_mfc_runtime_suspend(struct device *dev)
1316{
1317 struct platform_device *pdev = to_platform_device(dev);
1318 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1319
1320 atomic_set(&m_dev->pm.power, 0);
1321 return 0;
1322}
1323
1324static int s5p_mfc_runtime_resume(struct device *dev)
1325{
1326 struct platform_device *pdev = to_platform_device(dev);
1327 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1328 int pre_power;
1329
1330 if (!m_dev->alloc_ctx)
1331 return 0;
1332 pre_power = atomic_read(&m_dev->pm.power);
1333 atomic_set(&m_dev->pm.power, 1);
1334 return 0;
1335}
1336#endif
1337
1338/* Power management */
1339static const struct dev_pm_ops s5p_mfc_pm_ops = {
1340 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1341 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1342 NULL)
1343};
1344
8f532a7f
AK		 1345struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1346 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1347 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1348 .dsc = DESC_BUF_SIZE,
1349 .shm = SHARED_BUF_SIZE,
1350};
1351
1352struct s5p_mfc_buf_size buf_size_v5 = {
1353 .fw = MAX_FW_SIZE,
1354 .cpb = MAX_CPB_SIZE,
1355 .priv = &mfc_buf_size_v5,
1356};
1357
1358struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1359 .base = MFC_BASE_ALIGN_ORDER,
1360};
1361
1362static struct s5p_mfc_variant mfc_drvdata_v5 = {
1363 .version = MFC_VERSION,
1364 .port_num = MFC_NUM_PORTS,
1365 .buf_size = &buf_size_v5,
1366 .buf_align = &mfc_buf_align_v5,
f96f3cfa
JP		 1367 .mclk_name = "sclk_mfc",
1368 .fw_name = "s5p-mfc.fw",
1369};
1370
1371struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1372 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1373 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1374 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1375 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1376 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1377};
1378
1379struct s5p_mfc_buf_size buf_size_v6 = {
1380 .fw = MAX_FW_SIZE_V6,
1381 .cpb = MAX_CPB_SIZE_V6,
1382 .priv = &mfc_buf_size_v6,
1383};
1384
1385struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1386 .base = 0,
1387};
1388
1389static struct s5p_mfc_variant mfc_drvdata_v6 = {
1390 .version = MFC_VERSION_V6,
1391 .port_num = MFC_NUM_PORTS_V6,
1392 .buf_size = &buf_size_v6,
1393 .buf_align = &mfc_buf_align_v6,
1394 .mclk_name = "aclk_333",
1395 .fw_name = "s5p-mfc-v6.fw",
8f532a7f
AK		 1396};
1397
1398static struct platform_device_id mfc_driver_ids[] = {
1399 {
1400 .name = "s5p-mfc",
1401 .driver_data = (unsigned long)&mfc_drvdata_v5,
f96f3cfa
JP		 1402 }, {
1403 .name = "s5p-mfc-v5",
1404 .driver_data = (unsigned long)&mfc_drvdata_v5,
1405 }, {
1406 .name = "s5p-mfc-v6",
1407 .driver_data = (unsigned long)&mfc_drvdata_v6,
8f532a7f
AK		 1408 },
1409 {},
1410};
1411MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1412
b27a23be
AK		 1413static const struct of_device_id exynos_mfc_match[] = {
1414 {
1415 .compatible = "samsung,mfc-v5",
1416 .data = &mfc_drvdata_v5,
1417 }, {
1418 .compatible = "samsung,mfc-v6",
1419 .data = &mfc_drvdata_v6,
1420 },
1421 {},
1422};
1423MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1424
1425static void *mfc_get_drv_data(struct platform_device *pdev)
1426{
1427 struct s5p_mfc_variant *driver_data = NULL;
1428
1429 if (pdev->dev.of_node) {
1430 const struct of_device_id *match;
1431 match = of_match_node(of_match_ptr(exynos_mfc_match),
1432 pdev->dev.of_node);
1433 if (match)
1434 driver_data = (struct s5p_mfc_variant *)match->data;
1435 } else {
1436 driver_data = (struct s5p_mfc_variant *)
1437 platform_get_device_id(pdev)->driver_data;
1438 }
1439 return driver_data;
1440}
1441
1e393e90 1442static struct platform_driver s5p_mfc_driver = {
8f532a7f
AK		 1443 .probe = s5p_mfc_probe,
1444 .remove = __devexit_p(s5p_mfc_remove),
1445 .id_table = mfc_driver_ids,
af935746
KD		 1446 .driver = {
1447 .name = S5P_MFC_NAME,
1448 .owner = THIS_MODULE,
b27a23be
AK		 1449 .pm = &s5p_mfc_pm_ops,
1450 .of_match_table = exynos_mfc_match,
af935746
KD		 1451 },
1452};
1453
1d6629b1 1454module_platform_driver(s5p_mfc_driver);
af935746
KD		 1455
1456MODULE_LICENSE("GPL");
1457MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1458MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1459
Linux kernel - Deliverables
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