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[media] s5p-mfc: Remove duplicate function s5p_mfc_reload_firmware
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
af935746 21#include <linux/videodev2.h>
f9f715a9 22#include <media/v4l2-event.h>
af935746 23#include <linux/workqueue.h>
b27a23be 24#include <linux/of.h>
af935746 25#include <media/videobuf2-core.h>
43a1ea1f 26#include "s5p_mfc_common.h"
af935746
KD		 27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
af935746 34#include "s5p_mfc_pm.h"
af935746
KD		 35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40int debug;
41module_param(debug, int, S_IRUGO | S_IWUSR);
42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44/* Helper functions for interrupt processing */
7fb89eca 45
af935746 46/* Remove from hw execution round robin */
7fb89eca 47void clear_work_bit(struct s5p_mfc_ctx *ctx)
af935746
KD		 48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
7fb89eca 52 __clear_bit(ctx->num, &dev->ctx_work_bits);
af935746
KD		 53 spin_unlock(&dev->condlock);
54}
55
7fb89eca
AH		 56/* Add to hw execution round robin */
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66/* Remove from hw execution round robin */
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77/* Add to hw execution round robin */
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
af935746
KD		 88/* Wake up context wait_queue */
89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91{
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96}
97
98/* Wake up device wait_queue */
99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101{
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106}
107
a13bba4f 108static void s5p_mfc_watchdog(unsigned long arg)
af935746
KD		 109{
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126}
127
128static void s5p_mfc_watchdog_worker(struct work_struct *work)
129{
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
43a1ea1f
AK		 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
154 &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
156 &ctx->vq_src);
af935746 157 clear_work_bit(ctx);
43a1ea1f 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
af935746
KD		 159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
46075006 165 ret = s5p_mfc_load_firmware(dev);
af935746
KD		 166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 if (ret)
173 mfc_err("Failed to reinit FW\n");
174 }
175unlock:
176 if (mutex_locked)
177 mutex_unlock(&dev->mfc_mutex);
178}
179
af935746
KD		 180static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
181{
182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
185}
186
187static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
188{
189 struct s5p_mfc_buf *dst_buf;
43a1ea1f 190 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 191
192 ctx->state = MFCINST_FINISHED;
193 ctx->sequence++;
194 while (!list_empty(&ctx->dst_queue)) {
195 dst_buf = list_entry(ctx->dst_queue.next,
196 struct s5p_mfc_buf, list);
197 mfc_debug(2, "Cleaning up buffer: %d\n",
198 dst_buf->b->v4l2_buf.index);
199 vb2_set_plane_payload(dst_buf->b, 0, 0);
200 vb2_set_plane_payload(dst_buf->b, 1, 0);
201 list_del(&dst_buf->list);
202 ctx->dst_queue_cnt--;
203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
204
43a1ea1f
AK		 205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
af935746
KD		 207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
208 else
209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
210
211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
213 }
214}
215
216static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
217{
218 struct s5p_mfc_dev *dev = ctx->dev;
219 struct s5p_mfc_buf *dst_buf, *src_buf;
43a1ea1f
AK		 220 size_t dec_y_addr;
221 unsigned int frame_type;
222
223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
af935746
KD		 225
226 /* Copy timestamp / timecode from decoded src to dst and set
39c1cb2b 227 appropriate flags */
af935746
KD		 228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
ba7fcb0c 230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
56006017
KD		 231 dst_buf->b->v4l2_buf.timecode =
232 src_buf->b->v4l2_buf.timecode;
233 dst_buf->b->v4l2_buf.timestamp =
234 src_buf->b->v4l2_buf.timestamp;
309f4d62
SA		 235 dst_buf->b->v4l2_buf.flags &=
236 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
237 dst_buf->b->v4l2_buf.flags |=
238 src_buf->b->v4l2_buf.flags
239 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
af935746
KD		 240 switch (frame_type) {
241 case S5P_FIMV_DECODE_FRAME_I_FRAME:
242 dst_buf->b->v4l2_buf.flags |=
243 V4L2_BUF_FLAG_KEYFRAME;
244 break;
245 case S5P_FIMV_DECODE_FRAME_P_FRAME:
246 dst_buf->b->v4l2_buf.flags |=
247 V4L2_BUF_FLAG_PFRAME;
248 break;
249 case S5P_FIMV_DECODE_FRAME_B_FRAME:
250 dst_buf->b->v4l2_buf.flags |=
251 V4L2_BUF_FLAG_BFRAME;
252 break;
253 }
254 break;
255 }
256 }
257}
258
259static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
260{
261 struct s5p_mfc_dev *dev = ctx->dev;
262 struct s5p_mfc_buf *dst_buf;
43a1ea1f
AK		 263 size_t dspl_y_addr;
264 unsigned int frame_type;
af935746 265
43a1ea1f 266 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
90c0ae50 267 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx);
43a1ea1f 268
af935746
KD		 269 /* If frame is same as previous then skip and do not dequeue */
270 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
271 if (!ctx->after_packed_pb)
272 ctx->sequence++;
273 ctx->after_packed_pb = 0;
274 return;
275 }
276 ctx->sequence++;
277 /* The MFC returns address of the buffer, now we have to
278 * check which videobuf does it correspond to */
279 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
280 /* Check if this is the buffer we're looking for */
ba7fcb0c 281 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
af935746
KD		 282 list_del(&dst_buf->list);
283 ctx->dst_queue_cnt--;
284 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
43a1ea1f
AK		 285 if (s5p_mfc_hw_call(dev->mfc_ops,
286 get_pic_type_top, ctx) ==
287 s5p_mfc_hw_call(dev->mfc_ops,
288 get_pic_type_bot, ctx))
af935746
KD		 289 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
290 else
291 dst_buf->b->v4l2_buf.field =
292 V4L2_FIELD_INTERLACED;
293 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
294 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
295 clear_bit(dst_buf->b->v4l2_buf.index,
296 &ctx->dec_dst_flag);
297
298 vb2_buffer_done(dst_buf->b,
299 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
300
af935746
KD		 301 break;
302 }
303 }
304}
305
306/* Handle frame decoding interrupt */
307static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
308 unsigned int reason, unsigned int err)
309{
310 struct s5p_mfc_dev *dev = ctx->dev;
311 unsigned int dst_frame_status;
a0517f5d 312 unsigned int dec_frame_status;
af935746
KD		 313 struct s5p_mfc_buf *src_buf;
314 unsigned long flags;
315 unsigned int res_change;
316
43a1ea1f 317 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
af935746 318 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
a0517f5d
PO		 319 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
320 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
f96f3cfa
JP		 321 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
322 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
323 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
af935746
KD		 324 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
325 if (ctx->state == MFCINST_RES_CHANGE_INIT)
326 ctx->state = MFCINST_RES_CHANGE_FLUSH;
f96f3cfa
JP		 327 if (res_change == S5P_FIMV_RES_INCREASE ||
328 res_change == S5P_FIMV_RES_DECREASE) {
af935746 329 ctx->state = MFCINST_RES_CHANGE_INIT;
43a1ea1f 330 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 331 wake_up_ctx(ctx, reason, err);
332 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
333 BUG();
334 s5p_mfc_clock_off();
43a1ea1f 335 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 336 return;
337 }
338 if (ctx->dpb_flush_flag)
339 ctx->dpb_flush_flag = 0;
340
341 spin_lock_irqsave(&dev->irqlock, flags);
342 /* All frames remaining in the buffer have been extracted */
343 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
344 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
0520e4cc
PO		 345 static const struct v4l2_event ev_src_ch = {
346 .type = V4L2_EVENT_SOURCE_CHANGE,
347 .u.src_change.changes =
348 V4L2_EVENT_SRC_CH_RESOLUTION,
349 };
350
af935746
KD		 351 s5p_mfc_handle_frame_all_extracted(ctx);
352 ctx->state = MFCINST_RES_CHANGE_END;
0520e4cc
PO		 353 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
354
af935746
KD		 355 goto leave_handle_frame;
356 } else {
357 s5p_mfc_handle_frame_all_extracted(ctx);
358 }
359 }
360
a0517f5d 361 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
af935746
KD		 362 s5p_mfc_handle_frame_copy_time(ctx);
363
364 /* A frame has been decoded and is in the buffer */
365 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
366 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
367 s5p_mfc_handle_frame_new(ctx, err);
368 } else {
369 mfc_debug(2, "No frame decode\n");
370 }
371 /* Mark source buffer as complete */
372 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
373 && !list_empty(&ctx->src_queue)) {
374 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
375 list);
43a1ea1f
AK		 376 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
377 get_consumed_stream, dev);
378 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
f49f3ed5 379 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
d2a0db1e
AK		 380 ctx->consumed_stream + STUFF_BYTE <
381 src_buf->b->v4l2_planes[0].bytesused) {
af935746
KD		 382 /* Run MFC again on the same buffer */
383 mfc_debug(2, "Running again the same buffer\n");
384 ctx->after_packed_pb = 1;
385 } else {
af935746
KD		 386 mfc_debug(2, "MFC needs next buffer\n");
387 ctx->consumed_stream = 0;
a34026e7
KD		 388 if (src_buf->flags & MFC_BUF_FLAG_EOS)
389 ctx->state = MFCINST_FINISHING;
af935746
KD		 390 list_del(&src_buf->list);
391 ctx->src_queue_cnt--;
43a1ea1f 392 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
af935746
KD		 393 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
394 else
395 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
396 }
397 }
398leave_handle_frame:
399 spin_unlock_irqrestore(&dev->irqlock, flags);
400 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
e9d98ddc 401 || ctx->dst_queue_cnt < ctx->pb_count)
af935746 402 clear_work_bit(ctx);
43a1ea1f 403 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 404 wake_up_ctx(ctx, reason, err);
405 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
406 BUG();
407 s5p_mfc_clock_off();
76a4ddbd
P		 408 /* if suspending, wake up device and do not try_run again*/
409 if (test_bit(0, &dev->enter_suspend))
410 wake_up_dev(dev, reason, err);
411 else
412 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 413}
414
415/* Error handling for interrupt */
7296e25f
KD		 416static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
417 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
af935746 418{
af935746
KD		 419 unsigned long flags;
420
af935746 421 mfc_err("Interrupt Error: %08x\n", err);
af935746 422
7296e25f
KD		 423 if (ctx != NULL) {
424 /* Error recovery is dependent on the state of context */
425 switch (ctx->state) {
426 case MFCINST_RES_CHANGE_INIT:
427 case MFCINST_RES_CHANGE_FLUSH:
428 case MFCINST_RES_CHANGE_END:
429 case MFCINST_FINISHING:
430 case MFCINST_FINISHED:
431 case MFCINST_RUNNING:
39c1cb2b 432 /* It is highly probable that an error occurred
7296e25f
KD		 433 * while decoding a frame */
434 clear_work_bit(ctx);
435 ctx->state = MFCINST_ERROR;
436 /* Mark all dst buffers as having an error */
437 spin_lock_irqsave(&dev->irqlock, flags);
438 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
439 &ctx->dst_queue, &ctx->vq_dst);
440 /* Mark all src buffers as having an error */
441 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
442 &ctx->src_queue, &ctx->vq_src);
443 spin_unlock_irqrestore(&dev->irqlock, flags);
444 wake_up_ctx(ctx, reason, err);
445 break;
446 default:
447 clear_work_bit(ctx);
448 ctx->state = MFCINST_ERROR;
449 wake_up_ctx(ctx, reason, err);
450 break;
451 }
af935746 452 }
7296e25f
KD		 453 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
454 BUG();
455 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
456 s5p_mfc_clock_off();
457 wake_up_dev(dev, reason, err);
af935746
KD		 458 return;
459}
460
461/* Header parsing interrupt handling */
462static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
463 unsigned int reason, unsigned int err)
464{
465 struct s5p_mfc_dev *dev;
af935746 466
1259762f 467 if (ctx == NULL)
af935746
KD		 468 return;
469 dev = ctx->dev;
470 if (ctx->c_ops->post_seq_start) {
471 if (ctx->c_ops->post_seq_start(ctx))
472 mfc_err("post_seq_start() failed\n");
473 } else {
43a1ea1f
AK		 474 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
475 dev);
476 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
477 dev);
af935746 478
8f532a7f
AK		 479 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
480
e9d98ddc 481 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
43a1ea1f 482 dev);
f96f3cfa
JP		 483 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
484 dev);
bb869368 485 if (ctx->img_width == 0 || ctx->img_height == 0)
af935746
KD		 486 ctx->state = MFCINST_ERROR;
487 else
488 ctx->state = MFCINST_HEAD_PARSED;
f96f3cfa
JP		 489
490 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
491 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
492 !list_empty(&ctx->src_queue)) {
493 struct s5p_mfc_buf *src_buf;
494 src_buf = list_entry(ctx->src_queue.next,
495 struct s5p_mfc_buf, list);
496 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
497 dev) <
498 src_buf->b->v4l2_planes[0].bytesused)
499 ctx->head_processed = 0;
500 else
501 ctx->head_processed = 1;
502 } else {
503 ctx->head_processed = 1;
504 }
af935746 505 }
43a1ea1f 506 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 507 clear_work_bit(ctx);
508 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
509 BUG();
510 s5p_mfc_clock_off();
43a1ea1f 511 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 512 wake_up_ctx(ctx, reason, err);
513}
514
515/* Header parsing interrupt handling */
516static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
517 unsigned int reason, unsigned int err)
518{
519 struct s5p_mfc_buf *src_buf;
520 struct s5p_mfc_dev *dev;
521 unsigned long flags;
522
1259762f 523 if (ctx == NULL)
af935746
KD		 524 return;
525 dev = ctx->dev;
43a1ea1f 526 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 527 ctx->int_type = reason;
528 ctx->int_err = err;
529 ctx->int_cond = 1;
7fb89eca 530 clear_work_bit(ctx);
af935746
KD		 531 if (err == 0) {
532 ctx->state = MFCINST_RUNNING;
f96f3cfa 533 if (!ctx->dpb_flush_flag && ctx->head_processed) {
af935746
KD		 534 spin_lock_irqsave(&dev->irqlock, flags);
535 if (!list_empty(&ctx->src_queue)) {
536 src_buf = list_entry(ctx->src_queue.next,
537 struct s5p_mfc_buf, list);
538 list_del(&src_buf->list);
539 ctx->src_queue_cnt--;
540 vb2_buffer_done(src_buf->b,
541 VB2_BUF_STATE_DONE);
542 }
543 spin_unlock_irqrestore(&dev->irqlock, flags);
544 } else {
545 ctx->dpb_flush_flag = 0;
546 }
547 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
548 BUG();
549
550 s5p_mfc_clock_off();
551
552 wake_up(&ctx->queue);
43a1ea1f 553 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 554 } else {
555 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
556 BUG();
557
558 s5p_mfc_clock_off();
559
560 wake_up(&ctx->queue);
561 }
562}
563
f9f715a9
AH		 564static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
565 unsigned int reason, unsigned int err)
566{
567 struct s5p_mfc_dev *dev = ctx->dev;
568 struct s5p_mfc_buf *mb_entry;
569
4130eabc 570 mfc_debug(2, "Stream completed\n");
f9f715a9
AH		 571
572 s5p_mfc_clear_int_flags(dev);
573 ctx->int_type = reason;
574 ctx->int_err = err;
575 ctx->state = MFCINST_FINISHED;
576
577 spin_lock(&dev->irqlock);
578 if (!list_empty(&ctx->dst_queue)) {
579 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
580 list);
581 list_del(&mb_entry->list);
582 ctx->dst_queue_cnt--;
583 vb2_set_plane_payload(mb_entry->b, 0, 0);
584 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
585 }
586 spin_unlock(&dev->irqlock);
587
588 clear_work_bit(ctx);
589
e8256447 590 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
f9f715a9
AH		 591
592 s5p_mfc_clock_off();
593 wake_up(&ctx->queue);
43a1ea1f 594 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
f9f715a9
AH		 595}
596
af935746
KD		 597/* Interrupt processing */
598static irqreturn_t s5p_mfc_irq(int irq, void *priv)
599{
600 struct s5p_mfc_dev *dev = priv;
601 struct s5p_mfc_ctx *ctx;
602 unsigned int reason;
603 unsigned int err;
604
605 mfc_debug_enter();
606 /* Reset the timeout watchdog */
607 atomic_set(&dev->watchdog_cnt, 0);
608 ctx = dev->ctx[dev->curr_ctx];
609 /* Get the reason of interrupt and the error code */
43a1ea1f
AK		 610 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
611 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
af935746
KD		 612 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
613 switch (reason) {
43a1ea1f 614 case S5P_MFC_R2H_CMD_ERR_RET:
39c1cb2b 615 /* An error has occurred */
af935746 616 if (ctx->state == MFCINST_RUNNING &&
43a1ea1f
AK		 617 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
618 dev->warn_start)
af935746
KD		 619 s5p_mfc_handle_frame(ctx, reason, err);
620 else
7296e25f 621 s5p_mfc_handle_error(dev, ctx, reason, err);
af935746
KD		 622 clear_bit(0, &dev->enter_suspend);
623 break;
624
43a1ea1f
AK		 625 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
626 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
627 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
af935746
KD		 628 if (ctx->c_ops->post_frame_start) {
629 if (ctx->c_ops->post_frame_start(ctx))
630 mfc_err("post_frame_start() failed\n");
43a1ea1f 631 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 632 wake_up_ctx(ctx, reason, err);
633 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
634 BUG();
635 s5p_mfc_clock_off();
43a1ea1f 636 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 637 } else {
638 s5p_mfc_handle_frame(ctx, reason, err);
639 }
640 break;
641
43a1ea1f 642 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
af935746
KD		 643 s5p_mfc_handle_seq_done(ctx, reason, err);
644 break;
645
43a1ea1f
AK		 646 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
647 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
af935746
KD		 648 ctx->state = MFCINST_GOT_INST;
649 clear_work_bit(ctx);
650 wake_up(&ctx->queue);
651 goto irq_cleanup_hw;
652
43a1ea1f 653 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
af935746 654 clear_work_bit(ctx);
9d87e837 655 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD		 656 ctx->state = MFCINST_FREE;
657 wake_up(&ctx->queue);
658 goto irq_cleanup_hw;
659
43a1ea1f
AK		 660 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
661 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
662 case S5P_MFC_R2H_CMD_SLEEP_RET:
663 case S5P_MFC_R2H_CMD_WAKEUP_RET:
af935746
KD		 664 if (ctx)
665 clear_work_bit(ctx);
43a1ea1f 666 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 667 wake_up_dev(dev, reason, err);
668 clear_bit(0, &dev->hw_lock);
669 clear_bit(0, &dev->enter_suspend);
670 break;
671
43a1ea1f 672 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
af935746
KD		 673 s5p_mfc_handle_init_buffers(ctx, reason, err);
674 break;
f9f715a9 675
43a1ea1f 676 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
f9f715a9
AH		 677 s5p_mfc_handle_stream_complete(ctx, reason, err);
678 break;
679
8f23cc02
AK		 680 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
681 clear_work_bit(ctx);
682 ctx->state = MFCINST_RUNNING;
683 wake_up(&ctx->queue);
684 goto irq_cleanup_hw;
685
af935746
KD		 686 default:
687 mfc_debug(2, "Unknown int reason\n");
43a1ea1f 688 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 689 }
690 mfc_debug_leave();
691 return IRQ_HANDLED;
692irq_cleanup_hw:
43a1ea1f 693 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 694 ctx->int_type = reason;
695 ctx->int_err = err;
696 ctx->int_cond = 1;
697 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
698 mfc_err("Failed to unlock hw\n");
699
700 s5p_mfc_clock_off();
701
43a1ea1f 702 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 703 mfc_debug(2, "Exit via irq_cleanup_hw\n");
704 return IRQ_HANDLED;
705}
706
707/* Open an MFC node */
708static int s5p_mfc_open(struct file *file)
709{
b80cb8dc 710 struct video_device *vdev = video_devdata(file);
af935746
KD		 711 struct s5p_mfc_dev *dev = video_drvdata(file);
712 struct s5p_mfc_ctx *ctx = NULL;
713 struct vb2_queue *q;
af935746
KD		 714 int ret = 0;
715
716 mfc_debug_enter();
bc738301
HV		 717 if (mutex_lock_interruptible(&dev->mfc_mutex))
718 return -ERESTARTSYS;
af935746
KD		 719 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
720 /* Allocate memory for context */
bae061b4 721 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
af935746
KD		 722 if (!ctx) {
723 mfc_err("Not enough memory\n");
724 ret = -ENOMEM;
725 goto err_alloc;
726 }
727 v4l2_fh_init(&ctx->fh, video_devdata(file));
728 file->private_data = &ctx->fh;
729 v4l2_fh_add(&ctx->fh);
730 ctx->dev = dev;
731 INIT_LIST_HEAD(&ctx->src_queue);
732 INIT_LIST_HEAD(&ctx->dst_queue);
733 ctx->src_queue_cnt = 0;
734 ctx->dst_queue_cnt = 0;
735 /* Get context number */
736 ctx->num = 0;
737 while (dev->ctx[ctx->num]) {
738 ctx->num++;
739 if (ctx->num >= MFC_NUM_CONTEXTS) {
740 mfc_err("Too many open contexts\n");
741 ret = -EBUSY;
742 goto err_no_ctx;
743 }
744 }
745 /* Mark context as idle */
7fb89eca 746 clear_work_bit_irqsave(ctx);
af935746 747 dev->ctx[ctx->num] = ctx;
b80cb8dc 748 if (vdev == dev->vfd_dec) {
af935746
KD		 749 ctx->type = MFCINST_DECODER;
750 ctx->c_ops = get_dec_codec_ops();
43a1ea1f 751 s5p_mfc_dec_init(ctx);
af935746
KD		 752 /* Setup ctrl handler */
753 ret = s5p_mfc_dec_ctrls_setup(ctx);
754 if (ret) {
755 mfc_err("Failed to setup mfc controls\n");
756 goto err_ctrls_setup;
757 }
b80cb8dc 758 } else if (vdev == dev->vfd_enc) {
af935746
KD		 759 ctx->type = MFCINST_ENCODER;
760 ctx->c_ops = get_enc_codec_ops();
761 /* only for encoder */
762 INIT_LIST_HEAD(&ctx->ref_queue);
763 ctx->ref_queue_cnt = 0;
43a1ea1f 764 s5p_mfc_enc_init(ctx);
af935746
KD		 765 /* Setup ctrl handler */
766 ret = s5p_mfc_enc_ctrls_setup(ctx);
767 if (ret) {
768 mfc_err("Failed to setup mfc controls\n");
769 goto err_ctrls_setup;
770 }
771 } else {
772 ret = -ENOENT;
773 goto err_bad_node;
774 }
775 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
9d87e837 776 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD		 777 /* Load firmware if this is the first instance */
778 if (dev->num_inst == 1) {
779 dev->watchdog_timer.expires = jiffies +
780 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
781 add_timer(&dev->watchdog_timer);
782 ret = s5p_mfc_power_on();
783 if (ret < 0) {
784 mfc_err("power on failed\n");
785 goto err_pwr_enable;
786 }
787 s5p_mfc_clock_on();
2e731e44
KD		 788 ret = s5p_mfc_load_firmware(dev);
789 if (ret) {
790 s5p_mfc_clock_off();
791 goto err_load_fw;
792 }
af935746
KD		 793 /* Init the FW */
794 ret = s5p_mfc_init_hw(dev);
2e731e44 795 s5p_mfc_clock_off();
af935746
KD		 796 if (ret)
797 goto err_init_hw;
af935746
KD		 798 }
799 /* Init videobuf2 queue for CAPTURE */
800 q = &ctx->vq_dst;
801 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
802 q->drv_priv = &ctx->fh;
b80cb8dc 803 if (vdev == dev->vfd_dec) {
af935746
KD		 804 q->io_modes = VB2_MMAP;
805 q->ops = get_dec_queue_ops();
b80cb8dc 806 } else if (vdev == dev->vfd_enc) {
af935746
KD		 807 q->io_modes = VB2_MMAP | VB2_USERPTR;
808 q->ops = get_enc_queue_ops();
809 } else {
810 ret = -ENOENT;
811 goto err_queue_init;
812 }
813 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
ade48681 814 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 815 ret = vb2_queue_init(q);
816 if (ret) {
817 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
818 goto err_queue_init;
819 }
820 /* Init videobuf2 queue for OUTPUT */
821 q = &ctx->vq_src;
822 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
823 q->io_modes = VB2_MMAP;
824 q->drv_priv = &ctx->fh;
b80cb8dc 825 if (vdev == dev->vfd_dec) {
af935746
KD		 826 q->io_modes = VB2_MMAP;
827 q->ops = get_dec_queue_ops();
b80cb8dc 828 } else if (vdev == dev->vfd_enc) {
af935746
KD		 829 q->io_modes = VB2_MMAP | VB2_USERPTR;
830 q->ops = get_enc_queue_ops();
831 } else {
832 ret = -ENOENT;
833 goto err_queue_init;
834 }
835 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
ade48681 836 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 837 ret = vb2_queue_init(q);
838 if (ret) {
839 mfc_err("Failed to initialize videobuf2 queue(output)\n");
840 goto err_queue_init;
841 }
842 init_waitqueue_head(&ctx->queue);
bc738301 843 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 844 mfc_debug_leave();
845 return ret;
39c1cb2b 846 /* Deinit when failure occurred */
af935746 847err_queue_init:
2e731e44
KD		 848 if (dev->num_inst == 1)
849 s5p_mfc_deinit_hw(dev);
af935746 850err_init_hw:
2e731e44 851err_load_fw:
af935746
KD		 852err_pwr_enable:
853 if (dev->num_inst == 1) {
854 if (s5p_mfc_power_off() < 0)
855 mfc_err("power off failed\n");
1b73ba0b 856 del_timer_sync(&dev->watchdog_timer);
af935746
KD		 857 }
858err_ctrls_setup:
859 s5p_mfc_dec_ctrls_delete(ctx);
860err_bad_node:
1b73ba0b 861 dev->ctx[ctx->num] = NULL;
af935746
KD		 862err_no_ctx:
863 v4l2_fh_del(&ctx->fh);
864 v4l2_fh_exit(&ctx->fh);
865 kfree(ctx);
866err_alloc:
867 dev->num_inst--;
bc738301 868 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 869 mfc_debug_leave();
870 return ret;
871}
872
873/* Release MFC context */
874static int s5p_mfc_release(struct file *file)
875{
876 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
877 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 878
879 mfc_debug_enter();
bc738301 880 mutex_lock(&dev->mfc_mutex);
af935746
KD		 881 s5p_mfc_clock_on();
882 vb2_queue_release(&ctx->vq_src);
883 vb2_queue_release(&ctx->vq_dst);
884 /* Mark context as idle */
7fb89eca 885 clear_work_bit_irqsave(ctx);
9d87e837 886 /* If instance was initialised and not yet freed,
39c1cb2b 887 * return instance and free resources */
9d87e837 888 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
af935746 889 mfc_debug(2, "Has to free instance\n");
818cd91a 890 s5p_mfc_close_mfc_inst(dev, ctx);
af935746
KD		 891 }
892 /* hardware locking scheme */
893 if (dev->curr_ctx == ctx->num)
894 clear_bit(0, &dev->hw_lock);
895 dev->num_inst--;
896 if (dev->num_inst == 0) {
2e731e44 897 mfc_debug(2, "Last instance\n");
43a1ea1f 898 s5p_mfc_deinit_hw(dev);
af935746
KD		 899 del_timer_sync(&dev->watchdog_timer);
900 if (s5p_mfc_power_off() < 0)
901 mfc_err("Power off failed\n");
902 }
903 mfc_debug(2, "Shutting down clock\n");
904 s5p_mfc_clock_off();
1259762f 905 dev->ctx[ctx->num] = NULL;
af935746
KD		 906 s5p_mfc_dec_ctrls_delete(ctx);
907 v4l2_fh_del(&ctx->fh);
908 v4l2_fh_exit(&ctx->fh);
909 kfree(ctx);
910 mfc_debug_leave();
bc738301 911 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 912 return 0;
913}
914
915/* Poll */
916static unsigned int s5p_mfc_poll(struct file *file,
917 struct poll_table_struct *wait)
918{
919 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
920 struct s5p_mfc_dev *dev = ctx->dev;
921 struct vb2_queue *src_q, *dst_q;
922 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
923 unsigned int rc = 0;
924 unsigned long flags;
925
bc738301 926 mutex_lock(&dev->mfc_mutex);
af935746
KD		 927 src_q = &ctx->vq_src;
928 dst_q = &ctx->vq_dst;
929 /*
930 * There has to be at least one buffer queued on each queued_list, which
931 * means either in driver already or waiting for driver to claim it
932 * and start processing.
933 */
934 if ((!src_q->streaming || list_empty(&src_q->queued_list))
935 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
936 rc = POLLERR;
937 goto end;
938 }
939 mutex_unlock(&dev->mfc_mutex);
f9f715a9 940 poll_wait(file, &ctx->fh.wait, wait);
af935746
KD		 941 poll_wait(file, &src_q->done_wq, wait);
942 poll_wait(file, &dst_q->done_wq, wait);
943 mutex_lock(&dev->mfc_mutex);
f9f715a9
AH		 944 if (v4l2_event_pending(&ctx->fh))
945 rc |= POLLPRI;
af935746
KD		 946 spin_lock_irqsave(&src_q->done_lock, flags);
947 if (!list_empty(&src_q->done_list))
948 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
949 done_entry);
950 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
951 || src_vb->state == VB2_BUF_STATE_ERROR))
952 rc |= POLLOUT | POLLWRNORM;
953 spin_unlock_irqrestore(&src_q->done_lock, flags);
954 spin_lock_irqsave(&dst_q->done_lock, flags);
955 if (!list_empty(&dst_q->done_list))
956 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
957 done_entry);
958 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
959 || dst_vb->state == VB2_BUF_STATE_ERROR))
960 rc |= POLLIN | POLLRDNORM;
961 spin_unlock_irqrestore(&dst_q->done_lock, flags);
962end:
bc738301 963 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 964 return rc;
965}
966
967/* Mmap */
968static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
969{
970 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
bc738301 971 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 972 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
973 int ret;
bc738301
HV		 974
975 if (mutex_lock_interruptible(&dev->mfc_mutex))
976 return -ERESTARTSYS;
af935746
KD		 977 if (offset < DST_QUEUE_OFF_BASE) {
978 mfc_debug(2, "mmaping source\n");
979 ret = vb2_mmap(&ctx->vq_src, vma);
980 } else { /* capture */
981 mfc_debug(2, "mmaping destination\n");
982 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
983 ret = vb2_mmap(&ctx->vq_dst, vma);
984 }
bc738301 985 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 986 return ret;
987}
988
989/* v4l2 ops */
990static const struct v4l2_file_operations s5p_mfc_fops = {
991 .owner = THIS_MODULE,
992 .open = s5p_mfc_open,
993 .release = s5p_mfc_release,
994 .poll = s5p_mfc_poll,
995 .unlocked_ioctl = video_ioctl2,
996 .mmap = s5p_mfc_mmap,
997};
998
999static int match_child(struct device *dev, void *data)
1000{
1001 if (!dev_name(dev))
1002 return 0;
1003 return !strcmp(dev_name(dev), (char *)data);
1004}
1005
b27a23be
AK		 1006static void *mfc_get_drv_data(struct platform_device *pdev);
1007
6e83e6e2
AK		 1008static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1009{
65fccab5 1010 unsigned int mem_info[2] = { };
6e83e6e2
AK		 1011
1012 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1013 sizeof(struct device), GFP_KERNEL);
1014 if (!dev->mem_dev_l) {
1015 mfc_err("Not enough memory\n");
1016 return -ENOMEM;
1017 }
1018 device_initialize(dev->mem_dev_l);
1019 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1020 "samsung,mfc-l", mem_info, 2);
1021 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1022 mem_info[0], mem_info[1],
1023 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1024 mfc_err("Failed to declare coherent memory for\n"
1025 "MFC device\n");
1026 return -ENOMEM;
1027 }
1028
1029 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1030 sizeof(struct device), GFP_KERNEL);
1031 if (!dev->mem_dev_r) {
1032 mfc_err("Not enough memory\n");
1033 return -ENOMEM;
1034 }
1035 device_initialize(dev->mem_dev_r);
1036 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1037 "samsung,mfc-r", mem_info, 2);
1038 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1039 mem_info[0], mem_info[1],
1040 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1041 pr_err("Failed to declare coherent memory for\n"
1042 "MFC device\n");
1043 return -ENOMEM;
1044 }
1045 return 0;
1046}
1047
af935746 1048/* MFC probe function */
1e393e90 1049static int s5p_mfc_probe(struct platform_device *pdev)
af935746
KD		 1050{
1051 struct s5p_mfc_dev *dev;
1052 struct video_device *vfd;
1053 struct resource *res;
1054 int ret;
1055
1056 pr_debug("%s++\n", __func__);
bae061b4 1057 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
af935746
KD		 1058 if (!dev) {
1059 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1060 return -ENOMEM;
1061 }
1062
1063 spin_lock_init(&dev->irqlock);
1064 spin_lock_init(&dev->condlock);
1065 dev->plat_dev = pdev;
1066 if (!dev->plat_dev) {
1067 dev_err(&pdev->dev, "No platform data specified\n");
d310f478 1068 return -ENODEV;
af935746
KD		 1069 }
1070
b27a23be 1071 dev->variant = mfc_get_drv_data(pdev);
8f532a7f 1072
af935746
KD		 1073 ret = s5p_mfc_init_pm(dev);
1074 if (ret < 0) {
1075 dev_err(&pdev->dev, "failed to get mfc clock source\n");
d310f478 1076 return ret;
af935746
KD		 1077 }
1078
1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af935746 1080
f23999ec
TR		 1081 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1082 if (IS_ERR(dev->regs_base))
1083 return PTR_ERR(dev->regs_base);
af935746
KD		 1084
1085 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1086 if (res == NULL) {
1087 dev_err(&pdev->dev, "failed to get irq resource\n");
1088 ret = -ENOENT;
d310f478 1089 goto err_res;
af935746
KD		 1090 }
1091 dev->irq = res->start;
d310f478 1092 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1957f0d7 1093 0, pdev->name, dev);
af935746
KD		 1094 if (ret) {
1095 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
d310f478 1096 goto err_res;
af935746
KD		 1097 }
1098
b27a23be 1099 if (pdev->dev.of_node) {
d68b44e0
WY		 1100 ret = s5p_mfc_alloc_memdevs(dev);
1101 if (ret < 0)
b27a23be 1102 goto err_res;
b27a23be
AK		 1103 } else {
1104 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1105 "s5p-mfc-l", match_child);
1106 if (!dev->mem_dev_l) {
1107 mfc_err("Mem child (L) device get failed\n");
1108 ret = -ENODEV;
1109 goto err_res;
1110 }
1111 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1112 "s5p-mfc-r", match_child);
1113 if (!dev->mem_dev_r) {
1114 mfc_err("Mem child (R) device get failed\n");
1115 ret = -ENODEV;
1116 goto err_res;
1117 }
af935746
KD		 1118 }
1119
1120 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
ef89fff8 1121 if (IS_ERR(dev->alloc_ctx[0])) {
af935746 1122 ret = PTR_ERR(dev->alloc_ctx[0]);
d310f478 1123 goto err_res;
af935746
KD		 1124 }
1125 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
ef89fff8 1126 if (IS_ERR(dev->alloc_ctx[1])) {
af935746
KD		 1127 ret = PTR_ERR(dev->alloc_ctx[1]);
1128 goto err_mem_init_ctx_1;
1129 }
1130
1131 mutex_init(&dev->mfc_mutex);
1132
2e731e44
KD		 1133 ret = s5p_mfc_alloc_firmware(dev);
1134 if (ret)
1135 goto err_alloc_fw;
1136
af935746
KD		 1137 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1138 if (ret)
1139 goto err_v4l2_dev_reg;
1140 init_waitqueue_head(&dev->queue);
1141
1142 /* decoder */
1143 vfd = video_device_alloc();
1144 if (!vfd) {
1145 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1146 ret = -ENOMEM;
1147 goto err_dec_alloc;
1148 }
d0ce898c 1149 vfd->fops = &s5p_mfc_fops;
af935746 1150 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
d0ce898c 1151 vfd->release = video_device_release;
af935746
KD		 1152 vfd->lock = &dev->mfc_mutex;
1153 vfd->v4l2_dev = &dev->v4l2_dev;
954f340f 1154 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1155 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1156 dev->vfd_dec = vfd;
1157 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1158 if (ret) {
1159 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1160 video_device_release(vfd);
1161 goto err_dec_reg;
1162 }
1163 v4l2_info(&dev->v4l2_dev,
1164 "decoder registered as /dev/video%d\n", vfd->num);
1165 video_set_drvdata(vfd, dev);
1166
1167 /* encoder */
1168 vfd = video_device_alloc();
1169 if (!vfd) {
1170 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1171 ret = -ENOMEM;
1172 goto err_enc_alloc;
1173 }
d0ce898c 1174 vfd->fops = &s5p_mfc_fops;
af935746 1175 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
d0ce898c 1176 vfd->release = video_device_release;
af935746
KD		 1177 vfd->lock = &dev->mfc_mutex;
1178 vfd->v4l2_dev = &dev->v4l2_dev;
cdcf45e7 1179 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1180 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1181 dev->vfd_enc = vfd;
1182 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1183 if (ret) {
1184 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1185 video_device_release(vfd);
1186 goto err_enc_reg;
1187 }
1188 v4l2_info(&dev->v4l2_dev,
1189 "encoder registered as /dev/video%d\n", vfd->num);
1190 video_set_drvdata(vfd, dev);
1191 platform_set_drvdata(pdev, dev);
1192
1193 dev->hw_lock = 0;
1194 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1195 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1196 atomic_set(&dev->watchdog_cnt, 0);
1197 init_timer(&dev->watchdog_timer);
1198 dev->watchdog_timer.data = (unsigned long)dev;
1199 dev->watchdog_timer.function = s5p_mfc_watchdog;
1200
43a1ea1f
AK		 1201 /* Initialize HW ops and commands based on MFC version */
1202 s5p_mfc_init_hw_ops(dev);
1203 s5p_mfc_init_hw_cmds(dev);
6a9c6f68 1204 s5p_mfc_init_regs(dev);
43a1ea1f 1205
af935746
KD		 1206 pr_debug("%s--\n", __func__);
1207 return 0;
1208
1209/* Deinit MFC if probe had failed */
1210err_enc_reg:
1211 video_device_release(dev->vfd_enc);
1212err_enc_alloc:
1213 video_unregister_device(dev->vfd_dec);
1214err_dec_reg:
1215 video_device_release(dev->vfd_dec);
1216err_dec_alloc:
1217 v4l2_device_unregister(&dev->v4l2_dev);
1218err_v4l2_dev_reg:
2e731e44
KD		 1219 s5p_mfc_release_firmware(dev);
1220err_alloc_fw:
af935746
KD		 1221 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1222err_mem_init_ctx_1:
1223 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
af935746
KD		 1224err_res:
1225 s5p_mfc_final_pm(dev);
d310f478 1226
af935746
KD		 1227 pr_debug("%s-- with error\n", __func__);
1228 return ret;
1229
1230}
1231
1232/* Remove the driver */
4c62e976 1233static int s5p_mfc_remove(struct platform_device *pdev)
af935746
KD		 1234{
1235 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1236
1237 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1238
1239 del_timer_sync(&dev->watchdog_timer);
1240 flush_workqueue(dev->watchdog_workqueue);
1241 destroy_workqueue(dev->watchdog_workqueue);
1242
1243 video_unregister_device(dev->vfd_enc);
1244 video_unregister_device(dev->vfd_dec);
1245 v4l2_device_unregister(&dev->v4l2_dev);
2e731e44 1246 s5p_mfc_release_firmware(dev);
af935746
KD		 1247 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1248 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
6e83e6e2
AK		 1249 if (pdev->dev.of_node) {
1250 put_device(dev->mem_dev_l);
1251 put_device(dev->mem_dev_r);
1252 }
af935746 1253
af935746 1254 s5p_mfc_final_pm(dev);
af935746
KD		 1255 return 0;
1256}
1257
1258#ifdef CONFIG_PM_SLEEP
1259
1260static int s5p_mfc_suspend(struct device *dev)
1261{
1262 struct platform_device *pdev = to_platform_device(dev);
1263 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1264 int ret;
1265
1266 if (m_dev->num_inst == 0)
1267 return 0;
81c9bcfb 1268
af935746
KD		 1269 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1270 mfc_err("Error: going to suspend for a second time\n");
1271 return -EIO;
1272 }
1273
1274 /* Check if we're processing then wait if it necessary. */
1275 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1276 /* Try and lock the HW */
1277 /* Wait on the interrupt waitqueue */
1278 ret = wait_event_interruptible_timeout(m_dev->queue,
76a4ddbd 1279 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
af935746
KD		 1280 if (ret == 0) {
1281 mfc_err("Waiting for hardware to finish timed out\n");
1282 return -EIO;
1283 }
1284 }
81c9bcfb
SK		 1285
1286 return s5p_mfc_sleep(m_dev);
af935746
KD		 1287}
1288
1289static int s5p_mfc_resume(struct device *dev)
1290{
1291 struct platform_device *pdev = to_platform_device(dev);
1292 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1293
1294 if (m_dev->num_inst == 0)
1295 return 0;
1296 return s5p_mfc_wakeup(m_dev);
1297}
1298#endif
1299
1300#ifdef CONFIG_PM_RUNTIME
1301static int s5p_mfc_runtime_suspend(struct device *dev)
1302{
1303 struct platform_device *pdev = to_platform_device(dev);
1304 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1305
1306 atomic_set(&m_dev->pm.power, 0);
1307 return 0;
1308}
1309
1310static int s5p_mfc_runtime_resume(struct device *dev)
1311{
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1314 int pre_power;
1315
1316 if (!m_dev->alloc_ctx)
1317 return 0;
1318 pre_power = atomic_read(&m_dev->pm.power);
1319 atomic_set(&m_dev->pm.power, 1);
1320 return 0;
1321}
1322#endif
1323
1324/* Power management */
1325static const struct dev_pm_ops s5p_mfc_pm_ops = {
1326 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1327 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1328 NULL)
1329};
1330
8f532a7f
AK		 1331struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1332 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1333 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1334 .dsc = DESC_BUF_SIZE,
1335 .shm = SHARED_BUF_SIZE,
1336};
1337
1338struct s5p_mfc_buf_size buf_size_v5 = {
1339 .fw = MAX_FW_SIZE,
1340 .cpb = MAX_CPB_SIZE,
1341 .priv = &mfc_buf_size_v5,
1342};
1343
1344struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1345 .base = MFC_BASE_ALIGN_ORDER,
1346};
1347
1348static struct s5p_mfc_variant mfc_drvdata_v5 = {
1349 .version = MFC_VERSION,
9aa5f008 1350 .version_bit = MFC_V5_BIT,
8f532a7f
AK		 1351 .port_num = MFC_NUM_PORTS,
1352 .buf_size = &buf_size_v5,
1353 .buf_align = &mfc_buf_align_v5,
f96f3cfa
JP		 1354 .fw_name = "s5p-mfc.fw",
1355};
1356
1357struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1358 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1359 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1360 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1361 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1362 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1363};
1364
1365struct s5p_mfc_buf_size buf_size_v6 = {
1366 .fw = MAX_FW_SIZE_V6,
1367 .cpb = MAX_CPB_SIZE_V6,
1368 .priv = &mfc_buf_size_v6,
1369};
1370
1371struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1372 .base = 0,
1373};
1374
1375static struct s5p_mfc_variant mfc_drvdata_v6 = {
1376 .version = MFC_VERSION_V6,
9aa5f008 1377 .version_bit = MFC_V6_BIT,
f96f3cfa
JP		 1378 .port_num = MFC_NUM_PORTS_V6,
1379 .buf_size = &buf_size_v6,
1380 .buf_align = &mfc_buf_align_v6,
f96f3cfa 1381 .fw_name = "s5p-mfc-v6.fw",
8f532a7f
AK		 1382};
1383
5441e9da
AK		 1384struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1385 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1386 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1387 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1388 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1389 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1390};
1391
1392struct s5p_mfc_buf_size buf_size_v7 = {
1393 .fw = MAX_FW_SIZE_V7,
1394 .cpb = MAX_CPB_SIZE_V7,
1395 .priv = &mfc_buf_size_v7,
1396};
1397
1398struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1399 .base = 0,
1400};
1401
1402static struct s5p_mfc_variant mfc_drvdata_v7 = {
1403 .version = MFC_VERSION_V7,
9aa5f008 1404 .version_bit = MFC_V7_BIT,
5441e9da
AK		 1405 .port_num = MFC_NUM_PORTS_V7,
1406 .buf_size = &buf_size_v7,
1407 .buf_align = &mfc_buf_align_v7,
1408 .fw_name = "s5p-mfc-v7.fw",
1409};
1410
e2b9deb2
KA		 1411struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1412 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1413 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1414 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
3e594ce7
KA		 1415 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1416 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
e2b9deb2
KA		 1417};
1418
1419struct s5p_mfc_buf_size buf_size_v8 = {
1420 .fw = MAX_FW_SIZE_V8,
1421 .cpb = MAX_CPB_SIZE_V8,
1422 .priv = &mfc_buf_size_v8,
1423};
1424
1425struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1426 .base = 0,
1427};
1428
1429static struct s5p_mfc_variant mfc_drvdata_v8 = {
1430 .version = MFC_VERSION_V8,
1431 .version_bit = MFC_V8_BIT,
1432 .port_num = MFC_NUM_PORTS_V8,
1433 .buf_size = &buf_size_v8,
1434 .buf_align = &mfc_buf_align_v8,
1435 .fw_name = "s5p-mfc-v8.fw",
1436};
1437
8f532a7f
AK		 1438static struct platform_device_id mfc_driver_ids[] = {
1439 {
1440 .name = "s5p-mfc",
1441 .driver_data = (unsigned long)&mfc_drvdata_v5,
f96f3cfa
JP		 1442 }, {
1443 .name = "s5p-mfc-v5",
1444 .driver_data = (unsigned long)&mfc_drvdata_v5,
1445 }, {
1446 .name = "s5p-mfc-v6",
1447 .driver_data = (unsigned long)&mfc_drvdata_v6,
5441e9da
AK		 1448 }, {
1449 .name = "s5p-mfc-v7",
1450 .driver_data = (unsigned long)&mfc_drvdata_v7,
e2b9deb2
KA		 1451 }, {
1452 .name = "s5p-mfc-v8",
1453 .driver_data = (unsigned long)&mfc_drvdata_v8,
8f532a7f
AK		 1454 },
1455 {},
1456};
1457MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1458
b27a23be
AK		 1459static const struct of_device_id exynos_mfc_match[] = {
1460 {
1461 .compatible = "samsung,mfc-v5",
1462 .data = &mfc_drvdata_v5,
1463 }, {
1464 .compatible = "samsung,mfc-v6",
1465 .data = &mfc_drvdata_v6,
5441e9da
AK		 1466 }, {
1467 .compatible = "samsung,mfc-v7",
1468 .data = &mfc_drvdata_v7,
e2b9deb2
KA		 1469 }, {
1470 .compatible = "samsung,mfc-v8",
1471 .data = &mfc_drvdata_v8,
b27a23be
AK		 1472 },
1473 {},
1474};
1475MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1476
1477static void *mfc_get_drv_data(struct platform_device *pdev)
1478{
1479 struct s5p_mfc_variant *driver_data = NULL;
1480
1481 if (pdev->dev.of_node) {
1482 const struct of_device_id *match;
a40a1382 1483 match = of_match_node(exynos_mfc_match,
b27a23be
AK		 1484 pdev->dev.of_node);
1485 if (match)
1486 driver_data = (struct s5p_mfc_variant *)match->data;
1487 } else {
1488 driver_data = (struct s5p_mfc_variant *)
1489 platform_get_device_id(pdev)->driver_data;
1490 }
1491 return driver_data;
1492}
1493
1e393e90 1494static struct platform_driver s5p_mfc_driver = {
8f532a7f 1495 .probe = s5p_mfc_probe,
4c62e976 1496 .remove = s5p_mfc_remove,
8f532a7f 1497 .id_table = mfc_driver_ids,
af935746
KD		 1498 .driver = {
1499 .name = S5P_MFC_NAME,
1500 .owner = THIS_MODULE,
b27a23be
AK		 1501 .pm = &s5p_mfc_pm_ops,
1502 .of_match_table = exynos_mfc_match,
af935746
KD		 1503 },
1504};
1505
1d6629b1 1506module_platform_driver(s5p_mfc_driver);
af935746
KD		 1507
1508MODULE_LICENSE("GPL");
1509MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1510MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1511
Linux kernel - Deliverables
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