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[media] media: s5p-mfc: use vb2_ops_wait_prepare/finish helper
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
af935746 21#include <linux/videodev2.h>
f9f715a9 22#include <media/v4l2-event.h>
af935746 23#include <linux/workqueue.h>
b27a23be 24#include <linux/of.h>
af935746 25#include <media/videobuf2-core.h>
43a1ea1f 26#include "s5p_mfc_common.h"
af935746
KD		 27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
af935746 34#include "s5p_mfc_pm.h"
af935746
KD		 35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
139adba6
MCC		 40int mfc_debug_level;
41module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
af935746
KD		 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44/* Helper functions for interrupt processing */
7fb89eca 45
af935746 46/* Remove from hw execution round robin */
7fb89eca 47void clear_work_bit(struct s5p_mfc_ctx *ctx)
af935746
KD		 48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
7fb89eca 52 __clear_bit(ctx->num, &dev->ctx_work_bits);
af935746
KD		 53 spin_unlock(&dev->condlock);
54}
55
7fb89eca
AH		 56/* Add to hw execution round robin */
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66/* Remove from hw execution round robin */
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77/* Add to hw execution round robin */
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
af935746
KD		 88/* Wake up context wait_queue */
89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91{
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96}
97
98/* Wake up device wait_queue */
99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101{
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106}
107
a13bba4f 108static void s5p_mfc_watchdog(unsigned long arg)
af935746
KD		 109{
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126}
127
128static void s5p_mfc_watchdog_worker(struct work_struct *work)
129{
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
e2c3be2a
KD		 153 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
154 &ctx->dst_queue, &ctx->vq_dst);
155 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
156 &ctx->src_queue, &ctx->vq_src);
af935746 157 clear_work_bit(ctx);
43a1ea1f 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
af935746
KD		 159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
b16e6448
AM		 162
163 /* De-init MFC */
164 s5p_mfc_deinit_hw(dev);
165
af935746
KD		 166 /* Double check if there is at least one instance running.
167 * If no instance is in memory than no firmware should be present */
168 if (dev->num_inst > 0) {
46075006 169 ret = s5p_mfc_load_firmware(dev);
af935746
KD		 170 if (ret) {
171 mfc_err("Failed to reload FW\n");
172 goto unlock;
173 }
174 s5p_mfc_clock_on();
175 ret = s5p_mfc_init_hw(dev);
176 if (ret)
177 mfc_err("Failed to reinit FW\n");
178 }
179unlock:
180 if (mutex_locked)
181 mutex_unlock(&dev->mfc_mutex);
182}
183
af935746
KD		 184static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
185{
186 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
187 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
188 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
189}
190
191static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
192{
193 struct s5p_mfc_buf *dst_buf;
43a1ea1f 194 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 195
196 ctx->state = MFCINST_FINISHED;
197 ctx->sequence++;
198 while (!list_empty(&ctx->dst_queue)) {
199 dst_buf = list_entry(ctx->dst_queue.next,
200 struct s5p_mfc_buf, list);
201 mfc_debug(2, "Cleaning up buffer: %d\n",
202 dst_buf->b->v4l2_buf.index);
203 vb2_set_plane_payload(dst_buf->b, 0, 0);
204 vb2_set_plane_payload(dst_buf->b, 1, 0);
205 list_del(&dst_buf->list);
206 ctx->dst_queue_cnt--;
207 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
208
43a1ea1f
AK		 209 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
210 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
af935746
KD		 211 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
212 else
213 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
214
215 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
216 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
217 }
218}
219
220static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
221{
222 struct s5p_mfc_dev *dev = ctx->dev;
223 struct s5p_mfc_buf *dst_buf, *src_buf;
43a1ea1f
AK		 224 size_t dec_y_addr;
225 unsigned int frame_type;
226
bb21c54a 227 /* Make sure we actually have a new frame before continuing. */
43a1ea1f 228 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
bb21c54a
IF		 229 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
230 return;
231 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
af935746
KD		 232
233 /* Copy timestamp / timecode from decoded src to dst and set
bb21c54a 234 appropriate flags. */
af935746
KD		 235 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
236 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
ba7fcb0c 237 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
56006017
KD		 238 dst_buf->b->v4l2_buf.timecode =
239 src_buf->b->v4l2_buf.timecode;
240 dst_buf->b->v4l2_buf.timestamp =
241 src_buf->b->v4l2_buf.timestamp;
309f4d62
SA		 242 dst_buf->b->v4l2_buf.flags &=
243 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
244 dst_buf->b->v4l2_buf.flags |=
245 src_buf->b->v4l2_buf.flags
246 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
af935746
KD		 247 switch (frame_type) {
248 case S5P_FIMV_DECODE_FRAME_I_FRAME:
249 dst_buf->b->v4l2_buf.flags |=
250 V4L2_BUF_FLAG_KEYFRAME;
251 break;
252 case S5P_FIMV_DECODE_FRAME_P_FRAME:
253 dst_buf->b->v4l2_buf.flags |=
254 V4L2_BUF_FLAG_PFRAME;
255 break;
256 case S5P_FIMV_DECODE_FRAME_B_FRAME:
257 dst_buf->b->v4l2_buf.flags |=
258 V4L2_BUF_FLAG_BFRAME;
259 break;
bb21c54a
IF		 260 default:
261 /* Don't know how to handle
262 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
263 mfc_debug(2, "Unexpected frame type: %d\n",
264 frame_type);
af935746
KD		 265 }
266 break;
267 }
268 }
269}
270
271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
272{
273 struct s5p_mfc_dev *dev = ctx->dev;
274 struct s5p_mfc_buf *dst_buf;
43a1ea1f
AK		 275 size_t dspl_y_addr;
276 unsigned int frame_type;
af935746 277
43a1ea1f 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
7c672812
SS		 279 if (IS_MFCV6_PLUS(dev))
280 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
281 get_disp_frame_type, ctx);
282 else
283 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
284 get_dec_frame_type, dev);
43a1ea1f 285
af935746
KD		 286 /* If frame is same as previous then skip and do not dequeue */
287 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
288 if (!ctx->after_packed_pb)
289 ctx->sequence++;
290 ctx->after_packed_pb = 0;
291 return;
292 }
293 ctx->sequence++;
294 /* The MFC returns address of the buffer, now we have to
295 * check which videobuf does it correspond to */
296 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
297 /* Check if this is the buffer we're looking for */
ba7fcb0c 298 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
af935746
KD		 299 list_del(&dst_buf->list);
300 ctx->dst_queue_cnt--;
301 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
43a1ea1f
AK		 302 if (s5p_mfc_hw_call(dev->mfc_ops,
303 get_pic_type_top, ctx) ==
304 s5p_mfc_hw_call(dev->mfc_ops,
305 get_pic_type_bot, ctx))
af935746
KD		 306 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
307 else
308 dst_buf->b->v4l2_buf.field =
309 V4L2_FIELD_INTERLACED;
310 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
311 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
312 clear_bit(dst_buf->b->v4l2_buf.index,
313 &ctx->dec_dst_flag);
314
315 vb2_buffer_done(dst_buf->b,
316 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
317
af935746
KD		 318 break;
319 }
320 }
321}
322
323/* Handle frame decoding interrupt */
324static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
325 unsigned int reason, unsigned int err)
326{
327 struct s5p_mfc_dev *dev = ctx->dev;
328 unsigned int dst_frame_status;
a0517f5d 329 unsigned int dec_frame_status;
af935746
KD		 330 struct s5p_mfc_buf *src_buf;
331 unsigned long flags;
332 unsigned int res_change;
333
43a1ea1f 334 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
af935746 335 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
a0517f5d
PO		 336 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
337 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
f96f3cfa
JP		 338 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
339 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
340 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
af935746
KD		 341 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
342 if (ctx->state == MFCINST_RES_CHANGE_INIT)
343 ctx->state = MFCINST_RES_CHANGE_FLUSH;
f96f3cfa
JP		 344 if (res_change == S5P_FIMV_RES_INCREASE ||
345 res_change == S5P_FIMV_RES_DECREASE) {
af935746 346 ctx->state = MFCINST_RES_CHANGE_INIT;
e2c3be2a 347 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 348 wake_up_ctx(ctx, reason, err);
9a7bc6b0 349 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 350 s5p_mfc_clock_off();
e2c3be2a 351 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD		 352 return;
353 }
354 if (ctx->dpb_flush_flag)
355 ctx->dpb_flush_flag = 0;
356
357 spin_lock_irqsave(&dev->irqlock, flags);
358 /* All frames remaining in the buffer have been extracted */
359 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
360 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
0520e4cc
PO		 361 static const struct v4l2_event ev_src_ch = {
362 .type = V4L2_EVENT_SOURCE_CHANGE,
363 .u.src_change.changes =
364 V4L2_EVENT_SRC_CH_RESOLUTION,
365 };
366
af935746
KD		 367 s5p_mfc_handle_frame_all_extracted(ctx);
368 ctx->state = MFCINST_RES_CHANGE_END;
0520e4cc
PO		 369 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
370
af935746
KD		 371 goto leave_handle_frame;
372 } else {
373 s5p_mfc_handle_frame_all_extracted(ctx);
374 }
375 }
376
a0517f5d 377 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
af935746
KD		 378 s5p_mfc_handle_frame_copy_time(ctx);
379
380 /* A frame has been decoded and is in the buffer */
381 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
382 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
383 s5p_mfc_handle_frame_new(ctx, err);
384 } else {
385 mfc_debug(2, "No frame decode\n");
386 }
387 /* Mark source buffer as complete */
388 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
389 && !list_empty(&ctx->src_queue)) {
390 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
391 list);
43a1ea1f
AK		 392 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
393 get_consumed_stream, dev);
394 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
f49f3ed5 395 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
d2a0db1e
AK		 396 ctx->consumed_stream + STUFF_BYTE <
397 src_buf->b->v4l2_planes[0].bytesused) {
af935746
KD		 398 /* Run MFC again on the same buffer */
399 mfc_debug(2, "Running again the same buffer\n");
400 ctx->after_packed_pb = 1;
401 } else {
af935746
KD		 402 mfc_debug(2, "MFC needs next buffer\n");
403 ctx->consumed_stream = 0;
a34026e7
KD		 404 if (src_buf->flags & MFC_BUF_FLAG_EOS)
405 ctx->state = MFCINST_FINISHING;
af935746
KD		 406 list_del(&src_buf->list);
407 ctx->src_queue_cnt--;
43a1ea1f 408 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
af935746
KD		 409 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
410 else
411 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
412 }
413 }
414leave_handle_frame:
415 spin_unlock_irqrestore(&dev->irqlock, flags);
416 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
e9d98ddc 417 || ctx->dst_queue_cnt < ctx->pb_count)
af935746 418 clear_work_bit(ctx);
e2c3be2a 419 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 420 wake_up_ctx(ctx, reason, err);
9a7bc6b0 421 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 422 s5p_mfc_clock_off();
76a4ddbd
P		 423 /* if suspending, wake up device and do not try_run again*/
424 if (test_bit(0, &dev->enter_suspend))
425 wake_up_dev(dev, reason, err);
426 else
e2c3be2a 427 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD		 428}
429
430/* Error handling for interrupt */
7296e25f
KD		 431static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
432 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
af935746 433{
af935746
KD		 434 unsigned long flags;
435
af935746 436 mfc_err("Interrupt Error: %08x\n", err);
af935746 437
7296e25f
KD		 438 if (ctx != NULL) {
439 /* Error recovery is dependent on the state of context */
440 switch (ctx->state) {
441 case MFCINST_RES_CHANGE_INIT:
442 case MFCINST_RES_CHANGE_FLUSH:
443 case MFCINST_RES_CHANGE_END:
444 case MFCINST_FINISHING:
445 case MFCINST_FINISHED:
446 case MFCINST_RUNNING:
39c1cb2b 447 /* It is highly probable that an error occurred
7296e25f
KD		 448 * while decoding a frame */
449 clear_work_bit(ctx);
450 ctx->state = MFCINST_ERROR;
451 /* Mark all dst buffers as having an error */
452 spin_lock_irqsave(&dev->irqlock, flags);
e2c3be2a 453 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
7296e25f
KD		 454 &ctx->dst_queue, &ctx->vq_dst);
455 /* Mark all src buffers as having an error */
e2c3be2a 456 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
7296e25f
KD		 457 &ctx->src_queue, &ctx->vq_src);
458 spin_unlock_irqrestore(&dev->irqlock, flags);
459 wake_up_ctx(ctx, reason, err);
460 break;
461 default:
462 clear_work_bit(ctx);
463 ctx->state = MFCINST_ERROR;
464 wake_up_ctx(ctx, reason, err);
465 break;
466 }
af935746 467 }
9a7bc6b0 468 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
e2c3be2a 469 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
7296e25f
KD		 470 s5p_mfc_clock_off();
471 wake_up_dev(dev, reason, err);
af935746
KD		 472 return;
473}
474
475/* Header parsing interrupt handling */
476static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
477 unsigned int reason, unsigned int err)
478{
479 struct s5p_mfc_dev *dev;
af935746 480
1259762f 481 if (ctx == NULL)
af935746
KD		 482 return;
483 dev = ctx->dev;
484 if (ctx->c_ops->post_seq_start) {
485 if (ctx->c_ops->post_seq_start(ctx))
486 mfc_err("post_seq_start() failed\n");
487 } else {
43a1ea1f
AK		 488 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
489 dev);
490 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
491 dev);
af935746 492
e2c3be2a 493 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
8f532a7f 494
e9d98ddc 495 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
43a1ea1f 496 dev);
f96f3cfa
JP		 497 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
498 dev);
bb869368 499 if (ctx->img_width == 0 || ctx->img_height == 0)
af935746
KD		 500 ctx->state = MFCINST_ERROR;
501 else
502 ctx->state = MFCINST_HEAD_PARSED;
f96f3cfa
JP		 503
504 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
505 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
506 !list_empty(&ctx->src_queue)) {
507 struct s5p_mfc_buf *src_buf;
508 src_buf = list_entry(ctx->src_queue.next,
509 struct s5p_mfc_buf, list);
510 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
511 dev) <
512 src_buf->b->v4l2_planes[0].bytesused)
513 ctx->head_processed = 0;
514 else
515 ctx->head_processed = 1;
516 } else {
517 ctx->head_processed = 1;
518 }
af935746 519 }
e2c3be2a 520 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 521 clear_work_bit(ctx);
9a7bc6b0 522 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 523 s5p_mfc_clock_off();
e2c3be2a 524 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD		 525 wake_up_ctx(ctx, reason, err);
526}
527
528/* Header parsing interrupt handling */
529static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
530 unsigned int reason, unsigned int err)
531{
532 struct s5p_mfc_buf *src_buf;
533 struct s5p_mfc_dev *dev;
534 unsigned long flags;
535
1259762f 536 if (ctx == NULL)
af935746
KD		 537 return;
538 dev = ctx->dev;
e2c3be2a 539 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 540 ctx->int_type = reason;
541 ctx->int_err = err;
542 ctx->int_cond = 1;
7fb89eca 543 clear_work_bit(ctx);
af935746
KD		 544 if (err == 0) {
545 ctx->state = MFCINST_RUNNING;
f96f3cfa 546 if (!ctx->dpb_flush_flag && ctx->head_processed) {
af935746
KD		 547 spin_lock_irqsave(&dev->irqlock, flags);
548 if (!list_empty(&ctx->src_queue)) {
549 src_buf = list_entry(ctx->src_queue.next,
550 struct s5p_mfc_buf, list);
551 list_del(&src_buf->list);
552 ctx->src_queue_cnt--;
553 vb2_buffer_done(src_buf->b,
554 VB2_BUF_STATE_DONE);
555 }
556 spin_unlock_irqrestore(&dev->irqlock, flags);
557 } else {
558 ctx->dpb_flush_flag = 0;
559 }
9a7bc6b0 560 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746
KD		 561
562 s5p_mfc_clock_off();
563
564 wake_up(&ctx->queue);
e2c3be2a 565 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746 566 } else {
9a7bc6b0 567 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746
KD		 568
569 s5p_mfc_clock_off();
570
571 wake_up(&ctx->queue);
572 }
573}
574
f9f715a9
AH		 575static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
576 unsigned int reason, unsigned int err)
577{
578 struct s5p_mfc_dev *dev = ctx->dev;
579 struct s5p_mfc_buf *mb_entry;
580
4130eabc 581 mfc_debug(2, "Stream completed\n");
f9f715a9
AH		 582
583 s5p_mfc_clear_int_flags(dev);
584 ctx->int_type = reason;
585 ctx->int_err = err;
586 ctx->state = MFCINST_FINISHED;
587
588 spin_lock(&dev->irqlock);
589 if (!list_empty(&ctx->dst_queue)) {
590 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
591 list);
592 list_del(&mb_entry->list);
593 ctx->dst_queue_cnt--;
594 vb2_set_plane_payload(mb_entry->b, 0, 0);
595 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
596 }
597 spin_unlock(&dev->irqlock);
598
599 clear_work_bit(ctx);
600
e8256447 601 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
f9f715a9
AH		 602
603 s5p_mfc_clock_off();
604 wake_up(&ctx->queue);
e2c3be2a 605 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
f9f715a9
AH		 606}
607
af935746
KD		 608/* Interrupt processing */
609static irqreturn_t s5p_mfc_irq(int irq, void *priv)
610{
611 struct s5p_mfc_dev *dev = priv;
612 struct s5p_mfc_ctx *ctx;
613 unsigned int reason;
614 unsigned int err;
615
616 mfc_debug_enter();
617 /* Reset the timeout watchdog */
618 atomic_set(&dev->watchdog_cnt, 0);
619 ctx = dev->ctx[dev->curr_ctx];
620 /* Get the reason of interrupt and the error code */
43a1ea1f
AK		 621 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
622 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
af935746
KD		 623 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
624 switch (reason) {
43a1ea1f 625 case S5P_MFC_R2H_CMD_ERR_RET:
39c1cb2b 626 /* An error has occurred */
af935746 627 if (ctx->state == MFCINST_RUNNING &&
43a1ea1f
AK		 628 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
629 dev->warn_start)
af935746
KD		 630 s5p_mfc_handle_frame(ctx, reason, err);
631 else
7296e25f 632 s5p_mfc_handle_error(dev, ctx, reason, err);
af935746
KD		 633 clear_bit(0, &dev->enter_suspend);
634 break;
635
43a1ea1f
AK		 636 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
637 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
638 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
af935746
KD		 639 if (ctx->c_ops->post_frame_start) {
640 if (ctx->c_ops->post_frame_start(ctx))
641 mfc_err("post_frame_start() failed\n");
e2c3be2a 642 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746 643 wake_up_ctx(ctx, reason, err);
9a7bc6b0 644 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
af935746 645 s5p_mfc_clock_off();
e2c3be2a 646 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD		 647 } else {
648 s5p_mfc_handle_frame(ctx, reason, err);
649 }
650 break;
651
43a1ea1f 652 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
af935746
KD		 653 s5p_mfc_handle_seq_done(ctx, reason, err);
654 break;
655
43a1ea1f
AK		 656 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
657 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
af935746
KD		 658 ctx->state = MFCINST_GOT_INST;
659 clear_work_bit(ctx);
660 wake_up(&ctx->queue);
661 goto irq_cleanup_hw;
662
43a1ea1f 663 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
af935746 664 clear_work_bit(ctx);
9d87e837 665 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD		 666 ctx->state = MFCINST_FREE;
667 wake_up(&ctx->queue);
668 goto irq_cleanup_hw;
669
43a1ea1f
AK		 670 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
671 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
672 case S5P_MFC_R2H_CMD_SLEEP_RET:
673 case S5P_MFC_R2H_CMD_WAKEUP_RET:
af935746
KD		 674 if (ctx)
675 clear_work_bit(ctx);
e2c3be2a 676 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 677 wake_up_dev(dev, reason, err);
678 clear_bit(0, &dev->hw_lock);
679 clear_bit(0, &dev->enter_suspend);
680 break;
681
43a1ea1f 682 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
af935746
KD		 683 s5p_mfc_handle_init_buffers(ctx, reason, err);
684 break;
f9f715a9 685
43a1ea1f 686 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
f9f715a9
AH		 687 s5p_mfc_handle_stream_complete(ctx, reason, err);
688 break;
689
8f23cc02
AK		 690 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
691 clear_work_bit(ctx);
692 ctx->state = MFCINST_RUNNING;
693 wake_up(&ctx->queue);
694 goto irq_cleanup_hw;
695
af935746
KD		 696 default:
697 mfc_debug(2, "Unknown int reason\n");
e2c3be2a 698 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 699 }
700 mfc_debug_leave();
701 return IRQ_HANDLED;
702irq_cleanup_hw:
e2c3be2a 703 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 704 ctx->int_type = reason;
705 ctx->int_err = err;
706 ctx->int_cond = 1;
707 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
708 mfc_err("Failed to unlock hw\n");
709
710 s5p_mfc_clock_off();
711
e2c3be2a 712 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
af935746
KD		 713 mfc_debug(2, "Exit via irq_cleanup_hw\n");
714 return IRQ_HANDLED;
715}
716
717/* Open an MFC node */
718static int s5p_mfc_open(struct file *file)
719{
b80cb8dc 720 struct video_device *vdev = video_devdata(file);
af935746
KD		 721 struct s5p_mfc_dev *dev = video_drvdata(file);
722 struct s5p_mfc_ctx *ctx = NULL;
723 struct vb2_queue *q;
af935746
KD		 724 int ret = 0;
725
726 mfc_debug_enter();
bc738301
HV		 727 if (mutex_lock_interruptible(&dev->mfc_mutex))
728 return -ERESTARTSYS;
af935746
KD		 729 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
730 /* Allocate memory for context */
bae061b4 731 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
af935746
KD		 732 if (!ctx) {
733 mfc_err("Not enough memory\n");
734 ret = -ENOMEM;
735 goto err_alloc;
736 }
55647a99 737 v4l2_fh_init(&ctx->fh, vdev);
af935746
KD		 738 file->private_data = &ctx->fh;
739 v4l2_fh_add(&ctx->fh);
740 ctx->dev = dev;
741 INIT_LIST_HEAD(&ctx->src_queue);
742 INIT_LIST_HEAD(&ctx->dst_queue);
743 ctx->src_queue_cnt = 0;
744 ctx->dst_queue_cnt = 0;
745 /* Get context number */
746 ctx->num = 0;
747 while (dev->ctx[ctx->num]) {
748 ctx->num++;
749 if (ctx->num >= MFC_NUM_CONTEXTS) {
750 mfc_err("Too many open contexts\n");
751 ret = -EBUSY;
752 goto err_no_ctx;
753 }
754 }
755 /* Mark context as idle */
7fb89eca 756 clear_work_bit_irqsave(ctx);
af935746 757 dev->ctx[ctx->num] = ctx;
b80cb8dc 758 if (vdev == dev->vfd_dec) {
af935746
KD		 759 ctx->type = MFCINST_DECODER;
760 ctx->c_ops = get_dec_codec_ops();
43a1ea1f 761 s5p_mfc_dec_init(ctx);
af935746
KD		 762 /* Setup ctrl handler */
763 ret = s5p_mfc_dec_ctrls_setup(ctx);
764 if (ret) {
765 mfc_err("Failed to setup mfc controls\n");
766 goto err_ctrls_setup;
767 }
b80cb8dc 768 } else if (vdev == dev->vfd_enc) {
af935746
KD		 769 ctx->type = MFCINST_ENCODER;
770 ctx->c_ops = get_enc_codec_ops();
771 /* only for encoder */
772 INIT_LIST_HEAD(&ctx->ref_queue);
773 ctx->ref_queue_cnt = 0;
43a1ea1f 774 s5p_mfc_enc_init(ctx);
af935746
KD		 775 /* Setup ctrl handler */
776 ret = s5p_mfc_enc_ctrls_setup(ctx);
777 if (ret) {
778 mfc_err("Failed to setup mfc controls\n");
779 goto err_ctrls_setup;
780 }
781 } else {
782 ret = -ENOENT;
783 goto err_bad_node;
784 }
785 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
9d87e837 786 ctx->inst_no = MFC_NO_INSTANCE_SET;
af935746
KD		 787 /* Load firmware if this is the first instance */
788 if (dev->num_inst == 1) {
789 dev->watchdog_timer.expires = jiffies +
790 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
791 add_timer(&dev->watchdog_timer);
792 ret = s5p_mfc_power_on();
793 if (ret < 0) {
794 mfc_err("power on failed\n");
795 goto err_pwr_enable;
796 }
797 s5p_mfc_clock_on();
2e731e44
KD		 798 ret = s5p_mfc_load_firmware(dev);
799 if (ret) {
800 s5p_mfc_clock_off();
801 goto err_load_fw;
802 }
af935746
KD		 803 /* Init the FW */
804 ret = s5p_mfc_init_hw(dev);
2e731e44 805 s5p_mfc_clock_off();
af935746
KD		 806 if (ret)
807 goto err_init_hw;
af935746
KD		 808 }
809 /* Init videobuf2 queue for CAPTURE */
810 q = &ctx->vq_dst;
811 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
812 q->drv_priv = &ctx->fh;
654a731b 813 q->lock = &dev->mfc_mutex;
b80cb8dc 814 if (vdev == dev->vfd_dec) {
af935746
KD		 815 q->io_modes = VB2_MMAP;
816 q->ops = get_dec_queue_ops();
b80cb8dc 817 } else if (vdev == dev->vfd_enc) {
af935746
KD		 818 q->io_modes = VB2_MMAP | VB2_USERPTR;
819 q->ops = get_enc_queue_ops();
820 } else {
821 ret = -ENOENT;
822 goto err_queue_init;
823 }
749ae716 824 q->mem_ops = &vb2_dma_contig_memops;
ade48681 825 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 826 ret = vb2_queue_init(q);
827 if (ret) {
828 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
829 goto err_queue_init;
830 }
831 /* Init videobuf2 queue for OUTPUT */
832 q = &ctx->vq_src;
833 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
834 q->io_modes = VB2_MMAP;
835 q->drv_priv = &ctx->fh;
b80cb8dc 836 if (vdev == dev->vfd_dec) {
af935746
KD		 837 q->io_modes = VB2_MMAP;
838 q->ops = get_dec_queue_ops();
b80cb8dc 839 } else if (vdev == dev->vfd_enc) {
af935746
KD		 840 q->io_modes = VB2_MMAP | VB2_USERPTR;
841 q->ops = get_enc_queue_ops();
842 } else {
843 ret = -ENOENT;
844 goto err_queue_init;
845 }
749ae716 846 q->mem_ops = &vb2_dma_contig_memops;
ade48681 847 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 848 ret = vb2_queue_init(q);
849 if (ret) {
850 mfc_err("Failed to initialize videobuf2 queue(output)\n");
851 goto err_queue_init;
852 }
853 init_waitqueue_head(&ctx->queue);
bc738301 854 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 855 mfc_debug_leave();
856 return ret;
39c1cb2b 857 /* Deinit when failure occurred */
af935746 858err_queue_init:
2e731e44
KD		 859 if (dev->num_inst == 1)
860 s5p_mfc_deinit_hw(dev);
af935746 861err_init_hw:
2e731e44 862err_load_fw:
af935746
KD		 863err_pwr_enable:
864 if (dev->num_inst == 1) {
865 if (s5p_mfc_power_off() < 0)
866 mfc_err("power off failed\n");
1b73ba0b 867 del_timer_sync(&dev->watchdog_timer);
af935746
KD		 868 }
869err_ctrls_setup:
870 s5p_mfc_dec_ctrls_delete(ctx);
871err_bad_node:
1b73ba0b 872 dev->ctx[ctx->num] = NULL;
af935746
KD		 873err_no_ctx:
874 v4l2_fh_del(&ctx->fh);
875 v4l2_fh_exit(&ctx->fh);
876 kfree(ctx);
877err_alloc:
878 dev->num_inst--;
bc738301 879 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 880 mfc_debug_leave();
881 return ret;
882}
883
884/* Release MFC context */
885static int s5p_mfc_release(struct file *file)
886{
887 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
888 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 889
890 mfc_debug_enter();
bc738301 891 mutex_lock(&dev->mfc_mutex);
af935746
KD		 892 s5p_mfc_clock_on();
893 vb2_queue_release(&ctx->vq_src);
894 vb2_queue_release(&ctx->vq_dst);
895 /* Mark context as idle */
7fb89eca 896 clear_work_bit_irqsave(ctx);
9d87e837 897 /* If instance was initialised and not yet freed,
39c1cb2b 898 * return instance and free resources */
9d87e837 899 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
af935746 900 mfc_debug(2, "Has to free instance\n");
818cd91a 901 s5p_mfc_close_mfc_inst(dev, ctx);
af935746
KD		 902 }
903 /* hardware locking scheme */
904 if (dev->curr_ctx == ctx->num)
905 clear_bit(0, &dev->hw_lock);
906 dev->num_inst--;
907 if (dev->num_inst == 0) {
2e731e44 908 mfc_debug(2, "Last instance\n");
43a1ea1f 909 s5p_mfc_deinit_hw(dev);
af935746
KD		 910 del_timer_sync(&dev->watchdog_timer);
911 if (s5p_mfc_power_off() < 0)
912 mfc_err("Power off failed\n");
913 }
914 mfc_debug(2, "Shutting down clock\n");
915 s5p_mfc_clock_off();
1259762f 916 dev->ctx[ctx->num] = NULL;
af935746
KD		 917 s5p_mfc_dec_ctrls_delete(ctx);
918 v4l2_fh_del(&ctx->fh);
919 v4l2_fh_exit(&ctx->fh);
920 kfree(ctx);
921 mfc_debug_leave();
bc738301 922 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 923 return 0;
924}
925
926/* Poll */
927static unsigned int s5p_mfc_poll(struct file *file,
928 struct poll_table_struct *wait)
929{
930 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
931 struct s5p_mfc_dev *dev = ctx->dev;
932 struct vb2_queue *src_q, *dst_q;
933 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
934 unsigned int rc = 0;
935 unsigned long flags;
936
bc738301 937 mutex_lock(&dev->mfc_mutex);
af935746
KD		 938 src_q = &ctx->vq_src;
939 dst_q = &ctx->vq_dst;
940 /*
941 * There has to be at least one buffer queued on each queued_list, which
942 * means either in driver already or waiting for driver to claim it
943 * and start processing.
944 */
945 if ((!src_q->streaming || list_empty(&src_q->queued_list))
946 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
947 rc = POLLERR;
948 goto end;
949 }
950 mutex_unlock(&dev->mfc_mutex);
f9f715a9 951 poll_wait(file, &ctx->fh.wait, wait);
af935746
KD		 952 poll_wait(file, &src_q->done_wq, wait);
953 poll_wait(file, &dst_q->done_wq, wait);
954 mutex_lock(&dev->mfc_mutex);
f9f715a9
AH		 955 if (v4l2_event_pending(&ctx->fh))
956 rc |= POLLPRI;
af935746
KD		 957 spin_lock_irqsave(&src_q->done_lock, flags);
958 if (!list_empty(&src_q->done_list))
959 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
960 done_entry);
961 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
962 || src_vb->state == VB2_BUF_STATE_ERROR))
963 rc |= POLLOUT | POLLWRNORM;
964 spin_unlock_irqrestore(&src_q->done_lock, flags);
965 spin_lock_irqsave(&dst_q->done_lock, flags);
966 if (!list_empty(&dst_q->done_list))
967 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
968 done_entry);
969 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
970 || dst_vb->state == VB2_BUF_STATE_ERROR))
971 rc |= POLLIN | POLLRDNORM;
972 spin_unlock_irqrestore(&dst_q->done_lock, flags);
973end:
bc738301 974 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 975 return rc;
976}
977
978/* Mmap */
979static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
980{
981 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
bc738301 982 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 983 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
984 int ret;
bc738301
HV		 985
986 if (mutex_lock_interruptible(&dev->mfc_mutex))
987 return -ERESTARTSYS;
af935746
KD		 988 if (offset < DST_QUEUE_OFF_BASE) {
989 mfc_debug(2, "mmaping source\n");
990 ret = vb2_mmap(&ctx->vq_src, vma);
991 } else { /* capture */
992 mfc_debug(2, "mmaping destination\n");
993 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
994 ret = vb2_mmap(&ctx->vq_dst, vma);
995 }
bc738301 996 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 997 return ret;
998}
999
1000/* v4l2 ops */
1001static const struct v4l2_file_operations s5p_mfc_fops = {
1002 .owner = THIS_MODULE,
1003 .open = s5p_mfc_open,
1004 .release = s5p_mfc_release,
1005 .poll = s5p_mfc_poll,
1006 .unlocked_ioctl = video_ioctl2,
1007 .mmap = s5p_mfc_mmap,
1008};
1009
1010static int match_child(struct device *dev, void *data)
1011{
1012 if (!dev_name(dev))
1013 return 0;
1014 return !strcmp(dev_name(dev), (char *)data);
1015}
1016
b27a23be
AK		 1017static void *mfc_get_drv_data(struct platform_device *pdev);
1018
6e83e6e2
AK		 1019static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1020{
65fccab5 1021 unsigned int mem_info[2] = { };
6e83e6e2
AK		 1022
1023 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1024 sizeof(struct device), GFP_KERNEL);
1025 if (!dev->mem_dev_l) {
1026 mfc_err("Not enough memory\n");
1027 return -ENOMEM;
1028 }
1029 device_initialize(dev->mem_dev_l);
1030 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1031 "samsung,mfc-l", mem_info, 2);
1032 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1033 mem_info[0], mem_info[1],
1034 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1035 mfc_err("Failed to declare coherent memory for\n"
1036 "MFC device\n");
1037 return -ENOMEM;
1038 }
1039
1040 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1041 sizeof(struct device), GFP_KERNEL);
1042 if (!dev->mem_dev_r) {
1043 mfc_err("Not enough memory\n");
1044 return -ENOMEM;
1045 }
1046 device_initialize(dev->mem_dev_r);
1047 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1048 "samsung,mfc-r", mem_info, 2);
1049 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1050 mem_info[0], mem_info[1],
1051 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1052 pr_err("Failed to declare coherent memory for\n"
1053 "MFC device\n");
1054 return -ENOMEM;
1055 }
1056 return 0;
1057}
1058
af935746 1059/* MFC probe function */
1e393e90 1060static int s5p_mfc_probe(struct platform_device *pdev)
af935746
KD		 1061{
1062 struct s5p_mfc_dev *dev;
1063 struct video_device *vfd;
1064 struct resource *res;
1065 int ret;
1066
1067 pr_debug("%s++\n", __func__);
bae061b4 1068 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
af935746
KD		 1069 if (!dev) {
1070 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1071 return -ENOMEM;
1072 }
1073
1074 spin_lock_init(&dev->irqlock);
1075 spin_lock_init(&dev->condlock);
1076 dev->plat_dev = pdev;
1077 if (!dev->plat_dev) {
1078 dev_err(&pdev->dev, "No platform data specified\n");
d310f478 1079 return -ENODEV;
af935746
KD		 1080 }
1081
b27a23be 1082 dev->variant = mfc_get_drv_data(pdev);
8f532a7f 1083
af935746
KD		 1084 ret = s5p_mfc_init_pm(dev);
1085 if (ret < 0) {
1086 dev_err(&pdev->dev, "failed to get mfc clock source\n");
d310f478 1087 return ret;
af935746
KD		 1088 }
1089
1090 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af935746 1091
f23999ec
TR		 1092 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1093 if (IS_ERR(dev->regs_base))
1094 return PTR_ERR(dev->regs_base);
af935746
KD		 1095
1096 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1097 if (res == NULL) {
1098 dev_err(&pdev->dev, "failed to get irq resource\n");
1099 ret = -ENOENT;
d310f478 1100 goto err_res;
af935746
KD		 1101 }
1102 dev->irq = res->start;
d310f478 1103 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1957f0d7 1104 0, pdev->name, dev);
af935746
KD		 1105 if (ret) {
1106 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
d310f478 1107 goto err_res;
af935746
KD		 1108 }
1109
b27a23be 1110 if (pdev->dev.of_node) {
d68b44e0
WY		 1111 ret = s5p_mfc_alloc_memdevs(dev);
1112 if (ret < 0)
b27a23be 1113 goto err_res;
b27a23be
AK		 1114 } else {
1115 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1116 "s5p-mfc-l", match_child);
1117 if (!dev->mem_dev_l) {
1118 mfc_err("Mem child (L) device get failed\n");
1119 ret = -ENODEV;
1120 goto err_res;
1121 }
1122 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1123 "s5p-mfc-r", match_child);
1124 if (!dev->mem_dev_r) {
1125 mfc_err("Mem child (R) device get failed\n");
1126 ret = -ENODEV;
1127 goto err_res;
1128 }
af935746
KD		 1129 }
1130
1131 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
ef89fff8 1132 if (IS_ERR(dev->alloc_ctx[0])) {
af935746 1133 ret = PTR_ERR(dev->alloc_ctx[0]);
d310f478 1134 goto err_res;
af935746
KD		 1135 }
1136 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
ef89fff8 1137 if (IS_ERR(dev->alloc_ctx[1])) {
af935746
KD		 1138 ret = PTR_ERR(dev->alloc_ctx[1]);
1139 goto err_mem_init_ctx_1;
1140 }
1141
1142 mutex_init(&dev->mfc_mutex);
1143
2e731e44
KD		 1144 ret = s5p_mfc_alloc_firmware(dev);
1145 if (ret)
1146 goto err_alloc_fw;
1147
af935746
KD		 1148 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1149 if (ret)
1150 goto err_v4l2_dev_reg;
1151 init_waitqueue_head(&dev->queue);
1152
1153 /* decoder */
1154 vfd = video_device_alloc();
1155 if (!vfd) {
1156 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1157 ret = -ENOMEM;
1158 goto err_dec_alloc;
1159 }
d0ce898c 1160 vfd->fops = &s5p_mfc_fops;
af935746 1161 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
d0ce898c 1162 vfd->release = video_device_release;
af935746
KD		 1163 vfd->lock = &dev->mfc_mutex;
1164 vfd->v4l2_dev = &dev->v4l2_dev;
954f340f 1165 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1166 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1167 dev->vfd_dec = vfd;
1168 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1169 if (ret) {
1170 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1171 video_device_release(vfd);
1172 goto err_dec_reg;
1173 }
1174 v4l2_info(&dev->v4l2_dev,
1175 "decoder registered as /dev/video%d\n", vfd->num);
1176 video_set_drvdata(vfd, dev);
1177
1178 /* encoder */
1179 vfd = video_device_alloc();
1180 if (!vfd) {
1181 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1182 ret = -ENOMEM;
1183 goto err_enc_alloc;
1184 }
d0ce898c 1185 vfd->fops = &s5p_mfc_fops;
af935746 1186 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
d0ce898c 1187 vfd->release = video_device_release;
af935746
KD		 1188 vfd->lock = &dev->mfc_mutex;
1189 vfd->v4l2_dev = &dev->v4l2_dev;
cdcf45e7 1190 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1191 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1192 dev->vfd_enc = vfd;
1193 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1194 if (ret) {
1195 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1196 video_device_release(vfd);
1197 goto err_enc_reg;
1198 }
1199 v4l2_info(&dev->v4l2_dev,
1200 "encoder registered as /dev/video%d\n", vfd->num);
1201 video_set_drvdata(vfd, dev);
1202 platform_set_drvdata(pdev, dev);
1203
1204 dev->hw_lock = 0;
1205 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1206 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1207 atomic_set(&dev->watchdog_cnt, 0);
1208 init_timer(&dev->watchdog_timer);
1209 dev->watchdog_timer.data = (unsigned long)dev;
1210 dev->watchdog_timer.function = s5p_mfc_watchdog;
1211
43a1ea1f
AK		 1212 /* Initialize HW ops and commands based on MFC version */
1213 s5p_mfc_init_hw_ops(dev);
1214 s5p_mfc_init_hw_cmds(dev);
6a9c6f68 1215 s5p_mfc_init_regs(dev);
43a1ea1f 1216
af935746
KD		 1217 pr_debug("%s--\n", __func__);
1218 return 0;
1219
1220/* Deinit MFC if probe had failed */
1221err_enc_reg:
1222 video_device_release(dev->vfd_enc);
1223err_enc_alloc:
1224 video_unregister_device(dev->vfd_dec);
1225err_dec_reg:
1226 video_device_release(dev->vfd_dec);
1227err_dec_alloc:
1228 v4l2_device_unregister(&dev->v4l2_dev);
1229err_v4l2_dev_reg:
2e731e44
KD		 1230 s5p_mfc_release_firmware(dev);
1231err_alloc_fw:
af935746
KD		 1232 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1233err_mem_init_ctx_1:
1234 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
af935746
KD		 1235err_res:
1236 s5p_mfc_final_pm(dev);
d310f478 1237
af935746
KD		 1238 pr_debug("%s-- with error\n", __func__);
1239 return ret;
1240
1241}
1242
1243/* Remove the driver */
4c62e976 1244static int s5p_mfc_remove(struct platform_device *pdev)
af935746
KD		 1245{
1246 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1247
1248 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1249
1250 del_timer_sync(&dev->watchdog_timer);
1251 flush_workqueue(dev->watchdog_workqueue);
1252 destroy_workqueue(dev->watchdog_workqueue);
1253
1254 video_unregister_device(dev->vfd_enc);
1255 video_unregister_device(dev->vfd_dec);
1256 v4l2_device_unregister(&dev->v4l2_dev);
2e731e44 1257 s5p_mfc_release_firmware(dev);
af935746
KD		 1258 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1259 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
6e83e6e2
AK		 1260 if (pdev->dev.of_node) {
1261 put_device(dev->mem_dev_l);
1262 put_device(dev->mem_dev_r);
1263 }
af935746 1264
af935746 1265 s5p_mfc_final_pm(dev);
af935746
KD		 1266 return 0;
1267}
1268
1269#ifdef CONFIG_PM_SLEEP
1270
1271static int s5p_mfc_suspend(struct device *dev)
1272{
1273 struct platform_device *pdev = to_platform_device(dev);
1274 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1275 int ret;
1276
1277 if (m_dev->num_inst == 0)
1278 return 0;
81c9bcfb 1279
af935746
KD		 1280 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1281 mfc_err("Error: going to suspend for a second time\n");
1282 return -EIO;
1283 }
1284
1285 /* Check if we're processing then wait if it necessary. */
1286 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1287 /* Try and lock the HW */
1288 /* Wait on the interrupt waitqueue */
1289 ret = wait_event_interruptible_timeout(m_dev->queue,
76a4ddbd 1290 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
af935746
KD		 1291 if (ret == 0) {
1292 mfc_err("Waiting for hardware to finish timed out\n");
64370994 1293 clear_bit(0, &m_dev->enter_suspend);
af935746
KD		 1294 return -EIO;
1295 }
1296 }
81c9bcfb 1297
64370994
P		 1298 ret = s5p_mfc_sleep(m_dev);
1299 if (ret) {
1300 clear_bit(0, &m_dev->enter_suspend);
1301 clear_bit(0, &m_dev->hw_lock);
1302 }
1303 return ret;
af935746
KD		 1304}
1305
1306static int s5p_mfc_resume(struct device *dev)
1307{
1308 struct platform_device *pdev = to_platform_device(dev);
1309 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1310
1311 if (m_dev->num_inst == 0)
1312 return 0;
1313 return s5p_mfc_wakeup(m_dev);
1314}
1315#endif
1316
e243c7c1 1317#ifdef CONFIG_PM
af935746
KD		 1318static int s5p_mfc_runtime_suspend(struct device *dev)
1319{
1320 struct platform_device *pdev = to_platform_device(dev);
1321 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1322
1323 atomic_set(&m_dev->pm.power, 0);
1324 return 0;
1325}
1326
1327static int s5p_mfc_runtime_resume(struct device *dev)
1328{
1329 struct platform_device *pdev = to_platform_device(dev);
1330 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
af935746
KD		 1331
1332 if (!m_dev->alloc_ctx)
1333 return 0;
af935746
KD		 1334 atomic_set(&m_dev->pm.power, 1);
1335 return 0;
1336}
1337#endif
1338
1339/* Power management */
1340static const struct dev_pm_ops s5p_mfc_pm_ops = {
1341 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1342 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1343 NULL)
1344};
1345
ca5ea0c5 1346static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
8f532a7f
AK		 1347 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1348 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1349 .dsc = DESC_BUF_SIZE,
1350 .shm = SHARED_BUF_SIZE,
1351};
1352
ca5ea0c5 1353static struct s5p_mfc_buf_size buf_size_v5 = {
8f532a7f
AK		 1354 .fw = MAX_FW_SIZE,
1355 .cpb = MAX_CPB_SIZE,
1356 .priv = &mfc_buf_size_v5,
1357};
1358
ca5ea0c5 1359static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
8f532a7f
AK		 1360 .base = MFC_BASE_ALIGN_ORDER,
1361};
1362
1363static struct s5p_mfc_variant mfc_drvdata_v5 = {
1364 .version = MFC_VERSION,
9aa5f008 1365 .version_bit = MFC_V5_BIT,
8f532a7f
AK		 1366 .port_num = MFC_NUM_PORTS,
1367 .buf_size = &buf_size_v5,
1368 .buf_align = &mfc_buf_align_v5,
77ba6b73 1369 .fw_name[0] = "s5p-mfc.fw",
f96f3cfa
JP		 1370};
1371
ca5ea0c5 1372static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
f96f3cfa
JP		 1373 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1374 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1375 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1376 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1377 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1378};
1379
ca5ea0c5 1380static struct s5p_mfc_buf_size buf_size_v6 = {
f96f3cfa
JP		 1381 .fw = MAX_FW_SIZE_V6,
1382 .cpb = MAX_CPB_SIZE_V6,
1383 .priv = &mfc_buf_size_v6,
1384};
1385
ca5ea0c5 1386static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
f96f3cfa
JP		 1387 .base = 0,
1388};
1389
1390static struct s5p_mfc_variant mfc_drvdata_v6 = {
1391 .version = MFC_VERSION_V6,
9aa5f008 1392 .version_bit = MFC_V6_BIT,
f96f3cfa
JP		 1393 .port_num = MFC_NUM_PORTS_V6,
1394 .buf_size = &buf_size_v6,
1395 .buf_align = &mfc_buf_align_v6,
77ba6b73
AK		 1396 .fw_name[0] = "s5p-mfc-v6.fw",
1397 /*
1398 * v6-v2 firmware contains bug fixes and interface change
1399 * for init buffer command
1400 */
1401 .fw_name[1] = "s5p-mfc-v6-v2.fw",
8f532a7f
AK		 1402};
1403
ca5ea0c5 1404static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
5441e9da
AK		 1405 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1406 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1407 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1408 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1409 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1410};
1411
ca5ea0c5 1412static struct s5p_mfc_buf_size buf_size_v7 = {
5441e9da
AK		 1413 .fw = MAX_FW_SIZE_V7,
1414 .cpb = MAX_CPB_SIZE_V7,
1415 .priv = &mfc_buf_size_v7,
1416};
1417
ca5ea0c5 1418static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
5441e9da
AK		 1419 .base = 0,
1420};
1421
1422static struct s5p_mfc_variant mfc_drvdata_v7 = {
1423 .version = MFC_VERSION_V7,
9aa5f008 1424 .version_bit = MFC_V7_BIT,
5441e9da
AK		 1425 .port_num = MFC_NUM_PORTS_V7,
1426 .buf_size = &buf_size_v7,
1427 .buf_align = &mfc_buf_align_v7,
77ba6b73 1428 .fw_name[0] = "s5p-mfc-v7.fw",
5441e9da
AK		 1429};
1430
ca5ea0c5 1431static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
e2b9deb2
KA		 1432 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1433 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1434 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
3e594ce7
KA		 1435 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1436 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
e2b9deb2
KA		 1437};
1438
ca5ea0c5 1439static struct s5p_mfc_buf_size buf_size_v8 = {
e2b9deb2
KA		 1440 .fw = MAX_FW_SIZE_V8,
1441 .cpb = MAX_CPB_SIZE_V8,
1442 .priv = &mfc_buf_size_v8,
1443};
1444
ca5ea0c5 1445static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
e2b9deb2
KA		 1446 .base = 0,
1447};
1448
1449static struct s5p_mfc_variant mfc_drvdata_v8 = {
1450 .version = MFC_VERSION_V8,
1451 .version_bit = MFC_V8_BIT,
1452 .port_num = MFC_NUM_PORTS_V8,
1453 .buf_size = &buf_size_v8,
1454 .buf_align = &mfc_buf_align_v8,
77ba6b73 1455 .fw_name[0] = "s5p-mfc-v8.fw",
e2b9deb2
KA		 1456};
1457
8f532a7f
AK		 1458static struct platform_device_id mfc_driver_ids[] = {
1459 {
1460 .name = "s5p-mfc",
1461 .driver_data = (unsigned long)&mfc_drvdata_v5,
f96f3cfa
JP		 1462 }, {
1463 .name = "s5p-mfc-v5",
1464 .driver_data = (unsigned long)&mfc_drvdata_v5,
1465 }, {
1466 .name = "s5p-mfc-v6",
1467 .driver_data = (unsigned long)&mfc_drvdata_v6,
5441e9da
AK		 1468 }, {
1469 .name = "s5p-mfc-v7",
1470 .driver_data = (unsigned long)&mfc_drvdata_v7,
e2b9deb2
KA		 1471 }, {
1472 .name = "s5p-mfc-v8",
1473 .driver_data = (unsigned long)&mfc_drvdata_v8,
8f532a7f
AK		 1474 },
1475 {},
1476};
1477MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1478
b27a23be
AK		 1479static const struct of_device_id exynos_mfc_match[] = {
1480 {
1481 .compatible = "samsung,mfc-v5",
1482 .data = &mfc_drvdata_v5,
1483 }, {
1484 .compatible = "samsung,mfc-v6",
1485 .data = &mfc_drvdata_v6,
5441e9da
AK		 1486 }, {
1487 .compatible = "samsung,mfc-v7",
1488 .data = &mfc_drvdata_v7,
e2b9deb2
KA		 1489 }, {
1490 .compatible = "samsung,mfc-v8",
1491 .data = &mfc_drvdata_v8,
b27a23be
AK		 1492 },
1493 {},
1494};
1495MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1496
1497static void *mfc_get_drv_data(struct platform_device *pdev)
1498{
1499 struct s5p_mfc_variant *driver_data = NULL;
1500
1501 if (pdev->dev.of_node) {
1502 const struct of_device_id *match;
a40a1382 1503 match = of_match_node(exynos_mfc_match,
b27a23be
AK		 1504 pdev->dev.of_node);
1505 if (match)
1506 driver_data = (struct s5p_mfc_variant *)match->data;
1507 } else {
1508 driver_data = (struct s5p_mfc_variant *)
1509 platform_get_device_id(pdev)->driver_data;
1510 }
1511 return driver_data;
1512}
1513
1e393e90 1514static struct platform_driver s5p_mfc_driver = {
8f532a7f 1515 .probe = s5p_mfc_probe,
4c62e976 1516 .remove = s5p_mfc_remove,
8f532a7f 1517 .id_table = mfc_driver_ids,
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KD		 1518 .driver = {
1519 .name = S5P_MFC_NAME,
b27a23be
AK		 1520 .pm = &s5p_mfc_pm_ops,
1521 .of_match_table = exynos_mfc_match,
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KD		 1522 },
1523};
1524
1d6629b1 1525module_platform_driver(s5p_mfc_driver);
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KD		 1526
1527MODULE_LICENSE("GPL");
1528MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1529MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1530
Linux kernel - Deliverables
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