Commit | Line | Data |
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af935746 KD |
1 | /* |
2 | * Samsung S5P Multi Format Codec v 5.1 | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Kamil Debski, <k.debski@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
af935746 | 21 | #include <linux/videodev2.h> |
f9f715a9 | 22 | #include <media/v4l2-event.h> |
af935746 | 23 | #include <linux/workqueue.h> |
b27a23be | 24 | #include <linux/of.h> |
af935746 | 25 | #include <media/videobuf2-core.h> |
43a1ea1f | 26 | #include "s5p_mfc_common.h" |
af935746 KD |
27 | #include "s5p_mfc_ctrl.h" |
28 | #include "s5p_mfc_debug.h" | |
29 | #include "s5p_mfc_dec.h" | |
30 | #include "s5p_mfc_enc.h" | |
31 | #include "s5p_mfc_intr.h" | |
43a1ea1f AK |
32 | #include "s5p_mfc_opr.h" |
33 | #include "s5p_mfc_cmd.h" | |
af935746 | 34 | #include "s5p_mfc_pm.h" |
af935746 KD |
35 | |
36 | #define S5P_MFC_NAME "s5p-mfc" | |
37 | #define S5P_MFC_DEC_NAME "s5p-mfc-dec" | |
38 | #define S5P_MFC_ENC_NAME "s5p-mfc-enc" | |
39 | ||
40 | int debug; | |
41 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
42 | MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); | |
43 | ||
44 | /* Helper functions for interrupt processing */ | |
7fb89eca | 45 | |
af935746 | 46 | /* Remove from hw execution round robin */ |
7fb89eca | 47 | void clear_work_bit(struct s5p_mfc_ctx *ctx) |
af935746 KD |
48 | { |
49 | struct s5p_mfc_dev *dev = ctx->dev; | |
50 | ||
51 | spin_lock(&dev->condlock); | |
7fb89eca | 52 | __clear_bit(ctx->num, &dev->ctx_work_bits); |
af935746 KD |
53 | spin_unlock(&dev->condlock); |
54 | } | |
55 | ||
7fb89eca AH |
56 | /* Add to hw execution round robin */ |
57 | void set_work_bit(struct s5p_mfc_ctx *ctx) | |
58 | { | |
59 | struct s5p_mfc_dev *dev = ctx->dev; | |
60 | ||
61 | spin_lock(&dev->condlock); | |
62 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
63 | spin_unlock(&dev->condlock); | |
64 | } | |
65 | ||
66 | /* Remove from hw execution round robin */ | |
67 | void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
68 | { | |
69 | struct s5p_mfc_dev *dev = ctx->dev; | |
70 | unsigned long flags; | |
71 | ||
72 | spin_lock_irqsave(&dev->condlock, flags); | |
73 | __clear_bit(ctx->num, &dev->ctx_work_bits); | |
74 | spin_unlock_irqrestore(&dev->condlock, flags); | |
75 | } | |
76 | ||
77 | /* Add to hw execution round robin */ | |
78 | void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
79 | { | |
80 | struct s5p_mfc_dev *dev = ctx->dev; | |
81 | unsigned long flags; | |
82 | ||
83 | spin_lock_irqsave(&dev->condlock, flags); | |
84 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
85 | spin_unlock_irqrestore(&dev->condlock, flags); | |
86 | } | |
87 | ||
af935746 KD |
88 | /* Wake up context wait_queue */ |
89 | static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, | |
90 | unsigned int err) | |
91 | { | |
92 | ctx->int_cond = 1; | |
93 | ctx->int_type = reason; | |
94 | ctx->int_err = err; | |
95 | wake_up(&ctx->queue); | |
96 | } | |
97 | ||
98 | /* Wake up device wait_queue */ | |
99 | static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, | |
100 | unsigned int err) | |
101 | { | |
102 | dev->int_cond = 1; | |
103 | dev->int_type = reason; | |
104 | dev->int_err = err; | |
105 | wake_up(&dev->queue); | |
106 | } | |
107 | ||
a13bba4f | 108 | static void s5p_mfc_watchdog(unsigned long arg) |
af935746 KD |
109 | { |
110 | struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; | |
111 | ||
112 | if (test_bit(0, &dev->hw_lock)) | |
113 | atomic_inc(&dev->watchdog_cnt); | |
114 | if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { | |
115 | /* This means that hw is busy and no interrupts were | |
116 | * generated by hw for the Nth time of running this | |
117 | * watchdog timer. This usually means a serious hw | |
118 | * error. Now it is time to kill all instances and | |
119 | * reset the MFC. */ | |
120 | mfc_err("Time out during waiting for HW\n"); | |
121 | queue_work(dev->watchdog_workqueue, &dev->watchdog_work); | |
122 | } | |
123 | dev->watchdog_timer.expires = jiffies + | |
124 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
125 | add_timer(&dev->watchdog_timer); | |
126 | } | |
127 | ||
128 | static void s5p_mfc_watchdog_worker(struct work_struct *work) | |
129 | { | |
130 | struct s5p_mfc_dev *dev; | |
131 | struct s5p_mfc_ctx *ctx; | |
132 | unsigned long flags; | |
133 | int mutex_locked; | |
134 | int i, ret; | |
135 | ||
136 | dev = container_of(work, struct s5p_mfc_dev, watchdog_work); | |
137 | ||
138 | mfc_err("Driver timeout error handling\n"); | |
139 | /* Lock the mutex that protects open and release. | |
140 | * This is necessary as they may load and unload firmware. */ | |
141 | mutex_locked = mutex_trylock(&dev->mfc_mutex); | |
142 | if (!mutex_locked) | |
143 | mfc_err("Error: some instance may be closing/opening\n"); | |
144 | spin_lock_irqsave(&dev->irqlock, flags); | |
145 | ||
146 | s5p_mfc_clock_off(); | |
147 | ||
148 | for (i = 0; i < MFC_NUM_CONTEXTS; i++) { | |
149 | ctx = dev->ctx[i]; | |
150 | if (!ctx) | |
151 | continue; | |
152 | ctx->state = MFCINST_ERROR; | |
43a1ea1f AK |
153 | s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, |
154 | &ctx->vq_dst); | |
155 | s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, | |
156 | &ctx->vq_src); | |
af935746 | 157 | clear_work_bit(ctx); |
43a1ea1f | 158 | wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); |
af935746 KD |
159 | } |
160 | clear_bit(0, &dev->hw_lock); | |
161 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
162 | /* Double check if there is at least one instance running. | |
163 | * If no instance is in memory than no firmware should be present */ | |
164 | if (dev->num_inst > 0) { | |
165 | ret = s5p_mfc_reload_firmware(dev); | |
166 | if (ret) { | |
167 | mfc_err("Failed to reload FW\n"); | |
168 | goto unlock; | |
169 | } | |
170 | s5p_mfc_clock_on(); | |
171 | ret = s5p_mfc_init_hw(dev); | |
172 | if (ret) | |
173 | mfc_err("Failed to reinit FW\n"); | |
174 | } | |
175 | unlock: | |
176 | if (mutex_locked) | |
177 | mutex_unlock(&dev->mfc_mutex); | |
178 | } | |
179 | ||
180 | static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) | |
181 | { | |
182 | struct video_device *vdev = video_devdata(file); | |
183 | ||
184 | if (!vdev) { | |
185 | mfc_err("failed to get video_device"); | |
186 | return MFCNODE_INVALID; | |
187 | } | |
188 | if (vdev->index == 0) | |
189 | return MFCNODE_DECODER; | |
190 | else if (vdev->index == 1) | |
191 | return MFCNODE_ENCODER; | |
192 | return MFCNODE_INVALID; | |
193 | } | |
194 | ||
195 | static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) | |
196 | { | |
197 | mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); | |
198 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); | |
199 | mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); | |
200 | } | |
201 | ||
202 | static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) | |
203 | { | |
204 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f | 205 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
206 | |
207 | ctx->state = MFCINST_FINISHED; | |
208 | ctx->sequence++; | |
209 | while (!list_empty(&ctx->dst_queue)) { | |
210 | dst_buf = list_entry(ctx->dst_queue.next, | |
211 | struct s5p_mfc_buf, list); | |
212 | mfc_debug(2, "Cleaning up buffer: %d\n", | |
213 | dst_buf->b->v4l2_buf.index); | |
214 | vb2_set_plane_payload(dst_buf->b, 0, 0); | |
215 | vb2_set_plane_payload(dst_buf->b, 1, 0); | |
216 | list_del(&dst_buf->list); | |
217 | ctx->dst_queue_cnt--; | |
218 | dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); | |
219 | ||
43a1ea1f AK |
220 | if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == |
221 | s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) | |
af935746 KD |
222 | dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; |
223 | else | |
224 | dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; | |
225 | ||
226 | ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); | |
227 | vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); | |
228 | } | |
229 | } | |
230 | ||
231 | static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) | |
232 | { | |
233 | struct s5p_mfc_dev *dev = ctx->dev; | |
234 | struct s5p_mfc_buf *dst_buf, *src_buf; | |
43a1ea1f AK |
235 | size_t dec_y_addr; |
236 | unsigned int frame_type; | |
237 | ||
238 | dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); | |
239 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); | |
af935746 KD |
240 | |
241 | /* Copy timestamp / timecode from decoded src to dst and set | |
242 | appropraite flags */ | |
243 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
244 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
ba7fcb0c | 245 | if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { |
56006017 KD |
246 | dst_buf->b->v4l2_buf.timecode = |
247 | src_buf->b->v4l2_buf.timecode; | |
248 | dst_buf->b->v4l2_buf.timestamp = | |
249 | src_buf->b->v4l2_buf.timestamp; | |
af935746 KD |
250 | switch (frame_type) { |
251 | case S5P_FIMV_DECODE_FRAME_I_FRAME: | |
252 | dst_buf->b->v4l2_buf.flags |= | |
253 | V4L2_BUF_FLAG_KEYFRAME; | |
254 | break; | |
255 | case S5P_FIMV_DECODE_FRAME_P_FRAME: | |
256 | dst_buf->b->v4l2_buf.flags |= | |
257 | V4L2_BUF_FLAG_PFRAME; | |
258 | break; | |
259 | case S5P_FIMV_DECODE_FRAME_B_FRAME: | |
260 | dst_buf->b->v4l2_buf.flags |= | |
261 | V4L2_BUF_FLAG_BFRAME; | |
262 | break; | |
263 | } | |
264 | break; | |
265 | } | |
266 | } | |
267 | } | |
268 | ||
269 | static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) | |
270 | { | |
271 | struct s5p_mfc_dev *dev = ctx->dev; | |
272 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f AK |
273 | size_t dspl_y_addr; |
274 | unsigned int frame_type; | |
af935746 | 275 | |
43a1ea1f | 276 | dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); |
90c0ae50 | 277 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); |
43a1ea1f | 278 | |
af935746 KD |
279 | /* If frame is same as previous then skip and do not dequeue */ |
280 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { | |
281 | if (!ctx->after_packed_pb) | |
282 | ctx->sequence++; | |
283 | ctx->after_packed_pb = 0; | |
284 | return; | |
285 | } | |
286 | ctx->sequence++; | |
287 | /* The MFC returns address of the buffer, now we have to | |
288 | * check which videobuf does it correspond to */ | |
289 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
290 | /* Check if this is the buffer we're looking for */ | |
ba7fcb0c | 291 | if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { |
af935746 KD |
292 | list_del(&dst_buf->list); |
293 | ctx->dst_queue_cnt--; | |
294 | dst_buf->b->v4l2_buf.sequence = ctx->sequence; | |
43a1ea1f AK |
295 | if (s5p_mfc_hw_call(dev->mfc_ops, |
296 | get_pic_type_top, ctx) == | |
297 | s5p_mfc_hw_call(dev->mfc_ops, | |
298 | get_pic_type_bot, ctx)) | |
af935746 KD |
299 | dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; |
300 | else | |
301 | dst_buf->b->v4l2_buf.field = | |
302 | V4L2_FIELD_INTERLACED; | |
303 | vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); | |
304 | vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); | |
305 | clear_bit(dst_buf->b->v4l2_buf.index, | |
306 | &ctx->dec_dst_flag); | |
307 | ||
308 | vb2_buffer_done(dst_buf->b, | |
309 | err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); | |
310 | ||
af935746 KD |
311 | break; |
312 | } | |
313 | } | |
314 | } | |
315 | ||
316 | /* Handle frame decoding interrupt */ | |
317 | static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, | |
318 | unsigned int reason, unsigned int err) | |
319 | { | |
320 | struct s5p_mfc_dev *dev = ctx->dev; | |
321 | unsigned int dst_frame_status; | |
322 | struct s5p_mfc_buf *src_buf; | |
323 | unsigned long flags; | |
324 | unsigned int res_change; | |
325 | ||
43a1ea1f | 326 | dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
af935746 | 327 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; |
f96f3cfa JP |
328 | res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
329 | & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) | |
330 | >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; | |
af935746 KD |
331 | mfc_debug(2, "Frame Status: %x\n", dst_frame_status); |
332 | if (ctx->state == MFCINST_RES_CHANGE_INIT) | |
333 | ctx->state = MFCINST_RES_CHANGE_FLUSH; | |
f96f3cfa JP |
334 | if (res_change == S5P_FIMV_RES_INCREASE || |
335 | res_change == S5P_FIMV_RES_DECREASE) { | |
af935746 | 336 | ctx->state = MFCINST_RES_CHANGE_INIT; |
43a1ea1f | 337 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
338 | wake_up_ctx(ctx, reason, err); |
339 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
340 | BUG(); | |
341 | s5p_mfc_clock_off(); | |
43a1ea1f | 342 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
343 | return; |
344 | } | |
345 | if (ctx->dpb_flush_flag) | |
346 | ctx->dpb_flush_flag = 0; | |
347 | ||
348 | spin_lock_irqsave(&dev->irqlock, flags); | |
349 | /* All frames remaining in the buffer have been extracted */ | |
350 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { | |
351 | if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { | |
352 | s5p_mfc_handle_frame_all_extracted(ctx); | |
353 | ctx->state = MFCINST_RES_CHANGE_END; | |
354 | goto leave_handle_frame; | |
355 | } else { | |
356 | s5p_mfc_handle_frame_all_extracted(ctx); | |
357 | } | |
358 | } | |
359 | ||
360 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || | |
361 | dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) | |
362 | s5p_mfc_handle_frame_copy_time(ctx); | |
363 | ||
364 | /* A frame has been decoded and is in the buffer */ | |
365 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || | |
366 | dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { | |
367 | s5p_mfc_handle_frame_new(ctx, err); | |
368 | } else { | |
369 | mfc_debug(2, "No frame decode\n"); | |
370 | } | |
371 | /* Mark source buffer as complete */ | |
372 | if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY | |
373 | && !list_empty(&ctx->src_queue)) { | |
374 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, | |
375 | list); | |
43a1ea1f AK |
376 | ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, |
377 | get_consumed_stream, dev); | |
378 | if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && | |
d2a0db1e AK |
379 | ctx->consumed_stream + STUFF_BYTE < |
380 | src_buf->b->v4l2_planes[0].bytesused) { | |
af935746 KD |
381 | /* Run MFC again on the same buffer */ |
382 | mfc_debug(2, "Running again the same buffer\n"); | |
383 | ctx->after_packed_pb = 1; | |
384 | } else { | |
af935746 KD |
385 | mfc_debug(2, "MFC needs next buffer\n"); |
386 | ctx->consumed_stream = 0; | |
a34026e7 KD |
387 | if (src_buf->flags & MFC_BUF_FLAG_EOS) |
388 | ctx->state = MFCINST_FINISHING; | |
af935746 KD |
389 | list_del(&src_buf->list); |
390 | ctx->src_queue_cnt--; | |
43a1ea1f | 391 | if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) |
af935746 KD |
392 | vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); |
393 | else | |
394 | vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); | |
395 | } | |
396 | } | |
397 | leave_handle_frame: | |
398 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
399 | if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) | |
400 | || ctx->dst_queue_cnt < ctx->dpb_count) | |
401 | clear_work_bit(ctx); | |
43a1ea1f | 402 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
403 | wake_up_ctx(ctx, reason, err); |
404 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
405 | BUG(); | |
406 | s5p_mfc_clock_off(); | |
43a1ea1f | 407 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
408 | } |
409 | ||
410 | /* Error handling for interrupt */ | |
7296e25f KD |
411 | static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, |
412 | struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) | |
af935746 | 413 | { |
af935746 KD |
414 | unsigned long flags; |
415 | ||
af935746 | 416 | mfc_err("Interrupt Error: %08x\n", err); |
af935746 | 417 | |
7296e25f KD |
418 | if (ctx != NULL) { |
419 | /* Error recovery is dependent on the state of context */ | |
420 | switch (ctx->state) { | |
421 | case MFCINST_RES_CHANGE_INIT: | |
422 | case MFCINST_RES_CHANGE_FLUSH: | |
423 | case MFCINST_RES_CHANGE_END: | |
424 | case MFCINST_FINISHING: | |
425 | case MFCINST_FINISHED: | |
426 | case MFCINST_RUNNING: | |
427 | /* It is higly probable that an error occured | |
428 | * while decoding a frame */ | |
429 | clear_work_bit(ctx); | |
430 | ctx->state = MFCINST_ERROR; | |
431 | /* Mark all dst buffers as having an error */ | |
432 | spin_lock_irqsave(&dev->irqlock, flags); | |
433 | s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, | |
434 | &ctx->dst_queue, &ctx->vq_dst); | |
435 | /* Mark all src buffers as having an error */ | |
436 | s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, | |
437 | &ctx->src_queue, &ctx->vq_src); | |
438 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
439 | wake_up_ctx(ctx, reason, err); | |
440 | break; | |
441 | default: | |
442 | clear_work_bit(ctx); | |
443 | ctx->state = MFCINST_ERROR; | |
444 | wake_up_ctx(ctx, reason, err); | |
445 | break; | |
446 | } | |
af935746 | 447 | } |
7296e25f KD |
448 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) |
449 | BUG(); | |
450 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); | |
451 | s5p_mfc_clock_off(); | |
452 | wake_up_dev(dev, reason, err); | |
af935746 KD |
453 | return; |
454 | } | |
455 | ||
456 | /* Header parsing interrupt handling */ | |
457 | static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, | |
458 | unsigned int reason, unsigned int err) | |
459 | { | |
460 | struct s5p_mfc_dev *dev; | |
af935746 | 461 | |
1259762f | 462 | if (ctx == NULL) |
af935746 KD |
463 | return; |
464 | dev = ctx->dev; | |
465 | if (ctx->c_ops->post_seq_start) { | |
466 | if (ctx->c_ops->post_seq_start(ctx)) | |
467 | mfc_err("post_seq_start() failed\n"); | |
468 | } else { | |
43a1ea1f AK |
469 | ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, |
470 | dev); | |
471 | ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, | |
472 | dev); | |
af935746 | 473 | |
8f532a7f AK |
474 | s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); |
475 | ||
43a1ea1f AK |
476 | ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, |
477 | dev); | |
f96f3cfa JP |
478 | ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, |
479 | dev); | |
bb869368 | 480 | if (ctx->img_width == 0 || ctx->img_height == 0) |
af935746 KD |
481 | ctx->state = MFCINST_ERROR; |
482 | else | |
483 | ctx->state = MFCINST_HEAD_PARSED; | |
f96f3cfa JP |
484 | |
485 | if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
486 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && | |
487 | !list_empty(&ctx->src_queue)) { | |
488 | struct s5p_mfc_buf *src_buf; | |
489 | src_buf = list_entry(ctx->src_queue.next, | |
490 | struct s5p_mfc_buf, list); | |
491 | if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, | |
492 | dev) < | |
493 | src_buf->b->v4l2_planes[0].bytesused) | |
494 | ctx->head_processed = 0; | |
495 | else | |
496 | ctx->head_processed = 1; | |
497 | } else { | |
498 | ctx->head_processed = 1; | |
499 | } | |
af935746 | 500 | } |
43a1ea1f | 501 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
502 | clear_work_bit(ctx); |
503 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
504 | BUG(); | |
505 | s5p_mfc_clock_off(); | |
43a1ea1f | 506 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
507 | wake_up_ctx(ctx, reason, err); |
508 | } | |
509 | ||
510 | /* Header parsing interrupt handling */ | |
511 | static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, | |
512 | unsigned int reason, unsigned int err) | |
513 | { | |
514 | struct s5p_mfc_buf *src_buf; | |
515 | struct s5p_mfc_dev *dev; | |
516 | unsigned long flags; | |
517 | ||
1259762f | 518 | if (ctx == NULL) |
af935746 KD |
519 | return; |
520 | dev = ctx->dev; | |
43a1ea1f | 521 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
522 | ctx->int_type = reason; |
523 | ctx->int_err = err; | |
524 | ctx->int_cond = 1; | |
7fb89eca | 525 | clear_work_bit(ctx); |
af935746 KD |
526 | if (err == 0) { |
527 | ctx->state = MFCINST_RUNNING; | |
f96f3cfa | 528 | if (!ctx->dpb_flush_flag && ctx->head_processed) { |
af935746 KD |
529 | spin_lock_irqsave(&dev->irqlock, flags); |
530 | if (!list_empty(&ctx->src_queue)) { | |
531 | src_buf = list_entry(ctx->src_queue.next, | |
532 | struct s5p_mfc_buf, list); | |
533 | list_del(&src_buf->list); | |
534 | ctx->src_queue_cnt--; | |
535 | vb2_buffer_done(src_buf->b, | |
536 | VB2_BUF_STATE_DONE); | |
537 | } | |
538 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
539 | } else { | |
540 | ctx->dpb_flush_flag = 0; | |
541 | } | |
542 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
543 | BUG(); | |
544 | ||
545 | s5p_mfc_clock_off(); | |
546 | ||
547 | wake_up(&ctx->queue); | |
43a1ea1f | 548 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
549 | } else { |
550 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
551 | BUG(); | |
552 | ||
553 | s5p_mfc_clock_off(); | |
554 | ||
555 | wake_up(&ctx->queue); | |
556 | } | |
557 | } | |
558 | ||
f9f715a9 AH |
559 | static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, |
560 | unsigned int reason, unsigned int err) | |
561 | { | |
562 | struct s5p_mfc_dev *dev = ctx->dev; | |
563 | struct s5p_mfc_buf *mb_entry; | |
564 | ||
565 | mfc_debug(2, "Stream completed"); | |
566 | ||
567 | s5p_mfc_clear_int_flags(dev); | |
568 | ctx->int_type = reason; | |
569 | ctx->int_err = err; | |
570 | ctx->state = MFCINST_FINISHED; | |
571 | ||
572 | spin_lock(&dev->irqlock); | |
573 | if (!list_empty(&ctx->dst_queue)) { | |
574 | mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, | |
575 | list); | |
576 | list_del(&mb_entry->list); | |
577 | ctx->dst_queue_cnt--; | |
578 | vb2_set_plane_payload(mb_entry->b, 0, 0); | |
579 | vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); | |
580 | } | |
581 | spin_unlock(&dev->irqlock); | |
582 | ||
583 | clear_work_bit(ctx); | |
584 | ||
e8256447 | 585 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
f9f715a9 AH |
586 | |
587 | s5p_mfc_clock_off(); | |
588 | wake_up(&ctx->queue); | |
43a1ea1f | 589 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
f9f715a9 AH |
590 | } |
591 | ||
af935746 KD |
592 | /* Interrupt processing */ |
593 | static irqreturn_t s5p_mfc_irq(int irq, void *priv) | |
594 | { | |
595 | struct s5p_mfc_dev *dev = priv; | |
596 | struct s5p_mfc_ctx *ctx; | |
597 | unsigned int reason; | |
598 | unsigned int err; | |
599 | ||
600 | mfc_debug_enter(); | |
601 | /* Reset the timeout watchdog */ | |
602 | atomic_set(&dev->watchdog_cnt, 0); | |
603 | ctx = dev->ctx[dev->curr_ctx]; | |
604 | /* Get the reason of interrupt and the error code */ | |
43a1ea1f AK |
605 | reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); |
606 | err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); | |
af935746 KD |
607 | mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); |
608 | switch (reason) { | |
43a1ea1f | 609 | case S5P_MFC_R2H_CMD_ERR_RET: |
af935746 KD |
610 | /* An error has occured */ |
611 | if (ctx->state == MFCINST_RUNNING && | |
43a1ea1f AK |
612 | s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= |
613 | dev->warn_start) | |
af935746 KD |
614 | s5p_mfc_handle_frame(ctx, reason, err); |
615 | else | |
7296e25f | 616 | s5p_mfc_handle_error(dev, ctx, reason, err); |
af935746 KD |
617 | clear_bit(0, &dev->enter_suspend); |
618 | break; | |
619 | ||
43a1ea1f AK |
620 | case S5P_MFC_R2H_CMD_SLICE_DONE_RET: |
621 | case S5P_MFC_R2H_CMD_FIELD_DONE_RET: | |
622 | case S5P_MFC_R2H_CMD_FRAME_DONE_RET: | |
af935746 KD |
623 | if (ctx->c_ops->post_frame_start) { |
624 | if (ctx->c_ops->post_frame_start(ctx)) | |
625 | mfc_err("post_frame_start() failed\n"); | |
43a1ea1f | 626 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
627 | wake_up_ctx(ctx, reason, err); |
628 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
629 | BUG(); | |
630 | s5p_mfc_clock_off(); | |
43a1ea1f | 631 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
632 | } else { |
633 | s5p_mfc_handle_frame(ctx, reason, err); | |
634 | } | |
635 | break; | |
636 | ||
43a1ea1f | 637 | case S5P_MFC_R2H_CMD_SEQ_DONE_RET: |
af935746 KD |
638 | s5p_mfc_handle_seq_done(ctx, reason, err); |
639 | break; | |
640 | ||
43a1ea1f AK |
641 | case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: |
642 | ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); | |
af935746 KD |
643 | ctx->state = MFCINST_GOT_INST; |
644 | clear_work_bit(ctx); | |
645 | wake_up(&ctx->queue); | |
646 | goto irq_cleanup_hw; | |
647 | ||
43a1ea1f | 648 | case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: |
af935746 KD |
649 | clear_work_bit(ctx); |
650 | ctx->state = MFCINST_FREE; | |
651 | wake_up(&ctx->queue); | |
652 | goto irq_cleanup_hw; | |
653 | ||
43a1ea1f AK |
654 | case S5P_MFC_R2H_CMD_SYS_INIT_RET: |
655 | case S5P_MFC_R2H_CMD_FW_STATUS_RET: | |
656 | case S5P_MFC_R2H_CMD_SLEEP_RET: | |
657 | case S5P_MFC_R2H_CMD_WAKEUP_RET: | |
af935746 KD |
658 | if (ctx) |
659 | clear_work_bit(ctx); | |
43a1ea1f | 660 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
661 | wake_up_dev(dev, reason, err); |
662 | clear_bit(0, &dev->hw_lock); | |
663 | clear_bit(0, &dev->enter_suspend); | |
664 | break; | |
665 | ||
43a1ea1f | 666 | case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: |
af935746 KD |
667 | s5p_mfc_handle_init_buffers(ctx, reason, err); |
668 | break; | |
f9f715a9 | 669 | |
43a1ea1f | 670 | case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: |
f9f715a9 AH |
671 | s5p_mfc_handle_stream_complete(ctx, reason, err); |
672 | break; | |
673 | ||
8f23cc02 AK |
674 | case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: |
675 | clear_work_bit(ctx); | |
676 | ctx->state = MFCINST_RUNNING; | |
677 | wake_up(&ctx->queue); | |
678 | goto irq_cleanup_hw; | |
679 | ||
af935746 KD |
680 | default: |
681 | mfc_debug(2, "Unknown int reason\n"); | |
43a1ea1f | 682 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
683 | } |
684 | mfc_debug_leave(); | |
685 | return IRQ_HANDLED; | |
686 | irq_cleanup_hw: | |
43a1ea1f | 687 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
688 | ctx->int_type = reason; |
689 | ctx->int_err = err; | |
690 | ctx->int_cond = 1; | |
691 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
692 | mfc_err("Failed to unlock hw\n"); | |
693 | ||
694 | s5p_mfc_clock_off(); | |
695 | ||
43a1ea1f | 696 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
697 | mfc_debug(2, "Exit via irq_cleanup_hw\n"); |
698 | return IRQ_HANDLED; | |
699 | } | |
700 | ||
701 | /* Open an MFC node */ | |
702 | static int s5p_mfc_open(struct file *file) | |
703 | { | |
704 | struct s5p_mfc_dev *dev = video_drvdata(file); | |
705 | struct s5p_mfc_ctx *ctx = NULL; | |
706 | struct vb2_queue *q; | |
af935746 KD |
707 | int ret = 0; |
708 | ||
709 | mfc_debug_enter(); | |
bc738301 HV |
710 | if (mutex_lock_interruptible(&dev->mfc_mutex)) |
711 | return -ERESTARTSYS; | |
af935746 KD |
712 | dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ |
713 | /* Allocate memory for context */ | |
bae061b4 | 714 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
af935746 KD |
715 | if (!ctx) { |
716 | mfc_err("Not enough memory\n"); | |
717 | ret = -ENOMEM; | |
718 | goto err_alloc; | |
719 | } | |
720 | v4l2_fh_init(&ctx->fh, video_devdata(file)); | |
721 | file->private_data = &ctx->fh; | |
722 | v4l2_fh_add(&ctx->fh); | |
723 | ctx->dev = dev; | |
724 | INIT_LIST_HEAD(&ctx->src_queue); | |
725 | INIT_LIST_HEAD(&ctx->dst_queue); | |
726 | ctx->src_queue_cnt = 0; | |
727 | ctx->dst_queue_cnt = 0; | |
728 | /* Get context number */ | |
729 | ctx->num = 0; | |
730 | while (dev->ctx[ctx->num]) { | |
731 | ctx->num++; | |
732 | if (ctx->num >= MFC_NUM_CONTEXTS) { | |
733 | mfc_err("Too many open contexts\n"); | |
734 | ret = -EBUSY; | |
735 | goto err_no_ctx; | |
736 | } | |
737 | } | |
738 | /* Mark context as idle */ | |
7fb89eca | 739 | clear_work_bit_irqsave(ctx); |
af935746 KD |
740 | dev->ctx[ctx->num] = ctx; |
741 | if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { | |
742 | ctx->type = MFCINST_DECODER; | |
743 | ctx->c_ops = get_dec_codec_ops(); | |
43a1ea1f | 744 | s5p_mfc_dec_init(ctx); |
af935746 KD |
745 | /* Setup ctrl handler */ |
746 | ret = s5p_mfc_dec_ctrls_setup(ctx); | |
747 | if (ret) { | |
748 | mfc_err("Failed to setup mfc controls\n"); | |
749 | goto err_ctrls_setup; | |
750 | } | |
751 | } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { | |
752 | ctx->type = MFCINST_ENCODER; | |
753 | ctx->c_ops = get_enc_codec_ops(); | |
754 | /* only for encoder */ | |
755 | INIT_LIST_HEAD(&ctx->ref_queue); | |
756 | ctx->ref_queue_cnt = 0; | |
43a1ea1f | 757 | s5p_mfc_enc_init(ctx); |
af935746 KD |
758 | /* Setup ctrl handler */ |
759 | ret = s5p_mfc_enc_ctrls_setup(ctx); | |
760 | if (ret) { | |
761 | mfc_err("Failed to setup mfc controls\n"); | |
762 | goto err_ctrls_setup; | |
763 | } | |
764 | } else { | |
765 | ret = -ENOENT; | |
766 | goto err_bad_node; | |
767 | } | |
768 | ctx->fh.ctrl_handler = &ctx->ctrl_handler; | |
769 | ctx->inst_no = -1; | |
770 | /* Load firmware if this is the first instance */ | |
771 | if (dev->num_inst == 1) { | |
772 | dev->watchdog_timer.expires = jiffies + | |
773 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
774 | add_timer(&dev->watchdog_timer); | |
775 | ret = s5p_mfc_power_on(); | |
776 | if (ret < 0) { | |
777 | mfc_err("power on failed\n"); | |
778 | goto err_pwr_enable; | |
779 | } | |
780 | s5p_mfc_clock_on(); | |
2e731e44 KD |
781 | ret = s5p_mfc_load_firmware(dev); |
782 | if (ret) { | |
783 | s5p_mfc_clock_off(); | |
784 | goto err_load_fw; | |
785 | } | |
af935746 KD |
786 | /* Init the FW */ |
787 | ret = s5p_mfc_init_hw(dev); | |
2e731e44 | 788 | s5p_mfc_clock_off(); |
af935746 KD |
789 | if (ret) |
790 | goto err_init_hw; | |
af935746 KD |
791 | } |
792 | /* Init videobuf2 queue for CAPTURE */ | |
793 | q = &ctx->vq_dst; | |
794 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
795 | q->drv_priv = &ctx->fh; | |
796 | if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { | |
797 | q->io_modes = VB2_MMAP; | |
798 | q->ops = get_dec_queue_ops(); | |
799 | } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { | |
800 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
801 | q->ops = get_enc_queue_ops(); | |
802 | } else { | |
803 | ret = -ENOENT; | |
804 | goto err_queue_init; | |
805 | } | |
806 | q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; | |
6aa69f99 | 807 | q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
808 | ret = vb2_queue_init(q); |
809 | if (ret) { | |
810 | mfc_err("Failed to initialize videobuf2 queue(capture)\n"); | |
811 | goto err_queue_init; | |
812 | } | |
813 | /* Init videobuf2 queue for OUTPUT */ | |
814 | q = &ctx->vq_src; | |
815 | q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
816 | q->io_modes = VB2_MMAP; | |
817 | q->drv_priv = &ctx->fh; | |
818 | if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { | |
819 | q->io_modes = VB2_MMAP; | |
820 | q->ops = get_dec_queue_ops(); | |
821 | } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { | |
822 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
823 | q->ops = get_enc_queue_ops(); | |
824 | } else { | |
825 | ret = -ENOENT; | |
826 | goto err_queue_init; | |
827 | } | |
828 | q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; | |
6aa69f99 | 829 | q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
830 | ret = vb2_queue_init(q); |
831 | if (ret) { | |
832 | mfc_err("Failed to initialize videobuf2 queue(output)\n"); | |
833 | goto err_queue_init; | |
834 | } | |
835 | init_waitqueue_head(&ctx->queue); | |
bc738301 | 836 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
837 | mfc_debug_leave(); |
838 | return ret; | |
839 | /* Deinit when failure occured */ | |
840 | err_queue_init: | |
2e731e44 KD |
841 | if (dev->num_inst == 1) |
842 | s5p_mfc_deinit_hw(dev); | |
af935746 | 843 | err_init_hw: |
2e731e44 | 844 | err_load_fw: |
af935746 KD |
845 | err_pwr_enable: |
846 | if (dev->num_inst == 1) { | |
847 | if (s5p_mfc_power_off() < 0) | |
848 | mfc_err("power off failed\n"); | |
1b73ba0b | 849 | del_timer_sync(&dev->watchdog_timer); |
af935746 KD |
850 | } |
851 | err_ctrls_setup: | |
852 | s5p_mfc_dec_ctrls_delete(ctx); | |
853 | err_bad_node: | |
1b73ba0b | 854 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
855 | err_no_ctx: |
856 | v4l2_fh_del(&ctx->fh); | |
857 | v4l2_fh_exit(&ctx->fh); | |
858 | kfree(ctx); | |
859 | err_alloc: | |
860 | dev->num_inst--; | |
bc738301 | 861 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
862 | mfc_debug_leave(); |
863 | return ret; | |
864 | } | |
865 | ||
866 | /* Release MFC context */ | |
867 | static int s5p_mfc_release(struct file *file) | |
868 | { | |
869 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
870 | struct s5p_mfc_dev *dev = ctx->dev; | |
af935746 KD |
871 | |
872 | mfc_debug_enter(); | |
bc738301 | 873 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
874 | s5p_mfc_clock_on(); |
875 | vb2_queue_release(&ctx->vq_src); | |
876 | vb2_queue_release(&ctx->vq_dst); | |
877 | /* Mark context as idle */ | |
7fb89eca | 878 | clear_work_bit_irqsave(ctx); |
af935746 KD |
879 | /* If instance was initialised then |
880 | * return instance and free reosurces */ | |
881 | if (ctx->inst_no != MFC_NO_INSTANCE_SET) { | |
882 | mfc_debug(2, "Has to free instance\n"); | |
883 | ctx->state = MFCINST_RETURN_INST; | |
7fb89eca | 884 | set_work_bit_irqsave(ctx); |
af935746 | 885 | s5p_mfc_clean_ctx_int_flags(ctx); |
43a1ea1f | 886 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
887 | /* Wait until instance is returned or timeout occured */ |
888 | if (s5p_mfc_wait_for_done_ctx | |
43a1ea1f | 889 | (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { |
af935746 KD |
890 | s5p_mfc_clock_off(); |
891 | mfc_err("Err returning instance\n"); | |
892 | } | |
893 | mfc_debug(2, "After free instance\n"); | |
894 | /* Free resources */ | |
43a1ea1f AK |
895 | s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); |
896 | s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); | |
af935746 | 897 | if (ctx->type == MFCINST_DECODER) |
43a1ea1f AK |
898 | s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, |
899 | ctx); | |
af935746 KD |
900 | |
901 | ctx->inst_no = MFC_NO_INSTANCE_SET; | |
902 | } | |
903 | /* hardware locking scheme */ | |
904 | if (dev->curr_ctx == ctx->num) | |
905 | clear_bit(0, &dev->hw_lock); | |
906 | dev->num_inst--; | |
907 | if (dev->num_inst == 0) { | |
2e731e44 | 908 | mfc_debug(2, "Last instance\n"); |
43a1ea1f | 909 | s5p_mfc_deinit_hw(dev); |
af935746 KD |
910 | del_timer_sync(&dev->watchdog_timer); |
911 | if (s5p_mfc_power_off() < 0) | |
912 | mfc_err("Power off failed\n"); | |
913 | } | |
914 | mfc_debug(2, "Shutting down clock\n"); | |
915 | s5p_mfc_clock_off(); | |
1259762f | 916 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
917 | s5p_mfc_dec_ctrls_delete(ctx); |
918 | v4l2_fh_del(&ctx->fh); | |
919 | v4l2_fh_exit(&ctx->fh); | |
920 | kfree(ctx); | |
921 | mfc_debug_leave(); | |
bc738301 | 922 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
923 | return 0; |
924 | } | |
925 | ||
926 | /* Poll */ | |
927 | static unsigned int s5p_mfc_poll(struct file *file, | |
928 | struct poll_table_struct *wait) | |
929 | { | |
930 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
931 | struct s5p_mfc_dev *dev = ctx->dev; | |
932 | struct vb2_queue *src_q, *dst_q; | |
933 | struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; | |
934 | unsigned int rc = 0; | |
935 | unsigned long flags; | |
936 | ||
bc738301 | 937 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
938 | src_q = &ctx->vq_src; |
939 | dst_q = &ctx->vq_dst; | |
940 | /* | |
941 | * There has to be at least one buffer queued on each queued_list, which | |
942 | * means either in driver already or waiting for driver to claim it | |
943 | * and start processing. | |
944 | */ | |
945 | if ((!src_q->streaming || list_empty(&src_q->queued_list)) | |
946 | && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { | |
947 | rc = POLLERR; | |
948 | goto end; | |
949 | } | |
950 | mutex_unlock(&dev->mfc_mutex); | |
f9f715a9 | 951 | poll_wait(file, &ctx->fh.wait, wait); |
af935746 KD |
952 | poll_wait(file, &src_q->done_wq, wait); |
953 | poll_wait(file, &dst_q->done_wq, wait); | |
954 | mutex_lock(&dev->mfc_mutex); | |
f9f715a9 AH |
955 | if (v4l2_event_pending(&ctx->fh)) |
956 | rc |= POLLPRI; | |
af935746 KD |
957 | spin_lock_irqsave(&src_q->done_lock, flags); |
958 | if (!list_empty(&src_q->done_list)) | |
959 | src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, | |
960 | done_entry); | |
961 | if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE | |
962 | || src_vb->state == VB2_BUF_STATE_ERROR)) | |
963 | rc |= POLLOUT | POLLWRNORM; | |
964 | spin_unlock_irqrestore(&src_q->done_lock, flags); | |
965 | spin_lock_irqsave(&dst_q->done_lock, flags); | |
966 | if (!list_empty(&dst_q->done_list)) | |
967 | dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, | |
968 | done_entry); | |
969 | if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE | |
970 | || dst_vb->state == VB2_BUF_STATE_ERROR)) | |
971 | rc |= POLLIN | POLLRDNORM; | |
972 | spin_unlock_irqrestore(&dst_q->done_lock, flags); | |
973 | end: | |
bc738301 | 974 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
975 | return rc; |
976 | } | |
977 | ||
978 | /* Mmap */ | |
979 | static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) | |
980 | { | |
981 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
bc738301 | 982 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
983 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
984 | int ret; | |
bc738301 HV |
985 | |
986 | if (mutex_lock_interruptible(&dev->mfc_mutex)) | |
987 | return -ERESTARTSYS; | |
af935746 KD |
988 | if (offset < DST_QUEUE_OFF_BASE) { |
989 | mfc_debug(2, "mmaping source\n"); | |
990 | ret = vb2_mmap(&ctx->vq_src, vma); | |
991 | } else { /* capture */ | |
992 | mfc_debug(2, "mmaping destination\n"); | |
993 | vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); | |
994 | ret = vb2_mmap(&ctx->vq_dst, vma); | |
995 | } | |
bc738301 | 996 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
997 | return ret; |
998 | } | |
999 | ||
1000 | /* v4l2 ops */ | |
1001 | static const struct v4l2_file_operations s5p_mfc_fops = { | |
1002 | .owner = THIS_MODULE, | |
1003 | .open = s5p_mfc_open, | |
1004 | .release = s5p_mfc_release, | |
1005 | .poll = s5p_mfc_poll, | |
1006 | .unlocked_ioctl = video_ioctl2, | |
1007 | .mmap = s5p_mfc_mmap, | |
1008 | }; | |
1009 | ||
1010 | static int match_child(struct device *dev, void *data) | |
1011 | { | |
1012 | if (!dev_name(dev)) | |
1013 | return 0; | |
1014 | return !strcmp(dev_name(dev), (char *)data); | |
1015 | } | |
1016 | ||
b27a23be AK |
1017 | static void *mfc_get_drv_data(struct platform_device *pdev); |
1018 | ||
6e83e6e2 AK |
1019 | static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) |
1020 | { | |
65fccab5 | 1021 | unsigned int mem_info[2] = { }; |
6e83e6e2 AK |
1022 | |
1023 | dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, | |
1024 | sizeof(struct device), GFP_KERNEL); | |
1025 | if (!dev->mem_dev_l) { | |
1026 | mfc_err("Not enough memory\n"); | |
1027 | return -ENOMEM; | |
1028 | } | |
1029 | device_initialize(dev->mem_dev_l); | |
1030 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1031 | "samsung,mfc-l", mem_info, 2); | |
1032 | if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], | |
1033 | mem_info[0], mem_info[1], | |
1034 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1035 | mfc_err("Failed to declare coherent memory for\n" | |
1036 | "MFC device\n"); | |
1037 | return -ENOMEM; | |
1038 | } | |
1039 | ||
1040 | dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, | |
1041 | sizeof(struct device), GFP_KERNEL); | |
1042 | if (!dev->mem_dev_r) { | |
1043 | mfc_err("Not enough memory\n"); | |
1044 | return -ENOMEM; | |
1045 | } | |
1046 | device_initialize(dev->mem_dev_r); | |
1047 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1048 | "samsung,mfc-r", mem_info, 2); | |
1049 | if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], | |
1050 | mem_info[0], mem_info[1], | |
1051 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1052 | pr_err("Failed to declare coherent memory for\n" | |
1053 | "MFC device\n"); | |
1054 | return -ENOMEM; | |
1055 | } | |
1056 | return 0; | |
1057 | } | |
1058 | ||
af935746 | 1059 | /* MFC probe function */ |
1e393e90 | 1060 | static int s5p_mfc_probe(struct platform_device *pdev) |
af935746 KD |
1061 | { |
1062 | struct s5p_mfc_dev *dev; | |
1063 | struct video_device *vfd; | |
1064 | struct resource *res; | |
1065 | int ret; | |
1066 | ||
1067 | pr_debug("%s++\n", __func__); | |
bae061b4 | 1068 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
af935746 KD |
1069 | if (!dev) { |
1070 | dev_err(&pdev->dev, "Not enough memory for MFC device\n"); | |
1071 | return -ENOMEM; | |
1072 | } | |
1073 | ||
1074 | spin_lock_init(&dev->irqlock); | |
1075 | spin_lock_init(&dev->condlock); | |
1076 | dev->plat_dev = pdev; | |
1077 | if (!dev->plat_dev) { | |
1078 | dev_err(&pdev->dev, "No platform data specified\n"); | |
d310f478 | 1079 | return -ENODEV; |
af935746 KD |
1080 | } |
1081 | ||
b27a23be | 1082 | dev->variant = mfc_get_drv_data(pdev); |
8f532a7f | 1083 | |
af935746 KD |
1084 | ret = s5p_mfc_init_pm(dev); |
1085 | if (ret < 0) { | |
1086 | dev_err(&pdev->dev, "failed to get mfc clock source\n"); | |
d310f478 | 1087 | return ret; |
af935746 KD |
1088 | } |
1089 | ||
1090 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
af935746 | 1091 | |
f23999ec TR |
1092 | dev->regs_base = devm_ioremap_resource(&pdev->dev, res); |
1093 | if (IS_ERR(dev->regs_base)) | |
1094 | return PTR_ERR(dev->regs_base); | |
af935746 KD |
1095 | |
1096 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1097 | if (res == NULL) { | |
1098 | dev_err(&pdev->dev, "failed to get irq resource\n"); | |
1099 | ret = -ENOENT; | |
d310f478 | 1100 | goto err_res; |
af935746 KD |
1101 | } |
1102 | dev->irq = res->start; | |
d310f478 SK |
1103 | ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, |
1104 | IRQF_DISABLED, pdev->name, dev); | |
af935746 KD |
1105 | if (ret) { |
1106 | dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); | |
d310f478 | 1107 | goto err_res; |
af935746 KD |
1108 | } |
1109 | ||
b27a23be | 1110 | if (pdev->dev.of_node) { |
d68b44e0 WY |
1111 | ret = s5p_mfc_alloc_memdevs(dev); |
1112 | if (ret < 0) | |
b27a23be | 1113 | goto err_res; |
b27a23be AK |
1114 | } else { |
1115 | dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, | |
1116 | "s5p-mfc-l", match_child); | |
1117 | if (!dev->mem_dev_l) { | |
1118 | mfc_err("Mem child (L) device get failed\n"); | |
1119 | ret = -ENODEV; | |
1120 | goto err_res; | |
1121 | } | |
1122 | dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, | |
1123 | "s5p-mfc-r", match_child); | |
1124 | if (!dev->mem_dev_r) { | |
1125 | mfc_err("Mem child (R) device get failed\n"); | |
1126 | ret = -ENODEV; | |
1127 | goto err_res; | |
1128 | } | |
af935746 KD |
1129 | } |
1130 | ||
1131 | dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); | |
ef89fff8 | 1132 | if (IS_ERR(dev->alloc_ctx[0])) { |
af935746 | 1133 | ret = PTR_ERR(dev->alloc_ctx[0]); |
d310f478 | 1134 | goto err_res; |
af935746 KD |
1135 | } |
1136 | dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); | |
ef89fff8 | 1137 | if (IS_ERR(dev->alloc_ctx[1])) { |
af935746 KD |
1138 | ret = PTR_ERR(dev->alloc_ctx[1]); |
1139 | goto err_mem_init_ctx_1; | |
1140 | } | |
1141 | ||
1142 | mutex_init(&dev->mfc_mutex); | |
1143 | ||
2e731e44 KD |
1144 | ret = s5p_mfc_alloc_firmware(dev); |
1145 | if (ret) | |
1146 | goto err_alloc_fw; | |
1147 | ||
af935746 KD |
1148 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); |
1149 | if (ret) | |
1150 | goto err_v4l2_dev_reg; | |
1151 | init_waitqueue_head(&dev->queue); | |
1152 | ||
1153 | /* decoder */ | |
1154 | vfd = video_device_alloc(); | |
1155 | if (!vfd) { | |
1156 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1157 | ret = -ENOMEM; | |
1158 | goto err_dec_alloc; | |
1159 | } | |
1160 | vfd->fops = &s5p_mfc_fops, | |
1161 | vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); | |
1162 | vfd->release = video_device_release, | |
1163 | vfd->lock = &dev->mfc_mutex; | |
1164 | vfd->v4l2_dev = &dev->v4l2_dev; | |
954f340f | 1165 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1166 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); |
1167 | dev->vfd_dec = vfd; | |
1168 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1169 | if (ret) { | |
1170 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1171 | video_device_release(vfd); | |
1172 | goto err_dec_reg; | |
1173 | } | |
1174 | v4l2_info(&dev->v4l2_dev, | |
1175 | "decoder registered as /dev/video%d\n", vfd->num); | |
1176 | video_set_drvdata(vfd, dev); | |
1177 | ||
1178 | /* encoder */ | |
1179 | vfd = video_device_alloc(); | |
1180 | if (!vfd) { | |
1181 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1182 | ret = -ENOMEM; | |
1183 | goto err_enc_alloc; | |
1184 | } | |
1185 | vfd->fops = &s5p_mfc_fops, | |
1186 | vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); | |
1187 | vfd->release = video_device_release, | |
1188 | vfd->lock = &dev->mfc_mutex; | |
1189 | vfd->v4l2_dev = &dev->v4l2_dev; | |
cdcf45e7 | 1190 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1191 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); |
1192 | dev->vfd_enc = vfd; | |
1193 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1194 | if (ret) { | |
1195 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1196 | video_device_release(vfd); | |
1197 | goto err_enc_reg; | |
1198 | } | |
1199 | v4l2_info(&dev->v4l2_dev, | |
1200 | "encoder registered as /dev/video%d\n", vfd->num); | |
1201 | video_set_drvdata(vfd, dev); | |
1202 | platform_set_drvdata(pdev, dev); | |
1203 | ||
1204 | dev->hw_lock = 0; | |
1205 | dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); | |
1206 | INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); | |
1207 | atomic_set(&dev->watchdog_cnt, 0); | |
1208 | init_timer(&dev->watchdog_timer); | |
1209 | dev->watchdog_timer.data = (unsigned long)dev; | |
1210 | dev->watchdog_timer.function = s5p_mfc_watchdog; | |
1211 | ||
43a1ea1f AK |
1212 | /* Initialize HW ops and commands based on MFC version */ |
1213 | s5p_mfc_init_hw_ops(dev); | |
1214 | s5p_mfc_init_hw_cmds(dev); | |
1215 | ||
af935746 KD |
1216 | pr_debug("%s--\n", __func__); |
1217 | return 0; | |
1218 | ||
1219 | /* Deinit MFC if probe had failed */ | |
1220 | err_enc_reg: | |
1221 | video_device_release(dev->vfd_enc); | |
1222 | err_enc_alloc: | |
1223 | video_unregister_device(dev->vfd_dec); | |
1224 | err_dec_reg: | |
1225 | video_device_release(dev->vfd_dec); | |
1226 | err_dec_alloc: | |
1227 | v4l2_device_unregister(&dev->v4l2_dev); | |
1228 | err_v4l2_dev_reg: | |
2e731e44 KD |
1229 | s5p_mfc_release_firmware(dev); |
1230 | err_alloc_fw: | |
af935746 KD |
1231 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); |
1232 | err_mem_init_ctx_1: | |
1233 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); | |
af935746 KD |
1234 | err_res: |
1235 | s5p_mfc_final_pm(dev); | |
d310f478 | 1236 | |
af935746 KD |
1237 | pr_debug("%s-- with error\n", __func__); |
1238 | return ret; | |
1239 | ||
1240 | } | |
1241 | ||
1242 | /* Remove the driver */ | |
4c62e976 | 1243 | static int s5p_mfc_remove(struct platform_device *pdev) |
af935746 KD |
1244 | { |
1245 | struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); | |
1246 | ||
1247 | v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); | |
1248 | ||
1249 | del_timer_sync(&dev->watchdog_timer); | |
1250 | flush_workqueue(dev->watchdog_workqueue); | |
1251 | destroy_workqueue(dev->watchdog_workqueue); | |
1252 | ||
1253 | video_unregister_device(dev->vfd_enc); | |
1254 | video_unregister_device(dev->vfd_dec); | |
1255 | v4l2_device_unregister(&dev->v4l2_dev); | |
2e731e44 | 1256 | s5p_mfc_release_firmware(dev); |
af935746 KD |
1257 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); |
1258 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); | |
6e83e6e2 AK |
1259 | if (pdev->dev.of_node) { |
1260 | put_device(dev->mem_dev_l); | |
1261 | put_device(dev->mem_dev_r); | |
1262 | } | |
af935746 | 1263 | |
af935746 | 1264 | s5p_mfc_final_pm(dev); |
af935746 KD |
1265 | return 0; |
1266 | } | |
1267 | ||
1268 | #ifdef CONFIG_PM_SLEEP | |
1269 | ||
1270 | static int s5p_mfc_suspend(struct device *dev) | |
1271 | { | |
1272 | struct platform_device *pdev = to_platform_device(dev); | |
1273 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1274 | int ret; | |
1275 | ||
1276 | if (m_dev->num_inst == 0) | |
1277 | return 0; | |
81c9bcfb | 1278 | |
af935746 KD |
1279 | if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { |
1280 | mfc_err("Error: going to suspend for a second time\n"); | |
1281 | return -EIO; | |
1282 | } | |
1283 | ||
1284 | /* Check if we're processing then wait if it necessary. */ | |
1285 | while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { | |
1286 | /* Try and lock the HW */ | |
1287 | /* Wait on the interrupt waitqueue */ | |
1288 | ret = wait_event_interruptible_timeout(m_dev->queue, | |
1289 | m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, | |
1290 | msecs_to_jiffies(MFC_INT_TIMEOUT)); | |
1291 | ||
1292 | if (ret == 0) { | |
1293 | mfc_err("Waiting for hardware to finish timed out\n"); | |
1294 | return -EIO; | |
1295 | } | |
1296 | } | |
81c9bcfb SK |
1297 | |
1298 | return s5p_mfc_sleep(m_dev); | |
af935746 KD |
1299 | } |
1300 | ||
1301 | static int s5p_mfc_resume(struct device *dev) | |
1302 | { | |
1303 | struct platform_device *pdev = to_platform_device(dev); | |
1304 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1305 | ||
1306 | if (m_dev->num_inst == 0) | |
1307 | return 0; | |
1308 | return s5p_mfc_wakeup(m_dev); | |
1309 | } | |
1310 | #endif | |
1311 | ||
1312 | #ifdef CONFIG_PM_RUNTIME | |
1313 | static int s5p_mfc_runtime_suspend(struct device *dev) | |
1314 | { | |
1315 | struct platform_device *pdev = to_platform_device(dev); | |
1316 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1317 | ||
1318 | atomic_set(&m_dev->pm.power, 0); | |
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | static int s5p_mfc_runtime_resume(struct device *dev) | |
1323 | { | |
1324 | struct platform_device *pdev = to_platform_device(dev); | |
1325 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1326 | int pre_power; | |
1327 | ||
1328 | if (!m_dev->alloc_ctx) | |
1329 | return 0; | |
1330 | pre_power = atomic_read(&m_dev->pm.power); | |
1331 | atomic_set(&m_dev->pm.power, 1); | |
1332 | return 0; | |
1333 | } | |
1334 | #endif | |
1335 | ||
1336 | /* Power management */ | |
1337 | static const struct dev_pm_ops s5p_mfc_pm_ops = { | |
1338 | SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) | |
1339 | SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, | |
1340 | NULL) | |
1341 | }; | |
1342 | ||
8f532a7f AK |
1343 | struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { |
1344 | .h264_ctx = MFC_H264_CTX_BUF_SIZE, | |
1345 | .non_h264_ctx = MFC_CTX_BUF_SIZE, | |
1346 | .dsc = DESC_BUF_SIZE, | |
1347 | .shm = SHARED_BUF_SIZE, | |
1348 | }; | |
1349 | ||
1350 | struct s5p_mfc_buf_size buf_size_v5 = { | |
1351 | .fw = MAX_FW_SIZE, | |
1352 | .cpb = MAX_CPB_SIZE, | |
1353 | .priv = &mfc_buf_size_v5, | |
1354 | }; | |
1355 | ||
1356 | struct s5p_mfc_buf_align mfc_buf_align_v5 = { | |
1357 | .base = MFC_BASE_ALIGN_ORDER, | |
1358 | }; | |
1359 | ||
1360 | static struct s5p_mfc_variant mfc_drvdata_v5 = { | |
1361 | .version = MFC_VERSION, | |
1362 | .port_num = MFC_NUM_PORTS, | |
1363 | .buf_size = &buf_size_v5, | |
1364 | .buf_align = &mfc_buf_align_v5, | |
f96f3cfa JP |
1365 | .mclk_name = "sclk_mfc", |
1366 | .fw_name = "s5p-mfc.fw", | |
1367 | }; | |
1368 | ||
1369 | struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { | |
1370 | .dev_ctx = MFC_CTX_BUF_SIZE_V6, | |
1371 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, | |
1372 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, | |
1373 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, | |
1374 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, | |
1375 | }; | |
1376 | ||
1377 | struct s5p_mfc_buf_size buf_size_v6 = { | |
1378 | .fw = MAX_FW_SIZE_V6, | |
1379 | .cpb = MAX_CPB_SIZE_V6, | |
1380 | .priv = &mfc_buf_size_v6, | |
1381 | }; | |
1382 | ||
1383 | struct s5p_mfc_buf_align mfc_buf_align_v6 = { | |
1384 | .base = 0, | |
1385 | }; | |
1386 | ||
1387 | static struct s5p_mfc_variant mfc_drvdata_v6 = { | |
1388 | .version = MFC_VERSION_V6, | |
1389 | .port_num = MFC_NUM_PORTS_V6, | |
1390 | .buf_size = &buf_size_v6, | |
1391 | .buf_align = &mfc_buf_align_v6, | |
1392 | .mclk_name = "aclk_333", | |
1393 | .fw_name = "s5p-mfc-v6.fw", | |
8f532a7f AK |
1394 | }; |
1395 | ||
1396 | static struct platform_device_id mfc_driver_ids[] = { | |
1397 | { | |
1398 | .name = "s5p-mfc", | |
1399 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
f96f3cfa JP |
1400 | }, { |
1401 | .name = "s5p-mfc-v5", | |
1402 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
1403 | }, { | |
1404 | .name = "s5p-mfc-v6", | |
1405 | .driver_data = (unsigned long)&mfc_drvdata_v6, | |
8f532a7f AK |
1406 | }, |
1407 | {}, | |
1408 | }; | |
1409 | MODULE_DEVICE_TABLE(platform, mfc_driver_ids); | |
1410 | ||
b27a23be AK |
1411 | static const struct of_device_id exynos_mfc_match[] = { |
1412 | { | |
1413 | .compatible = "samsung,mfc-v5", | |
1414 | .data = &mfc_drvdata_v5, | |
1415 | }, { | |
1416 | .compatible = "samsung,mfc-v6", | |
1417 | .data = &mfc_drvdata_v6, | |
1418 | }, | |
1419 | {}, | |
1420 | }; | |
1421 | MODULE_DEVICE_TABLE(of, exynos_mfc_match); | |
1422 | ||
1423 | static void *mfc_get_drv_data(struct platform_device *pdev) | |
1424 | { | |
1425 | struct s5p_mfc_variant *driver_data = NULL; | |
1426 | ||
1427 | if (pdev->dev.of_node) { | |
1428 | const struct of_device_id *match; | |
1429 | match = of_match_node(of_match_ptr(exynos_mfc_match), | |
1430 | pdev->dev.of_node); | |
1431 | if (match) | |
1432 | driver_data = (struct s5p_mfc_variant *)match->data; | |
1433 | } else { | |
1434 | driver_data = (struct s5p_mfc_variant *) | |
1435 | platform_get_device_id(pdev)->driver_data; | |
1436 | } | |
1437 | return driver_data; | |
1438 | } | |
1439 | ||
1e393e90 | 1440 | static struct platform_driver s5p_mfc_driver = { |
8f532a7f | 1441 | .probe = s5p_mfc_probe, |
4c62e976 | 1442 | .remove = s5p_mfc_remove, |
8f532a7f | 1443 | .id_table = mfc_driver_ids, |
af935746 KD |
1444 | .driver = { |
1445 | .name = S5P_MFC_NAME, | |
1446 | .owner = THIS_MODULE, | |
b27a23be AK |
1447 | .pm = &s5p_mfc_pm_ops, |
1448 | .of_match_table = exynos_mfc_match, | |
af935746 KD |
1449 | }, |
1450 | }; | |
1451 | ||
1d6629b1 | 1452 | module_platform_driver(s5p_mfc_driver); |
af935746 KD |
1453 | |
1454 | MODULE_LICENSE("GPL"); | |
1455 | MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); | |
1456 | MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); | |
1457 |