Commit | Line | Data |
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af935746 KD |
1 | /* |
2 | * Samsung S5P Multi Format Codec v 5.1 | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Kamil Debski, <k.debski@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
af935746 | 21 | #include <linux/videodev2.h> |
f9f715a9 | 22 | #include <media/v4l2-event.h> |
af935746 | 23 | #include <linux/workqueue.h> |
b27a23be | 24 | #include <linux/of.h> |
c139990e | 25 | #include <media/videobuf2-v4l2.h> |
43a1ea1f | 26 | #include "s5p_mfc_common.h" |
af935746 KD |
27 | #include "s5p_mfc_ctrl.h" |
28 | #include "s5p_mfc_debug.h" | |
29 | #include "s5p_mfc_dec.h" | |
30 | #include "s5p_mfc_enc.h" | |
31 | #include "s5p_mfc_intr.h" | |
43a1ea1f AK |
32 | #include "s5p_mfc_opr.h" |
33 | #include "s5p_mfc_cmd.h" | |
af935746 | 34 | #include "s5p_mfc_pm.h" |
af935746 KD |
35 | |
36 | #define S5P_MFC_NAME "s5p-mfc" | |
37 | #define S5P_MFC_DEC_NAME "s5p-mfc-dec" | |
38 | #define S5P_MFC_ENC_NAME "s5p-mfc-enc" | |
39 | ||
139adba6 MCC |
40 | int mfc_debug_level; |
41 | module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR); | |
af935746 KD |
42 | MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); |
43 | ||
44 | /* Helper functions for interrupt processing */ | |
7fb89eca | 45 | |
af935746 | 46 | /* Remove from hw execution round robin */ |
7fb89eca | 47 | void clear_work_bit(struct s5p_mfc_ctx *ctx) |
af935746 KD |
48 | { |
49 | struct s5p_mfc_dev *dev = ctx->dev; | |
50 | ||
51 | spin_lock(&dev->condlock); | |
7fb89eca | 52 | __clear_bit(ctx->num, &dev->ctx_work_bits); |
af935746 KD |
53 | spin_unlock(&dev->condlock); |
54 | } | |
55 | ||
7fb89eca AH |
56 | /* Add to hw execution round robin */ |
57 | void set_work_bit(struct s5p_mfc_ctx *ctx) | |
58 | { | |
59 | struct s5p_mfc_dev *dev = ctx->dev; | |
60 | ||
61 | spin_lock(&dev->condlock); | |
62 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
63 | spin_unlock(&dev->condlock); | |
64 | } | |
65 | ||
66 | /* Remove from hw execution round robin */ | |
67 | void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
68 | { | |
69 | struct s5p_mfc_dev *dev = ctx->dev; | |
70 | unsigned long flags; | |
71 | ||
72 | spin_lock_irqsave(&dev->condlock, flags); | |
73 | __clear_bit(ctx->num, &dev->ctx_work_bits); | |
74 | spin_unlock_irqrestore(&dev->condlock, flags); | |
75 | } | |
76 | ||
77 | /* Add to hw execution round robin */ | |
78 | void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
79 | { | |
80 | struct s5p_mfc_dev *dev = ctx->dev; | |
81 | unsigned long flags; | |
82 | ||
83 | spin_lock_irqsave(&dev->condlock, flags); | |
84 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
85 | spin_unlock_irqrestore(&dev->condlock, flags); | |
86 | } | |
87 | ||
05d1d0f0 AH |
88 | int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) |
89 | { | |
90 | unsigned long flags; | |
91 | int ctx; | |
92 | ||
93 | spin_lock_irqsave(&dev->condlock, flags); | |
94 | ctx = dev->curr_ctx; | |
95 | do { | |
96 | ctx = (ctx + 1) % MFC_NUM_CONTEXTS; | |
97 | if (ctx == dev->curr_ctx) { | |
98 | if (!test_bit(ctx, &dev->ctx_work_bits)) | |
99 | ctx = -EAGAIN; | |
100 | break; | |
101 | } | |
102 | } while (!test_bit(ctx, &dev->ctx_work_bits)); | |
103 | spin_unlock_irqrestore(&dev->condlock, flags); | |
104 | ||
105 | return ctx; | |
106 | } | |
107 | ||
af935746 KD |
108 | /* Wake up context wait_queue */ |
109 | static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, | |
110 | unsigned int err) | |
111 | { | |
112 | ctx->int_cond = 1; | |
113 | ctx->int_type = reason; | |
114 | ctx->int_err = err; | |
115 | wake_up(&ctx->queue); | |
116 | } | |
117 | ||
118 | /* Wake up device wait_queue */ | |
119 | static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, | |
120 | unsigned int err) | |
121 | { | |
122 | dev->int_cond = 1; | |
123 | dev->int_type = reason; | |
124 | dev->int_err = err; | |
125 | wake_up(&dev->queue); | |
126 | } | |
127 | ||
62bbd72b AH |
128 | void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq) |
129 | { | |
130 | struct s5p_mfc_buf *b; | |
131 | int i; | |
132 | ||
133 | while (!list_empty(lh)) { | |
134 | b = list_entry(lh->next, struct s5p_mfc_buf, list); | |
135 | for (i = 0; i < b->b->vb2_buf.num_planes; i++) | |
136 | vb2_set_plane_payload(&b->b->vb2_buf, i, 0); | |
137 | vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR); | |
138 | list_del(&b->list); | |
139 | } | |
140 | } | |
141 | ||
a13bba4f | 142 | static void s5p_mfc_watchdog(unsigned long arg) |
af935746 KD |
143 | { |
144 | struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; | |
145 | ||
146 | if (test_bit(0, &dev->hw_lock)) | |
147 | atomic_inc(&dev->watchdog_cnt); | |
148 | if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { | |
149 | /* This means that hw is busy and no interrupts were | |
150 | * generated by hw for the Nth time of running this | |
151 | * watchdog timer. This usually means a serious hw | |
152 | * error. Now it is time to kill all instances and | |
153 | * reset the MFC. */ | |
154 | mfc_err("Time out during waiting for HW\n"); | |
155 | queue_work(dev->watchdog_workqueue, &dev->watchdog_work); | |
156 | } | |
157 | dev->watchdog_timer.expires = jiffies + | |
158 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
159 | add_timer(&dev->watchdog_timer); | |
160 | } | |
161 | ||
162 | static void s5p_mfc_watchdog_worker(struct work_struct *work) | |
163 | { | |
164 | struct s5p_mfc_dev *dev; | |
165 | struct s5p_mfc_ctx *ctx; | |
166 | unsigned long flags; | |
167 | int mutex_locked; | |
168 | int i, ret; | |
169 | ||
170 | dev = container_of(work, struct s5p_mfc_dev, watchdog_work); | |
171 | ||
172 | mfc_err("Driver timeout error handling\n"); | |
173 | /* Lock the mutex that protects open and release. | |
174 | * This is necessary as they may load and unload firmware. */ | |
175 | mutex_locked = mutex_trylock(&dev->mfc_mutex); | |
176 | if (!mutex_locked) | |
177 | mfc_err("Error: some instance may be closing/opening\n"); | |
178 | spin_lock_irqsave(&dev->irqlock, flags); | |
179 | ||
180 | s5p_mfc_clock_off(); | |
181 | ||
182 | for (i = 0; i < MFC_NUM_CONTEXTS; i++) { | |
183 | ctx = dev->ctx[i]; | |
184 | if (!ctx) | |
185 | continue; | |
186 | ctx->state = MFCINST_ERROR; | |
62bbd72b AH |
187 | s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); |
188 | s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); | |
af935746 | 189 | clear_work_bit(ctx); |
43a1ea1f | 190 | wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); |
af935746 KD |
191 | } |
192 | clear_bit(0, &dev->hw_lock); | |
193 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
b16e6448 AM |
194 | |
195 | /* De-init MFC */ | |
196 | s5p_mfc_deinit_hw(dev); | |
197 | ||
af935746 KD |
198 | /* Double check if there is at least one instance running. |
199 | * If no instance is in memory than no firmware should be present */ | |
200 | if (dev->num_inst > 0) { | |
46075006 | 201 | ret = s5p_mfc_load_firmware(dev); |
af935746 KD |
202 | if (ret) { |
203 | mfc_err("Failed to reload FW\n"); | |
204 | goto unlock; | |
205 | } | |
206 | s5p_mfc_clock_on(); | |
207 | ret = s5p_mfc_init_hw(dev); | |
208 | if (ret) | |
209 | mfc_err("Failed to reinit FW\n"); | |
210 | } | |
211 | unlock: | |
212 | if (mutex_locked) | |
213 | mutex_unlock(&dev->mfc_mutex); | |
214 | } | |
215 | ||
af935746 KD |
216 | static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) |
217 | { | |
218 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f | 219 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
220 | |
221 | ctx->state = MFCINST_FINISHED; | |
222 | ctx->sequence++; | |
223 | while (!list_empty(&ctx->dst_queue)) { | |
224 | dst_buf = list_entry(ctx->dst_queue.next, | |
225 | struct s5p_mfc_buf, list); | |
226 | mfc_debug(2, "Cleaning up buffer: %d\n", | |
2d700715 JS |
227 | dst_buf->b->vb2_buf.index); |
228 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0); | |
229 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0); | |
af935746 | 230 | list_del(&dst_buf->list); |
4d0b0ed6 | 231 | dst_buf->flags |= MFC_BUF_FLAG_EOS; |
af935746 | 232 | ctx->dst_queue_cnt--; |
2d700715 | 233 | dst_buf->b->sequence = (ctx->sequence++); |
af935746 | 234 | |
43a1ea1f AK |
235 | if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == |
236 | s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) | |
2d700715 | 237 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 238 | else |
2d700715 JS |
239 | dst_buf->b->field = V4L2_FIELD_INTERLACED; |
240 | dst_buf->b->flags |= V4L2_BUF_FLAG_LAST; | |
af935746 | 241 | |
2d700715 JS |
242 | ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index); |
243 | vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE); | |
af935746 KD |
244 | } |
245 | } | |
246 | ||
247 | static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) | |
248 | { | |
249 | struct s5p_mfc_dev *dev = ctx->dev; | |
250 | struct s5p_mfc_buf *dst_buf, *src_buf; | |
43a1ea1f AK |
251 | size_t dec_y_addr; |
252 | unsigned int frame_type; | |
253 | ||
bb21c54a | 254 | /* Make sure we actually have a new frame before continuing. */ |
43a1ea1f | 255 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); |
bb21c54a IF |
256 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) |
257 | return; | |
258 | dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); | |
af935746 KD |
259 | |
260 | /* Copy timestamp / timecode from decoded src to dst and set | |
bb21c54a | 261 | appropriate flags. */ |
af935746 KD |
262 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
263 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
2d700715 JS |
264 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
265 | == dec_y_addr) { | |
266 | dst_buf->b->timecode = | |
267 | src_buf->b->timecode; | |
d6dd645e JS |
268 | dst_buf->b->vb2_buf.timestamp = |
269 | src_buf->b->vb2_buf.timestamp; | |
2d700715 | 270 | dst_buf->b->flags &= |
309f4d62 | 271 | ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
2d700715 JS |
272 | dst_buf->b->flags |= |
273 | src_buf->b->flags | |
309f4d62 | 274 | & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
af935746 KD |
275 | switch (frame_type) { |
276 | case S5P_FIMV_DECODE_FRAME_I_FRAME: | |
2d700715 | 277 | dst_buf->b->flags |= |
af935746 KD |
278 | V4L2_BUF_FLAG_KEYFRAME; |
279 | break; | |
280 | case S5P_FIMV_DECODE_FRAME_P_FRAME: | |
2d700715 | 281 | dst_buf->b->flags |= |
af935746 KD |
282 | V4L2_BUF_FLAG_PFRAME; |
283 | break; | |
284 | case S5P_FIMV_DECODE_FRAME_B_FRAME: | |
2d700715 | 285 | dst_buf->b->flags |= |
af935746 KD |
286 | V4L2_BUF_FLAG_BFRAME; |
287 | break; | |
bb21c54a IF |
288 | default: |
289 | /* Don't know how to handle | |
290 | S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */ | |
291 | mfc_debug(2, "Unexpected frame type: %d\n", | |
292 | frame_type); | |
af935746 KD |
293 | } |
294 | break; | |
295 | } | |
296 | } | |
297 | } | |
298 | ||
299 | static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) | |
300 | { | |
301 | struct s5p_mfc_dev *dev = ctx->dev; | |
302 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f AK |
303 | size_t dspl_y_addr; |
304 | unsigned int frame_type; | |
af935746 | 305 | |
43a1ea1f | 306 | dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); |
7c672812 SS |
307 | if (IS_MFCV6_PLUS(dev)) |
308 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
309 | get_disp_frame_type, ctx); | |
310 | else | |
311 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
312 | get_dec_frame_type, dev); | |
43a1ea1f | 313 | |
af935746 KD |
314 | /* If frame is same as previous then skip and do not dequeue */ |
315 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { | |
316 | if (!ctx->after_packed_pb) | |
317 | ctx->sequence++; | |
318 | ctx->after_packed_pb = 0; | |
319 | return; | |
320 | } | |
321 | ctx->sequence++; | |
322 | /* The MFC returns address of the buffer, now we have to | |
323 | * check which videobuf does it correspond to */ | |
324 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
325 | /* Check if this is the buffer we're looking for */ | |
2d700715 JS |
326 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
327 | == dspl_y_addr) { | |
af935746 KD |
328 | list_del(&dst_buf->list); |
329 | ctx->dst_queue_cnt--; | |
2d700715 | 330 | dst_buf->b->sequence = ctx->sequence; |
43a1ea1f AK |
331 | if (s5p_mfc_hw_call(dev->mfc_ops, |
332 | get_pic_type_top, ctx) == | |
333 | s5p_mfc_hw_call(dev->mfc_ops, | |
334 | get_pic_type_bot, ctx)) | |
2d700715 | 335 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 336 | else |
2d700715 | 337 | dst_buf->b->field = |
af935746 | 338 | V4L2_FIELD_INTERLACED; |
2d700715 JS |
339 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, |
340 | ctx->luma_size); | |
341 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, | |
342 | ctx->chroma_size); | |
343 | clear_bit(dst_buf->b->vb2_buf.index, | |
af935746 KD |
344 | &ctx->dec_dst_flag); |
345 | ||
2d700715 JS |
346 | vb2_buffer_done(&dst_buf->b->vb2_buf, err ? |
347 | VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); | |
af935746 | 348 | |
af935746 KD |
349 | break; |
350 | } | |
351 | } | |
352 | } | |
353 | ||
354 | /* Handle frame decoding interrupt */ | |
355 | static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, | |
356 | unsigned int reason, unsigned int err) | |
357 | { | |
358 | struct s5p_mfc_dev *dev = ctx->dev; | |
359 | unsigned int dst_frame_status; | |
a0517f5d | 360 | unsigned int dec_frame_status; |
af935746 | 361 | struct s5p_mfc_buf *src_buf; |
af935746 KD |
362 | unsigned int res_change; |
363 | ||
43a1ea1f | 364 | dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
af935746 | 365 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; |
a0517f5d PO |
366 | dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev) |
367 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; | |
f96f3cfa JP |
368 | res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
369 | & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) | |
370 | >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; | |
af935746 KD |
371 | mfc_debug(2, "Frame Status: %x\n", dst_frame_status); |
372 | if (ctx->state == MFCINST_RES_CHANGE_INIT) | |
373 | ctx->state = MFCINST_RES_CHANGE_FLUSH; | |
f96f3cfa JP |
374 | if (res_change == S5P_FIMV_RES_INCREASE || |
375 | res_change == S5P_FIMV_RES_DECREASE) { | |
af935746 | 376 | ctx->state = MFCINST_RES_CHANGE_INIT; |
e2c3be2a | 377 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 378 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 379 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 380 | s5p_mfc_clock_off(); |
e2c3be2a | 381 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
382 | return; |
383 | } | |
384 | if (ctx->dpb_flush_flag) | |
385 | ctx->dpb_flush_flag = 0; | |
386 | ||
af935746 KD |
387 | /* All frames remaining in the buffer have been extracted */ |
388 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { | |
389 | if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { | |
0520e4cc PO |
390 | static const struct v4l2_event ev_src_ch = { |
391 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
392 | .u.src_change.changes = | |
393 | V4L2_EVENT_SRC_CH_RESOLUTION, | |
394 | }; | |
395 | ||
af935746 KD |
396 | s5p_mfc_handle_frame_all_extracted(ctx); |
397 | ctx->state = MFCINST_RES_CHANGE_END; | |
0520e4cc PO |
398 | v4l2_event_queue_fh(&ctx->fh, &ev_src_ch); |
399 | ||
af935746 KD |
400 | goto leave_handle_frame; |
401 | } else { | |
402 | s5p_mfc_handle_frame_all_extracted(ctx); | |
403 | } | |
404 | } | |
405 | ||
a0517f5d | 406 | if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) |
af935746 KD |
407 | s5p_mfc_handle_frame_copy_time(ctx); |
408 | ||
409 | /* A frame has been decoded and is in the buffer */ | |
410 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || | |
411 | dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { | |
412 | s5p_mfc_handle_frame_new(ctx, err); | |
413 | } else { | |
414 | mfc_debug(2, "No frame decode\n"); | |
415 | } | |
416 | /* Mark source buffer as complete */ | |
417 | if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY | |
418 | && !list_empty(&ctx->src_queue)) { | |
419 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, | |
420 | list); | |
43a1ea1f AK |
421 | ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, |
422 | get_consumed_stream, dev); | |
423 | if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && | |
f49f3ed5 | 424 | ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC && |
d2a0db1e | 425 | ctx->consumed_stream + STUFF_BYTE < |
2d700715 | 426 | src_buf->b->vb2_buf.planes[0].bytesused) { |
af935746 KD |
427 | /* Run MFC again on the same buffer */ |
428 | mfc_debug(2, "Running again the same buffer\n"); | |
429 | ctx->after_packed_pb = 1; | |
430 | } else { | |
af935746 KD |
431 | mfc_debug(2, "MFC needs next buffer\n"); |
432 | ctx->consumed_stream = 0; | |
a34026e7 KD |
433 | if (src_buf->flags & MFC_BUF_FLAG_EOS) |
434 | ctx->state = MFCINST_FINISHING; | |
af935746 KD |
435 | list_del(&src_buf->list); |
436 | ctx->src_queue_cnt--; | |
43a1ea1f | 437 | if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) |
2d700715 JS |
438 | vb2_buffer_done(&src_buf->b->vb2_buf, |
439 | VB2_BUF_STATE_ERROR); | |
af935746 | 440 | else |
2d700715 JS |
441 | vb2_buffer_done(&src_buf->b->vb2_buf, |
442 | VB2_BUF_STATE_DONE); | |
af935746 KD |
443 | } |
444 | } | |
445 | leave_handle_frame: | |
af935746 | 446 | if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) |
e9d98ddc | 447 | || ctx->dst_queue_cnt < ctx->pb_count) |
af935746 | 448 | clear_work_bit(ctx); |
e2c3be2a | 449 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 450 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 451 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 452 | s5p_mfc_clock_off(); |
76a4ddbd P |
453 | /* if suspending, wake up device and do not try_run again*/ |
454 | if (test_bit(0, &dev->enter_suspend)) | |
455 | wake_up_dev(dev, reason, err); | |
456 | else | |
e2c3be2a | 457 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
458 | } |
459 | ||
460 | /* Error handling for interrupt */ | |
7296e25f KD |
461 | static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, |
462 | struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) | |
af935746 | 463 | { |
af935746 | 464 | mfc_err("Interrupt Error: %08x\n", err); |
af935746 | 465 | |
7296e25f KD |
466 | if (ctx != NULL) { |
467 | /* Error recovery is dependent on the state of context */ | |
468 | switch (ctx->state) { | |
469 | case MFCINST_RES_CHANGE_INIT: | |
470 | case MFCINST_RES_CHANGE_FLUSH: | |
471 | case MFCINST_RES_CHANGE_END: | |
472 | case MFCINST_FINISHING: | |
473 | case MFCINST_FINISHED: | |
474 | case MFCINST_RUNNING: | |
39c1cb2b | 475 | /* It is highly probable that an error occurred |
7296e25f KD |
476 | * while decoding a frame */ |
477 | clear_work_bit(ctx); | |
478 | ctx->state = MFCINST_ERROR; | |
479 | /* Mark all dst buffers as having an error */ | |
62bbd72b | 480 | s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); |
7296e25f | 481 | /* Mark all src buffers as having an error */ |
62bbd72b | 482 | s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); |
7296e25f KD |
483 | wake_up_ctx(ctx, reason, err); |
484 | break; | |
485 | default: | |
486 | clear_work_bit(ctx); | |
487 | ctx->state = MFCINST_ERROR; | |
488 | wake_up_ctx(ctx, reason, err); | |
489 | break; | |
490 | } | |
af935746 | 491 | } |
9a7bc6b0 | 492 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
e2c3be2a | 493 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
7296e25f KD |
494 | s5p_mfc_clock_off(); |
495 | wake_up_dev(dev, reason, err); | |
af935746 KD |
496 | return; |
497 | } | |
498 | ||
499 | /* Header parsing interrupt handling */ | |
500 | static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, | |
501 | unsigned int reason, unsigned int err) | |
502 | { | |
503 | struct s5p_mfc_dev *dev; | |
af935746 | 504 | |
1259762f | 505 | if (ctx == NULL) |
af935746 KD |
506 | return; |
507 | dev = ctx->dev; | |
508 | if (ctx->c_ops->post_seq_start) { | |
509 | if (ctx->c_ops->post_seq_start(ctx)) | |
510 | mfc_err("post_seq_start() failed\n"); | |
511 | } else { | |
43a1ea1f AK |
512 | ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, |
513 | dev); | |
514 | ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, | |
515 | dev); | |
af935746 | 516 | |
e2c3be2a | 517 | s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx); |
8f532a7f | 518 | |
e9d98ddc | 519 | ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, |
43a1ea1f | 520 | dev); |
f96f3cfa JP |
521 | ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, |
522 | dev); | |
bb869368 | 523 | if (ctx->img_width == 0 || ctx->img_height == 0) |
af935746 KD |
524 | ctx->state = MFCINST_ERROR; |
525 | else | |
526 | ctx->state = MFCINST_HEAD_PARSED; | |
f96f3cfa JP |
527 | |
528 | if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
529 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && | |
530 | !list_empty(&ctx->src_queue)) { | |
531 | struct s5p_mfc_buf *src_buf; | |
532 | src_buf = list_entry(ctx->src_queue.next, | |
533 | struct s5p_mfc_buf, list); | |
534 | if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, | |
535 | dev) < | |
2d700715 | 536 | src_buf->b->vb2_buf.planes[0].bytesused) |
f96f3cfa JP |
537 | ctx->head_processed = 0; |
538 | else | |
539 | ctx->head_processed = 1; | |
540 | } else { | |
541 | ctx->head_processed = 1; | |
542 | } | |
af935746 | 543 | } |
e2c3be2a | 544 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 545 | clear_work_bit(ctx); |
9a7bc6b0 | 546 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 547 | s5p_mfc_clock_off(); |
e2c3be2a | 548 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
549 | wake_up_ctx(ctx, reason, err); |
550 | } | |
551 | ||
552 | /* Header parsing interrupt handling */ | |
553 | static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, | |
554 | unsigned int reason, unsigned int err) | |
555 | { | |
556 | struct s5p_mfc_buf *src_buf; | |
557 | struct s5p_mfc_dev *dev; | |
af935746 | 558 | |
1259762f | 559 | if (ctx == NULL) |
af935746 KD |
560 | return; |
561 | dev = ctx->dev; | |
e2c3be2a | 562 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
563 | ctx->int_type = reason; |
564 | ctx->int_err = err; | |
565 | ctx->int_cond = 1; | |
7fb89eca | 566 | clear_work_bit(ctx); |
af935746 KD |
567 | if (err == 0) { |
568 | ctx->state = MFCINST_RUNNING; | |
f96f3cfa | 569 | if (!ctx->dpb_flush_flag && ctx->head_processed) { |
af935746 KD |
570 | if (!list_empty(&ctx->src_queue)) { |
571 | src_buf = list_entry(ctx->src_queue.next, | |
572 | struct s5p_mfc_buf, list); | |
573 | list_del(&src_buf->list); | |
574 | ctx->src_queue_cnt--; | |
2d700715 | 575 | vb2_buffer_done(&src_buf->b->vb2_buf, |
af935746 KD |
576 | VB2_BUF_STATE_DONE); |
577 | } | |
af935746 KD |
578 | } else { |
579 | ctx->dpb_flush_flag = 0; | |
580 | } | |
9a7bc6b0 | 581 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
582 | |
583 | s5p_mfc_clock_off(); | |
584 | ||
585 | wake_up(&ctx->queue); | |
e2c3be2a | 586 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 | 587 | } else { |
9a7bc6b0 | 588 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
589 | |
590 | s5p_mfc_clock_off(); | |
591 | ||
592 | wake_up(&ctx->queue); | |
593 | } | |
594 | } | |
595 | ||
96c57776 | 596 | static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx) |
f9f715a9 AH |
597 | { |
598 | struct s5p_mfc_dev *dev = ctx->dev; | |
599 | struct s5p_mfc_buf *mb_entry; | |
600 | ||
4130eabc | 601 | mfc_debug(2, "Stream completed\n"); |
f9f715a9 | 602 | |
f9f715a9 AH |
603 | ctx->state = MFCINST_FINISHED; |
604 | ||
f9f715a9 AH |
605 | if (!list_empty(&ctx->dst_queue)) { |
606 | mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, | |
607 | list); | |
608 | list_del(&mb_entry->list); | |
609 | ctx->dst_queue_cnt--; | |
2d700715 JS |
610 | vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0); |
611 | vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE); | |
f9f715a9 | 612 | } |
f9f715a9 AH |
613 | |
614 | clear_work_bit(ctx); | |
615 | ||
e8256447 | 616 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
f9f715a9 AH |
617 | |
618 | s5p_mfc_clock_off(); | |
619 | wake_up(&ctx->queue); | |
e2c3be2a | 620 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
f9f715a9 AH |
621 | } |
622 | ||
af935746 KD |
623 | /* Interrupt processing */ |
624 | static irqreturn_t s5p_mfc_irq(int irq, void *priv) | |
625 | { | |
626 | struct s5p_mfc_dev *dev = priv; | |
627 | struct s5p_mfc_ctx *ctx; | |
628 | unsigned int reason; | |
629 | unsigned int err; | |
630 | ||
631 | mfc_debug_enter(); | |
632 | /* Reset the timeout watchdog */ | |
633 | atomic_set(&dev->watchdog_cnt, 0); | |
7969b125 | 634 | spin_lock(&dev->irqlock); |
af935746 KD |
635 | ctx = dev->ctx[dev->curr_ctx]; |
636 | /* Get the reason of interrupt and the error code */ | |
43a1ea1f AK |
637 | reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); |
638 | err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); | |
af935746 KD |
639 | mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); |
640 | switch (reason) { | |
43a1ea1f | 641 | case S5P_MFC_R2H_CMD_ERR_RET: |
39c1cb2b | 642 | /* An error has occurred */ |
af935746 | 643 | if (ctx->state == MFCINST_RUNNING && |
43a1ea1f AK |
644 | s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= |
645 | dev->warn_start) | |
af935746 KD |
646 | s5p_mfc_handle_frame(ctx, reason, err); |
647 | else | |
7296e25f | 648 | s5p_mfc_handle_error(dev, ctx, reason, err); |
af935746 KD |
649 | clear_bit(0, &dev->enter_suspend); |
650 | break; | |
651 | ||
43a1ea1f AK |
652 | case S5P_MFC_R2H_CMD_SLICE_DONE_RET: |
653 | case S5P_MFC_R2H_CMD_FIELD_DONE_RET: | |
654 | case S5P_MFC_R2H_CMD_FRAME_DONE_RET: | |
af935746 KD |
655 | if (ctx->c_ops->post_frame_start) { |
656 | if (ctx->c_ops->post_frame_start(ctx)) | |
657 | mfc_err("post_frame_start() failed\n"); | |
96c57776 AH |
658 | |
659 | if (ctx->state == MFCINST_FINISHING && | |
660 | list_empty(&ctx->ref_queue)) { | |
661 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); | |
662 | s5p_mfc_handle_stream_complete(ctx); | |
663 | break; | |
664 | } | |
e2c3be2a | 665 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 666 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 667 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 668 | s5p_mfc_clock_off(); |
e2c3be2a | 669 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
af935746 KD |
670 | } else { |
671 | s5p_mfc_handle_frame(ctx, reason, err); | |
672 | } | |
673 | break; | |
674 | ||
43a1ea1f | 675 | case S5P_MFC_R2H_CMD_SEQ_DONE_RET: |
af935746 KD |
676 | s5p_mfc_handle_seq_done(ctx, reason, err); |
677 | break; | |
678 | ||
43a1ea1f AK |
679 | case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: |
680 | ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); | |
af935746 KD |
681 | ctx->state = MFCINST_GOT_INST; |
682 | clear_work_bit(ctx); | |
683 | wake_up(&ctx->queue); | |
684 | goto irq_cleanup_hw; | |
685 | ||
43a1ea1f | 686 | case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: |
af935746 | 687 | clear_work_bit(ctx); |
9d87e837 | 688 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 KD |
689 | ctx->state = MFCINST_FREE; |
690 | wake_up(&ctx->queue); | |
691 | goto irq_cleanup_hw; | |
692 | ||
43a1ea1f AK |
693 | case S5P_MFC_R2H_CMD_SYS_INIT_RET: |
694 | case S5P_MFC_R2H_CMD_FW_STATUS_RET: | |
695 | case S5P_MFC_R2H_CMD_SLEEP_RET: | |
696 | case S5P_MFC_R2H_CMD_WAKEUP_RET: | |
af935746 KD |
697 | if (ctx) |
698 | clear_work_bit(ctx); | |
e2c3be2a | 699 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
700 | wake_up_dev(dev, reason, err); |
701 | clear_bit(0, &dev->hw_lock); | |
702 | clear_bit(0, &dev->enter_suspend); | |
703 | break; | |
704 | ||
43a1ea1f | 705 | case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: |
af935746 KD |
706 | s5p_mfc_handle_init_buffers(ctx, reason, err); |
707 | break; | |
f9f715a9 | 708 | |
43a1ea1f | 709 | case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: |
96c57776 AH |
710 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
711 | ctx->int_type = reason; | |
712 | ctx->int_err = err; | |
713 | s5p_mfc_handle_stream_complete(ctx); | |
f9f715a9 AH |
714 | break; |
715 | ||
8f23cc02 AK |
716 | case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: |
717 | clear_work_bit(ctx); | |
718 | ctx->state = MFCINST_RUNNING; | |
719 | wake_up(&ctx->queue); | |
720 | goto irq_cleanup_hw; | |
721 | ||
af935746 KD |
722 | default: |
723 | mfc_debug(2, "Unknown int reason\n"); | |
e2c3be2a | 724 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 725 | } |
7969b125 | 726 | spin_unlock(&dev->irqlock); |
af935746 KD |
727 | mfc_debug_leave(); |
728 | return IRQ_HANDLED; | |
729 | irq_cleanup_hw: | |
e2c3be2a | 730 | s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
731 | ctx->int_type = reason; |
732 | ctx->int_err = err; | |
733 | ctx->int_cond = 1; | |
734 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
735 | mfc_err("Failed to unlock hw\n"); | |
736 | ||
737 | s5p_mfc_clock_off(); | |
738 | ||
e2c3be2a | 739 | s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev); |
7969b125 | 740 | spin_unlock(&dev->irqlock); |
af935746 KD |
741 | mfc_debug(2, "Exit via irq_cleanup_hw\n"); |
742 | return IRQ_HANDLED; | |
743 | } | |
744 | ||
745 | /* Open an MFC node */ | |
746 | static int s5p_mfc_open(struct file *file) | |
747 | { | |
b80cb8dc | 748 | struct video_device *vdev = video_devdata(file); |
af935746 KD |
749 | struct s5p_mfc_dev *dev = video_drvdata(file); |
750 | struct s5p_mfc_ctx *ctx = NULL; | |
751 | struct vb2_queue *q; | |
af935746 KD |
752 | int ret = 0; |
753 | ||
754 | mfc_debug_enter(); | |
bc738301 HV |
755 | if (mutex_lock_interruptible(&dev->mfc_mutex)) |
756 | return -ERESTARTSYS; | |
af935746 KD |
757 | dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ |
758 | /* Allocate memory for context */ | |
bae061b4 | 759 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
af935746 KD |
760 | if (!ctx) { |
761 | mfc_err("Not enough memory\n"); | |
762 | ret = -ENOMEM; | |
763 | goto err_alloc; | |
764 | } | |
55647a99 | 765 | v4l2_fh_init(&ctx->fh, vdev); |
af935746 KD |
766 | file->private_data = &ctx->fh; |
767 | v4l2_fh_add(&ctx->fh); | |
768 | ctx->dev = dev; | |
769 | INIT_LIST_HEAD(&ctx->src_queue); | |
770 | INIT_LIST_HEAD(&ctx->dst_queue); | |
771 | ctx->src_queue_cnt = 0; | |
772 | ctx->dst_queue_cnt = 0; | |
773 | /* Get context number */ | |
774 | ctx->num = 0; | |
775 | while (dev->ctx[ctx->num]) { | |
776 | ctx->num++; | |
777 | if (ctx->num >= MFC_NUM_CONTEXTS) { | |
778 | mfc_err("Too many open contexts\n"); | |
779 | ret = -EBUSY; | |
780 | goto err_no_ctx; | |
781 | } | |
782 | } | |
783 | /* Mark context as idle */ | |
7fb89eca | 784 | clear_work_bit_irqsave(ctx); |
af935746 | 785 | dev->ctx[ctx->num] = ctx; |
b80cb8dc | 786 | if (vdev == dev->vfd_dec) { |
af935746 KD |
787 | ctx->type = MFCINST_DECODER; |
788 | ctx->c_ops = get_dec_codec_ops(); | |
43a1ea1f | 789 | s5p_mfc_dec_init(ctx); |
af935746 KD |
790 | /* Setup ctrl handler */ |
791 | ret = s5p_mfc_dec_ctrls_setup(ctx); | |
792 | if (ret) { | |
793 | mfc_err("Failed to setup mfc controls\n"); | |
794 | goto err_ctrls_setup; | |
795 | } | |
b80cb8dc | 796 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
797 | ctx->type = MFCINST_ENCODER; |
798 | ctx->c_ops = get_enc_codec_ops(); | |
799 | /* only for encoder */ | |
800 | INIT_LIST_HEAD(&ctx->ref_queue); | |
801 | ctx->ref_queue_cnt = 0; | |
43a1ea1f | 802 | s5p_mfc_enc_init(ctx); |
af935746 KD |
803 | /* Setup ctrl handler */ |
804 | ret = s5p_mfc_enc_ctrls_setup(ctx); | |
805 | if (ret) { | |
806 | mfc_err("Failed to setup mfc controls\n"); | |
807 | goto err_ctrls_setup; | |
808 | } | |
809 | } else { | |
810 | ret = -ENOENT; | |
811 | goto err_bad_node; | |
812 | } | |
813 | ctx->fh.ctrl_handler = &ctx->ctrl_handler; | |
9d87e837 | 814 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 KD |
815 | /* Load firmware if this is the first instance */ |
816 | if (dev->num_inst == 1) { | |
817 | dev->watchdog_timer.expires = jiffies + | |
818 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
819 | add_timer(&dev->watchdog_timer); | |
820 | ret = s5p_mfc_power_on(); | |
821 | if (ret < 0) { | |
822 | mfc_err("power on failed\n"); | |
823 | goto err_pwr_enable; | |
824 | } | |
825 | s5p_mfc_clock_on(); | |
2e731e44 KD |
826 | ret = s5p_mfc_load_firmware(dev); |
827 | if (ret) { | |
828 | s5p_mfc_clock_off(); | |
829 | goto err_load_fw; | |
830 | } | |
af935746 KD |
831 | /* Init the FW */ |
832 | ret = s5p_mfc_init_hw(dev); | |
2e731e44 | 833 | s5p_mfc_clock_off(); |
af935746 KD |
834 | if (ret) |
835 | goto err_init_hw; | |
af935746 KD |
836 | } |
837 | /* Init videobuf2 queue for CAPTURE */ | |
838 | q = &ctx->vq_dst; | |
839 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
840 | q->drv_priv = &ctx->fh; | |
654a731b | 841 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 842 | if (vdev == dev->vfd_dec) { |
af935746 KD |
843 | q->io_modes = VB2_MMAP; |
844 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 845 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
846 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
847 | q->ops = get_enc_queue_ops(); | |
848 | } else { | |
849 | ret = -ENOENT; | |
850 | goto err_queue_init; | |
851 | } | |
749ae716 | 852 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 853 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
854 | ret = vb2_queue_init(q); |
855 | if (ret) { | |
856 | mfc_err("Failed to initialize videobuf2 queue(capture)\n"); | |
857 | goto err_queue_init; | |
858 | } | |
859 | /* Init videobuf2 queue for OUTPUT */ | |
860 | q = &ctx->vq_src; | |
861 | q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
862 | q->io_modes = VB2_MMAP; | |
863 | q->drv_priv = &ctx->fh; | |
41f03a00 | 864 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 865 | if (vdev == dev->vfd_dec) { |
af935746 KD |
866 | q->io_modes = VB2_MMAP; |
867 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 868 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
869 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
870 | q->ops = get_enc_queue_ops(); | |
871 | } else { | |
872 | ret = -ENOENT; | |
873 | goto err_queue_init; | |
874 | } | |
e6c9dec3 KD |
875 | /* One way to indicate end-of-stream for MFC is to set the |
876 | * bytesused == 0. However by default videobuf2 handles bytesused | |
877 | * equal to 0 as a special case and changes its value to the size | |
878 | * of the buffer. Set the allow_zero_bytesused flag so that videobuf2 | |
879 | * will keep the value of bytesused intact. | |
880 | */ | |
881 | q->allow_zero_bytesused = 1; | |
749ae716 | 882 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 883 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
884 | ret = vb2_queue_init(q); |
885 | if (ret) { | |
886 | mfc_err("Failed to initialize videobuf2 queue(output)\n"); | |
887 | goto err_queue_init; | |
888 | } | |
889 | init_waitqueue_head(&ctx->queue); | |
bc738301 | 890 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
891 | mfc_debug_leave(); |
892 | return ret; | |
39c1cb2b | 893 | /* Deinit when failure occurred */ |
af935746 | 894 | err_queue_init: |
2e731e44 KD |
895 | if (dev->num_inst == 1) |
896 | s5p_mfc_deinit_hw(dev); | |
af935746 | 897 | err_init_hw: |
2e731e44 | 898 | err_load_fw: |
af935746 KD |
899 | err_pwr_enable: |
900 | if (dev->num_inst == 1) { | |
901 | if (s5p_mfc_power_off() < 0) | |
902 | mfc_err("power off failed\n"); | |
1b73ba0b | 903 | del_timer_sync(&dev->watchdog_timer); |
af935746 KD |
904 | } |
905 | err_ctrls_setup: | |
906 | s5p_mfc_dec_ctrls_delete(ctx); | |
907 | err_bad_node: | |
1b73ba0b | 908 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
909 | err_no_ctx: |
910 | v4l2_fh_del(&ctx->fh); | |
911 | v4l2_fh_exit(&ctx->fh); | |
912 | kfree(ctx); | |
913 | err_alloc: | |
914 | dev->num_inst--; | |
bc738301 | 915 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
916 | mfc_debug_leave(); |
917 | return ret; | |
918 | } | |
919 | ||
920 | /* Release MFC context */ | |
921 | static int s5p_mfc_release(struct file *file) | |
922 | { | |
923 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
924 | struct s5p_mfc_dev *dev = ctx->dev; | |
af935746 KD |
925 | |
926 | mfc_debug_enter(); | |
bc738301 | 927 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
928 | s5p_mfc_clock_on(); |
929 | vb2_queue_release(&ctx->vq_src); | |
930 | vb2_queue_release(&ctx->vq_dst); | |
931 | /* Mark context as idle */ | |
7fb89eca | 932 | clear_work_bit_irqsave(ctx); |
9d87e837 | 933 | /* If instance was initialised and not yet freed, |
39c1cb2b | 934 | * return instance and free resources */ |
9d87e837 | 935 | if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) { |
af935746 | 936 | mfc_debug(2, "Has to free instance\n"); |
818cd91a | 937 | s5p_mfc_close_mfc_inst(dev, ctx); |
af935746 KD |
938 | } |
939 | /* hardware locking scheme */ | |
940 | if (dev->curr_ctx == ctx->num) | |
941 | clear_bit(0, &dev->hw_lock); | |
942 | dev->num_inst--; | |
943 | if (dev->num_inst == 0) { | |
2e731e44 | 944 | mfc_debug(2, "Last instance\n"); |
43a1ea1f | 945 | s5p_mfc_deinit_hw(dev); |
af935746 KD |
946 | del_timer_sync(&dev->watchdog_timer); |
947 | if (s5p_mfc_power_off() < 0) | |
948 | mfc_err("Power off failed\n"); | |
949 | } | |
950 | mfc_debug(2, "Shutting down clock\n"); | |
951 | s5p_mfc_clock_off(); | |
1259762f | 952 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
953 | s5p_mfc_dec_ctrls_delete(ctx); |
954 | v4l2_fh_del(&ctx->fh); | |
955 | v4l2_fh_exit(&ctx->fh); | |
956 | kfree(ctx); | |
957 | mfc_debug_leave(); | |
bc738301 | 958 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
959 | return 0; |
960 | } | |
961 | ||
962 | /* Poll */ | |
963 | static unsigned int s5p_mfc_poll(struct file *file, | |
964 | struct poll_table_struct *wait) | |
965 | { | |
966 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
967 | struct s5p_mfc_dev *dev = ctx->dev; | |
968 | struct vb2_queue *src_q, *dst_q; | |
969 | struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; | |
970 | unsigned int rc = 0; | |
971 | unsigned long flags; | |
972 | ||
bc738301 | 973 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
974 | src_q = &ctx->vq_src; |
975 | dst_q = &ctx->vq_dst; | |
976 | /* | |
977 | * There has to be at least one buffer queued on each queued_list, which | |
978 | * means either in driver already or waiting for driver to claim it | |
979 | * and start processing. | |
980 | */ | |
981 | if ((!src_q->streaming || list_empty(&src_q->queued_list)) | |
982 | && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { | |
983 | rc = POLLERR; | |
984 | goto end; | |
985 | } | |
986 | mutex_unlock(&dev->mfc_mutex); | |
f9f715a9 | 987 | poll_wait(file, &ctx->fh.wait, wait); |
af935746 KD |
988 | poll_wait(file, &src_q->done_wq, wait); |
989 | poll_wait(file, &dst_q->done_wq, wait); | |
990 | mutex_lock(&dev->mfc_mutex); | |
f9f715a9 AH |
991 | if (v4l2_event_pending(&ctx->fh)) |
992 | rc |= POLLPRI; | |
af935746 KD |
993 | spin_lock_irqsave(&src_q->done_lock, flags); |
994 | if (!list_empty(&src_q->done_list)) | |
995 | src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, | |
996 | done_entry); | |
997 | if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE | |
998 | || src_vb->state == VB2_BUF_STATE_ERROR)) | |
999 | rc |= POLLOUT | POLLWRNORM; | |
1000 | spin_unlock_irqrestore(&src_q->done_lock, flags); | |
1001 | spin_lock_irqsave(&dst_q->done_lock, flags); | |
1002 | if (!list_empty(&dst_q->done_list)) | |
1003 | dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, | |
1004 | done_entry); | |
1005 | if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE | |
1006 | || dst_vb->state == VB2_BUF_STATE_ERROR)) | |
1007 | rc |= POLLIN | POLLRDNORM; | |
1008 | spin_unlock_irqrestore(&dst_q->done_lock, flags); | |
1009 | end: | |
bc738301 | 1010 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
1011 | return rc; |
1012 | } | |
1013 | ||
1014 | /* Mmap */ | |
1015 | static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) | |
1016 | { | |
1017 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
bc738301 | 1018 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
1019 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
1020 | int ret; | |
bc738301 HV |
1021 | |
1022 | if (mutex_lock_interruptible(&dev->mfc_mutex)) | |
1023 | return -ERESTARTSYS; | |
af935746 KD |
1024 | if (offset < DST_QUEUE_OFF_BASE) { |
1025 | mfc_debug(2, "mmaping source\n"); | |
1026 | ret = vb2_mmap(&ctx->vq_src, vma); | |
1027 | } else { /* capture */ | |
1028 | mfc_debug(2, "mmaping destination\n"); | |
1029 | vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); | |
1030 | ret = vb2_mmap(&ctx->vq_dst, vma); | |
1031 | } | |
bc738301 | 1032 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
1033 | return ret; |
1034 | } | |
1035 | ||
1036 | /* v4l2 ops */ | |
1037 | static const struct v4l2_file_operations s5p_mfc_fops = { | |
1038 | .owner = THIS_MODULE, | |
1039 | .open = s5p_mfc_open, | |
1040 | .release = s5p_mfc_release, | |
1041 | .poll = s5p_mfc_poll, | |
1042 | .unlocked_ioctl = video_ioctl2, | |
1043 | .mmap = s5p_mfc_mmap, | |
1044 | }; | |
1045 | ||
1046 | static int match_child(struct device *dev, void *data) | |
1047 | { | |
1048 | if (!dev_name(dev)) | |
1049 | return 0; | |
1050 | return !strcmp(dev_name(dev), (char *)data); | |
1051 | } | |
1052 | ||
b27a23be AK |
1053 | static void *mfc_get_drv_data(struct platform_device *pdev); |
1054 | ||
6e83e6e2 AK |
1055 | static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) |
1056 | { | |
65fccab5 | 1057 | unsigned int mem_info[2] = { }; |
6e83e6e2 AK |
1058 | |
1059 | dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, | |
1060 | sizeof(struct device), GFP_KERNEL); | |
1061 | if (!dev->mem_dev_l) { | |
1062 | mfc_err("Not enough memory\n"); | |
1063 | return -ENOMEM; | |
1064 | } | |
1065 | device_initialize(dev->mem_dev_l); | |
1066 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1067 | "samsung,mfc-l", mem_info, 2); | |
1068 | if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], | |
1069 | mem_info[0], mem_info[1], | |
1070 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1071 | mfc_err("Failed to declare coherent memory for\n" | |
1072 | "MFC device\n"); | |
1073 | return -ENOMEM; | |
1074 | } | |
1075 | ||
1076 | dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, | |
1077 | sizeof(struct device), GFP_KERNEL); | |
1078 | if (!dev->mem_dev_r) { | |
1079 | mfc_err("Not enough memory\n"); | |
1080 | return -ENOMEM; | |
1081 | } | |
1082 | device_initialize(dev->mem_dev_r); | |
1083 | of_property_read_u32_array(dev->plat_dev->dev.of_node, | |
1084 | "samsung,mfc-r", mem_info, 2); | |
1085 | if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], | |
1086 | mem_info[0], mem_info[1], | |
1087 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { | |
1088 | pr_err("Failed to declare coherent memory for\n" | |
1089 | "MFC device\n"); | |
1090 | return -ENOMEM; | |
1091 | } | |
1092 | return 0; | |
1093 | } | |
1094 | ||
af935746 | 1095 | /* MFC probe function */ |
1e393e90 | 1096 | static int s5p_mfc_probe(struct platform_device *pdev) |
af935746 KD |
1097 | { |
1098 | struct s5p_mfc_dev *dev; | |
1099 | struct video_device *vfd; | |
1100 | struct resource *res; | |
1101 | int ret; | |
1102 | ||
1103 | pr_debug("%s++\n", __func__); | |
bae061b4 | 1104 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
af935746 KD |
1105 | if (!dev) { |
1106 | dev_err(&pdev->dev, "Not enough memory for MFC device\n"); | |
1107 | return -ENOMEM; | |
1108 | } | |
1109 | ||
1110 | spin_lock_init(&dev->irqlock); | |
1111 | spin_lock_init(&dev->condlock); | |
1112 | dev->plat_dev = pdev; | |
1113 | if (!dev->plat_dev) { | |
1114 | dev_err(&pdev->dev, "No platform data specified\n"); | |
d310f478 | 1115 | return -ENODEV; |
af935746 KD |
1116 | } |
1117 | ||
b27a23be | 1118 | dev->variant = mfc_get_drv_data(pdev); |
8f532a7f | 1119 | |
af935746 KD |
1120 | ret = s5p_mfc_init_pm(dev); |
1121 | if (ret < 0) { | |
1122 | dev_err(&pdev->dev, "failed to get mfc clock source\n"); | |
d310f478 | 1123 | return ret; |
af935746 KD |
1124 | } |
1125 | ||
1126 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
af935746 | 1127 | |
f23999ec TR |
1128 | dev->regs_base = devm_ioremap_resource(&pdev->dev, res); |
1129 | if (IS_ERR(dev->regs_base)) | |
1130 | return PTR_ERR(dev->regs_base); | |
af935746 KD |
1131 | |
1132 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1133 | if (res == NULL) { | |
1134 | dev_err(&pdev->dev, "failed to get irq resource\n"); | |
1135 | ret = -ENOENT; | |
d310f478 | 1136 | goto err_res; |
af935746 KD |
1137 | } |
1138 | dev->irq = res->start; | |
d310f478 | 1139 | ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, |
1957f0d7 | 1140 | 0, pdev->name, dev); |
af935746 KD |
1141 | if (ret) { |
1142 | dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); | |
d310f478 | 1143 | goto err_res; |
af935746 KD |
1144 | } |
1145 | ||
b27a23be | 1146 | if (pdev->dev.of_node) { |
d68b44e0 WY |
1147 | ret = s5p_mfc_alloc_memdevs(dev); |
1148 | if (ret < 0) | |
b27a23be | 1149 | goto err_res; |
b27a23be AK |
1150 | } else { |
1151 | dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, | |
1152 | "s5p-mfc-l", match_child); | |
1153 | if (!dev->mem_dev_l) { | |
1154 | mfc_err("Mem child (L) device get failed\n"); | |
1155 | ret = -ENODEV; | |
1156 | goto err_res; | |
1157 | } | |
1158 | dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, | |
1159 | "s5p-mfc-r", match_child); | |
1160 | if (!dev->mem_dev_r) { | |
1161 | mfc_err("Mem child (R) device get failed\n"); | |
1162 | ret = -ENODEV; | |
1163 | goto err_res; | |
1164 | } | |
af935746 KD |
1165 | } |
1166 | ||
1167 | dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); | |
ef89fff8 | 1168 | if (IS_ERR(dev->alloc_ctx[0])) { |
af935746 | 1169 | ret = PTR_ERR(dev->alloc_ctx[0]); |
d310f478 | 1170 | goto err_res; |
af935746 KD |
1171 | } |
1172 | dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); | |
ef89fff8 | 1173 | if (IS_ERR(dev->alloc_ctx[1])) { |
af935746 KD |
1174 | ret = PTR_ERR(dev->alloc_ctx[1]); |
1175 | goto err_mem_init_ctx_1; | |
1176 | } | |
1177 | ||
1178 | mutex_init(&dev->mfc_mutex); | |
1179 | ||
2e731e44 KD |
1180 | ret = s5p_mfc_alloc_firmware(dev); |
1181 | if (ret) | |
1182 | goto err_alloc_fw; | |
1183 | ||
af935746 KD |
1184 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); |
1185 | if (ret) | |
1186 | goto err_v4l2_dev_reg; | |
1187 | init_waitqueue_head(&dev->queue); | |
1188 | ||
1189 | /* decoder */ | |
1190 | vfd = video_device_alloc(); | |
1191 | if (!vfd) { | |
1192 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1193 | ret = -ENOMEM; | |
1194 | goto err_dec_alloc; | |
1195 | } | |
d0ce898c | 1196 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1197 | vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); |
d0ce898c | 1198 | vfd->release = video_device_release; |
af935746 KD |
1199 | vfd->lock = &dev->mfc_mutex; |
1200 | vfd->v4l2_dev = &dev->v4l2_dev; | |
954f340f | 1201 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1202 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); |
1203 | dev->vfd_dec = vfd; | |
1204 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1205 | if (ret) { | |
1206 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1207 | video_device_release(vfd); | |
1208 | goto err_dec_reg; | |
1209 | } | |
1210 | v4l2_info(&dev->v4l2_dev, | |
1211 | "decoder registered as /dev/video%d\n", vfd->num); | |
1212 | video_set_drvdata(vfd, dev); | |
1213 | ||
1214 | /* encoder */ | |
1215 | vfd = video_device_alloc(); | |
1216 | if (!vfd) { | |
1217 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1218 | ret = -ENOMEM; | |
1219 | goto err_enc_alloc; | |
1220 | } | |
d0ce898c | 1221 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1222 | vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); |
d0ce898c | 1223 | vfd->release = video_device_release; |
af935746 KD |
1224 | vfd->lock = &dev->mfc_mutex; |
1225 | vfd->v4l2_dev = &dev->v4l2_dev; | |
cdcf45e7 | 1226 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1227 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); |
1228 | dev->vfd_enc = vfd; | |
1229 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
1230 | if (ret) { | |
1231 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
1232 | video_device_release(vfd); | |
1233 | goto err_enc_reg; | |
1234 | } | |
1235 | v4l2_info(&dev->v4l2_dev, | |
1236 | "encoder registered as /dev/video%d\n", vfd->num); | |
1237 | video_set_drvdata(vfd, dev); | |
1238 | platform_set_drvdata(pdev, dev); | |
1239 | ||
1240 | dev->hw_lock = 0; | |
1241 | dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); | |
1242 | INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); | |
1243 | atomic_set(&dev->watchdog_cnt, 0); | |
1244 | init_timer(&dev->watchdog_timer); | |
1245 | dev->watchdog_timer.data = (unsigned long)dev; | |
1246 | dev->watchdog_timer.function = s5p_mfc_watchdog; | |
1247 | ||
43a1ea1f AK |
1248 | /* Initialize HW ops and commands based on MFC version */ |
1249 | s5p_mfc_init_hw_ops(dev); | |
1250 | s5p_mfc_init_hw_cmds(dev); | |
6a9c6f68 | 1251 | s5p_mfc_init_regs(dev); |
43a1ea1f | 1252 | |
af935746 KD |
1253 | pr_debug("%s--\n", __func__); |
1254 | return 0; | |
1255 | ||
1256 | /* Deinit MFC if probe had failed */ | |
1257 | err_enc_reg: | |
1258 | video_device_release(dev->vfd_enc); | |
1259 | err_enc_alloc: | |
1260 | video_unregister_device(dev->vfd_dec); | |
1261 | err_dec_reg: | |
1262 | video_device_release(dev->vfd_dec); | |
1263 | err_dec_alloc: | |
1264 | v4l2_device_unregister(&dev->v4l2_dev); | |
1265 | err_v4l2_dev_reg: | |
2e731e44 KD |
1266 | s5p_mfc_release_firmware(dev); |
1267 | err_alloc_fw: | |
af935746 KD |
1268 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); |
1269 | err_mem_init_ctx_1: | |
1270 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); | |
af935746 KD |
1271 | err_res: |
1272 | s5p_mfc_final_pm(dev); | |
d310f478 | 1273 | |
af935746 KD |
1274 | pr_debug("%s-- with error\n", __func__); |
1275 | return ret; | |
1276 | ||
1277 | } | |
1278 | ||
1279 | /* Remove the driver */ | |
4c62e976 | 1280 | static int s5p_mfc_remove(struct platform_device *pdev) |
af935746 KD |
1281 | { |
1282 | struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); | |
1283 | ||
1284 | v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); | |
1285 | ||
1286 | del_timer_sync(&dev->watchdog_timer); | |
1287 | flush_workqueue(dev->watchdog_workqueue); | |
1288 | destroy_workqueue(dev->watchdog_workqueue); | |
1289 | ||
1290 | video_unregister_device(dev->vfd_enc); | |
1291 | video_unregister_device(dev->vfd_dec); | |
1292 | v4l2_device_unregister(&dev->v4l2_dev); | |
2e731e44 | 1293 | s5p_mfc_release_firmware(dev); |
af935746 KD |
1294 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); |
1295 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); | |
6e83e6e2 AK |
1296 | if (pdev->dev.of_node) { |
1297 | put_device(dev->mem_dev_l); | |
1298 | put_device(dev->mem_dev_r); | |
1299 | } | |
af935746 | 1300 | |
af935746 | 1301 | s5p_mfc_final_pm(dev); |
af935746 KD |
1302 | return 0; |
1303 | } | |
1304 | ||
1305 | #ifdef CONFIG_PM_SLEEP | |
1306 | ||
1307 | static int s5p_mfc_suspend(struct device *dev) | |
1308 | { | |
1309 | struct platform_device *pdev = to_platform_device(dev); | |
1310 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1311 | int ret; | |
1312 | ||
1313 | if (m_dev->num_inst == 0) | |
1314 | return 0; | |
81c9bcfb | 1315 | |
af935746 KD |
1316 | if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { |
1317 | mfc_err("Error: going to suspend for a second time\n"); | |
1318 | return -EIO; | |
1319 | } | |
1320 | ||
1321 | /* Check if we're processing then wait if it necessary. */ | |
1322 | while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { | |
1323 | /* Try and lock the HW */ | |
1324 | /* Wait on the interrupt waitqueue */ | |
1325 | ret = wait_event_interruptible_timeout(m_dev->queue, | |
76a4ddbd | 1326 | m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); |
af935746 KD |
1327 | if (ret == 0) { |
1328 | mfc_err("Waiting for hardware to finish timed out\n"); | |
64370994 | 1329 | clear_bit(0, &m_dev->enter_suspend); |
af935746 KD |
1330 | return -EIO; |
1331 | } | |
1332 | } | |
81c9bcfb | 1333 | |
64370994 P |
1334 | ret = s5p_mfc_sleep(m_dev); |
1335 | if (ret) { | |
1336 | clear_bit(0, &m_dev->enter_suspend); | |
1337 | clear_bit(0, &m_dev->hw_lock); | |
1338 | } | |
1339 | return ret; | |
af935746 KD |
1340 | } |
1341 | ||
1342 | static int s5p_mfc_resume(struct device *dev) | |
1343 | { | |
1344 | struct platform_device *pdev = to_platform_device(dev); | |
1345 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1346 | ||
1347 | if (m_dev->num_inst == 0) | |
1348 | return 0; | |
1349 | return s5p_mfc_wakeup(m_dev); | |
1350 | } | |
1351 | #endif | |
1352 | ||
e243c7c1 | 1353 | #ifdef CONFIG_PM |
af935746 KD |
1354 | static int s5p_mfc_runtime_suspend(struct device *dev) |
1355 | { | |
1356 | struct platform_device *pdev = to_platform_device(dev); | |
1357 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1358 | ||
1359 | atomic_set(&m_dev->pm.power, 0); | |
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int s5p_mfc_runtime_resume(struct device *dev) | |
1364 | { | |
1365 | struct platform_device *pdev = to_platform_device(dev); | |
1366 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
af935746 | 1367 | |
af935746 KD |
1368 | atomic_set(&m_dev->pm.power, 1); |
1369 | return 0; | |
1370 | } | |
1371 | #endif | |
1372 | ||
1373 | /* Power management */ | |
1374 | static const struct dev_pm_ops s5p_mfc_pm_ops = { | |
1375 | SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) | |
1376 | SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, | |
1377 | NULL) | |
1378 | }; | |
1379 | ||
ca5ea0c5 | 1380 | static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { |
8f532a7f AK |
1381 | .h264_ctx = MFC_H264_CTX_BUF_SIZE, |
1382 | .non_h264_ctx = MFC_CTX_BUF_SIZE, | |
1383 | .dsc = DESC_BUF_SIZE, | |
1384 | .shm = SHARED_BUF_SIZE, | |
1385 | }; | |
1386 | ||
ca5ea0c5 | 1387 | static struct s5p_mfc_buf_size buf_size_v5 = { |
8f532a7f AK |
1388 | .fw = MAX_FW_SIZE, |
1389 | .cpb = MAX_CPB_SIZE, | |
1390 | .priv = &mfc_buf_size_v5, | |
1391 | }; | |
1392 | ||
ca5ea0c5 | 1393 | static struct s5p_mfc_buf_align mfc_buf_align_v5 = { |
8f532a7f AK |
1394 | .base = MFC_BASE_ALIGN_ORDER, |
1395 | }; | |
1396 | ||
1397 | static struct s5p_mfc_variant mfc_drvdata_v5 = { | |
1398 | .version = MFC_VERSION, | |
9aa5f008 | 1399 | .version_bit = MFC_V5_BIT, |
8f532a7f AK |
1400 | .port_num = MFC_NUM_PORTS, |
1401 | .buf_size = &buf_size_v5, | |
1402 | .buf_align = &mfc_buf_align_v5, | |
77ba6b73 | 1403 | .fw_name[0] = "s5p-mfc.fw", |
f96f3cfa JP |
1404 | }; |
1405 | ||
ca5ea0c5 | 1406 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { |
f96f3cfa JP |
1407 | .dev_ctx = MFC_CTX_BUF_SIZE_V6, |
1408 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, | |
1409 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, | |
1410 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, | |
1411 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, | |
1412 | }; | |
1413 | ||
ca5ea0c5 | 1414 | static struct s5p_mfc_buf_size buf_size_v6 = { |
f96f3cfa JP |
1415 | .fw = MAX_FW_SIZE_V6, |
1416 | .cpb = MAX_CPB_SIZE_V6, | |
1417 | .priv = &mfc_buf_size_v6, | |
1418 | }; | |
1419 | ||
ca5ea0c5 | 1420 | static struct s5p_mfc_buf_align mfc_buf_align_v6 = { |
f96f3cfa JP |
1421 | .base = 0, |
1422 | }; | |
1423 | ||
1424 | static struct s5p_mfc_variant mfc_drvdata_v6 = { | |
1425 | .version = MFC_VERSION_V6, | |
9aa5f008 | 1426 | .version_bit = MFC_V6_BIT, |
f96f3cfa JP |
1427 | .port_num = MFC_NUM_PORTS_V6, |
1428 | .buf_size = &buf_size_v6, | |
1429 | .buf_align = &mfc_buf_align_v6, | |
77ba6b73 AK |
1430 | .fw_name[0] = "s5p-mfc-v6.fw", |
1431 | /* | |
1432 | * v6-v2 firmware contains bug fixes and interface change | |
1433 | * for init buffer command | |
1434 | */ | |
1435 | .fw_name[1] = "s5p-mfc-v6-v2.fw", | |
8f532a7f AK |
1436 | }; |
1437 | ||
ca5ea0c5 | 1438 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { |
5441e9da AK |
1439 | .dev_ctx = MFC_CTX_BUF_SIZE_V7, |
1440 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, | |
1441 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, | |
1442 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, | |
1443 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, | |
1444 | }; | |
1445 | ||
ca5ea0c5 | 1446 | static struct s5p_mfc_buf_size buf_size_v7 = { |
5441e9da AK |
1447 | .fw = MAX_FW_SIZE_V7, |
1448 | .cpb = MAX_CPB_SIZE_V7, | |
1449 | .priv = &mfc_buf_size_v7, | |
1450 | }; | |
1451 | ||
ca5ea0c5 | 1452 | static struct s5p_mfc_buf_align mfc_buf_align_v7 = { |
5441e9da AK |
1453 | .base = 0, |
1454 | }; | |
1455 | ||
1456 | static struct s5p_mfc_variant mfc_drvdata_v7 = { | |
1457 | .version = MFC_VERSION_V7, | |
9aa5f008 | 1458 | .version_bit = MFC_V7_BIT, |
5441e9da AK |
1459 | .port_num = MFC_NUM_PORTS_V7, |
1460 | .buf_size = &buf_size_v7, | |
1461 | .buf_align = &mfc_buf_align_v7, | |
77ba6b73 | 1462 | .fw_name[0] = "s5p-mfc-v7.fw", |
5441e9da AK |
1463 | }; |
1464 | ||
ca5ea0c5 | 1465 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { |
e2b9deb2 KA |
1466 | .dev_ctx = MFC_CTX_BUF_SIZE_V8, |
1467 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8, | |
1468 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8, | |
3e594ce7 KA |
1469 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8, |
1470 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8, | |
e2b9deb2 KA |
1471 | }; |
1472 | ||
ca5ea0c5 | 1473 | static struct s5p_mfc_buf_size buf_size_v8 = { |
e2b9deb2 KA |
1474 | .fw = MAX_FW_SIZE_V8, |
1475 | .cpb = MAX_CPB_SIZE_V8, | |
1476 | .priv = &mfc_buf_size_v8, | |
1477 | }; | |
1478 | ||
ca5ea0c5 | 1479 | static struct s5p_mfc_buf_align mfc_buf_align_v8 = { |
e2b9deb2 KA |
1480 | .base = 0, |
1481 | }; | |
1482 | ||
1483 | static struct s5p_mfc_variant mfc_drvdata_v8 = { | |
1484 | .version = MFC_VERSION_V8, | |
1485 | .version_bit = MFC_V8_BIT, | |
1486 | .port_num = MFC_NUM_PORTS_V8, | |
1487 | .buf_size = &buf_size_v8, | |
1488 | .buf_align = &mfc_buf_align_v8, | |
77ba6b73 | 1489 | .fw_name[0] = "s5p-mfc-v8.fw", |
e2b9deb2 KA |
1490 | }; |
1491 | ||
6425f646 | 1492 | static const struct platform_device_id mfc_driver_ids[] = { |
8f532a7f AK |
1493 | { |
1494 | .name = "s5p-mfc", | |
1495 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
f96f3cfa JP |
1496 | }, { |
1497 | .name = "s5p-mfc-v5", | |
1498 | .driver_data = (unsigned long)&mfc_drvdata_v5, | |
1499 | }, { | |
1500 | .name = "s5p-mfc-v6", | |
1501 | .driver_data = (unsigned long)&mfc_drvdata_v6, | |
5441e9da AK |
1502 | }, { |
1503 | .name = "s5p-mfc-v7", | |
1504 | .driver_data = (unsigned long)&mfc_drvdata_v7, | |
e2b9deb2 KA |
1505 | }, { |
1506 | .name = "s5p-mfc-v8", | |
1507 | .driver_data = (unsigned long)&mfc_drvdata_v8, | |
8f532a7f AK |
1508 | }, |
1509 | {}, | |
1510 | }; | |
1511 | MODULE_DEVICE_TABLE(platform, mfc_driver_ids); | |
1512 | ||
b27a23be AK |
1513 | static const struct of_device_id exynos_mfc_match[] = { |
1514 | { | |
1515 | .compatible = "samsung,mfc-v5", | |
1516 | .data = &mfc_drvdata_v5, | |
1517 | }, { | |
1518 | .compatible = "samsung,mfc-v6", | |
1519 | .data = &mfc_drvdata_v6, | |
5441e9da AK |
1520 | }, { |
1521 | .compatible = "samsung,mfc-v7", | |
1522 | .data = &mfc_drvdata_v7, | |
e2b9deb2 KA |
1523 | }, { |
1524 | .compatible = "samsung,mfc-v8", | |
1525 | .data = &mfc_drvdata_v8, | |
b27a23be AK |
1526 | }, |
1527 | {}, | |
1528 | }; | |
1529 | MODULE_DEVICE_TABLE(of, exynos_mfc_match); | |
1530 | ||
1531 | static void *mfc_get_drv_data(struct platform_device *pdev) | |
1532 | { | |
1533 | struct s5p_mfc_variant *driver_data = NULL; | |
1534 | ||
1535 | if (pdev->dev.of_node) { | |
1536 | const struct of_device_id *match; | |
a40a1382 | 1537 | match = of_match_node(exynos_mfc_match, |
b27a23be AK |
1538 | pdev->dev.of_node); |
1539 | if (match) | |
1540 | driver_data = (struct s5p_mfc_variant *)match->data; | |
1541 | } else { | |
1542 | driver_data = (struct s5p_mfc_variant *) | |
1543 | platform_get_device_id(pdev)->driver_data; | |
1544 | } | |
1545 | return driver_data; | |
1546 | } | |
1547 | ||
1e393e90 | 1548 | static struct platform_driver s5p_mfc_driver = { |
8f532a7f | 1549 | .probe = s5p_mfc_probe, |
4c62e976 | 1550 | .remove = s5p_mfc_remove, |
8f532a7f | 1551 | .id_table = mfc_driver_ids, |
af935746 KD |
1552 | .driver = { |
1553 | .name = S5P_MFC_NAME, | |
b27a23be AK |
1554 | .pm = &s5p_mfc_pm_ops, |
1555 | .of_match_table = exynos_mfc_match, | |
af935746 KD |
1556 | }, |
1557 | }; | |
1558 | ||
1d6629b1 | 1559 | module_platform_driver(s5p_mfc_driver); |
af935746 KD |
1560 | |
1561 | MODULE_LICENSE("GPL"); | |
1562 | MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); | |
1563 | MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); | |
1564 |