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[media] s5p-mfc: Extract open/close MFC instance commands
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
af935746 21#include <linux/videodev2.h>
f9f715a9 22#include <media/v4l2-event.h>
af935746 23#include <linux/workqueue.h>
b27a23be 24#include <linux/of.h>
af935746 25#include <media/videobuf2-core.h>
43a1ea1f 26#include "s5p_mfc_common.h"
af935746
KD		 27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
af935746 34#include "s5p_mfc_pm.h"
af935746
KD		 35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40int debug;
41module_param(debug, int, S_IRUGO | S_IWUSR);
42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44/* Helper functions for interrupt processing */
7fb89eca 45
af935746 46/* Remove from hw execution round robin */
7fb89eca 47void clear_work_bit(struct s5p_mfc_ctx *ctx)
af935746
KD		 48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
7fb89eca 52 __clear_bit(ctx->num, &dev->ctx_work_bits);
af935746
KD		 53 spin_unlock(&dev->condlock);
54}
55
7fb89eca
AH		 56/* Add to hw execution round robin */
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66/* Remove from hw execution round robin */
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77/* Add to hw execution round robin */
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
af935746
KD		 88/* Wake up context wait_queue */
89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91{
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96}
97
98/* Wake up device wait_queue */
99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101{
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106}
107
a13bba4f 108static void s5p_mfc_watchdog(unsigned long arg)
af935746
KD		 109{
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126}
127
128static void s5p_mfc_watchdog_worker(struct work_struct *work)
129{
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
43a1ea1f
AK		 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
154 &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
156 &ctx->vq_src);
af935746 157 clear_work_bit(ctx);
43a1ea1f 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
af935746
KD		 159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_reload_firmware(dev);
166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 if (ret)
173 mfc_err("Failed to reinit FW\n");
174 }
175unlock:
176 if (mutex_locked)
177 mutex_unlock(&dev->mfc_mutex);
178}
179
af935746
KD		 180static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
181{
182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
185}
186
187static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
188{
189 struct s5p_mfc_buf *dst_buf;
43a1ea1f 190 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 191
192 ctx->state = MFCINST_FINISHED;
193 ctx->sequence++;
194 while (!list_empty(&ctx->dst_queue)) {
195 dst_buf = list_entry(ctx->dst_queue.next,
196 struct s5p_mfc_buf, list);
197 mfc_debug(2, "Cleaning up buffer: %d\n",
198 dst_buf->b->v4l2_buf.index);
199 vb2_set_plane_payload(dst_buf->b, 0, 0);
200 vb2_set_plane_payload(dst_buf->b, 1, 0);
201 list_del(&dst_buf->list);
202 ctx->dst_queue_cnt--;
203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
204
43a1ea1f
AK		 205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
af935746
KD		 207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
208 else
209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
210
211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
213 }
214}
215
216static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
217{
218 struct s5p_mfc_dev *dev = ctx->dev;
219 struct s5p_mfc_buf *dst_buf, *src_buf;
43a1ea1f
AK		 220 size_t dec_y_addr;
221 unsigned int frame_type;
222
223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
af935746
KD		 225
226 /* Copy timestamp / timecode from decoded src to dst and set
39c1cb2b 227 appropriate flags */
af935746
KD		 228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
ba7fcb0c 230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
56006017
KD		 231 dst_buf->b->v4l2_buf.timecode =
232 src_buf->b->v4l2_buf.timecode;
233 dst_buf->b->v4l2_buf.timestamp =
234 src_buf->b->v4l2_buf.timestamp;
309f4d62
SA		 235 dst_buf->b->v4l2_buf.flags &=
236 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
237 dst_buf->b->v4l2_buf.flags |=
238 src_buf->b->v4l2_buf.flags
239 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
af935746
KD		 240 switch (frame_type) {
241 case S5P_FIMV_DECODE_FRAME_I_FRAME:
242 dst_buf->b->v4l2_buf.flags |=
243 V4L2_BUF_FLAG_KEYFRAME;
244 break;
245 case S5P_FIMV_DECODE_FRAME_P_FRAME:
246 dst_buf->b->v4l2_buf.flags |=
247 V4L2_BUF_FLAG_PFRAME;
248 break;
249 case S5P_FIMV_DECODE_FRAME_B_FRAME:
250 dst_buf->b->v4l2_buf.flags |=
251 V4L2_BUF_FLAG_BFRAME;
252 break;
253 }
254 break;
255 }
256 }
257}
258
259static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
260{
261 struct s5p_mfc_dev *dev = ctx->dev;
262 struct s5p_mfc_buf *dst_buf;
43a1ea1f
AK		 263 size_t dspl_y_addr;
264 unsigned int frame_type;
af935746 265
43a1ea1f 266 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
90c0ae50 267 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx);
43a1ea1f 268
af935746
KD		 269 /* If frame is same as previous then skip and do not dequeue */
270 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
271 if (!ctx->after_packed_pb)
272 ctx->sequence++;
273 ctx->after_packed_pb = 0;
274 return;
275 }
276 ctx->sequence++;
277 /* The MFC returns address of the buffer, now we have to
278 * check which videobuf does it correspond to */
279 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
280 /* Check if this is the buffer we're looking for */
ba7fcb0c 281 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
af935746
KD		 282 list_del(&dst_buf->list);
283 ctx->dst_queue_cnt--;
284 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
43a1ea1f
AK		 285 if (s5p_mfc_hw_call(dev->mfc_ops,
286 get_pic_type_top, ctx) ==
287 s5p_mfc_hw_call(dev->mfc_ops,
288 get_pic_type_bot, ctx))
af935746
KD		 289 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
290 else
291 dst_buf->b->v4l2_buf.field =
292 V4L2_FIELD_INTERLACED;
293 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
294 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
295 clear_bit(dst_buf->b->v4l2_buf.index,
296 &ctx->dec_dst_flag);
297
298 vb2_buffer_done(dst_buf->b,
299 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
300
af935746
KD		 301 break;
302 }
303 }
304}
305
306/* Handle frame decoding interrupt */
307static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
308 unsigned int reason, unsigned int err)
309{
310 struct s5p_mfc_dev *dev = ctx->dev;
311 unsigned int dst_frame_status;
a0517f5d 312 unsigned int dec_frame_status;
af935746
KD		 313 struct s5p_mfc_buf *src_buf;
314 unsigned long flags;
315 unsigned int res_change;
316
43a1ea1f 317 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
af935746 318 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
a0517f5d
PO		 319 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
320 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
f96f3cfa
JP		 321 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
322 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
323 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
af935746
KD		 324 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
325 if (ctx->state == MFCINST_RES_CHANGE_INIT)
326 ctx->state = MFCINST_RES_CHANGE_FLUSH;
f96f3cfa
JP		 327 if (res_change == S5P_FIMV_RES_INCREASE ||
328 res_change == S5P_FIMV_RES_DECREASE) {
af935746 329 ctx->state = MFCINST_RES_CHANGE_INIT;
43a1ea1f 330 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 331 wake_up_ctx(ctx, reason, err);
332 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
333 BUG();
334 s5p_mfc_clock_off();
43a1ea1f 335 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 336 return;
337 }
338 if (ctx->dpb_flush_flag)
339 ctx->dpb_flush_flag = 0;
340
341 spin_lock_irqsave(&dev->irqlock, flags);
342 /* All frames remaining in the buffer have been extracted */
343 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
344 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
345 s5p_mfc_handle_frame_all_extracted(ctx);
346 ctx->state = MFCINST_RES_CHANGE_END;
347 goto leave_handle_frame;
348 } else {
349 s5p_mfc_handle_frame_all_extracted(ctx);
350 }
351 }
352
a0517f5d 353 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
af935746
KD		 354 s5p_mfc_handle_frame_copy_time(ctx);
355
356 /* A frame has been decoded and is in the buffer */
357 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
358 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
359 s5p_mfc_handle_frame_new(ctx, err);
360 } else {
361 mfc_debug(2, "No frame decode\n");
362 }
363 /* Mark source buffer as complete */
364 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
365 && !list_empty(&ctx->src_queue)) {
366 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
367 list);
43a1ea1f
AK		 368 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
369 get_consumed_stream, dev);
370 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
d2a0db1e
AK		 371 ctx->consumed_stream + STUFF_BYTE <
372 src_buf->b->v4l2_planes[0].bytesused) {
af935746
KD		 373 /* Run MFC again on the same buffer */
374 mfc_debug(2, "Running again the same buffer\n");
375 ctx->after_packed_pb = 1;
376 } else {
af935746
KD		 377 mfc_debug(2, "MFC needs next buffer\n");
378 ctx->consumed_stream = 0;
a34026e7
KD		 379 if (src_buf->flags & MFC_BUF_FLAG_EOS)
380 ctx->state = MFCINST_FINISHING;
af935746
KD		 381 list_del(&src_buf->list);
382 ctx->src_queue_cnt--;
43a1ea1f 383 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
af935746
KD		 384 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
385 else
386 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
387 }
388 }
389leave_handle_frame:
390 spin_unlock_irqrestore(&dev->irqlock, flags);
391 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
e9d98ddc 392 || ctx->dst_queue_cnt < ctx->pb_count)
af935746 393 clear_work_bit(ctx);
43a1ea1f 394 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 395 wake_up_ctx(ctx, reason, err);
396 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
397 BUG();
398 s5p_mfc_clock_off();
76a4ddbd
P		 399 /* if suspending, wake up device and do not try_run again*/
400 if (test_bit(0, &dev->enter_suspend))
401 wake_up_dev(dev, reason, err);
402 else
403 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 404}
405
406/* Error handling for interrupt */
7296e25f
KD		 407static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
408 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
af935746 409{
af935746
KD		 410 unsigned long flags;
411
af935746 412 mfc_err("Interrupt Error: %08x\n", err);
af935746 413
7296e25f
KD		 414 if (ctx != NULL) {
415 /* Error recovery is dependent on the state of context */
416 switch (ctx->state) {
417 case MFCINST_RES_CHANGE_INIT:
418 case MFCINST_RES_CHANGE_FLUSH:
419 case MFCINST_RES_CHANGE_END:
420 case MFCINST_FINISHING:
421 case MFCINST_FINISHED:
422 case MFCINST_RUNNING:
39c1cb2b 423 /* It is highly probable that an error occurred
7296e25f
KD		 424 * while decoding a frame */
425 clear_work_bit(ctx);
426 ctx->state = MFCINST_ERROR;
427 /* Mark all dst buffers as having an error */
428 spin_lock_irqsave(&dev->irqlock, flags);
429 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
430 &ctx->dst_queue, &ctx->vq_dst);
431 /* Mark all src buffers as having an error */
432 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
433 &ctx->src_queue, &ctx->vq_src);
434 spin_unlock_irqrestore(&dev->irqlock, flags);
435 wake_up_ctx(ctx, reason, err);
436 break;
437 default:
438 clear_work_bit(ctx);
439 ctx->state = MFCINST_ERROR;
440 wake_up_ctx(ctx, reason, err);
441 break;
442 }
af935746 443 }
7296e25f
KD		 444 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
445 BUG();
446 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
447 s5p_mfc_clock_off();
448 wake_up_dev(dev, reason, err);
af935746
KD		 449 return;
450}
451
452/* Header parsing interrupt handling */
453static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
454 unsigned int reason, unsigned int err)
455{
456 struct s5p_mfc_dev *dev;
af935746 457
1259762f 458 if (ctx == NULL)
af935746
KD		 459 return;
460 dev = ctx->dev;
461 if (ctx->c_ops->post_seq_start) {
462 if (ctx->c_ops->post_seq_start(ctx))
463 mfc_err("post_seq_start() failed\n");
464 } else {
43a1ea1f
AK		 465 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
466 dev);
467 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
468 dev);
af935746 469
8f532a7f
AK		 470 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
471
e9d98ddc 472 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
43a1ea1f 473 dev);
f96f3cfa
JP		 474 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
475 dev);
bb869368 476 if (ctx->img_width == 0 || ctx->img_height == 0)
af935746
KD		 477 ctx->state = MFCINST_ERROR;
478 else
479 ctx->state = MFCINST_HEAD_PARSED;
f96f3cfa
JP		 480
481 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
482 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
483 !list_empty(&ctx->src_queue)) {
484 struct s5p_mfc_buf *src_buf;
485 src_buf = list_entry(ctx->src_queue.next,
486 struct s5p_mfc_buf, list);
487 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
488 dev) <
489 src_buf->b->v4l2_planes[0].bytesused)
490 ctx->head_processed = 0;
491 else
492 ctx->head_processed = 1;
493 } else {
494 ctx->head_processed = 1;
495 }
af935746 496 }
43a1ea1f 497 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 498 clear_work_bit(ctx);
499 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
500 BUG();
501 s5p_mfc_clock_off();
43a1ea1f 502 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 503 wake_up_ctx(ctx, reason, err);
504}
505
506/* Header parsing interrupt handling */
507static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
508 unsigned int reason, unsigned int err)
509{
510 struct s5p_mfc_buf *src_buf;
511 struct s5p_mfc_dev *dev;
512 unsigned long flags;
513
1259762f 514 if (ctx == NULL)
af935746
KD		 515 return;
516 dev = ctx->dev;
43a1ea1f 517 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 518 ctx->int_type = reason;
519 ctx->int_err = err;
520 ctx->int_cond = 1;
7fb89eca 521 clear_work_bit(ctx);
af935746
KD		 522 if (err == 0) {
523 ctx->state = MFCINST_RUNNING;
f96f3cfa 524 if (!ctx->dpb_flush_flag && ctx->head_processed) {
af935746
KD		 525 spin_lock_irqsave(&dev->irqlock, flags);
526 if (!list_empty(&ctx->src_queue)) {
527 src_buf = list_entry(ctx->src_queue.next,
528 struct s5p_mfc_buf, list);
529 list_del(&src_buf->list);
530 ctx->src_queue_cnt--;
531 vb2_buffer_done(src_buf->b,
532 VB2_BUF_STATE_DONE);
533 }
534 spin_unlock_irqrestore(&dev->irqlock, flags);
535 } else {
536 ctx->dpb_flush_flag = 0;
537 }
538 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
539 BUG();
540
541 s5p_mfc_clock_off();
542
543 wake_up(&ctx->queue);
43a1ea1f 544 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 545 } else {
546 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
547 BUG();
548
549 s5p_mfc_clock_off();
550
551 wake_up(&ctx->queue);
552 }
553}
554
f9f715a9
AH		 555static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
556 unsigned int reason, unsigned int err)
557{
558 struct s5p_mfc_dev *dev = ctx->dev;
559 struct s5p_mfc_buf *mb_entry;
560
4130eabc 561 mfc_debug(2, "Stream completed\n");
f9f715a9
AH		 562
563 s5p_mfc_clear_int_flags(dev);
564 ctx->int_type = reason;
565 ctx->int_err = err;
566 ctx->state = MFCINST_FINISHED;
567
568 spin_lock(&dev->irqlock);
569 if (!list_empty(&ctx->dst_queue)) {
570 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
571 list);
572 list_del(&mb_entry->list);
573 ctx->dst_queue_cnt--;
574 vb2_set_plane_payload(mb_entry->b, 0, 0);
575 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
576 }
577 spin_unlock(&dev->irqlock);
578
579 clear_work_bit(ctx);
580
e8256447 581 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
f9f715a9
AH		 582
583 s5p_mfc_clock_off();
584 wake_up(&ctx->queue);
43a1ea1f 585 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
f9f715a9
AH		 586}
587
af935746
KD		 588/* Interrupt processing */
589static irqreturn_t s5p_mfc_irq(int irq, void *priv)
590{
591 struct s5p_mfc_dev *dev = priv;
592 struct s5p_mfc_ctx *ctx;
593 unsigned int reason;
594 unsigned int err;
595
596 mfc_debug_enter();
597 /* Reset the timeout watchdog */
598 atomic_set(&dev->watchdog_cnt, 0);
599 ctx = dev->ctx[dev->curr_ctx];
600 /* Get the reason of interrupt and the error code */
43a1ea1f
AK		 601 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
602 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
af935746
KD		 603 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
604 switch (reason) {
43a1ea1f 605 case S5P_MFC_R2H_CMD_ERR_RET:
39c1cb2b 606 /* An error has occurred */
af935746 607 if (ctx->state == MFCINST_RUNNING &&
43a1ea1f
AK		 608 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
609 dev->warn_start)
af935746
KD		 610 s5p_mfc_handle_frame(ctx, reason, err);
611 else
7296e25f 612 s5p_mfc_handle_error(dev, ctx, reason, err);
af935746
KD		 613 clear_bit(0, &dev->enter_suspend);
614 break;
615
43a1ea1f
AK		 616 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
617 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
618 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
af935746
KD		 619 if (ctx->c_ops->post_frame_start) {
620 if (ctx->c_ops->post_frame_start(ctx))
621 mfc_err("post_frame_start() failed\n");
43a1ea1f 622 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 623 wake_up_ctx(ctx, reason, err);
624 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
625 BUG();
626 s5p_mfc_clock_off();
43a1ea1f 627 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 628 } else {
629 s5p_mfc_handle_frame(ctx, reason, err);
630 }
631 break;
632
43a1ea1f 633 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
af935746
KD		 634 s5p_mfc_handle_seq_done(ctx, reason, err);
635 break;
636
43a1ea1f
AK		 637 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
638 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
af935746
KD		 639 ctx->state = MFCINST_GOT_INST;
640 clear_work_bit(ctx);
641 wake_up(&ctx->queue);
642 goto irq_cleanup_hw;
643
43a1ea1f 644 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
af935746
KD		 645 clear_work_bit(ctx);
646 ctx->state = MFCINST_FREE;
647 wake_up(&ctx->queue);
648 goto irq_cleanup_hw;
649
43a1ea1f
AK		 650 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
651 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
652 case S5P_MFC_R2H_CMD_SLEEP_RET:
653 case S5P_MFC_R2H_CMD_WAKEUP_RET:
af935746
KD		 654 if (ctx)
655 clear_work_bit(ctx);
43a1ea1f 656 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 657 wake_up_dev(dev, reason, err);
658 clear_bit(0, &dev->hw_lock);
659 clear_bit(0, &dev->enter_suspend);
660 break;
661
43a1ea1f 662 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
af935746
KD		 663 s5p_mfc_handle_init_buffers(ctx, reason, err);
664 break;
f9f715a9 665
43a1ea1f 666 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
f9f715a9
AH		 667 s5p_mfc_handle_stream_complete(ctx, reason, err);
668 break;
669
8f23cc02
AK		 670 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
671 clear_work_bit(ctx);
672 ctx->state = MFCINST_RUNNING;
673 wake_up(&ctx->queue);
674 goto irq_cleanup_hw;
675
af935746
KD		 676 default:
677 mfc_debug(2, "Unknown int reason\n");
43a1ea1f 678 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 679 }
680 mfc_debug_leave();
681 return IRQ_HANDLED;
682irq_cleanup_hw:
43a1ea1f 683 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
af935746
KD		 684 ctx->int_type = reason;
685 ctx->int_err = err;
686 ctx->int_cond = 1;
687 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
688 mfc_err("Failed to unlock hw\n");
689
690 s5p_mfc_clock_off();
691
43a1ea1f 692 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 693 mfc_debug(2, "Exit via irq_cleanup_hw\n");
694 return IRQ_HANDLED;
695}
696
697/* Open an MFC node */
698static int s5p_mfc_open(struct file *file)
699{
b80cb8dc 700 struct video_device *vdev = video_devdata(file);
af935746
KD		 701 struct s5p_mfc_dev *dev = video_drvdata(file);
702 struct s5p_mfc_ctx *ctx = NULL;
703 struct vb2_queue *q;
af935746
KD		 704 int ret = 0;
705
706 mfc_debug_enter();
bc738301
HV		 707 if (mutex_lock_interruptible(&dev->mfc_mutex))
708 return -ERESTARTSYS;
af935746
KD		 709 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
710 /* Allocate memory for context */
bae061b4 711 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
af935746
KD		 712 if (!ctx) {
713 mfc_err("Not enough memory\n");
714 ret = -ENOMEM;
715 goto err_alloc;
716 }
717 v4l2_fh_init(&ctx->fh, video_devdata(file));
718 file->private_data = &ctx->fh;
719 v4l2_fh_add(&ctx->fh);
720 ctx->dev = dev;
721 INIT_LIST_HEAD(&ctx->src_queue);
722 INIT_LIST_HEAD(&ctx->dst_queue);
723 ctx->src_queue_cnt = 0;
724 ctx->dst_queue_cnt = 0;
725 /* Get context number */
726 ctx->num = 0;
727 while (dev->ctx[ctx->num]) {
728 ctx->num++;
729 if (ctx->num >= MFC_NUM_CONTEXTS) {
730 mfc_err("Too many open contexts\n");
731 ret = -EBUSY;
732 goto err_no_ctx;
733 }
734 }
735 /* Mark context as idle */
7fb89eca 736 clear_work_bit_irqsave(ctx);
af935746 737 dev->ctx[ctx->num] = ctx;
b80cb8dc 738 if (vdev == dev->vfd_dec) {
af935746
KD		 739 ctx->type = MFCINST_DECODER;
740 ctx->c_ops = get_dec_codec_ops();
43a1ea1f 741 s5p_mfc_dec_init(ctx);
af935746
KD		 742 /* Setup ctrl handler */
743 ret = s5p_mfc_dec_ctrls_setup(ctx);
744 if (ret) {
745 mfc_err("Failed to setup mfc controls\n");
746 goto err_ctrls_setup;
747 }
b80cb8dc 748 } else if (vdev == dev->vfd_enc) {
af935746
KD		 749 ctx->type = MFCINST_ENCODER;
750 ctx->c_ops = get_enc_codec_ops();
751 /* only for encoder */
752 INIT_LIST_HEAD(&ctx->ref_queue);
753 ctx->ref_queue_cnt = 0;
43a1ea1f 754 s5p_mfc_enc_init(ctx);
af935746
KD		 755 /* Setup ctrl handler */
756 ret = s5p_mfc_enc_ctrls_setup(ctx);
757 if (ret) {
758 mfc_err("Failed to setup mfc controls\n");
759 goto err_ctrls_setup;
760 }
761 } else {
762 ret = -ENOENT;
763 goto err_bad_node;
764 }
765 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
766 ctx->inst_no = -1;
767 /* Load firmware if this is the first instance */
768 if (dev->num_inst == 1) {
769 dev->watchdog_timer.expires = jiffies +
770 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
771 add_timer(&dev->watchdog_timer);
772 ret = s5p_mfc_power_on();
773 if (ret < 0) {
774 mfc_err("power on failed\n");
775 goto err_pwr_enable;
776 }
777 s5p_mfc_clock_on();
2e731e44
KD		 778 ret = s5p_mfc_load_firmware(dev);
779 if (ret) {
780 s5p_mfc_clock_off();
781 goto err_load_fw;
782 }
af935746
KD		 783 /* Init the FW */
784 ret = s5p_mfc_init_hw(dev);
2e731e44 785 s5p_mfc_clock_off();
af935746
KD		 786 if (ret)
787 goto err_init_hw;
af935746
KD		 788 }
789 /* Init videobuf2 queue for CAPTURE */
790 q = &ctx->vq_dst;
791 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
792 q->drv_priv = &ctx->fh;
b80cb8dc 793 if (vdev == dev->vfd_dec) {
af935746
KD		 794 q->io_modes = VB2_MMAP;
795 q->ops = get_dec_queue_ops();
b80cb8dc 796 } else if (vdev == dev->vfd_enc) {
af935746
KD		 797 q->io_modes = VB2_MMAP | VB2_USERPTR;
798 q->ops = get_enc_queue_ops();
799 } else {
800 ret = -ENOENT;
801 goto err_queue_init;
802 }
803 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
ade48681 804 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 805 ret = vb2_queue_init(q);
806 if (ret) {
807 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
808 goto err_queue_init;
809 }
810 /* Init videobuf2 queue for OUTPUT */
811 q = &ctx->vq_src;
812 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
813 q->io_modes = VB2_MMAP;
814 q->drv_priv = &ctx->fh;
b80cb8dc 815 if (vdev == dev->vfd_dec) {
af935746
KD		 816 q->io_modes = VB2_MMAP;
817 q->ops = get_dec_queue_ops();
b80cb8dc 818 } else if (vdev == dev->vfd_enc) {
af935746
KD		 819 q->io_modes = VB2_MMAP | VB2_USERPTR;
820 q->ops = get_enc_queue_ops();
821 } else {
822 ret = -ENOENT;
823 goto err_queue_init;
824 }
825 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
ade48681 826 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
af935746
KD		 827 ret = vb2_queue_init(q);
828 if (ret) {
829 mfc_err("Failed to initialize videobuf2 queue(output)\n");
830 goto err_queue_init;
831 }
832 init_waitqueue_head(&ctx->queue);
bc738301 833 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 834 mfc_debug_leave();
835 return ret;
39c1cb2b 836 /* Deinit when failure occurred */
af935746 837err_queue_init:
2e731e44
KD		 838 if (dev->num_inst == 1)
839 s5p_mfc_deinit_hw(dev);
af935746 840err_init_hw:
2e731e44 841err_load_fw:
af935746
KD		 842err_pwr_enable:
843 if (dev->num_inst == 1) {
844 if (s5p_mfc_power_off() < 0)
845 mfc_err("power off failed\n");
1b73ba0b 846 del_timer_sync(&dev->watchdog_timer);
af935746
KD		 847 }
848err_ctrls_setup:
849 s5p_mfc_dec_ctrls_delete(ctx);
850err_bad_node:
1b73ba0b 851 dev->ctx[ctx->num] = NULL;
af935746
KD		 852err_no_ctx:
853 v4l2_fh_del(&ctx->fh);
854 v4l2_fh_exit(&ctx->fh);
855 kfree(ctx);
856err_alloc:
857 dev->num_inst--;
bc738301 858 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 859 mfc_debug_leave();
860 return ret;
861}
862
863/* Release MFC context */
864static int s5p_mfc_release(struct file *file)
865{
866 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
867 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 868
869 mfc_debug_enter();
bc738301 870 mutex_lock(&dev->mfc_mutex);
af935746
KD		 871 s5p_mfc_clock_on();
872 vb2_queue_release(&ctx->vq_src);
873 vb2_queue_release(&ctx->vq_dst);
874 /* Mark context as idle */
7fb89eca 875 clear_work_bit_irqsave(ctx);
af935746 876 /* If instance was initialised then
39c1cb2b 877 * return instance and free resources */
af935746
KD		 878 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
879 mfc_debug(2, "Has to free instance\n");
818cd91a 880 s5p_mfc_close_mfc_inst(dev, ctx);
af935746
KD		 881 ctx->inst_no = MFC_NO_INSTANCE_SET;
882 }
883 /* hardware locking scheme */
884 if (dev->curr_ctx == ctx->num)
885 clear_bit(0, &dev->hw_lock);
886 dev->num_inst--;
887 if (dev->num_inst == 0) {
2e731e44 888 mfc_debug(2, "Last instance\n");
43a1ea1f 889 s5p_mfc_deinit_hw(dev);
af935746
KD		 890 del_timer_sync(&dev->watchdog_timer);
891 if (s5p_mfc_power_off() < 0)
892 mfc_err("Power off failed\n");
893 }
894 mfc_debug(2, "Shutting down clock\n");
895 s5p_mfc_clock_off();
1259762f 896 dev->ctx[ctx->num] = NULL;
af935746
KD		 897 s5p_mfc_dec_ctrls_delete(ctx);
898 v4l2_fh_del(&ctx->fh);
899 v4l2_fh_exit(&ctx->fh);
900 kfree(ctx);
901 mfc_debug_leave();
bc738301 902 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 903 return 0;
904}
905
906/* Poll */
907static unsigned int s5p_mfc_poll(struct file *file,
908 struct poll_table_struct *wait)
909{
910 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
911 struct s5p_mfc_dev *dev = ctx->dev;
912 struct vb2_queue *src_q, *dst_q;
913 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
914 unsigned int rc = 0;
915 unsigned long flags;
916
bc738301 917 mutex_lock(&dev->mfc_mutex);
af935746
KD		 918 src_q = &ctx->vq_src;
919 dst_q = &ctx->vq_dst;
920 /*
921 * There has to be at least one buffer queued on each queued_list, which
922 * means either in driver already or waiting for driver to claim it
923 * and start processing.
924 */
925 if ((!src_q->streaming || list_empty(&src_q->queued_list))
926 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
927 rc = POLLERR;
928 goto end;
929 }
930 mutex_unlock(&dev->mfc_mutex);
f9f715a9 931 poll_wait(file, &ctx->fh.wait, wait);
af935746
KD		 932 poll_wait(file, &src_q->done_wq, wait);
933 poll_wait(file, &dst_q->done_wq, wait);
934 mutex_lock(&dev->mfc_mutex);
f9f715a9
AH		 935 if (v4l2_event_pending(&ctx->fh))
936 rc |= POLLPRI;
af935746
KD		 937 spin_lock_irqsave(&src_q->done_lock, flags);
938 if (!list_empty(&src_q->done_list))
939 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
940 done_entry);
941 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
942 || src_vb->state == VB2_BUF_STATE_ERROR))
943 rc |= POLLOUT | POLLWRNORM;
944 spin_unlock_irqrestore(&src_q->done_lock, flags);
945 spin_lock_irqsave(&dst_q->done_lock, flags);
946 if (!list_empty(&dst_q->done_list))
947 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
948 done_entry);
949 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
950 || dst_vb->state == VB2_BUF_STATE_ERROR))
951 rc |= POLLIN | POLLRDNORM;
952 spin_unlock_irqrestore(&dst_q->done_lock, flags);
953end:
bc738301 954 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 955 return rc;
956}
957
958/* Mmap */
959static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
960{
961 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
bc738301 962 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 963 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
964 int ret;
bc738301
HV		 965
966 if (mutex_lock_interruptible(&dev->mfc_mutex))
967 return -ERESTARTSYS;
af935746
KD		 968 if (offset < DST_QUEUE_OFF_BASE) {
969 mfc_debug(2, "mmaping source\n");
970 ret = vb2_mmap(&ctx->vq_src, vma);
971 } else { /* capture */
972 mfc_debug(2, "mmaping destination\n");
973 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
974 ret = vb2_mmap(&ctx->vq_dst, vma);
975 }
bc738301 976 mutex_unlock(&dev->mfc_mutex);
af935746
KD		 977 return ret;
978}
979
980/* v4l2 ops */
981static const struct v4l2_file_operations s5p_mfc_fops = {
982 .owner = THIS_MODULE,
983 .open = s5p_mfc_open,
984 .release = s5p_mfc_release,
985 .poll = s5p_mfc_poll,
986 .unlocked_ioctl = video_ioctl2,
987 .mmap = s5p_mfc_mmap,
988};
989
990static int match_child(struct device *dev, void *data)
991{
992 if (!dev_name(dev))
993 return 0;
994 return !strcmp(dev_name(dev), (char *)data);
995}
996
b27a23be
AK		 997static void *mfc_get_drv_data(struct platform_device *pdev);
998
6e83e6e2
AK		 999static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1000{
65fccab5 1001 unsigned int mem_info[2] = { };
6e83e6e2
AK		 1002
1003 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1004 sizeof(struct device), GFP_KERNEL);
1005 if (!dev->mem_dev_l) {
1006 mfc_err("Not enough memory\n");
1007 return -ENOMEM;
1008 }
1009 device_initialize(dev->mem_dev_l);
1010 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1011 "samsung,mfc-l", mem_info, 2);
1012 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1013 mem_info[0], mem_info[1],
1014 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1015 mfc_err("Failed to declare coherent memory for\n"
1016 "MFC device\n");
1017 return -ENOMEM;
1018 }
1019
1020 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1021 sizeof(struct device), GFP_KERNEL);
1022 if (!dev->mem_dev_r) {
1023 mfc_err("Not enough memory\n");
1024 return -ENOMEM;
1025 }
1026 device_initialize(dev->mem_dev_r);
1027 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1028 "samsung,mfc-r", mem_info, 2);
1029 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1030 mem_info[0], mem_info[1],
1031 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1032 pr_err("Failed to declare coherent memory for\n"
1033 "MFC device\n");
1034 return -ENOMEM;
1035 }
1036 return 0;
1037}
1038
af935746 1039/* MFC probe function */
1e393e90 1040static int s5p_mfc_probe(struct platform_device *pdev)
af935746
KD		 1041{
1042 struct s5p_mfc_dev *dev;
1043 struct video_device *vfd;
1044 struct resource *res;
1045 int ret;
1046
1047 pr_debug("%s++\n", __func__);
bae061b4 1048 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
af935746
KD		 1049 if (!dev) {
1050 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1051 return -ENOMEM;
1052 }
1053
1054 spin_lock_init(&dev->irqlock);
1055 spin_lock_init(&dev->condlock);
1056 dev->plat_dev = pdev;
1057 if (!dev->plat_dev) {
1058 dev_err(&pdev->dev, "No platform data specified\n");
d310f478 1059 return -ENODEV;
af935746
KD		 1060 }
1061
b27a23be 1062 dev->variant = mfc_get_drv_data(pdev);
8f532a7f 1063
af935746
KD		 1064 ret = s5p_mfc_init_pm(dev);
1065 if (ret < 0) {
1066 dev_err(&pdev->dev, "failed to get mfc clock source\n");
d310f478 1067 return ret;
af935746
KD		 1068 }
1069
1070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af935746 1071
f23999ec
TR		 1072 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1073 if (IS_ERR(dev->regs_base))
1074 return PTR_ERR(dev->regs_base);
af935746
KD		 1075
1076 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1077 if (res == NULL) {
1078 dev_err(&pdev->dev, "failed to get irq resource\n");
1079 ret = -ENOENT;
d310f478 1080 goto err_res;
af935746
KD		 1081 }
1082 dev->irq = res->start;
d310f478 1083 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1957f0d7 1084 0, pdev->name, dev);
af935746
KD		 1085 if (ret) {
1086 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
d310f478 1087 goto err_res;
af935746
KD		 1088 }
1089
b27a23be 1090 if (pdev->dev.of_node) {
d68b44e0
WY		 1091 ret = s5p_mfc_alloc_memdevs(dev);
1092 if (ret < 0)
b27a23be 1093 goto err_res;
b27a23be
AK		 1094 } else {
1095 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1096 "s5p-mfc-l", match_child);
1097 if (!dev->mem_dev_l) {
1098 mfc_err("Mem child (L) device get failed\n");
1099 ret = -ENODEV;
1100 goto err_res;
1101 }
1102 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1103 "s5p-mfc-r", match_child);
1104 if (!dev->mem_dev_r) {
1105 mfc_err("Mem child (R) device get failed\n");
1106 ret = -ENODEV;
1107 goto err_res;
1108 }
af935746
KD		 1109 }
1110
1111 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
ef89fff8 1112 if (IS_ERR(dev->alloc_ctx[0])) {
af935746 1113 ret = PTR_ERR(dev->alloc_ctx[0]);
d310f478 1114 goto err_res;
af935746
KD		 1115 }
1116 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
ef89fff8 1117 if (IS_ERR(dev->alloc_ctx[1])) {
af935746
KD		 1118 ret = PTR_ERR(dev->alloc_ctx[1]);
1119 goto err_mem_init_ctx_1;
1120 }
1121
1122 mutex_init(&dev->mfc_mutex);
1123
2e731e44
KD		 1124 ret = s5p_mfc_alloc_firmware(dev);
1125 if (ret)
1126 goto err_alloc_fw;
1127
af935746
KD		 1128 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1129 if (ret)
1130 goto err_v4l2_dev_reg;
1131 init_waitqueue_head(&dev->queue);
1132
1133 /* decoder */
1134 vfd = video_device_alloc();
1135 if (!vfd) {
1136 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1137 ret = -ENOMEM;
1138 goto err_dec_alloc;
1139 }
d0ce898c 1140 vfd->fops = &s5p_mfc_fops;
af935746 1141 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
d0ce898c 1142 vfd->release = video_device_release;
af935746
KD		 1143 vfd->lock = &dev->mfc_mutex;
1144 vfd->v4l2_dev = &dev->v4l2_dev;
954f340f 1145 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1146 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1147 dev->vfd_dec = vfd;
1148 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1149 if (ret) {
1150 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1151 video_device_release(vfd);
1152 goto err_dec_reg;
1153 }
1154 v4l2_info(&dev->v4l2_dev,
1155 "decoder registered as /dev/video%d\n", vfd->num);
1156 video_set_drvdata(vfd, dev);
1157
1158 /* encoder */
1159 vfd = video_device_alloc();
1160 if (!vfd) {
1161 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1162 ret = -ENOMEM;
1163 goto err_enc_alloc;
1164 }
d0ce898c 1165 vfd->fops = &s5p_mfc_fops;
af935746 1166 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
d0ce898c 1167 vfd->release = video_device_release;
af935746
KD		 1168 vfd->lock = &dev->mfc_mutex;
1169 vfd->v4l2_dev = &dev->v4l2_dev;
cdcf45e7 1170 vfd->vfl_dir = VFL_DIR_M2M;
af935746
KD		 1171 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1172 dev->vfd_enc = vfd;
1173 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1174 if (ret) {
1175 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1176 video_device_release(vfd);
1177 goto err_enc_reg;
1178 }
1179 v4l2_info(&dev->v4l2_dev,
1180 "encoder registered as /dev/video%d\n", vfd->num);
1181 video_set_drvdata(vfd, dev);
1182 platform_set_drvdata(pdev, dev);
1183
1184 dev->hw_lock = 0;
1185 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1186 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1187 atomic_set(&dev->watchdog_cnt, 0);
1188 init_timer(&dev->watchdog_timer);
1189 dev->watchdog_timer.data = (unsigned long)dev;
1190 dev->watchdog_timer.function = s5p_mfc_watchdog;
1191
43a1ea1f
AK		 1192 /* Initialize HW ops and commands based on MFC version */
1193 s5p_mfc_init_hw_ops(dev);
1194 s5p_mfc_init_hw_cmds(dev);
1195
af935746
KD		 1196 pr_debug("%s--\n", __func__);
1197 return 0;
1198
1199/* Deinit MFC if probe had failed */
1200err_enc_reg:
1201 video_device_release(dev->vfd_enc);
1202err_enc_alloc:
1203 video_unregister_device(dev->vfd_dec);
1204err_dec_reg:
1205 video_device_release(dev->vfd_dec);
1206err_dec_alloc:
1207 v4l2_device_unregister(&dev->v4l2_dev);
1208err_v4l2_dev_reg:
2e731e44
KD		 1209 s5p_mfc_release_firmware(dev);
1210err_alloc_fw:
af935746
KD		 1211 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1212err_mem_init_ctx_1:
1213 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
af935746
KD		 1214err_res:
1215 s5p_mfc_final_pm(dev);
d310f478 1216
af935746
KD		 1217 pr_debug("%s-- with error\n", __func__);
1218 return ret;
1219
1220}
1221
1222/* Remove the driver */
4c62e976 1223static int s5p_mfc_remove(struct platform_device *pdev)
af935746
KD		 1224{
1225 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1226
1227 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1228
1229 del_timer_sync(&dev->watchdog_timer);
1230 flush_workqueue(dev->watchdog_workqueue);
1231 destroy_workqueue(dev->watchdog_workqueue);
1232
1233 video_unregister_device(dev->vfd_enc);
1234 video_unregister_device(dev->vfd_dec);
1235 v4l2_device_unregister(&dev->v4l2_dev);
2e731e44 1236 s5p_mfc_release_firmware(dev);
af935746
KD		 1237 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1238 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
6e83e6e2
AK		 1239 if (pdev->dev.of_node) {
1240 put_device(dev->mem_dev_l);
1241 put_device(dev->mem_dev_r);
1242 }
af935746 1243
af935746 1244 s5p_mfc_final_pm(dev);
af935746
KD		 1245 return 0;
1246}
1247
1248#ifdef CONFIG_PM_SLEEP
1249
1250static int s5p_mfc_suspend(struct device *dev)
1251{
1252 struct platform_device *pdev = to_platform_device(dev);
1253 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1254 int ret;
1255
1256 if (m_dev->num_inst == 0)
1257 return 0;
81c9bcfb 1258
af935746
KD		 1259 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1260 mfc_err("Error: going to suspend for a second time\n");
1261 return -EIO;
1262 }
1263
1264 /* Check if we're processing then wait if it necessary. */
1265 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1266 /* Try and lock the HW */
1267 /* Wait on the interrupt waitqueue */
1268 ret = wait_event_interruptible_timeout(m_dev->queue,
76a4ddbd 1269 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
af935746
KD		 1270 if (ret == 0) {
1271 mfc_err("Waiting for hardware to finish timed out\n");
1272 return -EIO;
1273 }
1274 }
81c9bcfb
SK		 1275
1276 return s5p_mfc_sleep(m_dev);
af935746
KD		 1277}
1278
1279static int s5p_mfc_resume(struct device *dev)
1280{
1281 struct platform_device *pdev = to_platform_device(dev);
1282 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1283
1284 if (m_dev->num_inst == 0)
1285 return 0;
1286 return s5p_mfc_wakeup(m_dev);
1287}
1288#endif
1289
1290#ifdef CONFIG_PM_RUNTIME
1291static int s5p_mfc_runtime_suspend(struct device *dev)
1292{
1293 struct platform_device *pdev = to_platform_device(dev);
1294 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1295
1296 atomic_set(&m_dev->pm.power, 0);
1297 return 0;
1298}
1299
1300static int s5p_mfc_runtime_resume(struct device *dev)
1301{
1302 struct platform_device *pdev = to_platform_device(dev);
1303 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1304 int pre_power;
1305
1306 if (!m_dev->alloc_ctx)
1307 return 0;
1308 pre_power = atomic_read(&m_dev->pm.power);
1309 atomic_set(&m_dev->pm.power, 1);
1310 return 0;
1311}
1312#endif
1313
1314/* Power management */
1315static const struct dev_pm_ops s5p_mfc_pm_ops = {
1316 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1317 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1318 NULL)
1319};
1320
8f532a7f
AK		 1321struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1322 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1323 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1324 .dsc = DESC_BUF_SIZE,
1325 .shm = SHARED_BUF_SIZE,
1326};
1327
1328struct s5p_mfc_buf_size buf_size_v5 = {
1329 .fw = MAX_FW_SIZE,
1330 .cpb = MAX_CPB_SIZE,
1331 .priv = &mfc_buf_size_v5,
1332};
1333
1334struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1335 .base = MFC_BASE_ALIGN_ORDER,
1336};
1337
1338static struct s5p_mfc_variant mfc_drvdata_v5 = {
1339 .version = MFC_VERSION,
1340 .port_num = MFC_NUM_PORTS,
1341 .buf_size = &buf_size_v5,
1342 .buf_align = &mfc_buf_align_v5,
f96f3cfa
JP		 1343 .fw_name = "s5p-mfc.fw",
1344};
1345
1346struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1347 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1348 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1349 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1350 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1351 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1352};
1353
1354struct s5p_mfc_buf_size buf_size_v6 = {
1355 .fw = MAX_FW_SIZE_V6,
1356 .cpb = MAX_CPB_SIZE_V6,
1357 .priv = &mfc_buf_size_v6,
1358};
1359
1360struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1361 .base = 0,
1362};
1363
1364static struct s5p_mfc_variant mfc_drvdata_v6 = {
1365 .version = MFC_VERSION_V6,
1366 .port_num = MFC_NUM_PORTS_V6,
1367 .buf_size = &buf_size_v6,
1368 .buf_align = &mfc_buf_align_v6,
f96f3cfa 1369 .fw_name = "s5p-mfc-v6.fw",
8f532a7f
AK		 1370};
1371
5441e9da
AK		 1372struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1373 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1374 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1375 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1376 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1377 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1378};
1379
1380struct s5p_mfc_buf_size buf_size_v7 = {
1381 .fw = MAX_FW_SIZE_V7,
1382 .cpb = MAX_CPB_SIZE_V7,
1383 .priv = &mfc_buf_size_v7,
1384};
1385
1386struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1387 .base = 0,
1388};
1389
1390static struct s5p_mfc_variant mfc_drvdata_v7 = {
1391 .version = MFC_VERSION_V7,
1392 .port_num = MFC_NUM_PORTS_V7,
1393 .buf_size = &buf_size_v7,
1394 .buf_align = &mfc_buf_align_v7,
1395 .fw_name = "s5p-mfc-v7.fw",
1396};
1397
8f532a7f
AK		 1398static struct platform_device_id mfc_driver_ids[] = {
1399 {
1400 .name = "s5p-mfc",
1401 .driver_data = (unsigned long)&mfc_drvdata_v5,
f96f3cfa
JP		 1402 }, {
1403 .name = "s5p-mfc-v5",
1404 .driver_data = (unsigned long)&mfc_drvdata_v5,
1405 }, {
1406 .name = "s5p-mfc-v6",
1407 .driver_data = (unsigned long)&mfc_drvdata_v6,
5441e9da
AK		 1408 }, {
1409 .name = "s5p-mfc-v7",
1410 .driver_data = (unsigned long)&mfc_drvdata_v7,
8f532a7f
AK		 1411 },
1412 {},
1413};
1414MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1415
b27a23be
AK		 1416static const struct of_device_id exynos_mfc_match[] = {
1417 {
1418 .compatible = "samsung,mfc-v5",
1419 .data = &mfc_drvdata_v5,
1420 }, {
1421 .compatible = "samsung,mfc-v6",
1422 .data = &mfc_drvdata_v6,
5441e9da
AK		 1423 }, {
1424 .compatible = "samsung,mfc-v7",
1425 .data = &mfc_drvdata_v7,
b27a23be
AK		 1426 },
1427 {},
1428};
1429MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1430
1431static void *mfc_get_drv_data(struct platform_device *pdev)
1432{
1433 struct s5p_mfc_variant *driver_data = NULL;
1434
1435 if (pdev->dev.of_node) {
1436 const struct of_device_id *match;
a40a1382 1437 match = of_match_node(exynos_mfc_match,
b27a23be
AK		 1438 pdev->dev.of_node);
1439 if (match)
1440 driver_data = (struct s5p_mfc_variant *)match->data;
1441 } else {
1442 driver_data = (struct s5p_mfc_variant *)
1443 platform_get_device_id(pdev)->driver_data;
1444 }
1445 return driver_data;
1446}
1447
1e393e90 1448static struct platform_driver s5p_mfc_driver = {
8f532a7f 1449 .probe = s5p_mfc_probe,
4c62e976 1450 .remove = s5p_mfc_remove,
8f532a7f 1451 .id_table = mfc_driver_ids,
af935746
KD		 1452 .driver = {
1453 .name = S5P_MFC_NAME,
1454 .owner = THIS_MODULE,
b27a23be
AK		 1455 .pm = &s5p_mfc_pm_ops,
1456 .of_match_table = exynos_mfc_match,
af935746
KD		 1457 },
1458};
1459
1d6629b1 1460module_platform_driver(s5p_mfc_driver);
af935746
KD		 1461
1462MODULE_LICENSE("GPL");
1463MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1464MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1465
Linux kernel - Deliverables
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