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Merge remote-tracking branch 'asoc/topic/arizona' into asoc-next
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc_enc.c
CommitLineData
af935746 1/*
2c3fb08b 2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
af935746
KD		 3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * Jeongtae Park <jtp.park@samsung.com>
8 * Kamil Debski <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/clk.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/version.h>
23#include <linux/videodev2.h>
f9f715a9 24#include <media/v4l2-event.h>
af935746
KD		 25#include <linux/workqueue.h>
26#include <media/v4l2-ctrls.h>
27#include <media/videobuf2-core.h>
af935746
KD		 28#include "s5p_mfc_common.h"
29#include "s5p_mfc_debug.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33
34#define DEF_SRC_FMT_ENC V4L2_PIX_FMT_NV12MT
35#define DEF_DST_FMT_ENC V4L2_PIX_FMT_H264
af935746
KD		 36
37static struct s5p_mfc_fmt formats[] = {
38 {
f96f3cfa
JP		 39 .name = "4:2:0 2 Planes 16x16 Tiles",
40 .fourcc = V4L2_PIX_FMT_NV12MT_16X16,
41 .codec_mode = S5P_MFC_CODEC_NONE,
42 .type = MFC_FMT_RAW,
43 .num_planes = 2,
af935746
KD		 44 },
45 {
f96f3cfa
JP		 46 .name = "4:2:0 2 Planes 64x32 Tiles",
47 .fourcc = V4L2_PIX_FMT_NV12MT,
48 .codec_mode = S5P_MFC_CODEC_NONE,
49 .type = MFC_FMT_RAW,
50 .num_planes = 2,
af935746
KD		 51 },
52 {
f96f3cfa
JP		 53 .name = "4:2:0 2 Planes Y/CbCr",
54 .fourcc = V4L2_PIX_FMT_NV12M,
55 .codec_mode = S5P_MFC_CODEC_NONE,
56 .type = MFC_FMT_RAW,
57 .num_planes = 2,
af935746
KD		 58 },
59 {
f96f3cfa
JP		 60 .name = "4:2:0 2 Planes Y/CrCb",
61 .fourcc = V4L2_PIX_FMT_NV21M,
62 .codec_mode = S5P_MFC_CODEC_NONE,
63 .type = MFC_FMT_RAW,
64 .num_planes = 2,
af935746
KD		 65 },
66 {
f96f3cfa
JP		 67 .name = "H264 Encoded Stream",
68 .fourcc = V4L2_PIX_FMT_H264,
69 .codec_mode = S5P_MFC_CODEC_H264_ENC,
70 .type = MFC_FMT_ENC,
71 .num_planes = 1,
72 },
73 {
74 .name = "MPEG4 Encoded Stream",
75 .fourcc = V4L2_PIX_FMT_MPEG4,
76 .codec_mode = S5P_MFC_CODEC_MPEG4_ENC,
77 .type = MFC_FMT_ENC,
78 .num_planes = 1,
79 },
80 {
81 .name = "H263 Encoded Stream",
82 .fourcc = V4L2_PIX_FMT_H263,
83 .codec_mode = S5P_MFC_CODEC_H263_ENC,
84 .type = MFC_FMT_ENC,
85 .num_planes = 1,
af935746
KD		 86 },
87};
88
89#define NUM_FORMATS ARRAY_SIZE(formats)
90static struct s5p_mfc_fmt *find_format(struct v4l2_format *f, unsigned int t)
91{
92 unsigned int i;
93
94 for (i = 0; i < NUM_FORMATS; i++) {
95 if (formats[i].fourcc == f->fmt.pix_mp.pixelformat &&
96 formats[i].type == t)
97 return &formats[i];
98 }
99 return NULL;
100}
101
102static struct mfc_control controls[] = {
103 {
104 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
105 .type = V4L2_CTRL_TYPE_INTEGER,
106 .minimum = 0,
107 .maximum = (1 << 16) - 1,
108 .step = 1,
109 .default_value = 0,
110 },
111 {
112 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
113 .type = V4L2_CTRL_TYPE_MENU,
114 .minimum = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
115 .maximum = V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES,
116 .default_value = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
117 .menu_skip_mask = 0,
118 },
119 {
120 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB,
121 .type = V4L2_CTRL_TYPE_INTEGER,
122 .minimum = 1,
123 .maximum = (1 << 16) - 1,
124 .step = 1,
125 .default_value = 1,
126 },
127 {
128 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES,
129 .type = V4L2_CTRL_TYPE_INTEGER,
130 .minimum = 1900,
131 .maximum = (1 << 30) - 1,
132 .step = 1,
133 .default_value = 1900,
134 },
135 {
136 .id = V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB,
137 .type = V4L2_CTRL_TYPE_INTEGER,
138 .minimum = 0,
139 .maximum = (1 << 16) - 1,
140 .step = 1,
141 .default_value = 0,
142 },
143 {
144 .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING,
145 .type = V4L2_CTRL_TYPE_BOOLEAN,
146 .name = "Padding Control Enable",
147 .minimum = 0,
148 .maximum = 1,
149 .step = 1,
150 .default_value = 0,
151 },
152 {
153 .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV,
154 .type = V4L2_CTRL_TYPE_INTEGER,
155 .name = "Padding Color YUV Value",
156 .minimum = 0,
157 .maximum = (1 << 25) - 1,
158 .step = 1,
159 .default_value = 0,
160 },
161 {
162 .id = V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
163 .type = V4L2_CTRL_TYPE_BOOLEAN,
164 .minimum = 0,
165 .maximum = 1,
166 .step = 1,
167 .default_value = 0,
168 },
169 {
170 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
171 .type = V4L2_CTRL_TYPE_INTEGER,
172 .minimum = 1,
173 .maximum = (1 << 30) - 1,
174 .step = 1,
175 .default_value = 1,
176 },
177 {
178 .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF,
179 .type = V4L2_CTRL_TYPE_INTEGER,
180 .name = "Rate Control Reaction Coeff.",
181 .minimum = 1,
182 .maximum = (1 << 16) - 1,
183 .step = 1,
184 .default_value = 1,
185 },
186 {
187 .id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE,
188 .type = V4L2_CTRL_TYPE_MENU,
189 .name = "Force frame type",
190 .minimum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
191 .maximum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED,
192 .default_value = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
193 .menu_skip_mask = 0,
194 },
195 {
196 .id = V4L2_CID_MPEG_VIDEO_VBV_SIZE,
197 .type = V4L2_CTRL_TYPE_INTEGER,
198 .minimum = 0,
199 .maximum = (1 << 16) - 1,
200 .step = 1,
201 .default_value = 0,
202 },
203 {
204 .id = V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
205 .type = V4L2_CTRL_TYPE_INTEGER,
206 .minimum = 0,
207 .maximum = (1 << 16) - 1,
208 .step = 1,
209 .default_value = 0,
210 },
211 {
212 .id = V4L2_CID_MPEG_VIDEO_HEADER_MODE,
213 .type = V4L2_CTRL_TYPE_MENU,
214 .minimum = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
215 .maximum = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
216 .default_value = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
217 .menu_skip_mask = 0,
218 },
219 {
220 .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE,
221 .type = V4L2_CTRL_TYPE_MENU,
222 .name = "Frame Skip Enable",
223 .minimum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
224 .maximum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
225 .menu_skip_mask = 0,
226 .default_value = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
227 },
228 {
229 .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT,
230 .type = V4L2_CTRL_TYPE_BOOLEAN,
231 .name = "Fixed Target Bit Enable",
232 .minimum = 0,
233 .maximum = 1,
234 .default_value = 0,
053e09f3 235 .step = 1,
af935746
KD		 236 .menu_skip_mask = 0,
237 },
238 {
239 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
240 .type = V4L2_CTRL_TYPE_INTEGER,
241 .minimum = 0,
242 .maximum = 2,
243 .step = 1,
244 .default_value = 0,
245 },
246 {
247 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
248 .type = V4L2_CTRL_TYPE_MENU,
249 .minimum = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
250 .maximum = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH,
251 .default_value = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
252 .menu_skip_mask = ~(
253 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
254 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
255 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)
256 ),
257 },
258 {
259 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
260 .type = V4L2_CTRL_TYPE_MENU,
261 .minimum = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
262 .maximum = V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
263 .default_value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
af935746
KD		 264 },
265 {
266 .id = V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL,
267 .type = V4L2_CTRL_TYPE_MENU,
268 .minimum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
269 .maximum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_5,
270 .default_value = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
271 .menu_skip_mask = 0,
272 },
273 {
274 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
275 .type = V4L2_CTRL_TYPE_MENU,
276 .minimum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
277 .maximum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY,
278 .default_value = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
279 .menu_skip_mask = 0,
280 },
281 {
282 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA,
283 .type = V4L2_CTRL_TYPE_INTEGER,
284 .minimum = -6,
285 .maximum = 6,
286 .step = 1,
287 .default_value = 0,
288 },
289 {
290 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA,
291 .type = V4L2_CTRL_TYPE_INTEGER,
292 .minimum = -6,
293 .maximum = 6,
294 .step = 1,
295 .default_value = 0,
296 },
297 {
298 .id = V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE,
299 .type = V4L2_CTRL_TYPE_MENU,
300 .minimum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
301 .maximum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
302 .default_value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
303 .menu_skip_mask = 0,
304 },
305 {
306 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P,
307 .type = V4L2_CTRL_TYPE_INTEGER,
308 .name = "The Number of Ref. Pic for P",
309 .minimum = 1,
310 .maximum = 2,
311 .step = 1,
312 .default_value = 1,
313 },
314 {
315 .id = V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
316 .type = V4L2_CTRL_TYPE_BOOLEAN,
317 .minimum = 0,
318 .maximum = 1,
319 .step = 1,
320 .default_value = 0,
321 },
322 {
323 .id = V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE,
324 .type = V4L2_CTRL_TYPE_BOOLEAN,
325 .minimum = 0,
326 .maximum = 1,
327 .step = 1,
328 .default_value = 0,
329 },
330 {
331 .id = V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
332 .type = V4L2_CTRL_TYPE_INTEGER,
333 .minimum = 0,
334 .maximum = 51,
335 .step = 1,
336 .default_value = 1,
337 },
338 {
339 .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
340 .type = V4L2_CTRL_TYPE_INTEGER,
341 .minimum = 0,
342 .maximum = 51,
343 .step = 1,
344 .default_value = 1,
345 },
346 {
347 .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
348 .type = V4L2_CTRL_TYPE_INTEGER,
349 .minimum = 0,
350 .maximum = 51,
351 .step = 1,
352 .default_value = 1,
353 },
354 {
355 .id = V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
356 .type = V4L2_CTRL_TYPE_INTEGER,
357 .minimum = 0,
358 .maximum = 51,
359 .step = 1,
360 .default_value = 1,
361 },
362 {
363 .id = V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
364 .type = V4L2_CTRL_TYPE_INTEGER,
365 .minimum = 0,
366 .maximum = 51,
367 .step = 1,
368 .default_value = 1,
369 },
370 {
371 .id = V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP,
372 .type = V4L2_CTRL_TYPE_INTEGER,
373 .name = "H263 I-Frame QP value",
374 .minimum = 1,
375 .maximum = 31,
376 .step = 1,
377 .default_value = 1,
378 },
379 {
380 .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP,
381 .type = V4L2_CTRL_TYPE_INTEGER,
382 .name = "H263 Minimum QP value",
383 .minimum = 1,
384 .maximum = 31,
385 .step = 1,
386 .default_value = 1,
387 },
388 {
389 .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP,
390 .type = V4L2_CTRL_TYPE_INTEGER,
391 .name = "H263 Maximum QP value",
392 .minimum = 1,
393 .maximum = 31,
394 .step = 1,
395 .default_value = 1,
396 },
397 {
398 .id = V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP,
399 .type = V4L2_CTRL_TYPE_INTEGER,
400 .name = "H263 P frame QP value",
401 .minimum = 1,
402 .maximum = 31,
403 .step = 1,
404 .default_value = 1,
405 },
406 {
407 .id = V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP,
408 .type = V4L2_CTRL_TYPE_INTEGER,
409 .name = "H263 B frame QP value",
410 .minimum = 1,
411 .maximum = 31,
412 .step = 1,
413 .default_value = 1,
414 },
415 {
416 .id = V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP,
417 .type = V4L2_CTRL_TYPE_INTEGER,
418 .name = "MPEG4 I-Frame QP value",
419 .minimum = 1,
420 .maximum = 31,
421 .step = 1,
422 .default_value = 1,
423 },
424 {
425 .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP,
426 .type = V4L2_CTRL_TYPE_INTEGER,
427 .name = "MPEG4 Minimum QP value",
428 .minimum = 1,
429 .maximum = 31,
430 .step = 1,
431 .default_value = 1,
432 },
433 {
434 .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP,
435 .type = V4L2_CTRL_TYPE_INTEGER,
436 .name = "MPEG4 Maximum QP value",
437 .minimum = 0,
438 .maximum = 51,
439 .step = 1,
440 .default_value = 1,
441 },
442 {
443 .id = V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP,
444 .type = V4L2_CTRL_TYPE_INTEGER,
445 .name = "MPEG4 P frame QP value",
446 .minimum = 1,
447 .maximum = 31,
448 .step = 1,
449 .default_value = 1,
450 },
451 {
452 .id = V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP,
453 .type = V4L2_CTRL_TYPE_INTEGER,
454 .name = "MPEG4 B frame QP value",
455 .minimum = 1,
456 .maximum = 31,
457 .step = 1,
458 .default_value = 1,
459 },
460 {
461 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK,
462 .type = V4L2_CTRL_TYPE_BOOLEAN,
463 .name = "H264 Dark Reg Adaptive RC",
464 .minimum = 0,
465 .maximum = 1,
466 .step = 1,
467 .default_value = 0,
468 },
469 {
470 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH,
471 .type = V4L2_CTRL_TYPE_BOOLEAN,
472 .name = "H264 Smooth Reg Adaptive RC",
473 .minimum = 0,
474 .maximum = 1,
475 .step = 1,
476 .default_value = 0,
477 },
478 {
479 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC,
480 .type = V4L2_CTRL_TYPE_BOOLEAN,
481 .name = "H264 Static Reg Adaptive RC",
482 .minimum = 0,
483 .maximum = 1,
484 .step = 1,
485 .default_value = 0,
486 },
487 {
488 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY,
489 .type = V4L2_CTRL_TYPE_BOOLEAN,
490 .name = "H264 Activity Reg Adaptive RC",
491 .minimum = 0,
492 .maximum = 1,
493 .step = 1,
494 .default_value = 0,
495 },
496 {
497 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE,
498 .type = V4L2_CTRL_TYPE_BOOLEAN,
499 .minimum = 0,
500 .maximum = 1,
501 .step = 1,
502 .default_value = 0,
503 },
504 {
505 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
506 .type = V4L2_CTRL_TYPE_MENU,
507 .minimum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED,
508 .maximum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED,
afd14f48 509 .default_value = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED,
af935746
KD		 510 .menu_skip_mask = 0,
511 },
512 {
513 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
514 .type = V4L2_CTRL_TYPE_INTEGER,
515 .minimum = 0,
516 .maximum = (1 << 16) - 1,
517 .step = 1,
518 .default_value = 0,
519 },
520 {
521 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT,
522 .type = V4L2_CTRL_TYPE_INTEGER,
523 .minimum = 0,
524 .maximum = (1 << 16) - 1,
525 .step = 1,
526 .default_value = 0,
527 },
528 {
529 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
530 .type = V4L2_CTRL_TYPE_BOOLEAN,
531 .minimum = 0,
532 .maximum = 1,
533 .step = 1,
534 .default_value = 1,
535 },
536 {
537 .id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,
538 .type = V4L2_CTRL_TYPE_INTEGER,
539 .minimum = 0,
540 .maximum = (1 << 16) - 1,
541 .step = 1,
542 .default_value = 0,
543 },
544 {
545 .id = V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE,
546 .type = V4L2_CTRL_TYPE_MENU,
547 .minimum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
548 .maximum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE,
afd14f48 549 .default_value = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
af935746
KD		 550 .menu_skip_mask = 0,
551 },
552 {
553 .id = V4L2_CID_MPEG_VIDEO_MPEG4_QPEL,
554 .type = V4L2_CTRL_TYPE_BOOLEAN,
555 .minimum = 0,
556 .maximum = 1,
557 .step = 1,
558 .default_value = 0,
559 },
560};
561
562#define NUM_CTRLS ARRAY_SIZE(controls)
563static const char * const *mfc51_get_menu(u32 id)
564{
565 static const char * const mfc51_video_frame_skip[] = {
566 "Disabled",
567 "Level Limit",
568 "VBV/CPB Limit",
569 NULL,
570 };
571 static const char * const mfc51_video_force_frame[] = {
572 "Disabled",
573 "I Frame",
574 "Not Coded",
575 NULL,
576 };
577 switch (id) {
578 case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE:
579 return mfc51_video_frame_skip;
580 case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
581 return mfc51_video_force_frame;
582 }
583 return NULL;
584}
585
586static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
587{
588 mfc_debug(2, "src=%d, dst=%d, state=%d\n",
589 ctx->src_queue_cnt, ctx->dst_queue_cnt, ctx->state);
590 /* context is ready to make header */
591 if (ctx->state == MFCINST_GOT_INST && ctx->dst_queue_cnt >= 1)
592 return 1;
593 /* context is ready to encode a frame */
f96f3cfa 594 if ((ctx->state == MFCINST_RUNNING ||
e9d98ddc 595 ctx->state == MFCINST_HEAD_PRODUCED) &&
af935746
KD		 596 ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
597 return 1;
f9f715a9 598 /* context is ready to encode remaining frames */
af935746 599 if (ctx->state == MFCINST_FINISHING &&
f9f715a9 600 ctx->dst_queue_cnt >= 1)
af935746
KD		 601 return 1;
602 mfc_debug(2, "ctx is not ready\n");
603 return 0;
604}
605
606static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx)
607{
608 struct s5p_mfc_buf *mb_entry;
609 unsigned long mb_y_addr, mb_c_addr;
610
611 /* move buffers in ref queue to src queue */
612 while (!list_empty(&ctx->ref_queue)) {
613 mb_entry = list_entry((&ctx->ref_queue)->next,
614 struct s5p_mfc_buf, list);
ba7fcb0c
MS		 615 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
616 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 617 list_del(&mb_entry->list);
618 ctx->ref_queue_cnt--;
619 list_add_tail(&mb_entry->list, &ctx->src_queue);
620 ctx->src_queue_cnt++;
621 }
622 mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
623 ctx->src_queue_cnt, ctx->ref_queue_cnt);
624 INIT_LIST_HEAD(&ctx->ref_queue);
625 ctx->ref_queue_cnt = 0;
626}
627
628static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx)
629{
630 struct s5p_mfc_dev *dev = ctx->dev;
631 struct s5p_mfc_buf *dst_mb;
632 unsigned long dst_addr;
633 unsigned int dst_size;
634 unsigned long flags;
635
636 spin_lock_irqsave(&dev->irqlock, flags);
637 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c 638 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
af935746 639 dst_size = vb2_plane_size(dst_mb->b, 0);
43a1ea1f
AK		 640 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
641 dst_size);
af935746
KD		 642 spin_unlock_irqrestore(&dev->irqlock, flags);
643 return 0;
644}
645
646static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
647{
648 struct s5p_mfc_dev *dev = ctx->dev;
649 struct s5p_mfc_enc_params *p = &ctx->enc_params;
650 struct s5p_mfc_buf *dst_mb;
651 unsigned long flags;
e9d98ddc 652 unsigned int enc_pb_count;
af935746
KD		 653
654 if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) {
655 spin_lock_irqsave(&dev->irqlock, flags);
656 dst_mb = list_entry(ctx->dst_queue.next,
657 struct s5p_mfc_buf, list);
658 list_del(&dst_mb->list);
659 ctx->dst_queue_cnt--;
660 vb2_set_plane_payload(dst_mb->b, 0,
43a1ea1f 661 s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev));
af935746
KD		 662 vb2_buffer_done(dst_mb->b, VB2_BUF_STATE_DONE);
663 spin_unlock_irqrestore(&dev->irqlock, flags);
664 }
e9d98ddc
AK		 665
666 if (!IS_MFCV6(dev)) {
f96f3cfa
JP		 667 ctx->state = MFCINST_RUNNING;
668 if (s5p_mfc_ctx_ready(ctx))
669 set_work_bit_irqsave(ctx);
670 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
e9d98ddc
AK		 671 } else {
672 enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops,
f96f3cfa 673 get_enc_dpb_count, dev);
e9d98ddc
AK		 674 if (ctx->pb_count < enc_pb_count)
675 ctx->pb_count = enc_pb_count;
676 ctx->state = MFCINST_HEAD_PRODUCED;
677 }
f96f3cfa 678
af935746
KD		 679 return 0;
680}
681
682static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
683{
684 struct s5p_mfc_dev *dev = ctx->dev;
685 struct s5p_mfc_buf *dst_mb;
686 struct s5p_mfc_buf *src_mb;
687 unsigned long flags;
688 unsigned long src_y_addr, src_c_addr, dst_addr;
689 unsigned int dst_size;
690
691 spin_lock_irqsave(&dev->irqlock, flags);
692 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c
MS		 693 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
694 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
43a1ea1f
AK		 695 s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, src_y_addr,
696 src_c_addr);
af935746
KD		 697 spin_unlock_irqrestore(&dev->irqlock, flags);
698
699 spin_lock_irqsave(&dev->irqlock, flags);
700 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c 701 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
af935746 702 dst_size = vb2_plane_size(dst_mb->b, 0);
43a1ea1f
AK		 703 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
704 dst_size);
af935746
KD		 705 spin_unlock_irqrestore(&dev->irqlock, flags);
706
707 return 0;
708}
709
710static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
711{
712 struct s5p_mfc_dev *dev = ctx->dev;
713 struct s5p_mfc_buf *mb_entry;
714 unsigned long enc_y_addr, enc_c_addr;
715 unsigned long mb_y_addr, mb_c_addr;
716 int slice_type;
717 unsigned int strm_size;
718 unsigned long flags;
719
43a1ea1f
AK		 720 slice_type = s5p_mfc_hw_call(dev->mfc_ops, get_enc_slice_type, dev);
721 strm_size = s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev);
4130eabc
AH		 722 mfc_debug(2, "Encoded slice type: %d\n", slice_type);
723 mfc_debug(2, "Encoded stream size: %d\n", strm_size);
724 mfc_debug(2, "Display order: %d\n",
af935746
KD		 725 mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));
726 spin_lock_irqsave(&dev->irqlock, flags);
727 if (slice_type >= 0) {
43a1ea1f
AK		 728 s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx,
729 &enc_y_addr, &enc_c_addr);
af935746 730 list_for_each_entry(mb_entry, &ctx->src_queue, list) {
ba7fcb0c
MS		 731 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
732 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 733 if ((enc_y_addr == mb_y_addr) &&
734 (enc_c_addr == mb_c_addr)) {
735 list_del(&mb_entry->list);
736 ctx->src_queue_cnt--;
737 vb2_buffer_done(mb_entry->b,
738 VB2_BUF_STATE_DONE);
739 break;
740 }
741 }
742 list_for_each_entry(mb_entry, &ctx->ref_queue, list) {
ba7fcb0c
MS		 743 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
744 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 745 if ((enc_y_addr == mb_y_addr) &&
746 (enc_c_addr == mb_c_addr)) {
747 list_del(&mb_entry->list);
748 ctx->ref_queue_cnt--;
749 vb2_buffer_done(mb_entry->b,
750 VB2_BUF_STATE_DONE);
751 break;
752 }
753 }
754 }
755 if ((ctx->src_queue_cnt > 0) && (ctx->state == MFCINST_RUNNING)) {
756 mb_entry = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
757 list);
f9f715a9 758 if (mb_entry->flags & MFC_BUF_FLAG_USED) {
af935746
KD		 759 list_del(&mb_entry->list);
760 ctx->src_queue_cnt--;
761 list_add_tail(&mb_entry->list, &ctx->ref_queue);
762 ctx->ref_queue_cnt++;
763 }
764 mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
765 ctx->src_queue_cnt, ctx->ref_queue_cnt);
766 }
767 if (strm_size > 0) {
768 /* at least one more dest. buffers exist always */
769 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
770 list);
771 list_del(&mb_entry->list);
772 ctx->dst_queue_cnt--;
773 switch (slice_type) {
774 case S5P_FIMV_ENC_SI_SLICE_TYPE_I:
775 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
776 break;
777 case S5P_FIMV_ENC_SI_SLICE_TYPE_P:
778 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
779 break;
780 case S5P_FIMV_ENC_SI_SLICE_TYPE_B:
781 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_BFRAME;
782 break;
783 }
784 vb2_set_plane_payload(mb_entry->b, 0, strm_size);
785 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
786 }
787 spin_unlock_irqrestore(&dev->irqlock, flags);
7fb89eca
AH		 788 if ((ctx->src_queue_cnt == 0) || (ctx->dst_queue_cnt == 0))
789 clear_work_bit(ctx);
af935746
KD		 790 return 0;
791}
792
793static struct s5p_mfc_codec_ops encoder_codec_ops = {
794 .pre_seq_start = enc_pre_seq_start,
795 .post_seq_start = enc_post_seq_start,
796 .pre_frame_start = enc_pre_frame_start,
797 .post_frame_start = enc_post_frame_start,
798};
799
800/* Query capabilities of the device */
801static int vidioc_querycap(struct file *file, void *priv,
802 struct v4l2_capability *cap)
803{
804 struct s5p_mfc_dev *dev = video_drvdata(file);
805
806 strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
807 strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
808 cap->bus_info[0] = 0;
809 cap->version = KERNEL_VERSION(1, 0, 0);
f0476a83
SN		 810 /*
811 * This is only a mem-to-mem video device. The capture and output
812 * device capability flags are left only for backward compatibility
813 * and are scheduled for removal.
814 */
815 cap->capabilities = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING |
816 V4L2_CAP_VIDEO_CAPTURE_MPLANE |
817 V4L2_CAP_VIDEO_OUTPUT_MPLANE;
af935746
KD		 818 return 0;
819}
820
821static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool mplane, bool out)
822{
823 struct s5p_mfc_fmt *fmt;
824 int i, j = 0;
825
826 for (i = 0; i < ARRAY_SIZE(formats); ++i) {
827 if (mplane && formats[i].num_planes == 1)
828 continue;
829 else if (!mplane && formats[i].num_planes > 1)
830 continue;
831 if (out && formats[i].type != MFC_FMT_RAW)
832 continue;
833 else if (!out && formats[i].type != MFC_FMT_ENC)
834 continue;
835 if (j == f->index) {
836 fmt = &formats[i];
837 strlcpy(f->description, fmt->name,
838 sizeof(f->description));
839 f->pixelformat = fmt->fourcc;
840 return 0;
841 }
842 ++j;
843 }
844 return -EINVAL;
845}
846
847static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv,
848 struct v4l2_fmtdesc *f)
849{
850 return vidioc_enum_fmt(f, false, false);
851}
852
853static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
854 struct v4l2_fmtdesc *f)
855{
856 return vidioc_enum_fmt(f, true, false);
857}
858
859static int vidioc_enum_fmt_vid_out(struct file *file, void *prov,
860 struct v4l2_fmtdesc *f)
861{
862 return vidioc_enum_fmt(f, false, true);
863}
864
865static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov,
866 struct v4l2_fmtdesc *f)
867{
868 return vidioc_enum_fmt(f, true, true);
869}
870
871static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
872{
873 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
874 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
875
876 mfc_debug(2, "f->type = %d ctx->state = %d\n", f->type, ctx->state);
877 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
878 /* This is run on output (encoder dest) */
879 pix_fmt_mp->width = 0;
880 pix_fmt_mp->height = 0;
881 pix_fmt_mp->field = V4L2_FIELD_NONE;
882 pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc;
883 pix_fmt_mp->num_planes = ctx->dst_fmt->num_planes;
884
885 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->enc_dst_buf_size;
886 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->enc_dst_buf_size;
887 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
888 /* This is run on capture (encoder src) */
889 pix_fmt_mp->width = ctx->img_width;
890 pix_fmt_mp->height = ctx->img_height;
891
892 pix_fmt_mp->field = V4L2_FIELD_NONE;
893 pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc;
894 pix_fmt_mp->num_planes = ctx->src_fmt->num_planes;
895
896 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
897 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
898 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
899 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
900 } else {
901 mfc_err("invalid buf type\n");
902 return -EINVAL;
903 }
904 return 0;
905}
906
907static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
908{
b2634562 909 struct s5p_mfc_dev *dev = video_drvdata(file);
af935746
KD		 910 struct s5p_mfc_fmt *fmt;
911 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
912
913 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
914 fmt = find_format(f, MFC_FMT_ENC);
915 if (!fmt) {
916 mfc_err("failed to try output format\n");
917 return -EINVAL;
918 }
919
920 if (pix_fmt_mp->plane_fmt[0].sizeimage == 0) {
921 mfc_err("must be set encoding output size\n");
922 return -EINVAL;
923 }
924
925 pix_fmt_mp->plane_fmt[0].bytesperline =
926 pix_fmt_mp->plane_fmt[0].sizeimage;
927 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
928 fmt = find_format(f, MFC_FMT_RAW);
929 if (!fmt) {
930 mfc_err("failed to try output format\n");
931 return -EINVAL;
932 }
933
b2634562
JS		 934 if (!IS_MFCV6(dev)) {
935 if (fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
936 mfc_err("Not supported format.\n");
937 return -EINVAL;
938 }
939 } else if (IS_MFCV6(dev)) {
940 if (fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
941 mfc_err("Not supported format.\n");
942 return -EINVAL;
943 }
944 }
945
af935746
KD		 946 if (fmt->num_planes != pix_fmt_mp->num_planes) {
947 mfc_err("failed to try output format\n");
948 return -EINVAL;
949 }
0749ae35
AH		 950 v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1,
951 &pix_fmt_mp->height, 4, 1080, 1, 0);
af935746
KD		 952 } else {
953 mfc_err("invalid buf type\n");
954 return -EINVAL;
955 }
956 return 0;
957}
958
959static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
960{
961 struct s5p_mfc_dev *dev = video_drvdata(file);
962 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
af935746 963 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
af935746
KD		 964 int ret = 0;
965
966 ret = vidioc_try_fmt(file, priv, f);
967 if (ret)
968 return ret;
969 if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
970 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
971 ret = -EBUSY;
972 goto out;
973 }
974 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
b2634562
JS		 975 /* dst_fmt is validated by call to vidioc_try_fmt */
976 ctx->dst_fmt = find_format(f, MFC_FMT_ENC);
af935746 977 ctx->state = MFCINST_INIT;
af935746
KD		 978 ctx->codec_mode = ctx->dst_fmt->codec_mode;
979 ctx->enc_dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage;
980 pix_fmt_mp->plane_fmt[0].bytesperline = 0;
981 ctx->dst_bufs_cnt = 0;
982 ctx->capture_state = QUEUE_FREE;
43a1ea1f 983 s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
7fb89eca 984 set_work_bit_irqsave(ctx);
af935746 985 s5p_mfc_clean_ctx_int_flags(ctx);
43a1ea1f 986 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746 987 if (s5p_mfc_wait_for_done_ctx(ctx, \
43a1ea1f 988 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 1)) {
af935746
KD		 989 /* Error or timeout */
990 mfc_err("Error getting instance from hardware\n");
43a1ea1f
AK		 991 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer,
992 ctx);
af935746
KD		 993 ret = -EIO;
994 goto out;
995 }
996 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
997 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
b2634562
JS		 998 /* src_fmt is validated by call to vidioc_try_fmt */
999 ctx->src_fmt = find_format(f, MFC_FMT_RAW);
af935746
KD		 1000 ctx->img_width = pix_fmt_mp->width;
1001 ctx->img_height = pix_fmt_mp->height;
1002 mfc_debug(2, "codec number: %d\n", ctx->src_fmt->codec_mode);
1003 mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n",
1004 pix_fmt_mp->width, pix_fmt_mp->height,
1005 ctx->img_width, ctx->img_height);
af935746 1006
8f532a7f
AK		 1007 s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx);
1008 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
1009 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
1010 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
1011 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
af935746 1012
af935746
KD		 1013 ctx->src_bufs_cnt = 0;
1014 ctx->output_state = QUEUE_FREE;
1015 } else {
1016 mfc_err("invalid buf type\n");
1017 return -EINVAL;
1018 }
1019out:
1020 mfc_debug_leave();
1021 return ret;
1022}
1023
1024static int vidioc_reqbufs(struct file *file, void *priv,
1025 struct v4l2_requestbuffers *reqbufs)
1026{
f96f3cfa 1027 struct s5p_mfc_dev *dev = video_drvdata(file);
af935746
KD		 1028 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1029 int ret = 0;
1030
1031 /* if memory is not mmp or userptr return error */
1032 if ((reqbufs->memory != V4L2_MEMORY_MMAP) &&
1033 (reqbufs->memory != V4L2_MEMORY_USERPTR))
1034 return -EINVAL;
1035 if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1036 if (ctx->capture_state != QUEUE_FREE) {
1037 mfc_err("invalid capture state: %d\n",
1038 ctx->capture_state);
1039 return -EINVAL;
1040 }
1041 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1042 if (ret != 0) {
1043 mfc_err("error in vb2_reqbufs() for E(D)\n");
1044 return ret;
1045 }
1046 ctx->capture_state = QUEUE_BUFS_REQUESTED;
f96f3cfa 1047
e9d98ddc
AK		 1048 ret = s5p_mfc_hw_call(ctx->dev->mfc_ops,
1049 alloc_codec_buffers, ctx);
1050 if (ret) {
1051 mfc_err("Failed to allocate encoding buffers\n");
1052 reqbufs->count = 0;
1053 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1054 return -ENOMEM;
af935746
KD		 1055 }
1056 } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1057 if (ctx->output_state != QUEUE_FREE) {
1058 mfc_err("invalid output state: %d\n",
1059 ctx->output_state);
1060 return -EINVAL;
1061 }
e9d98ddc
AK		 1062
1063 if (IS_MFCV6(dev)) {
1064 /* Check for min encoder buffers */
1065 if (ctx->pb_count &&
1066 (reqbufs->count < ctx->pb_count)) {
1067 reqbufs->count = ctx->pb_count;
1068 mfc_debug(2, "Minimum %d output buffers needed\n",
1069 ctx->pb_count);
1070 } else {
1071 ctx->pb_count = reqbufs->count;
1072 }
1073 }
1074
af935746
KD		 1075 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
1076 if (ret != 0) {
1077 mfc_err("error in vb2_reqbufs() for E(S)\n");
1078 return ret;
1079 }
1080 ctx->output_state = QUEUE_BUFS_REQUESTED;
1081 } else {
1082 mfc_err("invalid buf type\n");
1083 return -EINVAL;
1084 }
1085 return ret;
1086}
1087
1088static int vidioc_querybuf(struct file *file, void *priv,
1089 struct v4l2_buffer *buf)
1090{
1091 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1092 int ret = 0;
1093
1094 /* if memory is not mmp or userptr return error */
1095 if ((buf->memory != V4L2_MEMORY_MMAP) &&
1096 (buf->memory != V4L2_MEMORY_USERPTR))
1097 return -EINVAL;
1098 if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1099 if (ctx->state != MFCINST_GOT_INST) {
1100 mfc_err("invalid context state: %d\n", ctx->state);
1101 return -EINVAL;
1102 }
1103 ret = vb2_querybuf(&ctx->vq_dst, buf);
1104 if (ret != 0) {
1105 mfc_err("error in vb2_querybuf() for E(D)\n");
1106 return ret;
1107 }
1108 buf->m.planes[0].m.mem_offset += DST_QUEUE_OFF_BASE;
1109 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1110 ret = vb2_querybuf(&ctx->vq_src, buf);
1111 if (ret != 0) {
1112 mfc_err("error in vb2_querybuf() for E(S)\n");
1113 return ret;
1114 }
1115 } else {
1116 mfc_err("invalid buf type\n");
1117 return -EINVAL;
1118 }
1119 return ret;
1120}
1121
1122/* Queue a buffer */
1123static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1124{
1125 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1126
1127 if (ctx->state == MFCINST_ERROR) {
1128 mfc_err("Call on QBUF after unrecoverable error\n");
1129 return -EIO;
1130 }
f9f715a9
AH		 1131 if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1132 if (ctx->state == MFCINST_FINISHING) {
1133 mfc_err("Call on QBUF after EOS command\n");
1134 return -EIO;
1135 }
af935746 1136 return vb2_qbuf(&ctx->vq_src, buf);
f9f715a9 1137 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
af935746 1138 return vb2_qbuf(&ctx->vq_dst, buf);
f9f715a9 1139 }
af935746
KD		 1140 return -EINVAL;
1141}
1142
1143/* Dequeue a buffer */
1144static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1145{
f9f715a9
AH		 1146 const struct v4l2_event ev = {
1147 .type = V4L2_EVENT_EOS
1148 };
af935746 1149 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
f9f715a9 1150 int ret;
af935746
KD		 1151
1152 if (ctx->state == MFCINST_ERROR) {
1153 mfc_err("Call on DQBUF after unrecoverable error\n");
1154 return -EIO;
1155 }
f9f715a9
AH		 1156 if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1157 ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
1158 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1159 ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
1160 if (ret == 0 && ctx->state == MFCINST_FINISHED
1161 && list_empty(&ctx->vq_dst.done_list))
1162 v4l2_event_queue_fh(&ctx->fh, &ev);
1163 } else {
1164 ret = -EINVAL;
1165 }
1166
1167 return ret;
af935746
KD		 1168}
1169
6fa9dd06
TS		 1170/* Export DMA buffer */
1171static int vidioc_expbuf(struct file *file, void *priv,
1172 struct v4l2_exportbuffer *eb)
1173{
1174 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1175
1176 if (eb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1177 return vb2_expbuf(&ctx->vq_src, eb);
1178 if (eb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1179 return vb2_expbuf(&ctx->vq_dst, eb);
1180 return -EINVAL;
1181}
1182
af935746
KD		 1183/* Stream on */
1184static int vidioc_streamon(struct file *file, void *priv,
1185 enum v4l2_buf_type type)
1186{
1187 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1188
1189 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1190 return vb2_streamon(&ctx->vq_src, type);
1191 else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1192 return vb2_streamon(&ctx->vq_dst, type);
1193 return -EINVAL;
1194}
1195
1196/* Stream off, which equals to a pause */
1197static int vidioc_streamoff(struct file *file, void *priv,
1198 enum v4l2_buf_type type)
1199{
1200 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1201
1202 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1203 return vb2_streamoff(&ctx->vq_src, type);
1204 else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1205 return vb2_streamoff(&ctx->vq_dst, type);
1206 return -EINVAL;
1207}
1208
1209static inline int h264_level(enum v4l2_mpeg_video_h264_level lvl)
1210{
1211 static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_4_0 + 1] = {
1212 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_0 */ 10,
1213 /* V4L2_MPEG_VIDEO_H264_LEVEL_1B */ 9,
1214 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_1 */ 11,
1215 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_2 */ 12,
1216 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_3 */ 13,
1217 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_0 */ 20,
1218 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_1 */ 21,
1219 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_2 */ 22,
1220 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_0 */ 30,
1221 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_1 */ 31,
1222 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_2 */ 32,
1223 /* V4L2_MPEG_VIDEO_H264_LEVEL_4_0 */ 40,
1224 };
1225 return t[lvl];
1226}
1227
1228static inline int mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl)
1229{
1230 static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 + 1] = {
1231 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 */ 0,
1232 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B */ 9,
1233 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 */ 1,
1234 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 */ 2,
1235 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 */ 3,
1236 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B */ 7,
1237 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 */ 4,
1238 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 */ 5,
1239 };
1240 return t[lvl];
1241}
1242
1243static inline int vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar)
1244{
1245 static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = {
1246 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED */ 0,
1247 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 */ 1,
1248 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 */ 2,
1249 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 */ 3,
1250 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 */ 4,
1251 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 */ 5,
1252 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 */ 6,
1253 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 */ 7,
1254 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 */ 8,
1255 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 */ 9,
1256 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 */ 10,
1257 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 */ 11,
1258 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 */ 12,
1259 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 */ 13,
1260 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 */ 14,
1261 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 */ 15,
1262 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 */ 16,
1263 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED */ 255,
1264 };
1265 return t[sar];
1266}
1267
1268static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
1269{
1270 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
1271 struct s5p_mfc_dev *dev = ctx->dev;
1272 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1273 int ret = 0;
1274
1275 switch (ctrl->id) {
1276 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1277 p->gop_size = ctrl->val;
1278 break;
1279 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1280 p->slice_mode = ctrl->val;
1281 break;
1282 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1283 p->slice_mb = ctrl->val;
1284 break;
1285 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
1286 p->slice_bit = ctrl->val * 8;
1287 break;
1288 case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB:
1289 p->intra_refresh_mb = ctrl->val;
1290 break;
1291 case V4L2_CID_MPEG_MFC51_VIDEO_PADDING:
1292 p->pad = ctrl->val;
1293 break;
1294 case V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV:
1295 p->pad_luma = (ctrl->val >> 16) & 0xff;
1296 p->pad_cb = (ctrl->val >> 8) & 0xff;
1297 p->pad_cr = (ctrl->val >> 0) & 0xff;
1298 break;
1299 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
1300 p->rc_frame = ctrl->val;
1301 break;
1302 case V4L2_CID_MPEG_VIDEO_BITRATE:
1303 p->rc_bitrate = ctrl->val;
1304 break;
1305 case V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF:
1306 p->rc_reaction_coeff = ctrl->val;
1307 break;
1308 case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
1309 ctx->force_frame_type = ctrl->val;
1310 break;
1311 case V4L2_CID_MPEG_VIDEO_VBV_SIZE:
1312 p->vbv_size = ctrl->val;
1313 break;
1314 case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
1315 p->codec.h264.cpb_size = ctrl->val;
1316 break;
1317 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1318 p->seq_hdr_mode = ctrl->val;
1319 break;
1320 case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE:
1321 p->frame_skip_mode = ctrl->val;
1322 break;
1323 case V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT:
1324 p->fixed_target_bit = ctrl->val;
1325 break;
1326 case V4L2_CID_MPEG_VIDEO_B_FRAMES:
1327 p->num_b_frame = ctrl->val;
1328 break;
1329 case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
1330 switch (ctrl->val) {
1331 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
1332 p->codec.h264.profile =
1333 S5P_FIMV_ENC_PROFILE_H264_MAIN;
1334 break;
1335 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
1336 p->codec.h264.profile =
1337 S5P_FIMV_ENC_PROFILE_H264_HIGH;
1338 break;
1339 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
1340 p->codec.h264.profile =
1341 S5P_FIMV_ENC_PROFILE_H264_BASELINE;
1342 break;
f96f3cfa
JP		 1343 case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
1344 if (IS_MFCV6(dev))
1345 p->codec.h264.profile =
1346 S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE;
1347 else
1348 ret = -EINVAL;
1349 break;
af935746
KD		 1350 default:
1351 ret = -EINVAL;
1352 }
1353 break;
1354 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
1355 p->codec.h264.level_v4l2 = ctrl->val;
1356 p->codec.h264.level = h264_level(ctrl->val);
1357 if (p->codec.h264.level < 0) {
1358 mfc_err("Level number is wrong\n");
1359 ret = p->codec.h264.level;
1360 }
1361 break;
1362 case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL:
1363 p->codec.mpeg4.level_v4l2 = ctrl->val;
1364 p->codec.mpeg4.level = mpeg4_level(ctrl->val);
1365 if (p->codec.mpeg4.level < 0) {
1366 mfc_err("Level number is wrong\n");
1367 ret = p->codec.mpeg4.level;
1368 }
1369 break;
1370 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
1371 p->codec.h264.loop_filter_mode = ctrl->val;
1372 break;
1373 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:
1374 p->codec.h264.loop_filter_alpha = ctrl->val;
1375 break;
1376 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:
1377 p->codec.h264.loop_filter_beta = ctrl->val;
1378 break;
1379 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
1380 p->codec.h264.entropy_mode = ctrl->val;
1381 break;
1382 case V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P:
1383 p->codec.h264.num_ref_pic_4p = ctrl->val;
1384 break;
1385 case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM:
1386 p->codec.h264._8x8_transform = ctrl->val;
1387 break;
1388 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:
8f532a7f 1389 p->rc_mb = ctrl->val;
af935746
KD		 1390 break;
1391 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1392 p->codec.h264.rc_frame_qp = ctrl->val;
1393 break;
1394 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
1395 p->codec.h264.rc_min_qp = ctrl->val;
1396 break;
1397 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
1398 p->codec.h264.rc_max_qp = ctrl->val;
1399 break;
1400 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1401 p->codec.h264.rc_p_frame_qp = ctrl->val;
1402 break;
1403 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
1404 p->codec.h264.rc_b_frame_qp = ctrl->val;
1405 break;
1406 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1407 case V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP:
1408 p->codec.mpeg4.rc_frame_qp = ctrl->val;
1409 break;
1410 case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP:
1411 case V4L2_CID_MPEG_VIDEO_H263_MIN_QP:
1412 p->codec.mpeg4.rc_min_qp = ctrl->val;
1413 break;
1414 case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP:
1415 case V4L2_CID_MPEG_VIDEO_H263_MAX_QP:
1416 p->codec.mpeg4.rc_max_qp = ctrl->val;
1417 break;
1418 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1419 case V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP:
1420 p->codec.mpeg4.rc_p_frame_qp = ctrl->val;
1421 break;
1422 case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP:
1423 case V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP:
1424 p->codec.mpeg4.rc_b_frame_qp = ctrl->val;
1425 break;
1426 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK:
1427 p->codec.h264.rc_mb_dark = ctrl->val;
1428 break;
1429 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH:
1430 p->codec.h264.rc_mb_smooth = ctrl->val;
1431 break;
1432 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC:
1433 p->codec.h264.rc_mb_static = ctrl->val;
1434 break;
1435 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY:
1436 p->codec.h264.rc_mb_activity = ctrl->val;
1437 break;
1438 case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE:
1439 p->codec.h264.vui_sar = ctrl->val;
1440 break;
1441 case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC:
1442 p->codec.h264.vui_sar_idc = vui_sar_idc(ctrl->val);
1443 break;
1444 case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH:
1445 p->codec.h264.vui_ext_sar_width = ctrl->val;
1446 break;
1447 case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT:
1448 p->codec.h264.vui_ext_sar_height = ctrl->val;
1449 break;
1450 case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE:
1451 p->codec.h264.open_gop = !ctrl->val;
1452 break;
1453 case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
1454 p->codec.h264.open_gop_size = ctrl->val;
1455 break;
1456 case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE:
1457 switch (ctrl->val) {
1458 case V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE:
1459 p->codec.mpeg4.profile =
1460 S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE;
1461 break;
1462 case V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE:
1463 p->codec.mpeg4.profile =
1464 S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE;
1465 break;
1466 default:
1467 ret = -EINVAL;
1468 }
1469 break;
1470 case V4L2_CID_MPEG_VIDEO_MPEG4_QPEL:
1471 p->codec.mpeg4.quarter_pixel = ctrl->val;
1472 break;
1473 default:
1474 v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
1475 ctrl->id, ctrl->val);
1476 ret = -EINVAL;
1477 }
1478 return ret;
1479}
1480
1481static const struct v4l2_ctrl_ops s5p_mfc_enc_ctrl_ops = {
1482 .s_ctrl = s5p_mfc_enc_s_ctrl,
1483};
1484
3e9095d5
SK		 1485static int vidioc_s_parm(struct file *file, void *priv,
1486 struct v4l2_streamparm *a)
af935746
KD		 1487{
1488 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1489
1490 if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1491 ctx->enc_params.rc_framerate_num =
1492 a->parm.output.timeperframe.denominator;
1493 ctx->enc_params.rc_framerate_denom =
1494 a->parm.output.timeperframe.numerator;
1495 } else {
1496 mfc_err("Setting FPS is only possible for the output queue\n");
1497 return -EINVAL;
1498 }
1499 return 0;
1500}
1501
3e9095d5
SK		 1502static int vidioc_g_parm(struct file *file, void *priv,
1503 struct v4l2_streamparm *a)
af935746
KD		 1504{
1505 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1506
1507 if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1508 a->parm.output.timeperframe.denominator =
1509 ctx->enc_params.rc_framerate_num;
1510 a->parm.output.timeperframe.numerator =
1511 ctx->enc_params.rc_framerate_denom;
1512 } else {
1513 mfc_err("Setting FPS is only possible for the output queue\n");
1514 return -EINVAL;
1515 }
1516 return 0;
1517}
1518
f9f715a9
AH		 1519int vidioc_encoder_cmd(struct file *file, void *priv,
1520 struct v4l2_encoder_cmd *cmd)
1521{
1522 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1523 struct s5p_mfc_dev *dev = ctx->dev;
1524 struct s5p_mfc_buf *buf;
1525 unsigned long flags;
1526
1527 switch (cmd->cmd) {
1528 case V4L2_ENC_CMD_STOP:
1529 if (cmd->flags != 0)
1530 return -EINVAL;
1531
1532 if (!ctx->vq_src.streaming)
1533 return -EINVAL;
1534
1535 spin_lock_irqsave(&dev->irqlock, flags);
1536 if (list_empty(&ctx->src_queue)) {
4130eabc 1537 mfc_debug(2, "EOS: empty src queue, entering finishing state\n");
f9f715a9 1538 ctx->state = MFCINST_FINISHING;
eb362092
KD		 1539 if (s5p_mfc_ctx_ready(ctx))
1540 set_work_bit_irqsave(ctx);
f9f715a9 1541 spin_unlock_irqrestore(&dev->irqlock, flags);
43a1ea1f 1542 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
f9f715a9 1543 } else {
4130eabc 1544 mfc_debug(2, "EOS: marking last buffer of stream\n");
f9f715a9
AH		 1545 buf = list_entry(ctx->src_queue.prev,
1546 struct s5p_mfc_buf, list);
1547 if (buf->flags & MFC_BUF_FLAG_USED)
1548 ctx->state = MFCINST_FINISHING;
1549 else
1550 buf->flags |= MFC_BUF_FLAG_EOS;
1551 spin_unlock_irqrestore(&dev->irqlock, flags);
1552 }
1553 break;
1554 default:
1555 return -EINVAL;
1556
1557 }
1558 return 0;
1559}
1560
1561static int vidioc_subscribe_event(struct v4l2_fh *fh,
e1393b59 1562 const struct v4l2_event_subscription *sub)
f9f715a9
AH		 1563{
1564 switch (sub->type) {
1565 case V4L2_EVENT_EOS:
1566 return v4l2_event_subscribe(fh, sub, 2, NULL);
1567 default:
1568 return -EINVAL;
1569 }
1570}
1571
af935746
KD		 1572static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = {
1573 .vidioc_querycap = vidioc_querycap,
1574 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1575 .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
1576 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
1577 .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane,
1578 .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
1579 .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
1580 .vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
1581 .vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
1582 .vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
1583 .vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
1584 .vidioc_reqbufs = vidioc_reqbufs,
1585 .vidioc_querybuf = vidioc_querybuf,
1586 .vidioc_qbuf = vidioc_qbuf,
1587 .vidioc_dqbuf = vidioc_dqbuf,
6fa9dd06 1588 .vidioc_expbuf = vidioc_expbuf,
af935746
KD		 1589 .vidioc_streamon = vidioc_streamon,
1590 .vidioc_streamoff = vidioc_streamoff,
1591 .vidioc_s_parm = vidioc_s_parm,
1592 .vidioc_g_parm = vidioc_g_parm,
f9f715a9
AH		 1593 .vidioc_encoder_cmd = vidioc_encoder_cmd,
1594 .vidioc_subscribe_event = vidioc_subscribe_event,
1595 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
af935746
KD		 1596};
1597
1598static int check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb)
1599{
1600 int i;
1601
1602 if (!fmt)
1603 return -EINVAL;
1604 if (fmt->num_planes != vb->num_planes) {
1605 mfc_err("invalid plane number for the format\n");
1606 return -EINVAL;
1607 }
1608 for (i = 0; i < fmt->num_planes; i++) {
ba7fcb0c 1609 if (!vb2_dma_contig_plane_dma_addr(vb, i)) {
af935746
KD		 1610 mfc_err("failed to get plane cookie\n");
1611 return -EINVAL;
1612 }
4130eabc
AH		 1613 mfc_debug(2, "index: %d, plane[%d] cookie: 0x%08zx\n",
1614 vb->v4l2_buf.index, i,
1615 vb2_dma_contig_plane_dma_addr(vb, i));
af935746
KD		 1616 }
1617 return 0;
1618}
1619
1620static int s5p_mfc_queue_setup(struct vb2_queue *vq,
fc714e70
GL		 1621 const struct v4l2_format *fmt,
1622 unsigned int *buf_count, unsigned int *plane_count,
1623 unsigned int psize[], void *allocators[])
af935746
KD		 1624{
1625 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
f96f3cfa 1626 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 1627
1628 if (ctx->state != MFCINST_GOT_INST) {
1629 mfc_err("inavlid state: %d\n", ctx->state);
1630 return -EINVAL;
1631 }
1632 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1633 if (ctx->dst_fmt)
1634 *plane_count = ctx->dst_fmt->num_planes;
1635 else
1636 *plane_count = MFC_ENC_CAP_PLANE_COUNT;
1637 if (*buf_count < 1)
1638 *buf_count = 1;
1639 if (*buf_count > MFC_MAX_BUFFERS)
1640 *buf_count = MFC_MAX_BUFFERS;
1641 psize[0] = ctx->enc_dst_buf_size;
1642 allocators[0] = ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1643 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1644 if (ctx->src_fmt)
1645 *plane_count = ctx->src_fmt->num_planes;
1646 else
1647 *plane_count = MFC_ENC_OUT_PLANE_COUNT;
1648
1649 if (*buf_count < 1)
1650 *buf_count = 1;
1651 if (*buf_count > MFC_MAX_BUFFERS)
1652 *buf_count = MFC_MAX_BUFFERS;
1653 psize[0] = ctx->luma_size;
1654 psize[1] = ctx->chroma_size;
f96f3cfa
JP		 1655 if (IS_MFCV6(dev)) {
1656 allocators[0] =
1657 ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1658 allocators[1] =
1659 ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1660 } else {
1661 allocators[0] =
1662 ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1663 allocators[1] =
1664 ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1665 }
af935746
KD		 1666 } else {
1667 mfc_err("inavlid queue type: %d\n", vq->type);
1668 return -EINVAL;
1669 }
1670 return 0;
1671}
1672
1673static void s5p_mfc_unlock(struct vb2_queue *q)
1674{
1675 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1676 struct s5p_mfc_dev *dev = ctx->dev;
1677
1678 mutex_unlock(&dev->mfc_mutex);
1679}
1680
1681static void s5p_mfc_lock(struct vb2_queue *q)
1682{
1683 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1684 struct s5p_mfc_dev *dev = ctx->dev;
1685
1686 mutex_lock(&dev->mfc_mutex);
1687}
1688
1689static int s5p_mfc_buf_init(struct vb2_buffer *vb)
1690{
1691 struct vb2_queue *vq = vb->vb2_queue;
1692 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1693 unsigned int i;
1694 int ret;
1695
1696 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1697 ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1698 if (ret < 0)
1699 return ret;
1700 i = vb->v4l2_buf.index;
1701 ctx->dst_bufs[i].b = vb;
1702 ctx->dst_bufs[i].cookie.stream =
ba7fcb0c 1703 vb2_dma_contig_plane_dma_addr(vb, 0);
af935746
KD		 1704 ctx->dst_bufs_cnt++;
1705 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1706 ret = check_vb_with_fmt(ctx->src_fmt, vb);
1707 if (ret < 0)
1708 return ret;
1709 i = vb->v4l2_buf.index;
1710 ctx->src_bufs[i].b = vb;
1711 ctx->src_bufs[i].cookie.raw.luma =
ba7fcb0c 1712 vb2_dma_contig_plane_dma_addr(vb, 0);
af935746 1713 ctx->src_bufs[i].cookie.raw.chroma =
ba7fcb0c 1714 vb2_dma_contig_plane_dma_addr(vb, 1);
af935746
KD		 1715 ctx->src_bufs_cnt++;
1716 } else {
1717 mfc_err("inavlid queue type: %d\n", vq->type);
1718 return -EINVAL;
1719 }
1720 return 0;
1721}
1722
1723static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
1724{
1725 struct vb2_queue *vq = vb->vb2_queue;
1726 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1727 int ret;
1728
1729 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1730 ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1731 if (ret < 0)
1732 return ret;
1733 mfc_debug(2, "plane size: %ld, dst size: %d\n",
1734 vb2_plane_size(vb, 0), ctx->enc_dst_buf_size);
1735 if (vb2_plane_size(vb, 0) < ctx->enc_dst_buf_size) {
1736 mfc_err("plane size is too small for capture\n");
1737 return -EINVAL;
1738 }
1739 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1740 ret = check_vb_with_fmt(ctx->src_fmt, vb);
1741 if (ret < 0)
1742 return ret;
1743 mfc_debug(2, "plane size: %ld, luma size: %d\n",
1744 vb2_plane_size(vb, 0), ctx->luma_size);
1745 mfc_debug(2, "plane size: %ld, chroma size: %d\n",
1746 vb2_plane_size(vb, 1), ctx->chroma_size);
1747 if (vb2_plane_size(vb, 0) < ctx->luma_size ||
1748 vb2_plane_size(vb, 1) < ctx->chroma_size) {
1749 mfc_err("plane size is too small for output\n");
1750 return -EINVAL;
1751 }
1752 } else {
1753 mfc_err("inavlid queue type: %d\n", vq->type);
1754 return -EINVAL;
1755 }
1756 return 0;
1757}
1758
bd323e28 1759static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
af935746
KD		 1760{
1761 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1762 struct s5p_mfc_dev *dev = ctx->dev;
af935746 1763
e9d98ddc
AK		 1764 if (IS_MFCV6(dev) && (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)) {
1765
1766 if ((ctx->state == MFCINST_GOT_INST) &&
1767 (dev->curr_ctx == ctx->num) && dev->hw_lock) {
1768 s5p_mfc_wait_for_done_ctx(ctx,
1769 S5P_MFC_R2H_CMD_SEQ_DONE_RET,
1770 0);
1771 }
1772
1773 if (ctx->src_bufs_cnt < ctx->pb_count) {
1774 mfc_err("Need minimum %d OUTPUT buffers\n",
1775 ctx->pb_count);
1776 return -EINVAL;
1777 }
1778 }
1779
af935746 1780 /* If context is ready then dev = work->data;schedule it to run */
7fb89eca
AH		 1781 if (s5p_mfc_ctx_ready(ctx))
1782 set_work_bit_irqsave(ctx);
43a1ea1f 1783 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
e9d98ddc 1784
af935746
KD		 1785 return 0;
1786}
1787
1788static int s5p_mfc_stop_streaming(struct vb2_queue *q)
1789{
1790 unsigned long flags;
1791 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1792 struct s5p_mfc_dev *dev = ctx->dev;
1793
1794 if ((ctx->state == MFCINST_FINISHING ||
1795 ctx->state == MFCINST_RUNNING) &&
1796 dev->curr_ctx == ctx->num && dev->hw_lock) {
1797 ctx->state = MFCINST_ABORT;
43a1ea1f 1798 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_FRAME_DONE_RET,
af935746
KD		 1799 0);
1800 }
1801 ctx->state = MFCINST_FINISHED;
1802 spin_lock_irqsave(&dev->irqlock, flags);
1803 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
43a1ea1f
AK		 1804 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
1805 &ctx->vq_dst);
af935746
KD		 1806 INIT_LIST_HEAD(&ctx->dst_queue);
1807 ctx->dst_queue_cnt = 0;
1808 }
1809 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1810 cleanup_ref_queue(ctx);
43a1ea1f
AK		 1811 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
1812 &ctx->vq_src);
af935746
KD		 1813 INIT_LIST_HEAD(&ctx->src_queue);
1814 ctx->src_queue_cnt = 0;
1815 }
1816 spin_unlock_irqrestore(&dev->irqlock, flags);
1817 return 0;
1818}
1819
1820static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
1821{
1822 struct vb2_queue *vq = vb->vb2_queue;
1823 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1824 struct s5p_mfc_dev *dev = ctx->dev;
1825 unsigned long flags;
1826 struct s5p_mfc_buf *mfc_buf;
1827
1828 if (ctx->state == MFCINST_ERROR) {
1829 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1830 cleanup_ref_queue(ctx);
1831 return;
1832 }
1833 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1834 mfc_buf = &ctx->dst_bufs[vb->v4l2_buf.index];
f9f715a9 1835 mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
af935746
KD		 1836 /* Mark destination as available for use by MFC */
1837 spin_lock_irqsave(&dev->irqlock, flags);
1838 list_add_tail(&mfc_buf->list, &ctx->dst_queue);
1839 ctx->dst_queue_cnt++;
1840 spin_unlock_irqrestore(&dev->irqlock, flags);
1841 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1842 mfc_buf = &ctx->src_bufs[vb->v4l2_buf.index];
f9f715a9 1843 mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
af935746 1844 spin_lock_irqsave(&dev->irqlock, flags);
f9f715a9
AH		 1845 list_add_tail(&mfc_buf->list, &ctx->src_queue);
1846 ctx->src_queue_cnt++;
af935746
KD		 1847 spin_unlock_irqrestore(&dev->irqlock, flags);
1848 } else {
1849 mfc_err("unsupported buffer type (%d)\n", vq->type);
1850 }
7fb89eca
AH		 1851 if (s5p_mfc_ctx_ready(ctx))
1852 set_work_bit_irqsave(ctx);
43a1ea1f 1853 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 1854}
1855
1856static struct vb2_ops s5p_mfc_enc_qops = {
1857 .queue_setup = s5p_mfc_queue_setup,
1858 .wait_prepare = s5p_mfc_unlock,
1859 .wait_finish = s5p_mfc_lock,
1860 .buf_init = s5p_mfc_buf_init,
1861 .buf_prepare = s5p_mfc_buf_prepare,
1862 .start_streaming = s5p_mfc_start_streaming,
1863 .stop_streaming = s5p_mfc_stop_streaming,
1864 .buf_queue = s5p_mfc_buf_queue,
1865};
1866
1867struct s5p_mfc_codec_ops *get_enc_codec_ops(void)
1868{
1869 return &encoder_codec_ops;
1870}
1871
1872struct vb2_ops *get_enc_queue_ops(void)
1873{
1874 return &s5p_mfc_enc_qops;
1875}
1876
1877const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void)
1878{
1879 return &s5p_mfc_enc_ioctl_ops;
1880}
1881
1882#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2CLASS(x) == V4L2_CTRL_CLASS_MPEG) \
1883 && V4L2_CTRL_DRIVER_PRIV(x))
1884
1885int s5p_mfc_enc_ctrls_setup(struct s5p_mfc_ctx *ctx)
1886{
1887 struct v4l2_ctrl_config cfg;
1888 int i;
1889
1890 v4l2_ctrl_handler_init(&ctx->ctrl_handler, NUM_CTRLS);
1891 if (ctx->ctrl_handler.error) {
1892 mfc_err("v4l2_ctrl_handler_init failed\n");
1893 return ctx->ctrl_handler.error;
1894 }
1895 for (i = 0; i < NUM_CTRLS; i++) {
1896 if (IS_MFC51_PRIV(controls[i].id)) {
a65c3262 1897 memset(&cfg, 0, sizeof(struct v4l2_ctrl_config));
af935746
KD		 1898 cfg.ops = &s5p_mfc_enc_ctrl_ops;
1899 cfg.id = controls[i].id;
1900 cfg.min = controls[i].minimum;
1901 cfg.max = controls[i].maximum;
1902 cfg.def = controls[i].default_value;
1903 cfg.name = controls[i].name;
1904 cfg.type = controls[i].type;
1905 cfg.flags = 0;
1906
1907 if (cfg.type == V4L2_CTRL_TYPE_MENU) {
1908 cfg.step = 0;
1909 cfg.menu_skip_mask = cfg.menu_skip_mask;
1910 cfg.qmenu = mfc51_get_menu(cfg.id);
1911 } else {
1912 cfg.step = controls[i].step;
1913 cfg.menu_skip_mask = 0;
1914 }
1915 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
1916 &cfg, NULL);
1917 } else {
1918 if (controls[i].type == V4L2_CTRL_TYPE_MENU) {
1919 ctx->ctrls[i] = v4l2_ctrl_new_std_menu(
1920 &ctx->ctrl_handler,
1921 &s5p_mfc_enc_ctrl_ops, controls[i].id,
1922 controls[i].maximum, 0,
1923 controls[i].default_value);
1924 } else {
1925 ctx->ctrls[i] = v4l2_ctrl_new_std(
1926 &ctx->ctrl_handler,
1927 &s5p_mfc_enc_ctrl_ops, controls[i].id,
1928 controls[i].minimum,
1929 controls[i].maximum, controls[i].step,
1930 controls[i].default_value);
1931 }
1932 }
1933 if (ctx->ctrl_handler.error) {
1934 mfc_err("Adding control (%d) failed\n", i);
1935 return ctx->ctrl_handler.error;
1936 }
1937 if (controls[i].is_volatile && ctx->ctrls[i])
88365105 1938 ctx->ctrls[i]->flags |= V4L2_CTRL_FLAG_VOLATILE;
af935746 1939 }
69c9fe6f 1940 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
af935746
KD		 1941 return 0;
1942}
1943
1944void s5p_mfc_enc_ctrls_delete(struct s5p_mfc_ctx *ctx)
1945{
1946 int i;
1947
1948 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1949 for (i = 0; i < NUM_CTRLS; i++)
1950 ctx->ctrls[i] = NULL;
1951}
43a1ea1f
AK		 1952
1953void s5p_mfc_enc_init(struct s5p_mfc_ctx *ctx)
1954{
1955 struct v4l2_format f;
1956 f.fmt.pix_mp.pixelformat = DEF_SRC_FMT_ENC;
1957 ctx->src_fmt = find_format(&f, MFC_FMT_RAW);
1958 f.fmt.pix_mp.pixelformat = DEF_DST_FMT_ENC;
1959 ctx->dst_fmt = find_format(&f, MFC_FMT_ENC);
1960}
1961
Linux kernel - Deliverables
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