projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'acpi-lpss'
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc_enc.c
CommitLineData
af935746 1/*
2c3fb08b 2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
af935746
KD		 3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * Jeongtae Park <jtp.park@samsung.com>
8 * Kamil Debski <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/clk.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/version.h>
23#include <linux/videodev2.h>
f9f715a9 24#include <media/v4l2-event.h>
af935746
KD		 25#include <linux/workqueue.h>
26#include <media/v4l2-ctrls.h>
27#include <media/videobuf2-core.h>
af935746
KD		 28#include "s5p_mfc_common.h"
29#include "s5p_mfc_debug.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
43a1ea1f
AK		 32#include "s5p_mfc_opr.h"
33
34#define DEF_SRC_FMT_ENC V4L2_PIX_FMT_NV12MT
35#define DEF_DST_FMT_ENC V4L2_PIX_FMT_H264
af935746
KD		 36
37static struct s5p_mfc_fmt formats[] = {
38 {
f96f3cfa
JP		 39 .name = "4:2:0 2 Planes 16x16 Tiles",
40 .fourcc = V4L2_PIX_FMT_NV12MT_16X16,
41 .codec_mode = S5P_MFC_CODEC_NONE,
42 .type = MFC_FMT_RAW,
43 .num_planes = 2,
af935746
KD		 44 },
45 {
f96f3cfa
JP		 46 .name = "4:2:0 2 Planes 64x32 Tiles",
47 .fourcc = V4L2_PIX_FMT_NV12MT,
48 .codec_mode = S5P_MFC_CODEC_NONE,
49 .type = MFC_FMT_RAW,
50 .num_planes = 2,
af935746
KD		 51 },
52 {
f96f3cfa
JP		 53 .name = "4:2:0 2 Planes Y/CbCr",
54 .fourcc = V4L2_PIX_FMT_NV12M,
55 .codec_mode = S5P_MFC_CODEC_NONE,
56 .type = MFC_FMT_RAW,
57 .num_planes = 2,
af935746
KD		 58 },
59 {
f96f3cfa
JP		 60 .name = "4:2:0 2 Planes Y/CrCb",
61 .fourcc = V4L2_PIX_FMT_NV21M,
62 .codec_mode = S5P_MFC_CODEC_NONE,
63 .type = MFC_FMT_RAW,
64 .num_planes = 2,
af935746
KD		 65 },
66 {
f96f3cfa
JP		 67 .name = "H264 Encoded Stream",
68 .fourcc = V4L2_PIX_FMT_H264,
69 .codec_mode = S5P_MFC_CODEC_H264_ENC,
70 .type = MFC_FMT_ENC,
71 .num_planes = 1,
72 },
73 {
74 .name = "MPEG4 Encoded Stream",
75 .fourcc = V4L2_PIX_FMT_MPEG4,
76 .codec_mode = S5P_MFC_CODEC_MPEG4_ENC,
77 .type = MFC_FMT_ENC,
78 .num_planes = 1,
79 },
80 {
81 .name = "H263 Encoded Stream",
82 .fourcc = V4L2_PIX_FMT_H263,
83 .codec_mode = S5P_MFC_CODEC_H263_ENC,
84 .type = MFC_FMT_ENC,
85 .num_planes = 1,
af935746
KD		 86 },
87};
88
89#define NUM_FORMATS ARRAY_SIZE(formats)
90static struct s5p_mfc_fmt *find_format(struct v4l2_format *f, unsigned int t)
91{
92 unsigned int i;
93
94 for (i = 0; i < NUM_FORMATS; i++) {
95 if (formats[i].fourcc == f->fmt.pix_mp.pixelformat &&
96 formats[i].type == t)
97 return &formats[i];
98 }
99 return NULL;
100}
101
102static struct mfc_control controls[] = {
103 {
104 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
105 .type = V4L2_CTRL_TYPE_INTEGER,
106 .minimum = 0,
107 .maximum = (1 << 16) - 1,
108 .step = 1,
109 .default_value = 0,
110 },
111 {
112 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
113 .type = V4L2_CTRL_TYPE_MENU,
114 .minimum = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
115 .maximum = V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES,
116 .default_value = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
117 .menu_skip_mask = 0,
118 },
119 {
120 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB,
121 .type = V4L2_CTRL_TYPE_INTEGER,
122 .minimum = 1,
123 .maximum = (1 << 16) - 1,
124 .step = 1,
125 .default_value = 1,
126 },
127 {
128 .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES,
129 .type = V4L2_CTRL_TYPE_INTEGER,
130 .minimum = 1900,
131 .maximum = (1 << 30) - 1,
132 .step = 1,
133 .default_value = 1900,
134 },
135 {
136 .id = V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB,
137 .type = V4L2_CTRL_TYPE_INTEGER,
138 .minimum = 0,
139 .maximum = (1 << 16) - 1,
140 .step = 1,
141 .default_value = 0,
142 },
143 {
144 .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING,
145 .type = V4L2_CTRL_TYPE_BOOLEAN,
146 .name = "Padding Control Enable",
147 .minimum = 0,
148 .maximum = 1,
149 .step = 1,
150 .default_value = 0,
151 },
152 {
153 .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV,
154 .type = V4L2_CTRL_TYPE_INTEGER,
155 .name = "Padding Color YUV Value",
156 .minimum = 0,
157 .maximum = (1 << 25) - 1,
158 .step = 1,
159 .default_value = 0,
160 },
161 {
162 .id = V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
163 .type = V4L2_CTRL_TYPE_BOOLEAN,
164 .minimum = 0,
165 .maximum = 1,
166 .step = 1,
167 .default_value = 0,
168 },
169 {
170 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
171 .type = V4L2_CTRL_TYPE_INTEGER,
172 .minimum = 1,
173 .maximum = (1 << 30) - 1,
174 .step = 1,
175 .default_value = 1,
176 },
177 {
178 .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF,
179 .type = V4L2_CTRL_TYPE_INTEGER,
180 .name = "Rate Control Reaction Coeff.",
181 .minimum = 1,
182 .maximum = (1 << 16) - 1,
183 .step = 1,
184 .default_value = 1,
185 },
186 {
187 .id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE,
188 .type = V4L2_CTRL_TYPE_MENU,
189 .name = "Force frame type",
190 .minimum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
191 .maximum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED,
192 .default_value = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
193 .menu_skip_mask = 0,
194 },
195 {
196 .id = V4L2_CID_MPEG_VIDEO_VBV_SIZE,
197 .type = V4L2_CTRL_TYPE_INTEGER,
198 .minimum = 0,
199 .maximum = (1 << 16) - 1,
200 .step = 1,
201 .default_value = 0,
202 },
203 {
204 .id = V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
205 .type = V4L2_CTRL_TYPE_INTEGER,
206 .minimum = 0,
207 .maximum = (1 << 16) - 1,
208 .step = 1,
209 .default_value = 0,
210 },
211 {
212 .id = V4L2_CID_MPEG_VIDEO_HEADER_MODE,
213 .type = V4L2_CTRL_TYPE_MENU,
214 .minimum = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
215 .maximum = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
216 .default_value = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
217 .menu_skip_mask = 0,
218 },
219 {
220 .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE,
221 .type = V4L2_CTRL_TYPE_MENU,
222 .name = "Frame Skip Enable",
223 .minimum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
224 .maximum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
225 .menu_skip_mask = 0,
226 .default_value = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
227 },
228 {
229 .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT,
230 .type = V4L2_CTRL_TYPE_BOOLEAN,
231 .name = "Fixed Target Bit Enable",
232 .minimum = 0,
233 .maximum = 1,
234 .default_value = 0,
053e09f3 235 .step = 1,
af935746
KD		 236 .menu_skip_mask = 0,
237 },
238 {
239 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
240 .type = V4L2_CTRL_TYPE_INTEGER,
241 .minimum = 0,
242 .maximum = 2,
243 .step = 1,
244 .default_value = 0,
245 },
246 {
247 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
248 .type = V4L2_CTRL_TYPE_MENU,
249 .minimum = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
250 .maximum = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH,
251 .default_value = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
252 .menu_skip_mask = ~(
253 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
254 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
255 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)
256 ),
257 },
258 {
259 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
260 .type = V4L2_CTRL_TYPE_MENU,
261 .minimum = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
262 .maximum = V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
263 .default_value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
af935746
KD		 264 },
265 {
266 .id = V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL,
267 .type = V4L2_CTRL_TYPE_MENU,
268 .minimum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
269 .maximum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_5,
270 .default_value = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
271 .menu_skip_mask = 0,
272 },
273 {
274 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
275 .type = V4L2_CTRL_TYPE_MENU,
276 .minimum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
277 .maximum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY,
278 .default_value = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
279 .menu_skip_mask = 0,
280 },
281 {
282 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA,
283 .type = V4L2_CTRL_TYPE_INTEGER,
284 .minimum = -6,
285 .maximum = 6,
286 .step = 1,
287 .default_value = 0,
288 },
289 {
290 .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA,
291 .type = V4L2_CTRL_TYPE_INTEGER,
292 .minimum = -6,
293 .maximum = 6,
294 .step = 1,
295 .default_value = 0,
296 },
297 {
298 .id = V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE,
299 .type = V4L2_CTRL_TYPE_MENU,
300 .minimum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
301 .maximum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
302 .default_value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
303 .menu_skip_mask = 0,
304 },
305 {
306 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P,
307 .type = V4L2_CTRL_TYPE_INTEGER,
308 .name = "The Number of Ref. Pic for P",
309 .minimum = 1,
310 .maximum = 2,
311 .step = 1,
312 .default_value = 1,
313 },
314 {
315 .id = V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
316 .type = V4L2_CTRL_TYPE_BOOLEAN,
317 .minimum = 0,
318 .maximum = 1,
319 .step = 1,
320 .default_value = 0,
321 },
322 {
323 .id = V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE,
324 .type = V4L2_CTRL_TYPE_BOOLEAN,
325 .minimum = 0,
326 .maximum = 1,
327 .step = 1,
328 .default_value = 0,
329 },
330 {
331 .id = V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
332 .type = V4L2_CTRL_TYPE_INTEGER,
333 .minimum = 0,
334 .maximum = 51,
335 .step = 1,
336 .default_value = 1,
337 },
338 {
339 .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
340 .type = V4L2_CTRL_TYPE_INTEGER,
341 .minimum = 0,
342 .maximum = 51,
343 .step = 1,
344 .default_value = 1,
345 },
346 {
347 .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
348 .type = V4L2_CTRL_TYPE_INTEGER,
349 .minimum = 0,
350 .maximum = 51,
351 .step = 1,
352 .default_value = 1,
353 },
354 {
355 .id = V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
356 .type = V4L2_CTRL_TYPE_INTEGER,
357 .minimum = 0,
358 .maximum = 51,
359 .step = 1,
360 .default_value = 1,
361 },
362 {
363 .id = V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
364 .type = V4L2_CTRL_TYPE_INTEGER,
365 .minimum = 0,
366 .maximum = 51,
367 .step = 1,
368 .default_value = 1,
369 },
370 {
371 .id = V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP,
372 .type = V4L2_CTRL_TYPE_INTEGER,
373 .name = "H263 I-Frame QP value",
374 .minimum = 1,
375 .maximum = 31,
376 .step = 1,
377 .default_value = 1,
378 },
379 {
380 .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP,
381 .type = V4L2_CTRL_TYPE_INTEGER,
382 .name = "H263 Minimum QP value",
383 .minimum = 1,
384 .maximum = 31,
385 .step = 1,
386 .default_value = 1,
387 },
388 {
389 .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP,
390 .type = V4L2_CTRL_TYPE_INTEGER,
391 .name = "H263 Maximum QP value",
392 .minimum = 1,
393 .maximum = 31,
394 .step = 1,
395 .default_value = 1,
396 },
397 {
398 .id = V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP,
399 .type = V4L2_CTRL_TYPE_INTEGER,
400 .name = "H263 P frame QP value",
401 .minimum = 1,
402 .maximum = 31,
403 .step = 1,
404 .default_value = 1,
405 },
406 {
407 .id = V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP,
408 .type = V4L2_CTRL_TYPE_INTEGER,
409 .name = "H263 B frame QP value",
410 .minimum = 1,
411 .maximum = 31,
412 .step = 1,
413 .default_value = 1,
414 },
415 {
416 .id = V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP,
417 .type = V4L2_CTRL_TYPE_INTEGER,
418 .name = "MPEG4 I-Frame QP value",
419 .minimum = 1,
420 .maximum = 31,
421 .step = 1,
422 .default_value = 1,
423 },
424 {
425 .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP,
426 .type = V4L2_CTRL_TYPE_INTEGER,
427 .name = "MPEG4 Minimum QP value",
428 .minimum = 1,
429 .maximum = 31,
430 .step = 1,
431 .default_value = 1,
432 },
433 {
434 .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP,
435 .type = V4L2_CTRL_TYPE_INTEGER,
436 .name = "MPEG4 Maximum QP value",
437 .minimum = 0,
438 .maximum = 51,
439 .step = 1,
440 .default_value = 1,
441 },
442 {
443 .id = V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP,
444 .type = V4L2_CTRL_TYPE_INTEGER,
445 .name = "MPEG4 P frame QP value",
446 .minimum = 1,
447 .maximum = 31,
448 .step = 1,
449 .default_value = 1,
450 },
451 {
452 .id = V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP,
453 .type = V4L2_CTRL_TYPE_INTEGER,
454 .name = "MPEG4 B frame QP value",
455 .minimum = 1,
456 .maximum = 31,
457 .step = 1,
458 .default_value = 1,
459 },
460 {
461 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK,
462 .type = V4L2_CTRL_TYPE_BOOLEAN,
463 .name = "H264 Dark Reg Adaptive RC",
464 .minimum = 0,
465 .maximum = 1,
466 .step = 1,
467 .default_value = 0,
468 },
469 {
470 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH,
471 .type = V4L2_CTRL_TYPE_BOOLEAN,
472 .name = "H264 Smooth Reg Adaptive RC",
473 .minimum = 0,
474 .maximum = 1,
475 .step = 1,
476 .default_value = 0,
477 },
478 {
479 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC,
480 .type = V4L2_CTRL_TYPE_BOOLEAN,
481 .name = "H264 Static Reg Adaptive RC",
482 .minimum = 0,
483 .maximum = 1,
484 .step = 1,
485 .default_value = 0,
486 },
487 {
488 .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY,
489 .type = V4L2_CTRL_TYPE_BOOLEAN,
490 .name = "H264 Activity Reg Adaptive RC",
491 .minimum = 0,
492 .maximum = 1,
493 .step = 1,
494 .default_value = 0,
495 },
496 {
497 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE,
498 .type = V4L2_CTRL_TYPE_BOOLEAN,
499 .minimum = 0,
500 .maximum = 1,
501 .step = 1,
502 .default_value = 0,
503 },
504 {
505 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
506 .type = V4L2_CTRL_TYPE_MENU,
507 .minimum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED,
508 .maximum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED,
afd14f48 509 .default_value = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED,
af935746
KD		 510 .menu_skip_mask = 0,
511 },
512 {
513 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
514 .type = V4L2_CTRL_TYPE_INTEGER,
515 .minimum = 0,
516 .maximum = (1 << 16) - 1,
517 .step = 1,
518 .default_value = 0,
519 },
520 {
521 .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT,
522 .type = V4L2_CTRL_TYPE_INTEGER,
523 .minimum = 0,
524 .maximum = (1 << 16) - 1,
525 .step = 1,
526 .default_value = 0,
527 },
528 {
529 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
530 .type = V4L2_CTRL_TYPE_BOOLEAN,
531 .minimum = 0,
532 .maximum = 1,
533 .step = 1,
534 .default_value = 1,
535 },
536 {
537 .id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,
538 .type = V4L2_CTRL_TYPE_INTEGER,
539 .minimum = 0,
540 .maximum = (1 << 16) - 1,
541 .step = 1,
542 .default_value = 0,
543 },
544 {
545 .id = V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE,
546 .type = V4L2_CTRL_TYPE_MENU,
547 .minimum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
548 .maximum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE,
afd14f48 549 .default_value = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
af935746
KD		 550 .menu_skip_mask = 0,
551 },
552 {
553 .id = V4L2_CID_MPEG_VIDEO_MPEG4_QPEL,
554 .type = V4L2_CTRL_TYPE_BOOLEAN,
555 .minimum = 0,
556 .maximum = 1,
557 .step = 1,
558 .default_value = 0,
559 },
560};
561
562#define NUM_CTRLS ARRAY_SIZE(controls)
563static const char * const *mfc51_get_menu(u32 id)
564{
565 static const char * const mfc51_video_frame_skip[] = {
566 "Disabled",
567 "Level Limit",
568 "VBV/CPB Limit",
569 NULL,
570 };
571 static const char * const mfc51_video_force_frame[] = {
572 "Disabled",
573 "I Frame",
574 "Not Coded",
575 NULL,
576 };
577 switch (id) {
578 case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE:
579 return mfc51_video_frame_skip;
580 case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
581 return mfc51_video_force_frame;
582 }
583 return NULL;
584}
585
586static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
587{
588 mfc_debug(2, "src=%d, dst=%d, state=%d\n",
589 ctx->src_queue_cnt, ctx->dst_queue_cnt, ctx->state);
590 /* context is ready to make header */
591 if (ctx->state == MFCINST_GOT_INST && ctx->dst_queue_cnt >= 1)
592 return 1;
593 /* context is ready to encode a frame */
f96f3cfa
JP		 594 if ((ctx->state == MFCINST_RUNNING ||
595 ctx->state == MFCINST_HEAD_PARSED) &&
af935746
KD		 596 ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
597 return 1;
f9f715a9 598 /* context is ready to encode remaining frames */
af935746 599 if (ctx->state == MFCINST_FINISHING &&
f9f715a9 600 ctx->dst_queue_cnt >= 1)
af935746
KD		 601 return 1;
602 mfc_debug(2, "ctx is not ready\n");
603 return 0;
604}
605
606static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx)
607{
608 struct s5p_mfc_buf *mb_entry;
609 unsigned long mb_y_addr, mb_c_addr;
610
611 /* move buffers in ref queue to src queue */
612 while (!list_empty(&ctx->ref_queue)) {
613 mb_entry = list_entry((&ctx->ref_queue)->next,
614 struct s5p_mfc_buf, list);
ba7fcb0c
MS		 615 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
616 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 617 list_del(&mb_entry->list);
618 ctx->ref_queue_cnt--;
619 list_add_tail(&mb_entry->list, &ctx->src_queue);
620 ctx->src_queue_cnt++;
621 }
622 mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
623 ctx->src_queue_cnt, ctx->ref_queue_cnt);
624 INIT_LIST_HEAD(&ctx->ref_queue);
625 ctx->ref_queue_cnt = 0;
626}
627
628static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx)
629{
630 struct s5p_mfc_dev *dev = ctx->dev;
631 struct s5p_mfc_buf *dst_mb;
632 unsigned long dst_addr;
633 unsigned int dst_size;
634 unsigned long flags;
635
636 spin_lock_irqsave(&dev->irqlock, flags);
637 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c 638 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
af935746 639 dst_size = vb2_plane_size(dst_mb->b, 0);
43a1ea1f
AK		 640 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
641 dst_size);
af935746
KD		 642 spin_unlock_irqrestore(&dev->irqlock, flags);
643 return 0;
644}
645
646static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
647{
648 struct s5p_mfc_dev *dev = ctx->dev;
649 struct s5p_mfc_enc_params *p = &ctx->enc_params;
650 struct s5p_mfc_buf *dst_mb;
651 unsigned long flags;
652
653 if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) {
654 spin_lock_irqsave(&dev->irqlock, flags);
655 dst_mb = list_entry(ctx->dst_queue.next,
656 struct s5p_mfc_buf, list);
657 list_del(&dst_mb->list);
658 ctx->dst_queue_cnt--;
659 vb2_set_plane_payload(dst_mb->b, 0,
43a1ea1f 660 s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev));
af935746
KD		 661 vb2_buffer_done(dst_mb->b, VB2_BUF_STATE_DONE);
662 spin_unlock_irqrestore(&dev->irqlock, flags);
663 }
f96f3cfa
JP		 664 if (IS_MFCV6(dev)) {
665 ctx->state = MFCINST_HEAD_PARSED; /* for INIT_BUFFER cmd */
666 } else {
667 ctx->state = MFCINST_RUNNING;
668 if (s5p_mfc_ctx_ready(ctx))
669 set_work_bit_irqsave(ctx);
670 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
671 }
672
673 if (IS_MFCV6(dev))
674 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops,
675 get_enc_dpb_count, dev);
676
af935746
KD		 677 return 0;
678}
679
680static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
681{
682 struct s5p_mfc_dev *dev = ctx->dev;
683 struct s5p_mfc_buf *dst_mb;
684 struct s5p_mfc_buf *src_mb;
685 unsigned long flags;
686 unsigned long src_y_addr, src_c_addr, dst_addr;
687 unsigned int dst_size;
688
689 spin_lock_irqsave(&dev->irqlock, flags);
690 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c
MS		 691 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
692 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
43a1ea1f
AK		 693 s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, src_y_addr,
694 src_c_addr);
af935746
KD		 695 spin_unlock_irqrestore(&dev->irqlock, flags);
696
697 spin_lock_irqsave(&dev->irqlock, flags);
698 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
ba7fcb0c 699 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
af935746 700 dst_size = vb2_plane_size(dst_mb->b, 0);
43a1ea1f
AK		 701 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
702 dst_size);
af935746
KD		 703 spin_unlock_irqrestore(&dev->irqlock, flags);
704
705 return 0;
706}
707
708static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
709{
710 struct s5p_mfc_dev *dev = ctx->dev;
711 struct s5p_mfc_buf *mb_entry;
712 unsigned long enc_y_addr, enc_c_addr;
713 unsigned long mb_y_addr, mb_c_addr;
714 int slice_type;
715 unsigned int strm_size;
716 unsigned long flags;
717
43a1ea1f
AK		 718 slice_type = s5p_mfc_hw_call(dev->mfc_ops, get_enc_slice_type, dev);
719 strm_size = s5p_mfc_hw_call(dev->mfc_ops, get_enc_strm_size, dev);
af935746
KD		 720 mfc_debug(2, "Encoded slice type: %d", slice_type);
721 mfc_debug(2, "Encoded stream size: %d", strm_size);
722 mfc_debug(2, "Display order: %d",
723 mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));
724 spin_lock_irqsave(&dev->irqlock, flags);
725 if (slice_type >= 0) {
43a1ea1f
AK		 726 s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx,
727 &enc_y_addr, &enc_c_addr);
af935746 728 list_for_each_entry(mb_entry, &ctx->src_queue, list) {
ba7fcb0c
MS		 729 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
730 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 731 if ((enc_y_addr == mb_y_addr) &&
732 (enc_c_addr == mb_c_addr)) {
733 list_del(&mb_entry->list);
734 ctx->src_queue_cnt--;
735 vb2_buffer_done(mb_entry->b,
736 VB2_BUF_STATE_DONE);
737 break;
738 }
739 }
740 list_for_each_entry(mb_entry, &ctx->ref_queue, list) {
ba7fcb0c
MS		 741 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
742 mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);
af935746
KD		 743 if ((enc_y_addr == mb_y_addr) &&
744 (enc_c_addr == mb_c_addr)) {
745 list_del(&mb_entry->list);
746 ctx->ref_queue_cnt--;
747 vb2_buffer_done(mb_entry->b,
748 VB2_BUF_STATE_DONE);
749 break;
750 }
751 }
752 }
753 if ((ctx->src_queue_cnt > 0) && (ctx->state == MFCINST_RUNNING)) {
754 mb_entry = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
755 list);
f9f715a9 756 if (mb_entry->flags & MFC_BUF_FLAG_USED) {
af935746
KD		 757 list_del(&mb_entry->list);
758 ctx->src_queue_cnt--;
759 list_add_tail(&mb_entry->list, &ctx->ref_queue);
760 ctx->ref_queue_cnt++;
761 }
762 mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
763 ctx->src_queue_cnt, ctx->ref_queue_cnt);
764 }
765 if (strm_size > 0) {
766 /* at least one more dest. buffers exist always */
767 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
768 list);
769 list_del(&mb_entry->list);
770 ctx->dst_queue_cnt--;
771 switch (slice_type) {
772 case S5P_FIMV_ENC_SI_SLICE_TYPE_I:
773 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
774 break;
775 case S5P_FIMV_ENC_SI_SLICE_TYPE_P:
776 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
777 break;
778 case S5P_FIMV_ENC_SI_SLICE_TYPE_B:
779 mb_entry->b->v4l2_buf.flags |= V4L2_BUF_FLAG_BFRAME;
780 break;
781 }
782 vb2_set_plane_payload(mb_entry->b, 0, strm_size);
783 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
784 }
785 spin_unlock_irqrestore(&dev->irqlock, flags);
7fb89eca
AH		 786 if ((ctx->src_queue_cnt == 0) || (ctx->dst_queue_cnt == 0))
787 clear_work_bit(ctx);
af935746
KD		 788 return 0;
789}
790
791static struct s5p_mfc_codec_ops encoder_codec_ops = {
792 .pre_seq_start = enc_pre_seq_start,
793 .post_seq_start = enc_post_seq_start,
794 .pre_frame_start = enc_pre_frame_start,
795 .post_frame_start = enc_post_frame_start,
796};
797
798/* Query capabilities of the device */
799static int vidioc_querycap(struct file *file, void *priv,
800 struct v4l2_capability *cap)
801{
802 struct s5p_mfc_dev *dev = video_drvdata(file);
803
804 strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
805 strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
806 cap->bus_info[0] = 0;
807 cap->version = KERNEL_VERSION(1, 0, 0);
f0476a83
SN		 808 /*
809 * This is only a mem-to-mem video device. The capture and output
810 * device capability flags are left only for backward compatibility
811 * and are scheduled for removal.
812 */
813 cap->capabilities = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING |
814 V4L2_CAP_VIDEO_CAPTURE_MPLANE |
815 V4L2_CAP_VIDEO_OUTPUT_MPLANE;
af935746
KD		 816 return 0;
817}
818
819static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool mplane, bool out)
820{
821 struct s5p_mfc_fmt *fmt;
822 int i, j = 0;
823
824 for (i = 0; i < ARRAY_SIZE(formats); ++i) {
825 if (mplane && formats[i].num_planes == 1)
826 continue;
827 else if (!mplane && formats[i].num_planes > 1)
828 continue;
829 if (out && formats[i].type != MFC_FMT_RAW)
830 continue;
831 else if (!out && formats[i].type != MFC_FMT_ENC)
832 continue;
833 if (j == f->index) {
834 fmt = &formats[i];
835 strlcpy(f->description, fmt->name,
836 sizeof(f->description));
837 f->pixelformat = fmt->fourcc;
838 return 0;
839 }
840 ++j;
841 }
842 return -EINVAL;
843}
844
845static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv,
846 struct v4l2_fmtdesc *f)
847{
848 return vidioc_enum_fmt(f, false, false);
849}
850
851static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
852 struct v4l2_fmtdesc *f)
853{
854 return vidioc_enum_fmt(f, true, false);
855}
856
857static int vidioc_enum_fmt_vid_out(struct file *file, void *prov,
858 struct v4l2_fmtdesc *f)
859{
860 return vidioc_enum_fmt(f, false, true);
861}
862
863static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov,
864 struct v4l2_fmtdesc *f)
865{
866 return vidioc_enum_fmt(f, true, true);
867}
868
869static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
870{
871 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
872 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
873
874 mfc_debug(2, "f->type = %d ctx->state = %d\n", f->type, ctx->state);
875 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
876 /* This is run on output (encoder dest) */
877 pix_fmt_mp->width = 0;
878 pix_fmt_mp->height = 0;
879 pix_fmt_mp->field = V4L2_FIELD_NONE;
880 pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc;
881 pix_fmt_mp->num_planes = ctx->dst_fmt->num_planes;
882
883 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->enc_dst_buf_size;
884 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->enc_dst_buf_size;
885 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
886 /* This is run on capture (encoder src) */
887 pix_fmt_mp->width = ctx->img_width;
888 pix_fmt_mp->height = ctx->img_height;
889
890 pix_fmt_mp->field = V4L2_FIELD_NONE;
891 pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc;
892 pix_fmt_mp->num_planes = ctx->src_fmt->num_planes;
893
894 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
895 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
896 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
897 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
898 } else {
899 mfc_err("invalid buf type\n");
900 return -EINVAL;
901 }
902 return 0;
903}
904
905static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
906{
907 struct s5p_mfc_fmt *fmt;
908 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
909
910 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
911 fmt = find_format(f, MFC_FMT_ENC);
912 if (!fmt) {
913 mfc_err("failed to try output format\n");
914 return -EINVAL;
915 }
916
917 if (pix_fmt_mp->plane_fmt[0].sizeimage == 0) {
918 mfc_err("must be set encoding output size\n");
919 return -EINVAL;
920 }
921
922 pix_fmt_mp->plane_fmt[0].bytesperline =
923 pix_fmt_mp->plane_fmt[0].sizeimage;
924 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
925 fmt = find_format(f, MFC_FMT_RAW);
926 if (!fmt) {
927 mfc_err("failed to try output format\n");
928 return -EINVAL;
929 }
930
931 if (fmt->num_planes != pix_fmt_mp->num_planes) {
932 mfc_err("failed to try output format\n");
933 return -EINVAL;
934 }
0749ae35
AH		 935 v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1,
936 &pix_fmt_mp->height, 4, 1080, 1, 0);
af935746
KD		 937 } else {
938 mfc_err("invalid buf type\n");
939 return -EINVAL;
940 }
941 return 0;
942}
943
944static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
945{
946 struct s5p_mfc_dev *dev = video_drvdata(file);
947 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
948 struct s5p_mfc_fmt *fmt;
949 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
af935746
KD		 950 int ret = 0;
951
952 ret = vidioc_try_fmt(file, priv, f);
953 if (ret)
954 return ret;
955 if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
956 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
957 ret = -EBUSY;
958 goto out;
959 }
960 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
961 fmt = find_format(f, MFC_FMT_ENC);
962 if (!fmt) {
963 mfc_err("failed to set capture format\n");
964 return -EINVAL;
965 }
966 ctx->state = MFCINST_INIT;
967 ctx->dst_fmt = fmt;
968 ctx->codec_mode = ctx->dst_fmt->codec_mode;
969 ctx->enc_dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage;
970 pix_fmt_mp->plane_fmt[0].bytesperline = 0;
971 ctx->dst_bufs_cnt = 0;
972 ctx->capture_state = QUEUE_FREE;
43a1ea1f 973 s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
7fb89eca 974 set_work_bit_irqsave(ctx);
af935746 975 s5p_mfc_clean_ctx_int_flags(ctx);
43a1ea1f 976 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746 977 if (s5p_mfc_wait_for_done_ctx(ctx, \
43a1ea1f 978 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 1)) {
af935746
KD		 979 /* Error or timeout */
980 mfc_err("Error getting instance from hardware\n");
43a1ea1f
AK		 981 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer,
982 ctx);
af935746
KD		 983 ret = -EIO;
984 goto out;
985 }
986 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
987 } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
988 fmt = find_format(f, MFC_FMT_RAW);
989 if (!fmt) {
990 mfc_err("failed to set output format\n");
991 return -EINVAL;
992 }
f96f3cfa
JP		 993
994 if (!IS_MFCV6(dev) &&
995 (fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)) {
996 mfc_err("Not supported format.\n");
997 return -EINVAL;
998 } else if (IS_MFCV6(dev) &&
999 (fmt->fourcc == V4L2_PIX_FMT_NV12MT)) {
1000 mfc_err("Not supported format.\n");
1001 return -EINVAL;
1002 }
1003
af935746
KD		 1004 if (fmt->num_planes != pix_fmt_mp->num_planes) {
1005 mfc_err("failed to set output format\n");
1006 ret = -EINVAL;
1007 goto out;
1008 }
1009 ctx->src_fmt = fmt;
1010 ctx->img_width = pix_fmt_mp->width;
1011 ctx->img_height = pix_fmt_mp->height;
1012 mfc_debug(2, "codec number: %d\n", ctx->src_fmt->codec_mode);
1013 mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n",
1014 pix_fmt_mp->width, pix_fmt_mp->height,
1015 ctx->img_width, ctx->img_height);
af935746 1016
8f532a7f
AK		 1017 s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx);
1018 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
1019 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
1020 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
1021 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
af935746 1022
af935746
KD		 1023 ctx->src_bufs_cnt = 0;
1024 ctx->output_state = QUEUE_FREE;
1025 } else {
1026 mfc_err("invalid buf type\n");
1027 return -EINVAL;
1028 }
1029out:
1030 mfc_debug_leave();
1031 return ret;
1032}
1033
1034static int vidioc_reqbufs(struct file *file, void *priv,
1035 struct v4l2_requestbuffers *reqbufs)
1036{
f96f3cfa 1037 struct s5p_mfc_dev *dev = video_drvdata(file);
af935746
KD		 1038 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1039 int ret = 0;
1040
1041 /* if memory is not mmp or userptr return error */
1042 if ((reqbufs->memory != V4L2_MEMORY_MMAP) &&
1043 (reqbufs->memory != V4L2_MEMORY_USERPTR))
1044 return -EINVAL;
1045 if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1046 if (ctx->capture_state != QUEUE_FREE) {
1047 mfc_err("invalid capture state: %d\n",
1048 ctx->capture_state);
1049 return -EINVAL;
1050 }
1051 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1052 if (ret != 0) {
1053 mfc_err("error in vb2_reqbufs() for E(D)\n");
1054 return ret;
1055 }
1056 ctx->capture_state = QUEUE_BUFS_REQUESTED;
f96f3cfa
JP		 1057
1058 if (!IS_MFCV6(dev)) {
1059 ret = s5p_mfc_hw_call(ctx->dev->mfc_ops,
1060 alloc_codec_buffers, ctx);
1061 if (ret) {
1062 mfc_err("Failed to allocate encoding buffers\n");
1063 reqbufs->count = 0;
1064 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
1065 return -ENOMEM;
1066 }
af935746
KD		 1067 }
1068 } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1069 if (ctx->output_state != QUEUE_FREE) {
1070 mfc_err("invalid output state: %d\n",
1071 ctx->output_state);
1072 return -EINVAL;
1073 }
1074 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
1075 if (ret != 0) {
1076 mfc_err("error in vb2_reqbufs() for E(S)\n");
1077 return ret;
1078 }
1079 ctx->output_state = QUEUE_BUFS_REQUESTED;
1080 } else {
1081 mfc_err("invalid buf type\n");
1082 return -EINVAL;
1083 }
1084 return ret;
1085}
1086
1087static int vidioc_querybuf(struct file *file, void *priv,
1088 struct v4l2_buffer *buf)
1089{
1090 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1091 int ret = 0;
1092
1093 /* if memory is not mmp or userptr return error */
1094 if ((buf->memory != V4L2_MEMORY_MMAP) &&
1095 (buf->memory != V4L2_MEMORY_USERPTR))
1096 return -EINVAL;
1097 if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1098 if (ctx->state != MFCINST_GOT_INST) {
1099 mfc_err("invalid context state: %d\n", ctx->state);
1100 return -EINVAL;
1101 }
1102 ret = vb2_querybuf(&ctx->vq_dst, buf);
1103 if (ret != 0) {
1104 mfc_err("error in vb2_querybuf() for E(D)\n");
1105 return ret;
1106 }
1107 buf->m.planes[0].m.mem_offset += DST_QUEUE_OFF_BASE;
1108 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1109 ret = vb2_querybuf(&ctx->vq_src, buf);
1110 if (ret != 0) {
1111 mfc_err("error in vb2_querybuf() for E(S)\n");
1112 return ret;
1113 }
1114 } else {
1115 mfc_err("invalid buf type\n");
1116 return -EINVAL;
1117 }
1118 return ret;
1119}
1120
1121/* Queue a buffer */
1122static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1123{
1124 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1125
1126 if (ctx->state == MFCINST_ERROR) {
1127 mfc_err("Call on QBUF after unrecoverable error\n");
1128 return -EIO;
1129 }
f9f715a9
AH		 1130 if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1131 if (ctx->state == MFCINST_FINISHING) {
1132 mfc_err("Call on QBUF after EOS command\n");
1133 return -EIO;
1134 }
af935746 1135 return vb2_qbuf(&ctx->vq_src, buf);
f9f715a9 1136 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
af935746 1137 return vb2_qbuf(&ctx->vq_dst, buf);
f9f715a9 1138 }
af935746
KD		 1139 return -EINVAL;
1140}
1141
1142/* Dequeue a buffer */
1143static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1144{
f9f715a9
AH		 1145 const struct v4l2_event ev = {
1146 .type = V4L2_EVENT_EOS
1147 };
af935746 1148 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
f9f715a9 1149 int ret;
af935746
KD		 1150
1151 if (ctx->state == MFCINST_ERROR) {
1152 mfc_err("Call on DQBUF after unrecoverable error\n");
1153 return -EIO;
1154 }
f9f715a9
AH		 1155 if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1156 ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
1157 } else if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1158 ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
1159 if (ret == 0 && ctx->state == MFCINST_FINISHED
1160 && list_empty(&ctx->vq_dst.done_list))
1161 v4l2_event_queue_fh(&ctx->fh, &ev);
1162 } else {
1163 ret = -EINVAL;
1164 }
1165
1166 return ret;
af935746
KD		 1167}
1168
6fa9dd06
TS		 1169/* Export DMA buffer */
1170static int vidioc_expbuf(struct file *file, void *priv,
1171 struct v4l2_exportbuffer *eb)
1172{
1173 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1174
1175 if (eb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1176 return vb2_expbuf(&ctx->vq_src, eb);
1177 if (eb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1178 return vb2_expbuf(&ctx->vq_dst, eb);
1179 return -EINVAL;
1180}
1181
af935746
KD		 1182/* Stream on */
1183static int vidioc_streamon(struct file *file, void *priv,
1184 enum v4l2_buf_type type)
1185{
1186 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1187
1188 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1189 return vb2_streamon(&ctx->vq_src, type);
1190 else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1191 return vb2_streamon(&ctx->vq_dst, type);
1192 return -EINVAL;
1193}
1194
1195/* Stream off, which equals to a pause */
1196static int vidioc_streamoff(struct file *file, void *priv,
1197 enum v4l2_buf_type type)
1198{
1199 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1200
1201 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1202 return vb2_streamoff(&ctx->vq_src, type);
1203 else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1204 return vb2_streamoff(&ctx->vq_dst, type);
1205 return -EINVAL;
1206}
1207
1208static inline int h264_level(enum v4l2_mpeg_video_h264_level lvl)
1209{
1210 static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_4_0 + 1] = {
1211 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_0 */ 10,
1212 /* V4L2_MPEG_VIDEO_H264_LEVEL_1B */ 9,
1213 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_1 */ 11,
1214 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_2 */ 12,
1215 /* V4L2_MPEG_VIDEO_H264_LEVEL_1_3 */ 13,
1216 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_0 */ 20,
1217 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_1 */ 21,
1218 /* V4L2_MPEG_VIDEO_H264_LEVEL_2_2 */ 22,
1219 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_0 */ 30,
1220 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_1 */ 31,
1221 /* V4L2_MPEG_VIDEO_H264_LEVEL_3_2 */ 32,
1222 /* V4L2_MPEG_VIDEO_H264_LEVEL_4_0 */ 40,
1223 };
1224 return t[lvl];
1225}
1226
1227static inline int mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl)
1228{
1229 static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 + 1] = {
1230 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 */ 0,
1231 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B */ 9,
1232 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 */ 1,
1233 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 */ 2,
1234 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 */ 3,
1235 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B */ 7,
1236 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 */ 4,
1237 /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 */ 5,
1238 };
1239 return t[lvl];
1240}
1241
1242static inline int vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar)
1243{
1244 static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = {
1245 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED */ 0,
1246 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 */ 1,
1247 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 */ 2,
1248 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 */ 3,
1249 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 */ 4,
1250 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 */ 5,
1251 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 */ 6,
1252 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 */ 7,
1253 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 */ 8,
1254 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 */ 9,
1255 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 */ 10,
1256 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 */ 11,
1257 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 */ 12,
1258 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 */ 13,
1259 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 */ 14,
1260 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 */ 15,
1261 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 */ 16,
1262 /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED */ 255,
1263 };
1264 return t[sar];
1265}
1266
1267static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
1268{
1269 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
1270 struct s5p_mfc_dev *dev = ctx->dev;
1271 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1272 int ret = 0;
1273
1274 switch (ctrl->id) {
1275 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1276 p->gop_size = ctrl->val;
1277 break;
1278 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1279 p->slice_mode = ctrl->val;
1280 break;
1281 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1282 p->slice_mb = ctrl->val;
1283 break;
1284 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
1285 p->slice_bit = ctrl->val * 8;
1286 break;
1287 case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB:
1288 p->intra_refresh_mb = ctrl->val;
1289 break;
1290 case V4L2_CID_MPEG_MFC51_VIDEO_PADDING:
1291 p->pad = ctrl->val;
1292 break;
1293 case V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV:
1294 p->pad_luma = (ctrl->val >> 16) & 0xff;
1295 p->pad_cb = (ctrl->val >> 8) & 0xff;
1296 p->pad_cr = (ctrl->val >> 0) & 0xff;
1297 break;
1298 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
1299 p->rc_frame = ctrl->val;
1300 break;
1301 case V4L2_CID_MPEG_VIDEO_BITRATE:
1302 p->rc_bitrate = ctrl->val;
1303 break;
1304 case V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF:
1305 p->rc_reaction_coeff = ctrl->val;
1306 break;
1307 case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
1308 ctx->force_frame_type = ctrl->val;
1309 break;
1310 case V4L2_CID_MPEG_VIDEO_VBV_SIZE:
1311 p->vbv_size = ctrl->val;
1312 break;
1313 case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
1314 p->codec.h264.cpb_size = ctrl->val;
1315 break;
1316 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1317 p->seq_hdr_mode = ctrl->val;
1318 break;
1319 case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE:
1320 p->frame_skip_mode = ctrl->val;
1321 break;
1322 case V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT:
1323 p->fixed_target_bit = ctrl->val;
1324 break;
1325 case V4L2_CID_MPEG_VIDEO_B_FRAMES:
1326 p->num_b_frame = ctrl->val;
1327 break;
1328 case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
1329 switch (ctrl->val) {
1330 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
1331 p->codec.h264.profile =
1332 S5P_FIMV_ENC_PROFILE_H264_MAIN;
1333 break;
1334 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
1335 p->codec.h264.profile =
1336 S5P_FIMV_ENC_PROFILE_H264_HIGH;
1337 break;
1338 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
1339 p->codec.h264.profile =
1340 S5P_FIMV_ENC_PROFILE_H264_BASELINE;
1341 break;
f96f3cfa
JP		 1342 case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
1343 if (IS_MFCV6(dev))
1344 p->codec.h264.profile =
1345 S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE;
1346 else
1347 ret = -EINVAL;
1348 break;
af935746
KD		 1349 default:
1350 ret = -EINVAL;
1351 }
1352 break;
1353 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
1354 p->codec.h264.level_v4l2 = ctrl->val;
1355 p->codec.h264.level = h264_level(ctrl->val);
1356 if (p->codec.h264.level < 0) {
1357 mfc_err("Level number is wrong\n");
1358 ret = p->codec.h264.level;
1359 }
1360 break;
1361 case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL:
1362 p->codec.mpeg4.level_v4l2 = ctrl->val;
1363 p->codec.mpeg4.level = mpeg4_level(ctrl->val);
1364 if (p->codec.mpeg4.level < 0) {
1365 mfc_err("Level number is wrong\n");
1366 ret = p->codec.mpeg4.level;
1367 }
1368 break;
1369 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
1370 p->codec.h264.loop_filter_mode = ctrl->val;
1371 break;
1372 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:
1373 p->codec.h264.loop_filter_alpha = ctrl->val;
1374 break;
1375 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:
1376 p->codec.h264.loop_filter_beta = ctrl->val;
1377 break;
1378 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
1379 p->codec.h264.entropy_mode = ctrl->val;
1380 break;
1381 case V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P:
1382 p->codec.h264.num_ref_pic_4p = ctrl->val;
1383 break;
1384 case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM:
1385 p->codec.h264._8x8_transform = ctrl->val;
1386 break;
1387 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:
8f532a7f 1388 p->rc_mb = ctrl->val;
af935746
KD		 1389 break;
1390 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1391 p->codec.h264.rc_frame_qp = ctrl->val;
1392 break;
1393 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
1394 p->codec.h264.rc_min_qp = ctrl->val;
1395 break;
1396 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
1397 p->codec.h264.rc_max_qp = ctrl->val;
1398 break;
1399 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1400 p->codec.h264.rc_p_frame_qp = ctrl->val;
1401 break;
1402 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
1403 p->codec.h264.rc_b_frame_qp = ctrl->val;
1404 break;
1405 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1406 case V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP:
1407 p->codec.mpeg4.rc_frame_qp = ctrl->val;
1408 break;
1409 case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP:
1410 case V4L2_CID_MPEG_VIDEO_H263_MIN_QP:
1411 p->codec.mpeg4.rc_min_qp = ctrl->val;
1412 break;
1413 case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP:
1414 case V4L2_CID_MPEG_VIDEO_H263_MAX_QP:
1415 p->codec.mpeg4.rc_max_qp = ctrl->val;
1416 break;
1417 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1418 case V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP:
1419 p->codec.mpeg4.rc_p_frame_qp = ctrl->val;
1420 break;
1421 case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP:
1422 case V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP:
1423 p->codec.mpeg4.rc_b_frame_qp = ctrl->val;
1424 break;
1425 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK:
1426 p->codec.h264.rc_mb_dark = ctrl->val;
1427 break;
1428 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH:
1429 p->codec.h264.rc_mb_smooth = ctrl->val;
1430 break;
1431 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC:
1432 p->codec.h264.rc_mb_static = ctrl->val;
1433 break;
1434 case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY:
1435 p->codec.h264.rc_mb_activity = ctrl->val;
1436 break;
1437 case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE:
1438 p->codec.h264.vui_sar = ctrl->val;
1439 break;
1440 case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC:
1441 p->codec.h264.vui_sar_idc = vui_sar_idc(ctrl->val);
1442 break;
1443 case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH:
1444 p->codec.h264.vui_ext_sar_width = ctrl->val;
1445 break;
1446 case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT:
1447 p->codec.h264.vui_ext_sar_height = ctrl->val;
1448 break;
1449 case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE:
1450 p->codec.h264.open_gop = !ctrl->val;
1451 break;
1452 case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
1453 p->codec.h264.open_gop_size = ctrl->val;
1454 break;
1455 case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE:
1456 switch (ctrl->val) {
1457 case V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE:
1458 p->codec.mpeg4.profile =
1459 S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE;
1460 break;
1461 case V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE:
1462 p->codec.mpeg4.profile =
1463 S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE;
1464 break;
1465 default:
1466 ret = -EINVAL;
1467 }
1468 break;
1469 case V4L2_CID_MPEG_VIDEO_MPEG4_QPEL:
1470 p->codec.mpeg4.quarter_pixel = ctrl->val;
1471 break;
1472 default:
1473 v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
1474 ctrl->id, ctrl->val);
1475 ret = -EINVAL;
1476 }
1477 return ret;
1478}
1479
1480static const struct v4l2_ctrl_ops s5p_mfc_enc_ctrl_ops = {
1481 .s_ctrl = s5p_mfc_enc_s_ctrl,
1482};
1483
3e9095d5
SK		 1484static int vidioc_s_parm(struct file *file, void *priv,
1485 struct v4l2_streamparm *a)
af935746
KD		 1486{
1487 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1488
1489 if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1490 ctx->enc_params.rc_framerate_num =
1491 a->parm.output.timeperframe.denominator;
1492 ctx->enc_params.rc_framerate_denom =
1493 a->parm.output.timeperframe.numerator;
1494 } else {
1495 mfc_err("Setting FPS is only possible for the output queue\n");
1496 return -EINVAL;
1497 }
1498 return 0;
1499}
1500
3e9095d5
SK		 1501static int vidioc_g_parm(struct file *file, void *priv,
1502 struct v4l2_streamparm *a)
af935746
KD		 1503{
1504 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1505
1506 if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1507 a->parm.output.timeperframe.denominator =
1508 ctx->enc_params.rc_framerate_num;
1509 a->parm.output.timeperframe.numerator =
1510 ctx->enc_params.rc_framerate_denom;
1511 } else {
1512 mfc_err("Setting FPS is only possible for the output queue\n");
1513 return -EINVAL;
1514 }
1515 return 0;
1516}
1517
f9f715a9
AH		 1518int vidioc_encoder_cmd(struct file *file, void *priv,
1519 struct v4l2_encoder_cmd *cmd)
1520{
1521 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
1522 struct s5p_mfc_dev *dev = ctx->dev;
1523 struct s5p_mfc_buf *buf;
1524 unsigned long flags;
1525
1526 switch (cmd->cmd) {
1527 case V4L2_ENC_CMD_STOP:
1528 if (cmd->flags != 0)
1529 return -EINVAL;
1530
1531 if (!ctx->vq_src.streaming)
1532 return -EINVAL;
1533
1534 spin_lock_irqsave(&dev->irqlock, flags);
1535 if (list_empty(&ctx->src_queue)) {
1536 mfc_debug(2, "EOS: empty src queue, entering finishing state");
1537 ctx->state = MFCINST_FINISHING;
eb362092
KD		 1538 if (s5p_mfc_ctx_ready(ctx))
1539 set_work_bit_irqsave(ctx);
f9f715a9 1540 spin_unlock_irqrestore(&dev->irqlock, flags);
43a1ea1f 1541 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
f9f715a9
AH		 1542 } else {
1543 mfc_debug(2, "EOS: marking last buffer of stream");
1544 buf = list_entry(ctx->src_queue.prev,
1545 struct s5p_mfc_buf, list);
1546 if (buf->flags & MFC_BUF_FLAG_USED)
1547 ctx->state = MFCINST_FINISHING;
1548 else
1549 buf->flags |= MFC_BUF_FLAG_EOS;
1550 spin_unlock_irqrestore(&dev->irqlock, flags);
1551 }
1552 break;
1553 default:
1554 return -EINVAL;
1555
1556 }
1557 return 0;
1558}
1559
1560static int vidioc_subscribe_event(struct v4l2_fh *fh,
e1393b59 1561 const struct v4l2_event_subscription *sub)
f9f715a9
AH		 1562{
1563 switch (sub->type) {
1564 case V4L2_EVENT_EOS:
1565 return v4l2_event_subscribe(fh, sub, 2, NULL);
1566 default:
1567 return -EINVAL;
1568 }
1569}
1570
af935746
KD		 1571static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = {
1572 .vidioc_querycap = vidioc_querycap,
1573 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1574 .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
1575 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
1576 .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane,
1577 .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
1578 .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
1579 .vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
1580 .vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
1581 .vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
1582 .vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
1583 .vidioc_reqbufs = vidioc_reqbufs,
1584 .vidioc_querybuf = vidioc_querybuf,
1585 .vidioc_qbuf = vidioc_qbuf,
1586 .vidioc_dqbuf = vidioc_dqbuf,
6fa9dd06 1587 .vidioc_expbuf = vidioc_expbuf,
af935746
KD		 1588 .vidioc_streamon = vidioc_streamon,
1589 .vidioc_streamoff = vidioc_streamoff,
1590 .vidioc_s_parm = vidioc_s_parm,
1591 .vidioc_g_parm = vidioc_g_parm,
f9f715a9
AH		 1592 .vidioc_encoder_cmd = vidioc_encoder_cmd,
1593 .vidioc_subscribe_event = vidioc_subscribe_event,
1594 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
af935746
KD		 1595};
1596
1597static int check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb)
1598{
1599 int i;
1600
1601 if (!fmt)
1602 return -EINVAL;
1603 if (fmt->num_planes != vb->num_planes) {
1604 mfc_err("invalid plane number for the format\n");
1605 return -EINVAL;
1606 }
1607 for (i = 0; i < fmt->num_planes; i++) {
ba7fcb0c 1608 if (!vb2_dma_contig_plane_dma_addr(vb, i)) {
af935746
KD		 1609 mfc_err("failed to get plane cookie\n");
1610 return -EINVAL;
1611 }
1612 mfc_debug(2, "index: %d, plane[%d] cookie: 0x%08zx",
1613 vb->v4l2_buf.index, i,
ba7fcb0c 1614 vb2_dma_contig_plane_dma_addr(vb, i));
af935746
KD		 1615 }
1616 return 0;
1617}
1618
1619static int s5p_mfc_queue_setup(struct vb2_queue *vq,
fc714e70
GL		 1620 const struct v4l2_format *fmt,
1621 unsigned int *buf_count, unsigned int *plane_count,
1622 unsigned int psize[], void *allocators[])
af935746
KD		 1623{
1624 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
f96f3cfa 1625 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 1626
1627 if (ctx->state != MFCINST_GOT_INST) {
1628 mfc_err("inavlid state: %d\n", ctx->state);
1629 return -EINVAL;
1630 }
1631 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1632 if (ctx->dst_fmt)
1633 *plane_count = ctx->dst_fmt->num_planes;
1634 else
1635 *plane_count = MFC_ENC_CAP_PLANE_COUNT;
1636 if (*buf_count < 1)
1637 *buf_count = 1;
1638 if (*buf_count > MFC_MAX_BUFFERS)
1639 *buf_count = MFC_MAX_BUFFERS;
1640 psize[0] = ctx->enc_dst_buf_size;
1641 allocators[0] = ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1642 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1643 if (ctx->src_fmt)
1644 *plane_count = ctx->src_fmt->num_planes;
1645 else
1646 *plane_count = MFC_ENC_OUT_PLANE_COUNT;
1647
1648 if (*buf_count < 1)
1649 *buf_count = 1;
1650 if (*buf_count > MFC_MAX_BUFFERS)
1651 *buf_count = MFC_MAX_BUFFERS;
1652 psize[0] = ctx->luma_size;
1653 psize[1] = ctx->chroma_size;
f96f3cfa
JP		 1654 if (IS_MFCV6(dev)) {
1655 allocators[0] =
1656 ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1657 allocators[1] =
1658 ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
1659 } else {
1660 allocators[0] =
1661 ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1662 allocators[1] =
1663 ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
1664 }
af935746
KD		 1665 } else {
1666 mfc_err("inavlid queue type: %d\n", vq->type);
1667 return -EINVAL;
1668 }
1669 return 0;
1670}
1671
1672static void s5p_mfc_unlock(struct vb2_queue *q)
1673{
1674 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1675 struct s5p_mfc_dev *dev = ctx->dev;
1676
1677 mutex_unlock(&dev->mfc_mutex);
1678}
1679
1680static void s5p_mfc_lock(struct vb2_queue *q)
1681{
1682 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1683 struct s5p_mfc_dev *dev = ctx->dev;
1684
1685 mutex_lock(&dev->mfc_mutex);
1686}
1687
1688static int s5p_mfc_buf_init(struct vb2_buffer *vb)
1689{
1690 struct vb2_queue *vq = vb->vb2_queue;
1691 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1692 unsigned int i;
1693 int ret;
1694
1695 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1696 ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1697 if (ret < 0)
1698 return ret;
1699 i = vb->v4l2_buf.index;
1700 ctx->dst_bufs[i].b = vb;
1701 ctx->dst_bufs[i].cookie.stream =
ba7fcb0c 1702 vb2_dma_contig_plane_dma_addr(vb, 0);
af935746
KD		 1703 ctx->dst_bufs_cnt++;
1704 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1705 ret = check_vb_with_fmt(ctx->src_fmt, vb);
1706 if (ret < 0)
1707 return ret;
1708 i = vb->v4l2_buf.index;
1709 ctx->src_bufs[i].b = vb;
1710 ctx->src_bufs[i].cookie.raw.luma =
ba7fcb0c 1711 vb2_dma_contig_plane_dma_addr(vb, 0);
af935746 1712 ctx->src_bufs[i].cookie.raw.chroma =
ba7fcb0c 1713 vb2_dma_contig_plane_dma_addr(vb, 1);
af935746
KD		 1714 ctx->src_bufs_cnt++;
1715 } else {
1716 mfc_err("inavlid queue type: %d\n", vq->type);
1717 return -EINVAL;
1718 }
1719 return 0;
1720}
1721
1722static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
1723{
1724 struct vb2_queue *vq = vb->vb2_queue;
1725 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1726 int ret;
1727
1728 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1729 ret = check_vb_with_fmt(ctx->dst_fmt, vb);
1730 if (ret < 0)
1731 return ret;
1732 mfc_debug(2, "plane size: %ld, dst size: %d\n",
1733 vb2_plane_size(vb, 0), ctx->enc_dst_buf_size);
1734 if (vb2_plane_size(vb, 0) < ctx->enc_dst_buf_size) {
1735 mfc_err("plane size is too small for capture\n");
1736 return -EINVAL;
1737 }
1738 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1739 ret = check_vb_with_fmt(ctx->src_fmt, vb);
1740 if (ret < 0)
1741 return ret;
1742 mfc_debug(2, "plane size: %ld, luma size: %d\n",
1743 vb2_plane_size(vb, 0), ctx->luma_size);
1744 mfc_debug(2, "plane size: %ld, chroma size: %d\n",
1745 vb2_plane_size(vb, 1), ctx->chroma_size);
1746 if (vb2_plane_size(vb, 0) < ctx->luma_size ||
1747 vb2_plane_size(vb, 1) < ctx->chroma_size) {
1748 mfc_err("plane size is too small for output\n");
1749 return -EINVAL;
1750 }
1751 } else {
1752 mfc_err("inavlid queue type: %d\n", vq->type);
1753 return -EINVAL;
1754 }
1755 return 0;
1756}
1757
bd323e28 1758static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
af935746
KD		 1759{
1760 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1761 struct s5p_mfc_dev *dev = ctx->dev;
af935746
KD		 1762
1763 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
1764 /* If context is ready then dev = work->data;schedule it to run */
7fb89eca
AH		 1765 if (s5p_mfc_ctx_ready(ctx))
1766 set_work_bit_irqsave(ctx);
43a1ea1f 1767 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 1768 return 0;
1769}
1770
1771static int s5p_mfc_stop_streaming(struct vb2_queue *q)
1772{
1773 unsigned long flags;
1774 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1775 struct s5p_mfc_dev *dev = ctx->dev;
1776
1777 if ((ctx->state == MFCINST_FINISHING ||
1778 ctx->state == MFCINST_RUNNING) &&
1779 dev->curr_ctx == ctx->num && dev->hw_lock) {
1780 ctx->state = MFCINST_ABORT;
43a1ea1f 1781 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_FRAME_DONE_RET,
af935746
KD		 1782 0);
1783 }
1784 ctx->state = MFCINST_FINISHED;
1785 spin_lock_irqsave(&dev->irqlock, flags);
1786 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
43a1ea1f
AK		 1787 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
1788 &ctx->vq_dst);
af935746
KD		 1789 INIT_LIST_HEAD(&ctx->dst_queue);
1790 ctx->dst_queue_cnt = 0;
1791 }
1792 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1793 cleanup_ref_queue(ctx);
43a1ea1f
AK		 1794 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
1795 &ctx->vq_src);
af935746
KD		 1796 INIT_LIST_HEAD(&ctx->src_queue);
1797 ctx->src_queue_cnt = 0;
1798 }
1799 spin_unlock_irqrestore(&dev->irqlock, flags);
1800 return 0;
1801}
1802
1803static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
1804{
1805 struct vb2_queue *vq = vb->vb2_queue;
1806 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1807 struct s5p_mfc_dev *dev = ctx->dev;
1808 unsigned long flags;
1809 struct s5p_mfc_buf *mfc_buf;
1810
1811 if (ctx->state == MFCINST_ERROR) {
1812 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1813 cleanup_ref_queue(ctx);
1814 return;
1815 }
1816 if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1817 mfc_buf = &ctx->dst_bufs[vb->v4l2_buf.index];
f9f715a9 1818 mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
af935746
KD		 1819 /* Mark destination as available for use by MFC */
1820 spin_lock_irqsave(&dev->irqlock, flags);
1821 list_add_tail(&mfc_buf->list, &ctx->dst_queue);
1822 ctx->dst_queue_cnt++;
1823 spin_unlock_irqrestore(&dev->irqlock, flags);
1824 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1825 mfc_buf = &ctx->src_bufs[vb->v4l2_buf.index];
f9f715a9 1826 mfc_buf->flags &= ~MFC_BUF_FLAG_USED;
af935746 1827 spin_lock_irqsave(&dev->irqlock, flags);
f9f715a9
AH		 1828 list_add_tail(&mfc_buf->list, &ctx->src_queue);
1829 ctx->src_queue_cnt++;
af935746
KD		 1830 spin_unlock_irqrestore(&dev->irqlock, flags);
1831 } else {
1832 mfc_err("unsupported buffer type (%d)\n", vq->type);
1833 }
7fb89eca
AH		 1834 if (s5p_mfc_ctx_ready(ctx))
1835 set_work_bit_irqsave(ctx);
43a1ea1f 1836 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
af935746
KD		 1837}
1838
1839static struct vb2_ops s5p_mfc_enc_qops = {
1840 .queue_setup = s5p_mfc_queue_setup,
1841 .wait_prepare = s5p_mfc_unlock,
1842 .wait_finish = s5p_mfc_lock,
1843 .buf_init = s5p_mfc_buf_init,
1844 .buf_prepare = s5p_mfc_buf_prepare,
1845 .start_streaming = s5p_mfc_start_streaming,
1846 .stop_streaming = s5p_mfc_stop_streaming,
1847 .buf_queue = s5p_mfc_buf_queue,
1848};
1849
1850struct s5p_mfc_codec_ops *get_enc_codec_ops(void)
1851{
1852 return &encoder_codec_ops;
1853}
1854
1855struct vb2_ops *get_enc_queue_ops(void)
1856{
1857 return &s5p_mfc_enc_qops;
1858}
1859
1860const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void)
1861{
1862 return &s5p_mfc_enc_ioctl_ops;
1863}
1864
1865#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2CLASS(x) == V4L2_CTRL_CLASS_MPEG) \
1866 && V4L2_CTRL_DRIVER_PRIV(x))
1867
1868int s5p_mfc_enc_ctrls_setup(struct s5p_mfc_ctx *ctx)
1869{
1870 struct v4l2_ctrl_config cfg;
1871 int i;
1872
1873 v4l2_ctrl_handler_init(&ctx->ctrl_handler, NUM_CTRLS);
1874 if (ctx->ctrl_handler.error) {
1875 mfc_err("v4l2_ctrl_handler_init failed\n");
1876 return ctx->ctrl_handler.error;
1877 }
1878 for (i = 0; i < NUM_CTRLS; i++) {
1879 if (IS_MFC51_PRIV(controls[i].id)) {
a65c3262 1880 memset(&cfg, 0, sizeof(struct v4l2_ctrl_config));
af935746
KD		 1881 cfg.ops = &s5p_mfc_enc_ctrl_ops;
1882 cfg.id = controls[i].id;
1883 cfg.min = controls[i].minimum;
1884 cfg.max = controls[i].maximum;
1885 cfg.def = controls[i].default_value;
1886 cfg.name = controls[i].name;
1887 cfg.type = controls[i].type;
1888 cfg.flags = 0;
1889
1890 if (cfg.type == V4L2_CTRL_TYPE_MENU) {
1891 cfg.step = 0;
1892 cfg.menu_skip_mask = cfg.menu_skip_mask;
1893 cfg.qmenu = mfc51_get_menu(cfg.id);
1894 } else {
1895 cfg.step = controls[i].step;
1896 cfg.menu_skip_mask = 0;
1897 }
1898 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
1899 &cfg, NULL);
1900 } else {
1901 if (controls[i].type == V4L2_CTRL_TYPE_MENU) {
1902 ctx->ctrls[i] = v4l2_ctrl_new_std_menu(
1903 &ctx->ctrl_handler,
1904 &s5p_mfc_enc_ctrl_ops, controls[i].id,
1905 controls[i].maximum, 0,
1906 controls[i].default_value);
1907 } else {
1908 ctx->ctrls[i] = v4l2_ctrl_new_std(
1909 &ctx->ctrl_handler,
1910 &s5p_mfc_enc_ctrl_ops, controls[i].id,
1911 controls[i].minimum,
1912 controls[i].maximum, controls[i].step,
1913 controls[i].default_value);
1914 }
1915 }
1916 if (ctx->ctrl_handler.error) {
1917 mfc_err("Adding control (%d) failed\n", i);
1918 return ctx->ctrl_handler.error;
1919 }
1920 if (controls[i].is_volatile && ctx->ctrls[i])
88365105 1921 ctx->ctrls[i]->flags |= V4L2_CTRL_FLAG_VOLATILE;
af935746
KD		 1922 }
1923 return 0;
1924}
1925
1926void s5p_mfc_enc_ctrls_delete(struct s5p_mfc_ctx *ctx)
1927{
1928 int i;
1929
1930 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1931 for (i = 0; i < NUM_CTRLS; i++)
1932 ctx->ctrls[i] = NULL;
1933}
43a1ea1f
AK		 1934
1935void s5p_mfc_enc_init(struct s5p_mfc_ctx *ctx)
1936{
1937 struct v4l2_format f;
1938 f.fmt.pix_mp.pixelformat = DEF_SRC_FMT_ENC;
1939 ctx->src_fmt = find_format(&f, MFC_FMT_RAW);
1940 f.fmt.pix_mp.pixelformat = DEF_DST_FMT_ENC;
1941 ctx->dst_fmt = find_format(&f, MFC_FMT_ENC);
1942}
1943
Linux kernel - Deliverables
This page took 0.198985 seconds and 5 git commands to generate.