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[media] v4l: atmel-isi: Should clear bits before set the hardware register
[deliverable/linux.git] / drivers / media / platform / soc_camera / atmel-isi.c
CommitLineData
195ebc43
JW		 1/*
2 * Copyright (c) 2011 Atmel Corporation
3 * Josh Wu, <josh.wu@atmel.com>
4 *
5 * Based on previous work by Lars Haring, <lars.haring@atmel.com>
6 * and Sedji Gaouaou
7 * Based on the bttv driver for Bt848 with respective copyright holders
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/completion.h>
16#include <linux/delay.h>
17#include <linux/fs.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24
25#include <media/atmel-isi.h>
26#include <media/soc_camera.h>
27#include <media/soc_mediabus.h>
28#include <media/videobuf2-dma-contig.h>
29
30#define MAX_BUFFER_NUM 32
31#define MAX_SUPPORT_WIDTH 2048
32#define MAX_SUPPORT_HEIGHT 2048
33#define VID_LIMIT_BYTES (16 * 1024 * 1024)
34#define MIN_FRAME_RATE 15
35#define FRAME_INTERVAL_MILLI_SEC (1000 / MIN_FRAME_RATE)
36
195ebc43
JW		 37/* Frame buffer descriptor */
38struct fbd {
39 /* Physical address of the frame buffer */
40 u32 fb_address;
41 /* DMA Control Register(only in HISI2) */
42 u32 dma_ctrl;
43 /* Physical address of the next fbd */
44 u32 next_fbd_address;
45};
46
47static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
48{
49 fb_desc->dma_ctrl = ctrl;
50}
51
52struct isi_dma_desc {
53 struct list_head list;
54 struct fbd *p_fbd;
55 u32 fbd_phys;
56};
57
58/* Frame buffer data */
59struct frame_buffer {
60 struct vb2_buffer vb;
61 struct isi_dma_desc *p_dma_desc;
62 struct list_head list;
63};
64
65struct atmel_isi {
66 /* Protects the access of variables shared with the ISR */
67 spinlock_t lock;
68 void __iomem *regs;
69
70 int sequence;
195ebc43
JW		 71
72 struct vb2_alloc_ctx *alloc_ctx;
73
74 /* Allocate descriptors for dma buffer use */
75 struct fbd *p_fb_descriptors;
76 u32 fb_descriptors_phys;
77 struct list_head dma_desc_head;
78 struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
79
80 struct completion complete;
d8ec0961 81 /* ISI peripherial clock */
195ebc43 82 struct clk *pclk;
d8ec0961
JW		 83 /* ISI_MCK, feed to camera sensor to generate pixel clock */
84 struct clk *mck;
195ebc43
JW		 85 unsigned int irq;
86
87 struct isi_platform_data *pdata;
a4e9f10b 88 u16 width_flags; /* max 12 bits */
195ebc43
JW		 89
90 struct list_head video_buffer_list;
91 struct frame_buffer *active;
92
195ebc43
JW		 93 struct soc_camera_host soc_host;
94};
95
96static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
97{
98 writel(val, isi->regs + reg);
99}
100static u32 isi_readl(struct atmel_isi *isi, u32 reg)
101{
102 return readl(isi->regs + reg);
103}
104
105static int configure_geometry(struct atmel_isi *isi, u32 width,
106 u32 height, enum v4l2_mbus_pixelcode code)
107{
108 u32 cfg2, cr;
109
110 switch (code) {
111 /* YUV, including grey */
112 case V4L2_MBUS_FMT_Y8_1X8:
113 cr = ISI_CFG2_GRAYSCALE;
114 break;
135983e8 115 case V4L2_MBUS_FMT_VYUY8_2X8:
195ebc43
JW		 116 cr = ISI_CFG2_YCC_SWAP_MODE_3;
117 break;
135983e8 118 case V4L2_MBUS_FMT_UYVY8_2X8:
195ebc43
JW		 119 cr = ISI_CFG2_YCC_SWAP_MODE_2;
120 break;
135983e8 121 case V4L2_MBUS_FMT_YVYU8_2X8:
195ebc43
JW		 122 cr = ISI_CFG2_YCC_SWAP_MODE_1;
123 break;
135983e8 124 case V4L2_MBUS_FMT_YUYV8_2X8:
195ebc43
JW		 125 cr = ISI_CFG2_YCC_SWAP_DEFAULT;
126 break;
127 /* RGB, TODO */
128 default:
129 return -EINVAL;
130 }
131
132 isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
133
134 cfg2 = isi_readl(isi, ISI_CFG2);
bd6f2745
JW		 135 /* Set YCC swap mode */
136 cfg2 &= ~ISI_CFG2_YCC_SWAP_MODE_MASK;
195ebc43
JW		 137 cfg2 |= cr;
138 /* Set width */
139 cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK);
140 cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
141 ISI_CFG2_IM_HSIZE_MASK;
142 /* Set height */
143 cfg2 &= ~(ISI_CFG2_IM_VSIZE_MASK);
144 cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
145 & ISI_CFG2_IM_VSIZE_MASK;
146 isi_writel(isi, ISI_CFG2, cfg2);
147
148 return 0;
149}
150
151static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
152{
153 if (isi->active) {
154 struct vb2_buffer *vb = &isi->active->vb;
155 struct frame_buffer *buf = isi->active;
156
157 list_del_init(&buf->list);
8e6057b5 158 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
195ebc43
JW		 159 vb->v4l2_buf.sequence = isi->sequence++;
160 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
161 }
162
163 if (list_empty(&isi->video_buffer_list)) {
164 isi->active = NULL;
165 } else {
166 /* start next dma frame. */
167 isi->active = list_entry(isi->video_buffer_list.next,
168 struct frame_buffer, list);
169 isi_writel(isi, ISI_DMA_C_DSCR,
170 isi->active->p_dma_desc->fbd_phys);
171 isi_writel(isi, ISI_DMA_C_CTRL,
172 ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
173 isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
174 }
175 return IRQ_HANDLED;
176}
177
178/* ISI interrupt service routine */
179static irqreturn_t isi_interrupt(int irq, void *dev_id)
180{
181 struct atmel_isi *isi = dev_id;
182 u32 status, mask, pending;
183 irqreturn_t ret = IRQ_NONE;
184
185 spin_lock(&isi->lock);
186
187 status = isi_readl(isi, ISI_STATUS);
188 mask = isi_readl(isi, ISI_INTMASK);
189 pending = status & mask;
190
191 if (pending & ISI_CTRL_SRST) {
192 complete(&isi->complete);
193 isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
194 ret = IRQ_HANDLED;
195 } else if (pending & ISI_CTRL_DIS) {
196 complete(&isi->complete);
197 isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
198 ret = IRQ_HANDLED;
199 } else {
195ebc43
JW		 200 if (likely(pending & ISI_SR_CXFR_DONE))
201 ret = atmel_isi_handle_streaming(isi);
202 }
203
204 spin_unlock(&isi->lock);
205 return ret;
206}
207
208#define WAIT_ISI_RESET 1
209#define WAIT_ISI_DISABLE 0
210static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
211{
212 unsigned long timeout;
213 /*
214 * The reset or disable will only succeed if we have a
215 * pixel clock from the camera.
216 */
217 init_completion(&isi->complete);
218
219 if (wait_reset) {
220 isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
221 isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
222 } else {
223 isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
224 isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
225 }
226
227 timeout = wait_for_completion_timeout(&isi->complete,
228 msecs_to_jiffies(100));
229 if (timeout == 0)
230 return -ETIMEDOUT;
231
232 return 0;
233}
234
235/* ------------------------------------------------------------------
236 Videobuf operations
237 ------------------------------------------------------------------*/
fc714e70
GL		 238static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
239 unsigned int *nbuffers, unsigned int *nplanes,
240 unsigned int sizes[], void *alloc_ctxs[])
195ebc43
JW		 241{
242 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
7dfff953 243 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 244 struct atmel_isi *isi = ici->priv;
245 unsigned long size;
195ebc43 246
2b61d46e 247 size = icd->sizeimage;
195ebc43
JW		 248
249 if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
250 *nbuffers = MAX_BUFFER_NUM;
251
252 if (size * *nbuffers > VID_LIMIT_BYTES)
253 *nbuffers = VID_LIMIT_BYTES / size;
254
255 *nplanes = 1;
256 sizes[0] = size;
257 alloc_ctxs[0] = isi->alloc_ctx;
258
259 isi->sequence = 0;
260 isi->active = NULL;
261
7dfff953 262 dev_dbg(icd->parent, "%s, count=%d, size=%ld\n", __func__,
195ebc43
JW		 263 *nbuffers, size);
264
265 return 0;
266}
267
268static int buffer_init(struct vb2_buffer *vb)
269{
270 struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
271
272 buf->p_dma_desc = NULL;
273 INIT_LIST_HEAD(&buf->list);
274
275 return 0;
276}
277
278static int buffer_prepare(struct vb2_buffer *vb)
279{
280 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
281 struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
7dfff953 282 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 283 struct atmel_isi *isi = ici->priv;
284 unsigned long size;
285 struct isi_dma_desc *desc;
195ebc43 286
2b61d46e 287 size = icd->sizeimage;
195ebc43
JW		 288
289 if (vb2_plane_size(vb, 0) < size) {
7dfff953 290 dev_err(icd->parent, "%s data will not fit into plane (%lu < %lu)\n",
195ebc43
JW		 291 __func__, vb2_plane_size(vb, 0), size);
292 return -EINVAL;
293 }
294
295 vb2_set_plane_payload(&buf->vb, 0, size);
296
297 if (!buf->p_dma_desc) {
298 if (list_empty(&isi->dma_desc_head)) {
7dfff953 299 dev_err(icd->parent, "Not enough dma descriptors.\n");
195ebc43
JW		 300 return -EINVAL;
301 } else {
302 /* Get an available descriptor */
303 desc = list_entry(isi->dma_desc_head.next,
304 struct isi_dma_desc, list);
305 /* Delete the descriptor since now it is used */
306 list_del_init(&desc->list);
307
308 /* Initialize the dma descriptor */
309 desc->p_fbd->fb_address =
ba7fcb0c 310 vb2_dma_contig_plane_dma_addr(vb, 0);
195ebc43
JW		 311 desc->p_fbd->next_fbd_address = 0;
312 set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
313
314 buf->p_dma_desc = desc;
315 }
316 }
317 return 0;
318}
319
320static void buffer_cleanup(struct vb2_buffer *vb)
321{
322 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
7dfff953 323 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 324 struct atmel_isi *isi = ici->priv;
325 struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
326
327 /* This descriptor is available now and we add to head list */
328 if (buf->p_dma_desc)
329 list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
330}
331
332static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
333{
334 u32 ctrl, cfg1;
335
336 cfg1 = isi_readl(isi, ISI_CFG1);
337 /* Enable irq: cxfr for the codec path, pxfr for the preview path */
338 isi_writel(isi, ISI_INTEN,
339 ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
340
341 /* Check if already in a frame */
342 if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
f7f6ce2d 343 dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
195ebc43
JW		 344 return;
345 }
346
347 isi_writel(isi, ISI_DMA_C_DSCR, buffer->p_dma_desc->fbd_phys);
348 isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
349 isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
350
bd6f2745 351 cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK;
195ebc43
JW		 352 /* Enable linked list */
353 cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR;
354
355 /* Enable codec path and ISI */
356 ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
357 isi_writel(isi, ISI_CTRL, ctrl);
358 isi_writel(isi, ISI_CFG1, cfg1);
359}
360
361static void buffer_queue(struct vb2_buffer *vb)
362{
363 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
7dfff953 364 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 365 struct atmel_isi *isi = ici->priv;
366 struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
367 unsigned long flags = 0;
368
369 spin_lock_irqsave(&isi->lock, flags);
370 list_add_tail(&buf->list, &isi->video_buffer_list);
371
372 if (isi->active == NULL) {
373 isi->active = buf;
bd323e28
MS		 374 if (vb2_is_streaming(vb->vb2_queue))
375 start_dma(isi, buf);
195ebc43
JW		 376 }
377 spin_unlock_irqrestore(&isi->lock, flags);
378}
379
bd323e28 380static int start_streaming(struct vb2_queue *vq, unsigned int count)
195ebc43
JW		 381{
382 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
7dfff953 383 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43 384 struct atmel_isi *isi = ici->priv;
195ebc43 385 u32 sr = 0;
c7686264
LP		 386 int ret;
387
388 /* Reset ISI */
389 ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
390 if (ret < 0) {
391 dev_err(icd->parent, "Reset ISI timed out\n");
392 return ret;
393 }
394 /* Disable all interrupts */
395 isi_writel(isi, ISI_INTDIS, ~0UL);
195ebc43
JW		 396
397 spin_lock_irq(&isi->lock);
1426f61b 398 /* Clear any pending interrupt */
195ebc43 399 sr = isi_readl(isi, ISI_STATUS);
195ebc43 400
bd323e28
MS		 401 if (count)
402 start_dma(isi, isi->active);
195ebc43
JW		 403 spin_unlock_irq(&isi->lock);
404
405 return 0;
406}
407
408/* abort streaming and wait for last buffer */
409static int stop_streaming(struct vb2_queue *vq)
410{
411 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
7dfff953 412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 413 struct atmel_isi *isi = ici->priv;
414 struct frame_buffer *buf, *node;
415 int ret = 0;
416 unsigned long timeout;
417
418 spin_lock_irq(&isi->lock);
419 isi->active = NULL;
420 /* Release all active buffers */
421 list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
422 list_del_init(&buf->list);
423 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
424 }
425 spin_unlock_irq(&isi->lock);
426
427 timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
428 /* Wait until the end of the current frame. */
429 while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
430 time_before(jiffies, timeout))
431 msleep(1);
432
433 if (time_after(jiffies, timeout)) {
7dfff953 434 dev_err(icd->parent,
195ebc43
JW		 435 "Timeout waiting for finishing codec request\n");
436 return -ETIMEDOUT;
437 }
438
439 /* Disable interrupts */
440 isi_writel(isi, ISI_INTDIS,
441 ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
442
443 /* Disable ISI and wait for it is done */
444 ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
445 if (ret < 0)
7dfff953 446 dev_err(icd->parent, "Disable ISI timed out\n");
195ebc43
JW		 447
448 return ret;
449}
450
451static struct vb2_ops isi_video_qops = {
452 .queue_setup = queue_setup,
453 .buf_init = buffer_init,
454 .buf_prepare = buffer_prepare,
455 .buf_cleanup = buffer_cleanup,
456 .buf_queue = buffer_queue,
457 .start_streaming = start_streaming,
458 .stop_streaming = stop_streaming,
459 .wait_prepare = soc_camera_unlock,
460 .wait_finish = soc_camera_lock,
461};
462
463/* ------------------------------------------------------------------
464 SOC camera operations for the device
465 ------------------------------------------------------------------*/
466static int isi_camera_init_videobuf(struct vb2_queue *q,
467 struct soc_camera_device *icd)
468{
469 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
470 q->io_modes = VB2_MMAP;
471 q->drv_priv = icd;
472 q->buf_struct_size = sizeof(struct frame_buffer);
473 q->ops = &isi_video_qops;
474 q->mem_ops = &vb2_dma_contig_memops;
6aa69f99 475 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
195ebc43
JW		 476
477 return vb2_queue_init(q);
478}
479
480static int isi_camera_set_fmt(struct soc_camera_device *icd,
481 struct v4l2_format *f)
482{
7dfff953 483 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43
JW		 484 struct atmel_isi *isi = ici->priv;
485 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
486 const struct soc_camera_format_xlate *xlate;
487 struct v4l2_pix_format *pix = &f->fmt.pix;
488 struct v4l2_mbus_framefmt mf;
489 int ret;
490
491 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
492 if (!xlate) {
7dfff953 493 dev_warn(icd->parent, "Format %x not found\n",
195ebc43
JW		 494 pix->pixelformat);
495 return -EINVAL;
496 }
497
7dfff953 498 dev_dbg(icd->parent, "Plan to set format %dx%d\n",
195ebc43
JW		 499 pix->width, pix->height);
500
501 mf.width = pix->width;
502 mf.height = pix->height;
503 mf.field = pix->field;
504 mf.colorspace = pix->colorspace;
505 mf.code = xlate->code;
506
507 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
508 if (ret < 0)
509 return ret;
510
511 if (mf.code != xlate->code)
512 return -EINVAL;
513
514 ret = configure_geometry(isi, pix->width, pix->height, xlate->code);
515 if (ret < 0)
516 return ret;
517
518 pix->width = mf.width;
519 pix->height = mf.height;
520 pix->field = mf.field;
521 pix->colorspace = mf.colorspace;
522 icd->current_fmt = xlate;
523
7dfff953 524 dev_dbg(icd->parent, "Finally set format %dx%d\n",
195ebc43
JW		 525 pix->width, pix->height);
526
527 return ret;
528}
529
530static int isi_camera_try_fmt(struct soc_camera_device *icd,
531 struct v4l2_format *f)
532{
533 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
534 const struct soc_camera_format_xlate *xlate;
535 struct v4l2_pix_format *pix = &f->fmt.pix;
536 struct v4l2_mbus_framefmt mf;
537 u32 pixfmt = pix->pixelformat;
538 int ret;
539
540 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
541 if (pixfmt && !xlate) {
7dfff953 542 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
195ebc43
JW		 543 return -EINVAL;
544 }
545
546 /* limit to Atmel ISI hardware capabilities */
547 if (pix->height > MAX_SUPPORT_HEIGHT)
548 pix->height = MAX_SUPPORT_HEIGHT;
549 if (pix->width > MAX_SUPPORT_WIDTH)
550 pix->width = MAX_SUPPORT_WIDTH;
551
552 /* limit to sensor capabilities */
553 mf.width = pix->width;
554 mf.height = pix->height;
555 mf.field = pix->field;
556 mf.colorspace = pix->colorspace;
557 mf.code = xlate->code;
558
559 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
560 if (ret < 0)
561 return ret;
562
563 pix->width = mf.width;
564 pix->height = mf.height;
565 pix->colorspace = mf.colorspace;
566
567 switch (mf.field) {
568 case V4L2_FIELD_ANY:
569 pix->field = V4L2_FIELD_NONE;
570 break;
571 case V4L2_FIELD_NONE:
572 break;
573 default:
7dfff953 574 dev_err(icd->parent, "Field type %d unsupported.\n",
195ebc43
JW		 575 mf.field);
576 ret = -EINVAL;
577 }
578
579 return ret;
580}
581
582static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
583 {
584 .fourcc = V4L2_PIX_FMT_YUYV,
585 .name = "Packed YUV422 16 bit",
586 .bits_per_sample = 8,
587 .packing = SOC_MBUS_PACKING_2X8_PADHI,
588 .order = SOC_MBUS_ORDER_LE,
ad3b81fa 589 .layout = SOC_MBUS_LAYOUT_PACKED,
195ebc43
JW		 590 },
591};
592
593/* This will be corrected as we get more formats */
594static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
595{
596 return fmt->packing == SOC_MBUS_PACKING_NONE ||
597 (fmt->bits_per_sample == 8 &&
598 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
599 (fmt->bits_per_sample > 8 &&
600 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
601}
602
a4e9f10b
GL		 603#define ISI_BUS_PARAM (V4L2_MBUS_MASTER | \
604 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
605 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
606 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
607 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
608 V4L2_MBUS_PCLK_SAMPLE_RISING | \
609 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
610 V4L2_MBUS_DATA_ACTIVE_HIGH)
195ebc43
JW		 611
612static int isi_camera_try_bus_param(struct soc_camera_device *icd,
613 unsigned char buswidth)
614{
a4e9f10b 615 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
7dfff953 616 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43 617 struct atmel_isi *isi = ici->priv;
a4e9f10b
GL		 618 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
619 unsigned long common_flags;
195ebc43
JW		 620 int ret;
621
a4e9f10b
GL		 622 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
623 if (!ret) {
624 common_flags = soc_mbus_config_compatible(&cfg,
625 ISI_BUS_PARAM);
626 if (!common_flags) {
627 dev_warn(icd->parent,
628 "Flags incompatible: camera 0x%x, host 0x%x\n",
629 cfg.flags, ISI_BUS_PARAM);
630 return -EINVAL;
631 }
632 } else if (ret != -ENOIOCTLCMD) {
633 return ret;
634 }
635
636 if ((1 << (buswidth - 1)) & isi->width_flags)
637 return 0;
638 return -EINVAL;
195ebc43
JW		 639}
640
641
642static int isi_camera_get_formats(struct soc_camera_device *icd,
643 unsigned int idx,
644 struct soc_camera_format_xlate *xlate)
645{
646 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
647 int formats = 0, ret;
648 /* sensor format */
649 enum v4l2_mbus_pixelcode code;
650 /* soc camera host format */
651 const struct soc_mbus_pixelfmt *fmt;
652
653 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
654 if (ret < 0)
655 /* No more formats */
656 return 0;
657
658 fmt = soc_mbus_get_fmtdesc(code);
659 if (!fmt) {
7dfff953 660 dev_err(icd->parent,
195ebc43
JW		 661 "Invalid format code #%u: %d\n", idx, code);
662 return 0;
663 }
664
665 /* This also checks support for the requested bits-per-sample */
666 ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
667 if (ret < 0) {
7dfff953 668 dev_err(icd->parent,
195ebc43
JW		 669 "Fail to try the bus parameters.\n");
670 return 0;
671 }
672
673 switch (code) {
674 case V4L2_MBUS_FMT_UYVY8_2X8:
675 case V4L2_MBUS_FMT_VYUY8_2X8:
676 case V4L2_MBUS_FMT_YUYV8_2X8:
677 case V4L2_MBUS_FMT_YVYU8_2X8:
678 formats++;
679 if (xlate) {
680 xlate->host_fmt = &isi_camera_formats[0];
681 xlate->code = code;
682 xlate++;
7dfff953 683 dev_dbg(icd->parent, "Providing format %s using code %d\n",
195ebc43
JW		 684 isi_camera_formats[0].name, code);
685 }
686 break;
687 default:
688 if (!isi_camera_packing_supported(fmt))
689 return 0;
690 if (xlate)
7dfff953 691 dev_dbg(icd->parent,
195ebc43
JW		 692 "Providing format %s in pass-through mode\n",
693 fmt->name);
694 }
695
696 /* Generic pass-through */
697 formats++;
698 if (xlate) {
699 xlate->host_fmt = fmt;
700 xlate->code = code;
701 xlate++;
702 }
703
704 return formats;
705}
706
195ebc43
JW		 707static int isi_camera_add_device(struct soc_camera_device *icd)
708{
ffebad79
GL		 709 dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n",
710 icd->devnum);
711
712 return 0;
713}
714
715static void isi_camera_remove_device(struct soc_camera_device *icd)
716{
717 dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n",
718 icd->devnum);
719}
720
721/* Called with .host_lock held */
722static int isi_camera_clock_start(struct soc_camera_host *ici)
723{
195ebc43
JW		 724 struct atmel_isi *isi = ici->priv;
725 int ret;
726
c01d568e 727 ret = clk_prepare_enable(isi->pclk);
195ebc43
JW		 728 if (ret)
729 return ret;
730
f389e89c
LP		 731 if (!IS_ERR(isi->mck)) {
732 ret = clk_prepare_enable(isi->mck);
733 if (ret) {
734 clk_disable_unprepare(isi->pclk);
735 return ret;
736 }
d8ec0961
JW		 737 }
738
195ebc43
JW		 739 return 0;
740}
ffebad79 741
dd669e90 742/* Called with .host_lock held */
ffebad79 743static void isi_camera_clock_stop(struct soc_camera_host *ici)
195ebc43 744{
195ebc43
JW		 745 struct atmel_isi *isi = ici->priv;
746
f389e89c
LP		 747 if (!IS_ERR(isi->mck))
748 clk_disable_unprepare(isi->mck);
c01d568e 749 clk_disable_unprepare(isi->pclk);
195ebc43
JW		 750}
751
752static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
753{
754 struct soc_camera_device *icd = file->private_data;
755
756 return vb2_poll(&icd->vb2_vidq, file, pt);
757}
758
759static int isi_camera_querycap(struct soc_camera_host *ici,
760 struct v4l2_capability *cap)
761{
762 strcpy(cap->driver, "atmel-isi");
763 strcpy(cap->card, "Atmel Image Sensor Interface");
764 cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE |
765 V4L2_CAP_STREAMING);
766 return 0;
767}
768
8843d119 769static int isi_camera_set_bus_param(struct soc_camera_device *icd)
195ebc43 770{
a4e9f10b 771 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
7dfff953 772 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195ebc43 773 struct atmel_isi *isi = ici->priv;
a4e9f10b
GL		 774 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
775 unsigned long common_flags;
195ebc43
JW		 776 int ret;
777 u32 cfg1 = 0;
778
a4e9f10b
GL		 779 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
780 if (!ret) {
781 common_flags = soc_mbus_config_compatible(&cfg,
782 ISI_BUS_PARAM);
783 if (!common_flags) {
784 dev_warn(icd->parent,
785 "Flags incompatible: camera 0x%x, host 0x%x\n",
786 cfg.flags, ISI_BUS_PARAM);
787 return -EINVAL;
788 }
789 } else if (ret != -ENOIOCTLCMD) {
790 return ret;
791 } else {
792 common_flags = ISI_BUS_PARAM;
793 }
794 dev_dbg(icd->parent, "Flags cam: 0x%x host: 0x%x common: 0x%lx\n",
795 cfg.flags, ISI_BUS_PARAM, common_flags);
195ebc43
JW		 796
797 /* Make choises, based on platform preferences */
a4e9f10b
GL		 798 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
799 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
195ebc43 800 if (isi->pdata->hsync_act_low)
a4e9f10b 801 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
195ebc43 802 else
a4e9f10b 803 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
195ebc43
JW		 804 }
805
a4e9f10b
GL		 806 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
807 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
195ebc43 808 if (isi->pdata->vsync_act_low)
a4e9f10b 809 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
195ebc43 810 else
a4e9f10b 811 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
195ebc43
JW		 812 }
813
a4e9f10b
GL		 814 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
815 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
195ebc43 816 if (isi->pdata->pclk_act_falling)
a4e9f10b 817 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
195ebc43 818 else
a4e9f10b 819 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
195ebc43
JW		 820 }
821
a4e9f10b
GL		 822 cfg.flags = common_flags;
823 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
824 if (ret < 0 && ret != -ENOIOCTLCMD) {
825 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
195ebc43
JW		 826 common_flags, ret);
827 return ret;
828 }
829
830 /* set bus param for ISI */
a4e9f10b 831 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
195ebc43 832 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
a4e9f10b 833 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
195ebc43 834 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
a4e9f10b 835 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
195ebc43
JW		 836 cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
837
838 if (isi->pdata->has_emb_sync)
839 cfg1 |= ISI_CFG1_EMB_SYNC;
d8ec0961 840 if (isi->pdata->full_mode)
195ebc43
JW		 841 cfg1 |= ISI_CFG1_FULL_MODE;
842
843 isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
844 isi_writel(isi, ISI_CFG1, cfg1);
845
846 return 0;
847}
848
849static struct soc_camera_host_ops isi_soc_camera_host_ops = {
850 .owner = THIS_MODULE,
851 .add = isi_camera_add_device,
852 .remove = isi_camera_remove_device,
ffebad79
GL		 853 .clock_start = isi_camera_clock_start,
854 .clock_stop = isi_camera_clock_stop,
195ebc43
JW		 855 .set_fmt = isi_camera_set_fmt,
856 .try_fmt = isi_camera_try_fmt,
857 .get_formats = isi_camera_get_formats,
858 .init_videobuf2 = isi_camera_init_videobuf,
859 .poll = isi_camera_poll,
860 .querycap = isi_camera_querycap,
861 .set_bus_param = isi_camera_set_bus_param,
862};
863
864/* -----------------------------------------------------------------------*/
4c62e976 865static int atmel_isi_remove(struct platform_device *pdev)
195ebc43
JW		 866{
867 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
868 struct atmel_isi *isi = container_of(soc_host,
869 struct atmel_isi, soc_host);
870
195ebc43
JW		 871 soc_camera_host_unregister(soc_host);
872 vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
873 dma_free_coherent(&pdev->dev,
874 sizeof(struct fbd) * MAX_BUFFER_NUM,
875 isi->p_fb_descriptors,
876 isi->fb_descriptors_phys);
877
195ebc43
JW		 878 return 0;
879}
880
4c62e976 881static int atmel_isi_probe(struct platform_device *pdev)
195ebc43
JW		 882{
883 unsigned int irq;
884 struct atmel_isi *isi;
195ebc43
JW		 885 struct resource *regs;
886 int ret, i;
887 struct device *dev = &pdev->dev;
888 struct soc_camera_host *soc_host;
889 struct isi_platform_data *pdata;
890
891 pdata = dev->platform_data;
f389e89c 892 if (!pdata || !pdata->data_width_flags) {
195ebc43
JW		 893 dev_err(&pdev->dev,
894 "No config available for Atmel ISI\n");
895 return -EINVAL;
896 }
897
c52c0cbf 898 isi = devm_kzalloc(&pdev->dev, sizeof(struct atmel_isi), GFP_KERNEL);
195ebc43 899 if (!isi) {
195ebc43 900 dev_err(&pdev->dev, "Can't allocate interface!\n");
c52c0cbf 901 return -ENOMEM;
195ebc43
JW		 902 }
903
c52c0cbf
LP		 904 isi->pclk = devm_clk_get(&pdev->dev, "isi_clk");
905 if (IS_ERR(isi->pclk))
906 return PTR_ERR(isi->pclk);
907
195ebc43
JW		 908 isi->pdata = pdata;
909 isi->active = NULL;
910 spin_lock_init(&isi->lock);
195ebc43
JW		 911 INIT_LIST_HEAD(&isi->video_buffer_list);
912 INIT_LIST_HEAD(&isi->dma_desc_head);
913
f389e89c
LP		 914 /* ISI_MCK is the sensor master clock. It should be handled by the
915 * sensor driver directly, as the ISI has no use for that clock. Make
916 * the clock optional here while platforms transition to the correct
917 * model.
918 */
c52c0cbf 919 isi->mck = devm_clk_get(dev, "isi_mck");
f389e89c
LP		 920 if (!IS_ERR(isi->mck)) {
921 /* Set ISI_MCK's frequency, it should be faster than pixel
922 * clock.
923 */
924 ret = clk_set_rate(isi->mck, pdata->mck_hz);
925 if (ret < 0)
926 return ret;
d8ec0961
JW		 927 }
928
195ebc43
JW		 929 isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
930 sizeof(struct fbd) * MAX_BUFFER_NUM,
931 &isi->fb_descriptors_phys,
932 GFP_KERNEL);
933 if (!isi->p_fb_descriptors) {
195ebc43 934 dev_err(&pdev->dev, "Can't allocate descriptors!\n");
c01d568e 935 return -ENOMEM;
195ebc43
JW		 936 }
937
938 for (i = 0; i < MAX_BUFFER_NUM; i++) {
939 isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
940 isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
941 i * sizeof(struct fbd);
942 list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
943 }
944
945 isi->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
946 if (IS_ERR(isi->alloc_ctx)) {
947 ret = PTR_ERR(isi->alloc_ctx);
948 goto err_alloc_ctx;
949 }
950
c52c0cbf
LP		 951 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
952 isi->regs = devm_ioremap_resource(&pdev->dev, regs);
953 if (IS_ERR(isi->regs)) {
954 ret = PTR_ERR(isi->regs);
195ebc43
JW		 955 goto err_ioremap;
956 }
957
a4e9f10b
GL		 958 if (pdata->data_width_flags & ISI_DATAWIDTH_8)
959 isi->width_flags = 1 << 7;
960 if (pdata->data_width_flags & ISI_DATAWIDTH_10)
961 isi->width_flags |= 1 << 9;
962
195ebc43
JW		 963 isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
964
965 irq = platform_get_irq(pdev, 0);
e35abd44 966 if (IS_ERR_VALUE(irq)) {
195ebc43
JW		 967 ret = irq;
968 goto err_req_irq;
969 }
970
c52c0cbf 971 ret = devm_request_irq(&pdev->dev, irq, isi_interrupt, 0, "isi", isi);
195ebc43
JW		 972 if (ret) {
973 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
974 goto err_req_irq;
975 }
976 isi->irq = irq;
977
978 soc_host = &isi->soc_host;
979 soc_host->drv_name = "isi-camera";
980 soc_host->ops = &isi_soc_camera_host_ops;
981 soc_host->priv = isi;
982 soc_host->v4l2_dev.dev = &pdev->dev;
983 soc_host->nr = pdev->id;
984
985 ret = soc_camera_host_register(soc_host);
986 if (ret) {
987 dev_err(&pdev->dev, "Unable to register soc camera host\n");
988 goto err_register_soc_camera_host;
989 }
990 return 0;
991
992err_register_soc_camera_host:
195ebc43 993err_req_irq:
195ebc43
JW		 994err_ioremap:
995 vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
996err_alloc_ctx:
997 dma_free_coherent(&pdev->dev,
998 sizeof(struct fbd) * MAX_BUFFER_NUM,
999 isi->p_fb_descriptors,
1000 isi->fb_descriptors_phys);
195ebc43
JW		 1001
1002 return ret;
1003}
1004
1005static struct platform_driver atmel_isi_driver = {
4c62e976 1006 .remove = atmel_isi_remove,
195ebc43
JW		 1007 .driver = {
1008 .name = "atmel_isi",
1009 .owner = THIS_MODULE,
1010 },
1011};
1012
8c31aeca 1013module_platform_driver_probe(atmel_isi_driver, atmel_isi_probe);
195ebc43
JW		 1014
1015MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
1016MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
1017MODULE_LICENSE("GPL");
1018MODULE_SUPPORTED_DEVICE("video");
Linux kernel - Deliverables
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