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2066930d BS |
1 | /* |
2 | * V4L2 Driver for i.MX27/i.MX25 camera host | |
3 | * | |
4 | * Copyright (C) 2008, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography | |
c6a41e32 | 6 | * Copyright (C) 2012, Javier Martin, Vista Silicon S.L. |
2066930d BS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/fs.h> | |
750a6dff | 22 | #include <linux/gcd.h> |
2066930d BS |
23 | #include <linux/interrupt.h> |
24 | #include <linux/kernel.h> | |
67e86524 | 25 | #include <linux/math64.h> |
2066930d BS |
26 | #include <linux/mm.h> |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/time.h> | |
2066930d BS |
29 | #include <linux/device.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/mutex.h> | |
32 | #include <linux/clk.h> | |
33 | ||
34 | #include <media/v4l2-common.h> | |
35 | #include <media/v4l2-dev.h> | |
c6a41e32 JM |
36 | #include <media/videobuf2-core.h> |
37 | #include <media/videobuf2-dma-contig.h> | |
2066930d BS |
38 | #include <media/soc_camera.h> |
39 | #include <media/soc_mediabus.h> | |
40 | ||
41 | #include <linux/videodev2.h> | |
42 | ||
82906b13 | 43 | #include <linux/platform_data/camera-mx2.h> |
2066930d BS |
44 | #include <mach/hardware.h> |
45 | ||
46 | #include <asm/dma.h> | |
47 | ||
48 | #define MX2_CAM_DRV_NAME "mx2-camera" | |
64dc3c1a | 49 | #define MX2_CAM_VERSION "0.0.6" |
2066930d BS |
50 | #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" |
51 | ||
52 | /* reset values */ | |
53 | #define CSICR1_RESET_VAL 0x40000800 | |
54 | #define CSICR2_RESET_VAL 0x0 | |
55 | #define CSICR3_RESET_VAL 0x0 | |
56 | ||
57 | /* csi control reg 1 */ | |
58 | #define CSICR1_SWAP16_EN (1 << 31) | |
59 | #define CSICR1_EXT_VSYNC (1 << 30) | |
60 | #define CSICR1_EOF_INTEN (1 << 29) | |
61 | #define CSICR1_PRP_IF_EN (1 << 28) | |
62 | #define CSICR1_CCIR_MODE (1 << 27) | |
63 | #define CSICR1_COF_INTEN (1 << 26) | |
64 | #define CSICR1_SF_OR_INTEN (1 << 25) | |
65 | #define CSICR1_RF_OR_INTEN (1 << 24) | |
66 | #define CSICR1_STATFF_LEVEL (3 << 22) | |
67 | #define CSICR1_STATFF_INTEN (1 << 21) | |
68 | #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ | |
69 | #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ | |
70 | #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ | |
71 | #define CSICR1_RXFF_INTEN (1 << 18) | |
72 | #define CSICR1_SOF_POL (1 << 17) | |
73 | #define CSICR1_SOF_INTEN (1 << 16) | |
74 | #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) | |
75 | #define CSICR1_HSYNC_POL (1 << 11) | |
76 | #define CSICR1_CCIR_EN (1 << 10) | |
77 | #define CSICR1_MCLKEN (1 << 9) | |
78 | #define CSICR1_FCC (1 << 8) | |
79 | #define CSICR1_PACK_DIR (1 << 7) | |
80 | #define CSICR1_CLR_STATFIFO (1 << 6) | |
81 | #define CSICR1_CLR_RXFIFO (1 << 5) | |
82 | #define CSICR1_GCLK_MODE (1 << 4) | |
83 | #define CSICR1_INV_DATA (1 << 3) | |
84 | #define CSICR1_INV_PCLK (1 << 2) | |
85 | #define CSICR1_REDGE (1 << 1) | |
8a76e538 | 86 | #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN) |
2066930d BS |
87 | |
88 | #define SHIFT_STATFF_LEVEL 22 | |
89 | #define SHIFT_RXFF_LEVEL 19 | |
90 | #define SHIFT_MCLKDIV 12 | |
91 | ||
92 | /* control reg 3 */ | |
93 | #define CSICR3_FRMCNT (0xFFFF << 16) | |
94 | #define CSICR3_FRMCNT_RST (1 << 15) | |
95 | #define CSICR3_DMA_REFLASH_RFF (1 << 14) | |
96 | #define CSICR3_DMA_REFLASH_SFF (1 << 13) | |
97 | #define CSICR3_DMA_REQ_EN_RFF (1 << 12) | |
98 | #define CSICR3_DMA_REQ_EN_SFF (1 << 11) | |
99 | #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ | |
100 | #define CSICR3_CSI_SUP (1 << 3) | |
101 | #define CSICR3_ZERO_PACK_EN (1 << 2) | |
102 | #define CSICR3_ECC_INT_EN (1 << 1) | |
103 | #define CSICR3_ECC_AUTO_EN (1 << 0) | |
104 | ||
105 | #define SHIFT_FRMCNT 16 | |
106 | ||
107 | /* csi status reg */ | |
108 | #define CSISR_SFF_OR_INT (1 << 25) | |
109 | #define CSISR_RFF_OR_INT (1 << 24) | |
110 | #define CSISR_STATFF_INT (1 << 21) | |
111 | #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ | |
112 | #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ | |
113 | #define CSISR_RXFF_INT (1 << 18) | |
114 | #define CSISR_EOF_INT (1 << 17) | |
115 | #define CSISR_SOF_INT (1 << 16) | |
116 | #define CSISR_F2_INT (1 << 15) | |
117 | #define CSISR_F1_INT (1 << 14) | |
118 | #define CSISR_COF_INT (1 << 13) | |
119 | #define CSISR_ECC_INT (1 << 1) | |
120 | #define CSISR_DRDY (1 << 0) | |
121 | ||
122 | #define CSICR1 0x00 | |
123 | #define CSICR2 0x04 | |
124 | #define CSISR (cpu_is_mx27() ? 0x08 : 0x18) | |
125 | #define CSISTATFIFO 0x0c | |
126 | #define CSIRFIFO 0x10 | |
127 | #define CSIRXCNT 0x14 | |
128 | #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) | |
129 | #define CSIDMASA_STATFIFO 0x20 | |
130 | #define CSIDMATA_STATFIFO 0x24 | |
131 | #define CSIDMASA_FB1 0x28 | |
132 | #define CSIDMASA_FB2 0x2c | |
133 | #define CSIFBUF_PARA 0x30 | |
134 | #define CSIIMAG_PARA 0x34 | |
135 | ||
136 | /* EMMA PrP */ | |
137 | #define PRP_CNTL 0x00 | |
138 | #define PRP_INTR_CNTL 0x04 | |
139 | #define PRP_INTRSTATUS 0x08 | |
140 | #define PRP_SOURCE_Y_PTR 0x0c | |
141 | #define PRP_SOURCE_CB_PTR 0x10 | |
142 | #define PRP_SOURCE_CR_PTR 0x14 | |
143 | #define PRP_DEST_RGB1_PTR 0x18 | |
144 | #define PRP_DEST_RGB2_PTR 0x1c | |
145 | #define PRP_DEST_Y_PTR 0x20 | |
146 | #define PRP_DEST_CB_PTR 0x24 | |
147 | #define PRP_DEST_CR_PTR 0x28 | |
148 | #define PRP_SRC_FRAME_SIZE 0x2c | |
149 | #define PRP_DEST_CH1_LINE_STRIDE 0x30 | |
150 | #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 | |
151 | #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 | |
152 | #define PRP_CH1_OUT_IMAGE_SIZE 0x3c | |
153 | #define PRP_CH2_OUT_IMAGE_SIZE 0x40 | |
154 | #define PRP_SRC_LINE_STRIDE 0x44 | |
155 | #define PRP_CSC_COEF_012 0x48 | |
156 | #define PRP_CSC_COEF_345 0x4c | |
157 | #define PRP_CSC_COEF_678 0x50 | |
158 | #define PRP_CH1_RZ_HORI_COEF1 0x54 | |
159 | #define PRP_CH1_RZ_HORI_COEF2 0x58 | |
160 | #define PRP_CH1_RZ_HORI_VALID 0x5c | |
161 | #define PRP_CH1_RZ_VERT_COEF1 0x60 | |
162 | #define PRP_CH1_RZ_VERT_COEF2 0x64 | |
163 | #define PRP_CH1_RZ_VERT_VALID 0x68 | |
164 | #define PRP_CH2_RZ_HORI_COEF1 0x6c | |
165 | #define PRP_CH2_RZ_HORI_COEF2 0x70 | |
166 | #define PRP_CH2_RZ_HORI_VALID 0x74 | |
167 | #define PRP_CH2_RZ_VERT_COEF1 0x78 | |
168 | #define PRP_CH2_RZ_VERT_COEF2 0x7c | |
169 | #define PRP_CH2_RZ_VERT_VALID 0x80 | |
170 | ||
171 | #define PRP_CNTL_CH1EN (1 << 0) | |
172 | #define PRP_CNTL_CH2EN (1 << 1) | |
173 | #define PRP_CNTL_CSIEN (1 << 2) | |
174 | #define PRP_CNTL_DATA_IN_YUV420 (0 << 3) | |
175 | #define PRP_CNTL_DATA_IN_YUV422 (1 << 3) | |
176 | #define PRP_CNTL_DATA_IN_RGB16 (2 << 3) | |
177 | #define PRP_CNTL_DATA_IN_RGB32 (3 << 3) | |
178 | #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) | |
179 | #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) | |
180 | #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) | |
181 | #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) | |
182 | #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) | |
183 | #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) | |
184 | #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) | |
185 | #define PRP_CNTL_CH1_LEN (1 << 9) | |
186 | #define PRP_CNTL_CH2_LEN (1 << 10) | |
187 | #define PRP_CNTL_SKIP_FRAME (1 << 11) | |
188 | #define PRP_CNTL_SWRST (1 << 12) | |
189 | #define PRP_CNTL_CLKEN (1 << 13) | |
190 | #define PRP_CNTL_WEN (1 << 14) | |
191 | #define PRP_CNTL_CH1BYP (1 << 15) | |
192 | #define PRP_CNTL_IN_TSKIP(x) ((x) << 16) | |
193 | #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) | |
194 | #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) | |
195 | #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) | |
196 | #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) | |
197 | #define PRP_CNTL_CH2B1EN (1 << 29) | |
198 | #define PRP_CNTL_CH2B2EN (1 << 30) | |
199 | #define PRP_CNTL_CH2FEN (1 << 31) | |
200 | ||
201 | /* IRQ Enable and status register */ | |
202 | #define PRP_INTR_RDERR (1 << 0) | |
203 | #define PRP_INTR_CH1WERR (1 << 1) | |
204 | #define PRP_INTR_CH2WERR (1 << 2) | |
205 | #define PRP_INTR_CH1FC (1 << 3) | |
206 | #define PRP_INTR_CH2FC (1 << 5) | |
207 | #define PRP_INTR_LBOVF (1 << 7) | |
208 | #define PRP_INTR_CH2OVF (1 << 8) | |
209 | ||
750a6dff JM |
210 | /* Resizing registers */ |
211 | #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24) | |
212 | #define PRP_RZ_VALID_BILINEAR (1 << 31) | |
213 | ||
2066930d BS |
214 | #define MAX_VIDEO_MEM 16 |
215 | ||
750a6dff JM |
216 | #define RESIZE_NUM_MIN 1 |
217 | #define RESIZE_NUM_MAX 20 | |
218 | #define BC_COEF 3 | |
219 | #define SZ_COEF (1 << BC_COEF) | |
220 | ||
221 | #define RESIZE_DIR_H 0 | |
222 | #define RESIZE_DIR_V 1 | |
223 | ||
224 | #define RESIZE_ALGO_BILINEAR 0 | |
225 | #define RESIZE_ALGO_AVERAGING 1 | |
226 | ||
f410991d JM |
227 | struct mx2_prp_cfg { |
228 | int channel; | |
229 | u32 in_fmt; | |
230 | u32 out_fmt; | |
231 | u32 src_pixel; | |
232 | u32 ch1_pixel; | |
233 | u32 irq_flags; | |
8a76e538 | 234 | u32 csicr1; |
f410991d JM |
235 | }; |
236 | ||
750a6dff JM |
237 | /* prp resizing parameters */ |
238 | struct emma_prp_resize { | |
239 | int algo; /* type of algorithm used */ | |
240 | int len; /* number of coefficients */ | |
241 | unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */ | |
242 | }; | |
243 | ||
f410991d JM |
244 | /* prp configuration for a client-host fmt pair */ |
245 | struct mx2_fmt_cfg { | |
246 | enum v4l2_mbus_pixelcode in_fmt; | |
247 | u32 out_fmt; | |
248 | struct mx2_prp_cfg cfg; | |
249 | }; | |
250 | ||
c6a41e32 JM |
251 | enum mx2_buffer_state { |
252 | MX2_STATE_QUEUED, | |
253 | MX2_STATE_ACTIVE, | |
254 | MX2_STATE_DONE, | |
255 | }; | |
256 | ||
560fab62 JM |
257 | struct mx2_buf_internal { |
258 | struct list_head queue; | |
259 | int bufnum; | |
260 | bool discard; | |
261 | }; | |
262 | ||
c6a41e32 JM |
263 | /* buffer for one video frame */ |
264 | struct mx2_buffer { | |
265 | /* common v4l buffer stuff -- must be first */ | |
266 | struct vb2_buffer vb; | |
c6a41e32 | 267 | enum mx2_buffer_state state; |
560fab62 | 268 | struct mx2_buf_internal internal; |
c6a41e32 JM |
269 | }; |
270 | ||
2066930d BS |
271 | struct mx2_camera_dev { |
272 | struct device *dev; | |
273 | struct soc_camera_host soc_host; | |
274 | struct soc_camera_device *icd; | |
eb68faaf | 275 | struct clk *clk_csi, *clk_emma_ahb, *clk_emma_ipg; |
2066930d | 276 | |
2066930d | 277 | void __iomem *base_csi, *base_emma; |
2066930d BS |
278 | |
279 | struct mx2_camera_platform_data *pdata; | |
2066930d BS |
280 | unsigned long platform_flags; |
281 | ||
282 | struct list_head capture; | |
283 | struct list_head active_bufs; | |
cdc9d6f1 | 284 | struct list_head discard; |
2066930d BS |
285 | |
286 | spinlock_t lock; | |
287 | ||
288 | int dma; | |
289 | struct mx2_buffer *active; | |
290 | struct mx2_buffer *fb1_active; | |
291 | struct mx2_buffer *fb2_active; | |
292 | ||
2066930d BS |
293 | u32 csicr1; |
294 | ||
560fab62 | 295 | struct mx2_buf_internal buf_discard[2]; |
79d3c2c2 | 296 | void *discard_buffer; |
2066930d BS |
297 | dma_addr_t discard_buffer_dma; |
298 | size_t discard_size; | |
f410991d | 299 | struct mx2_fmt_cfg *emma_prp; |
750a6dff JM |
300 | struct emma_prp_resize resizing[2]; |
301 | unsigned int s_width, s_height; | |
ccd1a499 | 302 | u32 frame_count; |
c6a41e32 | 303 | struct vb2_alloc_ctx *alloc_ctx; |
2066930d BS |
304 | }; |
305 | ||
560fab62 JM |
306 | static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf) |
307 | { | |
308 | return container_of(int_buf, struct mx2_buffer, internal); | |
309 | } | |
310 | ||
f410991d JM |
311 | static struct mx2_fmt_cfg mx27_emma_prp_table[] = { |
312 | /* | |
313 | * This is a generic configuration which is valid for most | |
314 | * prp input-output format combinations. | |
315 | * We set the incomming and outgoing pixelformat to a | |
316 | * 16 Bit wide format and adjust the bytesperline | |
317 | * accordingly. With this configuration the inputdata | |
318 | * will not be changed by the emma and could be any type | |
319 | * of 16 Bit Pixelformat. | |
320 | */ | |
321 | { | |
322 | .in_fmt = 0, | |
323 | .out_fmt = 0, | |
324 | .cfg = { | |
325 | .channel = 1, | |
326 | .in_fmt = PRP_CNTL_DATA_IN_RGB16, | |
327 | .out_fmt = PRP_CNTL_CH1_OUT_RGB16, | |
328 | .src_pixel = 0x2ca00565, /* RGB565 */ | |
329 | .ch1_pixel = 0x2ca00565, /* RGB565 */ | |
330 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | | |
331 | PRP_INTR_CH1FC | PRP_INTR_LBOVF, | |
8a76e538 | 332 | .csicr1 = 0, |
f410991d JM |
333 | } |
334 | }, | |
1cb7cf28 JM |
335 | { |
336 | .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8, | |
337 | .out_fmt = V4L2_PIX_FMT_YUYV, | |
338 | .cfg = { | |
339 | .channel = 1, | |
340 | .in_fmt = PRP_CNTL_DATA_IN_YUV422, | |
341 | .out_fmt = PRP_CNTL_CH1_OUT_YUV422, | |
342 | .src_pixel = 0x22000888, /* YUV422 (YUYV) */ | |
343 | .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */ | |
344 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | | |
345 | PRP_INTR_CH1FC | PRP_INTR_LBOVF, | |
346 | .csicr1 = CSICR1_SWAP16_EN, | |
347 | } | |
348 | }, | |
349 | { | |
350 | .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8, | |
351 | .out_fmt = V4L2_PIX_FMT_YUYV, | |
352 | .cfg = { | |
353 | .channel = 1, | |
354 | .in_fmt = PRP_CNTL_DATA_IN_YUV422, | |
355 | .out_fmt = PRP_CNTL_CH1_OUT_YUV422, | |
356 | .src_pixel = 0x22000888, /* YUV422 (YUYV) */ | |
357 | .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */ | |
358 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | | |
359 | PRP_INTR_CH1FC | PRP_INTR_LBOVF, | |
360 | .csicr1 = CSICR1_PACK_DIR, | |
361 | } | |
362 | }, | |
f410991d JM |
363 | { |
364 | .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8, | |
365 | .out_fmt = V4L2_PIX_FMT_YUV420, | |
366 | .cfg = { | |
367 | .channel = 2, | |
368 | .in_fmt = PRP_CNTL_DATA_IN_YUV422, | |
369 | .out_fmt = PRP_CNTL_CH2_OUT_YUV420, | |
370 | .src_pixel = 0x22000888, /* YUV422 (YUYV) */ | |
371 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR | | |
372 | PRP_INTR_CH2FC | PRP_INTR_LBOVF | | |
373 | PRP_INTR_CH2OVF, | |
8a76e538 JM |
374 | .csicr1 = CSICR1_PACK_DIR, |
375 | } | |
376 | }, | |
377 | { | |
378 | .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8, | |
379 | .out_fmt = V4L2_PIX_FMT_YUV420, | |
380 | .cfg = { | |
381 | .channel = 2, | |
382 | .in_fmt = PRP_CNTL_DATA_IN_YUV422, | |
383 | .out_fmt = PRP_CNTL_CH2_OUT_YUV420, | |
384 | .src_pixel = 0x22000888, /* YUV422 (YUYV) */ | |
385 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR | | |
386 | PRP_INTR_CH2FC | PRP_INTR_LBOVF | | |
387 | PRP_INTR_CH2OVF, | |
388 | .csicr1 = CSICR1_SWAP16_EN, | |
f410991d JM |
389 | } |
390 | }, | |
391 | }; | |
392 | ||
393 | static struct mx2_fmt_cfg *mx27_emma_prp_get_format( | |
394 | enum v4l2_mbus_pixelcode in_fmt, | |
395 | u32 out_fmt) | |
396 | { | |
397 | int i; | |
398 | ||
399 | for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++) | |
400 | if ((mx27_emma_prp_table[i].in_fmt == in_fmt) && | |
401 | (mx27_emma_prp_table[i].out_fmt == out_fmt)) { | |
402 | return &mx27_emma_prp_table[i]; | |
403 | } | |
404 | /* If no match return the most generic configuration */ | |
405 | return &mx27_emma_prp_table[0]; | |
406 | }; | |
407 | ||
cdc9d6f1 JM |
408 | static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev, |
409 | unsigned long phys, int bufnum) | |
410 | { | |
411 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
412 | ||
413 | if (prp->cfg.channel == 1) { | |
414 | writel(phys, pcdev->base_emma + | |
415 | PRP_DEST_RGB1_PTR + 4 * bufnum); | |
416 | } else { | |
417 | writel(phys, pcdev->base_emma + | |
418 | PRP_DEST_Y_PTR - 0x14 * bufnum); | |
419 | if (prp->out_fmt == V4L2_PIX_FMT_YUV420) { | |
420 | u32 imgsize = pcdev->icd->user_height * | |
421 | pcdev->icd->user_width; | |
422 | ||
423 | writel(phys + imgsize, pcdev->base_emma + | |
424 | PRP_DEST_CB_PTR - 0x14 * bufnum); | |
425 | writel(phys + ((5 * imgsize) / 4), pcdev->base_emma + | |
426 | PRP_DEST_CR_PTR - 0x14 * bufnum); | |
427 | } | |
428 | } | |
429 | } | |
430 | ||
2066930d BS |
431 | static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) |
432 | { | |
433 | unsigned long flags; | |
434 | ||
561d5d78 | 435 | clk_disable_unprepare(pcdev->clk_csi); |
2066930d | 436 | writel(0, pcdev->base_csi + CSICR1); |
2c9ba37d | 437 | if (cpu_is_mx27()) { |
2066930d BS |
438 | writel(0, pcdev->base_emma + PRP_CNTL); |
439 | } else if (cpu_is_mx25()) { | |
440 | spin_lock_irqsave(&pcdev->lock, flags); | |
441 | pcdev->fb1_active = NULL; | |
442 | pcdev->fb2_active = NULL; | |
443 | writel(0, pcdev->base_csi + CSIDMASA_FB1); | |
444 | writel(0, pcdev->base_csi + CSIDMASA_FB2); | |
445 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
446 | } | |
447 | } | |
448 | ||
449 | /* | |
450 | * The following two functions absolutely depend on the fact, that | |
451 | * there can be only one camera on mx2 camera sensor interface | |
452 | */ | |
453 | static int mx2_camera_add_device(struct soc_camera_device *icd) | |
454 | { | |
7dfff953 | 455 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
456 | struct mx2_camera_dev *pcdev = ici->priv; |
457 | int ret; | |
458 | u32 csicr1; | |
459 | ||
460 | if (pcdev->icd) | |
461 | return -EBUSY; | |
462 | ||
561d5d78 | 463 | ret = clk_prepare_enable(pcdev->clk_csi); |
2066930d BS |
464 | if (ret < 0) |
465 | return ret; | |
466 | ||
467 | csicr1 = CSICR1_MCLKEN; | |
468 | ||
4df6e868 | 469 | if (cpu_is_mx27()) |
2066930d BS |
470 | csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | |
471 | CSICR1_RXFF_LEVEL(0); | |
2066930d BS |
472 | |
473 | pcdev->csicr1 = csicr1; | |
474 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
475 | ||
476 | pcdev->icd = icd; | |
cdc9d6f1 | 477 | pcdev->frame_count = 0; |
2066930d | 478 | |
7dfff953 | 479 | dev_info(icd->parent, "Camera driver attached to camera %d\n", |
2066930d BS |
480 | icd->devnum); |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static void mx2_camera_remove_device(struct soc_camera_device *icd) | |
486 | { | |
7dfff953 | 487 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
488 | struct mx2_camera_dev *pcdev = ici->priv; |
489 | ||
490 | BUG_ON(icd != pcdev->icd); | |
491 | ||
7dfff953 | 492 | dev_info(icd->parent, "Camera driver detached from camera %d\n", |
2066930d BS |
493 | icd->devnum); |
494 | ||
495 | mx2_camera_deactivate(pcdev); | |
496 | ||
2066930d BS |
497 | pcdev->icd = NULL; |
498 | } | |
499 | ||
2066930d BS |
500 | static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, |
501 | int state) | |
502 | { | |
c6a41e32 | 503 | struct vb2_buffer *vb; |
2066930d BS |
504 | struct mx2_buffer *buf; |
505 | struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : | |
506 | &pcdev->fb2_active; | |
507 | u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; | |
508 | unsigned long flags; | |
509 | ||
510 | spin_lock_irqsave(&pcdev->lock, flags); | |
511 | ||
5384a12b BS |
512 | if (*fb_active == NULL) |
513 | goto out; | |
514 | ||
2066930d | 515 | vb = &(*fb_active)->vb; |
c6a41e32 JM |
516 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
517 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 518 | |
c6a41e32 JM |
519 | do_gettimeofday(&vb->v4l2_buf.timestamp); |
520 | vb->v4l2_buf.sequence++; | |
521 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
2066930d BS |
522 | |
523 | if (list_empty(&pcdev->capture)) { | |
524 | buf = NULL; | |
525 | writel(0, pcdev->base_csi + fb_reg); | |
526 | } else { | |
a654ba16 | 527 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 | 528 | internal.queue); |
2066930d | 529 | vb = &buf->vb; |
560fab62 | 530 | list_del(&buf->internal.queue); |
c6a41e32 JM |
531 | buf->state = MX2_STATE_ACTIVE; |
532 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), | |
533 | pcdev->base_csi + fb_reg); | |
2066930d BS |
534 | } |
535 | ||
536 | *fb_active = buf; | |
537 | ||
5384a12b | 538 | out: |
2066930d BS |
539 | spin_unlock_irqrestore(&pcdev->lock, flags); |
540 | } | |
541 | ||
542 | static irqreturn_t mx25_camera_irq(int irq_csi, void *data) | |
543 | { | |
544 | struct mx2_camera_dev *pcdev = data; | |
545 | u32 status = readl(pcdev->base_csi + CSISR); | |
546 | ||
547 | if (status & CSISR_DMA_TSF_FB1_INT) | |
c6a41e32 | 548 | mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE); |
2066930d | 549 | else if (status & CSISR_DMA_TSF_FB2_INT) |
c6a41e32 | 550 | mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE); |
2066930d BS |
551 | |
552 | /* FIXME: handle CSISR_RFF_OR_INT */ | |
553 | ||
554 | writel(status, pcdev->base_csi + CSISR); | |
555 | ||
556 | return IRQ_HANDLED; | |
557 | } | |
558 | ||
559 | /* | |
560 | * Videobuf operations | |
561 | */ | |
c6a41e32 JM |
562 | static int mx2_videobuf_setup(struct vb2_queue *vq, |
563 | const struct v4l2_format *fmt, | |
564 | unsigned int *count, unsigned int *num_planes, | |
565 | unsigned int sizes[], void *alloc_ctxs[]) | |
2066930d | 566 | { |
c6a41e32 JM |
567 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
568 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
569 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d | 570 | |
c6a41e32 JM |
571 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]); |
572 | ||
573 | /* TODO: support for VIDIOC_CREATE_BUFS not ready */ | |
574 | if (fmt != NULL) | |
575 | return -ENOTTY; | |
2066930d | 576 | |
c6a41e32 JM |
577 | alloc_ctxs[0] = pcdev->alloc_ctx; |
578 | ||
2b61d46e | 579 | sizes[0] = icd->sizeimage; |
2066930d BS |
580 | |
581 | if (0 == *count) | |
582 | *count = 32; | |
c6a41e32 JM |
583 | if (!*num_planes && |
584 | sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024) | |
585 | *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0]; | |
2066930d | 586 | |
c6a41e32 | 587 | *num_planes = 1; |
2066930d | 588 | |
c6a41e32 | 589 | return 0; |
2066930d BS |
590 | } |
591 | ||
c6a41e32 | 592 | static int mx2_videobuf_prepare(struct vb2_buffer *vb) |
2066930d | 593 | { |
c6a41e32 | 594 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
2066930d BS |
595 | int ret = 0; |
596 | ||
c6a41e32 JM |
597 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
598 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 599 | |
2066930d BS |
600 | #ifdef DEBUG |
601 | /* | |
602 | * This can be useful if you want to see if we actually fill | |
603 | * the buffer with something | |
604 | */ | |
c6a41e32 JM |
605 | memset((void *)vb2_plane_vaddr(vb, 0), |
606 | 0xaa, vb2_get_plane_payload(vb, 0)); | |
2066930d BS |
607 | #endif |
608 | ||
2b61d46e | 609 | vb2_set_plane_payload(vb, 0, icd->sizeimage); |
c6a41e32 JM |
610 | if (vb2_plane_vaddr(vb, 0) && |
611 | vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { | |
2066930d BS |
612 | ret = -EINVAL; |
613 | goto out; | |
614 | } | |
615 | ||
2066930d BS |
616 | return 0; |
617 | ||
2066930d BS |
618 | out: |
619 | return ret; | |
620 | } | |
621 | ||
c6a41e32 | 622 | static void mx2_videobuf_queue(struct vb2_buffer *vb) |
2066930d | 623 | { |
c6a41e32 | 624 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
2066930d | 625 | struct soc_camera_host *ici = |
7dfff953 | 626 | to_soc_camera_host(icd->parent); |
2066930d BS |
627 | struct mx2_camera_dev *pcdev = ici->priv; |
628 | struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); | |
629 | unsigned long flags; | |
630 | ||
c6a41e32 JM |
631 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
632 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d BS |
633 | |
634 | spin_lock_irqsave(&pcdev->lock, flags); | |
635 | ||
c6a41e32 | 636 | buf->state = MX2_STATE_QUEUED; |
560fab62 | 637 | list_add_tail(&buf->internal.queue, &pcdev->capture); |
2066930d | 638 | |
2c9ba37d | 639 | if (cpu_is_mx25()) { |
2066930d BS |
640 | u32 csicr3, dma_inten = 0; |
641 | ||
642 | if (pcdev->fb1_active == NULL) { | |
c6a41e32 | 643 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), |
2066930d BS |
644 | pcdev->base_csi + CSIDMASA_FB1); |
645 | pcdev->fb1_active = buf; | |
646 | dma_inten = CSICR1_FB1_DMA_INTEN; | |
647 | } else if (pcdev->fb2_active == NULL) { | |
c6a41e32 | 648 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), |
2066930d BS |
649 | pcdev->base_csi + CSIDMASA_FB2); |
650 | pcdev->fb2_active = buf; | |
651 | dma_inten = CSICR1_FB2_DMA_INTEN; | |
652 | } | |
653 | ||
654 | if (dma_inten) { | |
560fab62 | 655 | list_del(&buf->internal.queue); |
c6a41e32 | 656 | buf->state = MX2_STATE_ACTIVE; |
2066930d BS |
657 | |
658 | csicr3 = readl(pcdev->base_csi + CSICR3); | |
659 | ||
660 | /* Reflash DMA */ | |
661 | writel(csicr3 | CSICR3_DMA_REFLASH_RFF, | |
662 | pcdev->base_csi + CSICR3); | |
663 | ||
664 | /* clear & enable interrupts */ | |
665 | writel(dma_inten, pcdev->base_csi + CSISR); | |
666 | pcdev->csicr1 |= dma_inten; | |
667 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
668 | ||
669 | /* enable DMA */ | |
670 | csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); | |
671 | writel(csicr3, pcdev->base_csi + CSICR3); | |
672 | } | |
673 | } | |
674 | ||
2066930d BS |
675 | spin_unlock_irqrestore(&pcdev->lock, flags); |
676 | } | |
677 | ||
c6a41e32 | 678 | static void mx2_videobuf_release(struct vb2_buffer *vb) |
2066930d | 679 | { |
c6a41e32 | 680 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 681 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
682 | struct mx2_camera_dev *pcdev = ici->priv; |
683 | struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); | |
684 | unsigned long flags; | |
685 | ||
686 | #ifdef DEBUG | |
c6a41e32 JM |
687 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
688 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 689 | |
c6a41e32 JM |
690 | switch (buf->state) { |
691 | case MX2_STATE_ACTIVE: | |
7dfff953 | 692 | dev_info(icd->parent, "%s (active)\n", __func__); |
2066930d | 693 | break; |
c6a41e32 | 694 | case MX2_STATE_QUEUED: |
7dfff953 | 695 | dev_info(icd->parent, "%s (queued)\n", __func__); |
2066930d | 696 | break; |
2066930d | 697 | default: |
7dfff953 | 698 | dev_info(icd->parent, "%s (unknown) %d\n", __func__, |
c6a41e32 | 699 | buf->state); |
2066930d BS |
700 | break; |
701 | } | |
702 | #endif | |
703 | ||
704 | /* | |
705 | * Terminate only queued but inactive buffers. Active buffers are | |
706 | * released when they become inactive after videobuf_waiton(). | |
707 | * | |
7c6b7319 BS |
708 | * FIXME: implement forced termination of active buffers for mx27 and |
709 | * mx27 eMMA, so that the user won't get stuck in an uninterruptible | |
710 | * state. This requires a specific handling for each of the these DMA | |
711 | * types. | |
2066930d | 712 | */ |
c6a41e32 | 713 | |
2066930d | 714 | spin_lock_irqsave(&pcdev->lock, flags); |
c6a41e32 | 715 | if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) { |
7c6b7319 BS |
716 | if (pcdev->fb1_active == buf) { |
717 | pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; | |
718 | writel(0, pcdev->base_csi + CSIDMASA_FB1); | |
719 | pcdev->fb1_active = NULL; | |
720 | } else if (pcdev->fb2_active == buf) { | |
721 | pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN; | |
722 | writel(0, pcdev->base_csi + CSIDMASA_FB2); | |
723 | pcdev->fb2_active = NULL; | |
724 | } | |
725 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
2066930d BS |
726 | } |
727 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
2066930d BS |
728 | } |
729 | ||
cdc9d6f1 JM |
730 | static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, |
731 | int bytesperline) | |
732 | { | |
733 | struct soc_camera_host *ici = | |
734 | to_soc_camera_host(icd->parent); | |
735 | struct mx2_camera_dev *pcdev = ici->priv; | |
736 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
737 | ||
750a6dff | 738 | writel((pcdev->s_width << 16) | pcdev->s_height, |
cdc9d6f1 JM |
739 | pcdev->base_emma + PRP_SRC_FRAME_SIZE); |
740 | writel(prp->cfg.src_pixel, | |
741 | pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); | |
742 | if (prp->cfg.channel == 1) { | |
743 | writel((icd->user_width << 16) | icd->user_height, | |
744 | pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); | |
745 | writel(bytesperline, | |
746 | pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); | |
747 | writel(prp->cfg.ch1_pixel, | |
748 | pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); | |
749 | } else { /* channel 2 */ | |
750 | writel((icd->user_width << 16) | icd->user_height, | |
751 | pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE); | |
752 | } | |
753 | ||
754 | /* Enable interrupts */ | |
755 | writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL); | |
756 | } | |
757 | ||
750a6dff JM |
758 | static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev) |
759 | { | |
760 | int dir; | |
761 | ||
762 | for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { | |
763 | unsigned char *s = pcdev->resizing[dir].s; | |
764 | int len = pcdev->resizing[dir].len; | |
765 | unsigned int coeff[2] = {0, 0}; | |
766 | unsigned int valid = 0; | |
767 | int i; | |
768 | ||
769 | if (len == 0) | |
770 | continue; | |
771 | ||
772 | for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) { | |
773 | int j; | |
774 | ||
775 | j = i > 9 ? 1 : 0; | |
776 | coeff[j] = (coeff[j] << BC_COEF) | | |
777 | (s[i] & (SZ_COEF - 1)); | |
778 | ||
779 | if (i == 5 || i == 15) | |
780 | coeff[j] <<= 1; | |
781 | ||
782 | valid = (valid << 1) | (s[i] >> BC_COEF); | |
783 | } | |
784 | ||
785 | valid |= PRP_RZ_VALID_TBL_LEN(len); | |
786 | ||
787 | if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR) | |
788 | valid |= PRP_RZ_VALID_BILINEAR; | |
789 | ||
790 | if (pcdev->emma_prp->cfg.channel == 1) { | |
791 | if (dir == RESIZE_DIR_H) { | |
792 | writel(coeff[0], pcdev->base_emma + | |
793 | PRP_CH1_RZ_HORI_COEF1); | |
794 | writel(coeff[1], pcdev->base_emma + | |
795 | PRP_CH1_RZ_HORI_COEF2); | |
796 | writel(valid, pcdev->base_emma + | |
797 | PRP_CH1_RZ_HORI_VALID); | |
798 | } else { | |
799 | writel(coeff[0], pcdev->base_emma + | |
800 | PRP_CH1_RZ_VERT_COEF1); | |
801 | writel(coeff[1], pcdev->base_emma + | |
802 | PRP_CH1_RZ_VERT_COEF2); | |
803 | writel(valid, pcdev->base_emma + | |
804 | PRP_CH1_RZ_VERT_VALID); | |
805 | } | |
806 | } else { | |
807 | if (dir == RESIZE_DIR_H) { | |
808 | writel(coeff[0], pcdev->base_emma + | |
809 | PRP_CH2_RZ_HORI_COEF1); | |
810 | writel(coeff[1], pcdev->base_emma + | |
811 | PRP_CH2_RZ_HORI_COEF2); | |
812 | writel(valid, pcdev->base_emma + | |
813 | PRP_CH2_RZ_HORI_VALID); | |
814 | } else { | |
815 | writel(coeff[0], pcdev->base_emma + | |
816 | PRP_CH2_RZ_VERT_COEF1); | |
817 | writel(coeff[1], pcdev->base_emma + | |
818 | PRP_CH2_RZ_VERT_COEF2); | |
819 | writel(valid, pcdev->base_emma + | |
820 | PRP_CH2_RZ_VERT_VALID); | |
821 | } | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
fb51cbdd JM |
826 | static int mx2_start_streaming(struct vb2_queue *q, unsigned int count) |
827 | { | |
828 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
829 | struct soc_camera_host *ici = | |
830 | to_soc_camera_host(icd->parent); | |
831 | struct mx2_camera_dev *pcdev = ici->priv; | |
832 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
cdc9d6f1 JM |
833 | struct vb2_buffer *vb; |
834 | struct mx2_buffer *buf; | |
835 | unsigned long phys; | |
836 | int bytesperline; | |
fb51cbdd JM |
837 | |
838 | if (cpu_is_mx27()) { | |
839 | unsigned long flags; | |
840 | if (count < 2) | |
841 | return -EINVAL; | |
842 | ||
843 | spin_lock_irqsave(&pcdev->lock, flags); | |
cdc9d6f1 | 844 | |
a654ba16 | 845 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 JM |
846 | internal.queue); |
847 | buf->internal.bufnum = 0; | |
cdc9d6f1 JM |
848 | vb = &buf->vb; |
849 | buf->state = MX2_STATE_ACTIVE; | |
850 | ||
851 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); | |
560fab62 | 852 | mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); |
cdc9d6f1 JM |
853 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); |
854 | ||
a654ba16 | 855 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 JM |
856 | internal.queue); |
857 | buf->internal.bufnum = 1; | |
cdc9d6f1 JM |
858 | vb = &buf->vb; |
859 | buf->state = MX2_STATE_ACTIVE; | |
860 | ||
861 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); | |
560fab62 | 862 | mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); |
cdc9d6f1 JM |
863 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); |
864 | ||
865 | bytesperline = soc_mbus_bytes_per_line(icd->user_width, | |
866 | icd->current_fmt->host_fmt); | |
867 | if (bytesperline < 0) | |
868 | return bytesperline; | |
869 | ||
870 | /* | |
871 | * I didn't manage to properly enable/disable the prp | |
872 | * on a per frame basis during running transfers, | |
873 | * thus we allocate a buffer here and use it to | |
874 | * discard frames when no buffer is available. | |
875 | * Feel free to work on this ;) | |
876 | */ | |
877 | pcdev->discard_size = icd->user_height * bytesperline; | |
878 | pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, | |
879 | pcdev->discard_size, &pcdev->discard_buffer_dma, | |
880 | GFP_KERNEL); | |
881 | if (!pcdev->discard_buffer) | |
882 | return -ENOMEM; | |
883 | ||
884 | pcdev->buf_discard[0].discard = true; | |
885 | list_add_tail(&pcdev->buf_discard[0].queue, | |
886 | &pcdev->discard); | |
887 | ||
888 | pcdev->buf_discard[1].discard = true; | |
889 | list_add_tail(&pcdev->buf_discard[1].queue, | |
890 | &pcdev->discard); | |
891 | ||
750a6dff JM |
892 | mx2_prp_resize_commit(pcdev); |
893 | ||
cdc9d6f1 JM |
894 | mx27_camera_emma_buf_init(icd, bytesperline); |
895 | ||
fb51cbdd JM |
896 | if (prp->cfg.channel == 1) { |
897 | writel(PRP_CNTL_CH1EN | | |
898 | PRP_CNTL_CSIEN | | |
899 | prp->cfg.in_fmt | | |
900 | prp->cfg.out_fmt | | |
901 | PRP_CNTL_CH1_LEN | | |
902 | PRP_CNTL_CH1BYP | | |
903 | PRP_CNTL_CH1_TSKIP(0) | | |
904 | PRP_CNTL_IN_TSKIP(0), | |
905 | pcdev->base_emma + PRP_CNTL); | |
906 | } else { | |
907 | writel(PRP_CNTL_CH2EN | | |
908 | PRP_CNTL_CSIEN | | |
909 | prp->cfg.in_fmt | | |
910 | prp->cfg.out_fmt | | |
911 | PRP_CNTL_CH2_LEN | | |
912 | PRP_CNTL_CH2_TSKIP(0) | | |
913 | PRP_CNTL_IN_TSKIP(0), | |
914 | pcdev->base_emma + PRP_CNTL); | |
915 | } | |
916 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
917 | } | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | static int mx2_stop_streaming(struct vb2_queue *q) | |
923 | { | |
924 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
925 | struct soc_camera_host *ici = | |
926 | to_soc_camera_host(icd->parent); | |
927 | struct mx2_camera_dev *pcdev = ici->priv; | |
928 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
929 | unsigned long flags; | |
cdc9d6f1 | 930 | void *b; |
fb51cbdd JM |
931 | u32 cntl; |
932 | ||
fb51cbdd | 933 | if (cpu_is_mx27()) { |
cdc9d6f1 JM |
934 | spin_lock_irqsave(&pcdev->lock, flags); |
935 | ||
fb51cbdd JM |
936 | cntl = readl(pcdev->base_emma + PRP_CNTL); |
937 | if (prp->cfg.channel == 1) { | |
938 | writel(cntl & ~PRP_CNTL_CH1EN, | |
939 | pcdev->base_emma + PRP_CNTL); | |
940 | } else { | |
941 | writel(cntl & ~PRP_CNTL_CH2EN, | |
942 | pcdev->base_emma + PRP_CNTL); | |
943 | } | |
cdc9d6f1 JM |
944 | INIT_LIST_HEAD(&pcdev->capture); |
945 | INIT_LIST_HEAD(&pcdev->active_bufs); | |
946 | INIT_LIST_HEAD(&pcdev->discard); | |
947 | ||
948 | b = pcdev->discard_buffer; | |
949 | pcdev->discard_buffer = NULL; | |
950 | ||
951 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
952 | ||
953 | dma_free_coherent(ici->v4l2_dev.dev, | |
954 | pcdev->discard_size, b, pcdev->discard_buffer_dma); | |
fb51cbdd | 955 | } |
fb51cbdd JM |
956 | |
957 | return 0; | |
958 | } | |
959 | ||
c6a41e32 | 960 | static struct vb2_ops mx2_videobuf_ops = { |
fb51cbdd JM |
961 | .queue_setup = mx2_videobuf_setup, |
962 | .buf_prepare = mx2_videobuf_prepare, | |
963 | .buf_queue = mx2_videobuf_queue, | |
964 | .buf_cleanup = mx2_videobuf_release, | |
965 | .start_streaming = mx2_start_streaming, | |
966 | .stop_streaming = mx2_stop_streaming, | |
2066930d BS |
967 | }; |
968 | ||
c6a41e32 | 969 | static int mx2_camera_init_videobuf(struct vb2_queue *q, |
2066930d BS |
970 | struct soc_camera_device *icd) |
971 | { | |
c6a41e32 JM |
972 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
973 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
974 | q->drv_priv = icd; | |
975 | q->ops = &mx2_videobuf_ops; | |
976 | q->mem_ops = &vb2_dma_contig_memops; | |
977 | q->buf_struct_size = sizeof(struct mx2_buffer); | |
978 | ||
979 | return vb2_queue_init(q); | |
2066930d BS |
980 | } |
981 | ||
db592a24 GL |
982 | #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \ |
983 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ | |
984 | V4L2_MBUS_VSYNC_ACTIVE_LOW | \ | |
985 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | \ | |
986 | V4L2_MBUS_HSYNC_ACTIVE_LOW | \ | |
987 | V4L2_MBUS_PCLK_SAMPLE_RISING | \ | |
988 | V4L2_MBUS_PCLK_SAMPLE_FALLING | \ | |
989 | V4L2_MBUS_DATA_ACTIVE_HIGH | \ | |
990 | V4L2_MBUS_DATA_ACTIVE_LOW) | |
2066930d BS |
991 | |
992 | static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) | |
993 | { | |
994 | u32 cntl; | |
995 | int count = 0; | |
996 | ||
997 | cntl = readl(pcdev->base_emma + PRP_CNTL); | |
998 | writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); | |
999 | while (count++ < 100) { | |
1000 | if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) | |
1001 | return 0; | |
1002 | barrier(); | |
1003 | udelay(1); | |
1004 | } | |
1005 | ||
1006 | return -ETIMEDOUT; | |
1007 | } | |
1008 | ||
8843d119 | 1009 | static int mx2_camera_set_bus_param(struct soc_camera_device *icd) |
2066930d | 1010 | { |
db592a24 GL |
1011 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
1012 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
2066930d | 1013 | struct mx2_camera_dev *pcdev = ici->priv; |
db592a24 GL |
1014 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1015 | unsigned long common_flags; | |
1016 | int ret; | |
2066930d BS |
1017 | int bytesperline; |
1018 | u32 csicr1 = pcdev->csicr1; | |
1019 | ||
db592a24 GL |
1020 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1021 | if (!ret) { | |
1022 | common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS); | |
1023 | if (!common_flags) { | |
1024 | dev_warn(icd->parent, | |
1025 | "Flags incompatible: camera 0x%x, host 0x%x\n", | |
1026 | cfg.flags, MX2_BUS_FLAGS); | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | } else if (ret != -ENOIOCTLCMD) { | |
1030 | return ret; | |
1031 | } else { | |
1032 | common_flags = MX2_BUS_FLAGS; | |
1033 | } | |
2066930d | 1034 | |
db592a24 GL |
1035 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1036 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
2066930d | 1037 | if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) |
db592a24 | 1038 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
2066930d | 1039 | else |
db592a24 | 1040 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
2066930d BS |
1041 | } |
1042 | ||
db592a24 GL |
1043 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1044 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
2066930d | 1045 | if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) |
db592a24 | 1046 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
2066930d | 1047 | else |
db592a24 | 1048 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
2066930d BS |
1049 | } |
1050 | ||
db592a24 GL |
1051 | cfg.flags = common_flags; |
1052 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1053 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1054 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1055 | common_flags, ret); | |
2066930d | 1056 | return ret; |
db592a24 | 1057 | } |
2066930d | 1058 | |
8a76e538 JM |
1059 | csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1; |
1060 | ||
db592a24 | 1061 | if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) |
d86097e1 | 1062 | csicr1 |= CSICR1_REDGE; |
db592a24 | 1063 | if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) |
2066930d | 1064 | csicr1 |= CSICR1_SOF_POL; |
db592a24 | 1065 | if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) |
2066930d | 1066 | csicr1 |= CSICR1_HSYNC_POL; |
2066930d BS |
1067 | if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) |
1068 | csicr1 |= CSICR1_EXT_VSYNC; | |
1069 | if (pcdev->platform_flags & MX2_CAMERA_CCIR) | |
1070 | csicr1 |= CSICR1_CCIR_EN; | |
1071 | if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) | |
1072 | csicr1 |= CSICR1_CCIR_MODE; | |
1073 | if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) | |
1074 | csicr1 |= CSICR1_GCLK_MODE; | |
1075 | if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) | |
1076 | csicr1 |= CSICR1_INV_DATA; | |
2066930d BS |
1077 | |
1078 | pcdev->csicr1 = csicr1; | |
1079 | ||
1080 | bytesperline = soc_mbus_bytes_per_line(icd->user_width, | |
1081 | icd->current_fmt->host_fmt); | |
1082 | if (bytesperline < 0) | |
1083 | return bytesperline; | |
1084 | ||
2c9ba37d | 1085 | if (cpu_is_mx27()) { |
2066930d BS |
1086 | ret = mx27_camera_emma_prp_reset(pcdev); |
1087 | if (ret) | |
1088 | return ret; | |
2066930d BS |
1089 | } else if (cpu_is_mx25()) { |
1090 | writel((bytesperline * icd->user_height) >> 2, | |
1091 | pcdev->base_csi + CSIRXCNT); | |
1092 | writel((bytesperline << 16) | icd->user_height, | |
1093 | pcdev->base_csi + CSIIMAG_PARA); | |
1094 | } | |
1095 | ||
1096 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static int mx2_camera_set_crop(struct soc_camera_device *icd, | |
1102 | struct v4l2_crop *a) | |
1103 | { | |
1104 | struct v4l2_rect *rect = &a->c; | |
1105 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | |
1106 | struct v4l2_mbus_framefmt mf; | |
1107 | int ret; | |
1108 | ||
1109 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); | |
1110 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
1111 | ||
1112 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
1113 | if (ret < 0) | |
1114 | return ret; | |
1115 | ||
1116 | /* The capture device might have changed its output */ | |
1117 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); | |
1118 | if (ret < 0) | |
1119 | return ret; | |
1120 | ||
7dfff953 | 1121 | dev_dbg(icd->parent, "Sensor cropped %dx%d\n", |
2066930d BS |
1122 | mf.width, mf.height); |
1123 | ||
1124 | icd->user_width = mf.width; | |
1125 | icd->user_height = mf.height; | |
1126 | ||
1127 | return ret; | |
1128 | } | |
1129 | ||
f410991d JM |
1130 | static int mx2_camera_get_formats(struct soc_camera_device *icd, |
1131 | unsigned int idx, | |
1132 | struct soc_camera_format_xlate *xlate) | |
1133 | { | |
1134 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | |
1135 | const struct soc_mbus_pixelfmt *fmt; | |
1136 | struct device *dev = icd->parent; | |
1137 | enum v4l2_mbus_pixelcode code; | |
1138 | int ret, formats = 0; | |
1139 | ||
1140 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); | |
1141 | if (ret < 0) | |
1142 | /* no more formats */ | |
1143 | return 0; | |
1144 | ||
1145 | fmt = soc_mbus_get_fmtdesc(code); | |
1146 | if (!fmt) { | |
1147 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code); | |
1148 | return 0; | |
1149 | } | |
1150 | ||
8a76e538 JM |
1151 | if (code == V4L2_MBUS_FMT_YUYV8_2X8 || |
1152 | code == V4L2_MBUS_FMT_UYVY8_2X8) { | |
f410991d JM |
1153 | formats++; |
1154 | if (xlate) { | |
1155 | /* | |
1156 | * CH2 can output YUV420 which is a standard format in | |
1157 | * soc_mediabus.c | |
1158 | */ | |
1159 | xlate->host_fmt = | |
1160 | soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8); | |
1161 | xlate->code = code; | |
1162 | dev_dbg(dev, "Providing host format %s for sensor code %d\n", | |
1163 | xlate->host_fmt->name, code); | |
1164 | xlate++; | |
1165 | } | |
1166 | } | |
1167 | ||
1cb7cf28 JM |
1168 | if (code == V4L2_MBUS_FMT_UYVY8_2X8) { |
1169 | formats++; | |
1170 | if (xlate) { | |
1171 | xlate->host_fmt = | |
1172 | soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8); | |
1173 | xlate->code = code; | |
1174 | dev_dbg(dev, "Providing host format %s for sensor code %d\n", | |
1175 | xlate->host_fmt->name, code); | |
1176 | xlate++; | |
1177 | } | |
1178 | } | |
1179 | ||
f410991d JM |
1180 | /* Generic pass-trough */ |
1181 | formats++; | |
1182 | if (xlate) { | |
1183 | xlate->host_fmt = fmt; | |
1184 | xlate->code = code; | |
1185 | xlate++; | |
1186 | } | |
1187 | return formats; | |
1188 | } | |
1189 | ||
750a6dff JM |
1190 | static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev, |
1191 | struct v4l2_mbus_framefmt *mf_in, | |
1192 | struct v4l2_pix_format *pix_out, bool apply) | |
1193 | { | |
1194 | int num, den; | |
1195 | unsigned long m; | |
1196 | int i, dir; | |
1197 | ||
1198 | for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { | |
1199 | struct emma_prp_resize tmprsz; | |
1200 | unsigned char *s = tmprsz.s; | |
1201 | int len = 0; | |
1202 | int in, out; | |
1203 | ||
1204 | if (dir == RESIZE_DIR_H) { | |
1205 | in = mf_in->width; | |
1206 | out = pix_out->width; | |
1207 | } else { | |
1208 | in = mf_in->height; | |
1209 | out = pix_out->height; | |
1210 | } | |
1211 | ||
1212 | if (in < out) | |
1213 | return -EINVAL; | |
1214 | else if (in == out) | |
1215 | continue; | |
1216 | ||
1217 | /* Calculate ratio */ | |
1218 | m = gcd(in, out); | |
1219 | num = in / m; | |
1220 | den = out / m; | |
1221 | if (num > RESIZE_NUM_MAX) | |
1222 | return -EINVAL; | |
1223 | ||
1224 | if ((num >= 2 * den) && (den == 1) && | |
1225 | (num < 9) && (!(num & 0x01))) { | |
1226 | int sum = 0; | |
1227 | int j; | |
1228 | ||
1229 | /* Average scaling for >= 2:1 ratios */ | |
1230 | /* Support can be added for num >=9 and odd values */ | |
1231 | ||
1232 | tmprsz.algo = RESIZE_ALGO_AVERAGING; | |
1233 | len = num; | |
1234 | ||
1235 | for (i = 0; i < (len / 2); i++) | |
1236 | s[i] = 8; | |
1237 | ||
1238 | do { | |
1239 | for (i = 0; i < (len / 2); i++) { | |
1240 | s[i] = s[i] >> 1; | |
1241 | sum = 0; | |
1242 | for (j = 0; j < (len / 2); j++) | |
1243 | sum += s[j]; | |
1244 | if (sum == 4) | |
1245 | break; | |
1246 | } | |
1247 | } while (sum != 4); | |
1248 | ||
1249 | for (i = (len / 2); i < len; i++) | |
1250 | s[i] = s[len - i - 1]; | |
1251 | ||
1252 | s[len - 1] |= SZ_COEF; | |
1253 | } else { | |
1254 | /* bilinear scaling for < 2:1 ratios */ | |
1255 | int v; /* overflow counter */ | |
1256 | int coeff, nxt; /* table output */ | |
1257 | int in_pos_inc = 2 * den; | |
1258 | int out_pos = num; | |
1259 | int out_pos_inc = 2 * num; | |
1260 | int init_carry = num - den; | |
1261 | int carry = init_carry; | |
1262 | ||
1263 | tmprsz.algo = RESIZE_ALGO_BILINEAR; | |
1264 | v = den + in_pos_inc; | |
1265 | do { | |
1266 | coeff = v - out_pos; | |
1267 | out_pos += out_pos_inc; | |
1268 | carry += out_pos_inc; | |
1269 | for (nxt = 0; v < out_pos; nxt++) { | |
1270 | v += in_pos_inc; | |
1271 | carry -= in_pos_inc; | |
1272 | } | |
1273 | ||
1274 | if (len > RESIZE_NUM_MAX) | |
1275 | return -EINVAL; | |
1276 | ||
1277 | coeff = ((coeff << BC_COEF) + | |
1278 | (in_pos_inc >> 1)) / in_pos_inc; | |
1279 | ||
1280 | if (coeff >= (SZ_COEF - 1)) | |
1281 | coeff--; | |
1282 | ||
1283 | coeff |= SZ_COEF; | |
1284 | s[len] = (unsigned char)coeff; | |
1285 | len++; | |
1286 | ||
1287 | for (i = 1; i < nxt; i++) { | |
1288 | if (len >= RESIZE_NUM_MAX) | |
1289 | return -EINVAL; | |
1290 | s[len] = 0; | |
1291 | len++; | |
1292 | } | |
1293 | } while (carry != init_carry); | |
1294 | } | |
1295 | tmprsz.len = len; | |
1296 | if (dir == RESIZE_DIR_H) | |
1297 | mf_in->width = pix_out->width; | |
1298 | else | |
1299 | mf_in->height = pix_out->height; | |
1300 | ||
1301 | if (apply) | |
1302 | memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz)); | |
1303 | } | |
1304 | return 0; | |
1305 | } | |
1306 | ||
2066930d BS |
1307 | static int mx2_camera_set_fmt(struct soc_camera_device *icd, |
1308 | struct v4l2_format *f) | |
1309 | { | |
f410991d JM |
1310 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
1311 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d BS |
1312 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
1313 | const struct soc_camera_format_xlate *xlate; | |
1314 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1315 | struct v4l2_mbus_framefmt mf; | |
1316 | int ret; | |
1317 | ||
750a6dff JM |
1318 | dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", |
1319 | __func__, pix->width, pix->height); | |
1320 | ||
2066930d BS |
1321 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1322 | if (!xlate) { | |
7dfff953 | 1323 | dev_warn(icd->parent, "Format %x not found\n", |
2066930d BS |
1324 | pix->pixelformat); |
1325 | return -EINVAL; | |
1326 | } | |
1327 | ||
2066930d BS |
1328 | mf.width = pix->width; |
1329 | mf.height = pix->height; | |
1330 | mf.field = pix->field; | |
1331 | mf.colorspace = pix->colorspace; | |
1332 | mf.code = xlate->code; | |
1333 | ||
1334 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
1335 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1336 | return ret; | |
1337 | ||
750a6dff JM |
1338 | /* Store width and height returned by the sensor for resizing */ |
1339 | pcdev->s_width = mf.width; | |
1340 | pcdev->s_height = mf.height; | |
1341 | dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", | |
1342 | __func__, pcdev->s_width, pcdev->s_height); | |
1343 | ||
1344 | pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, | |
1345 | xlate->host_fmt->fourcc); | |
1346 | ||
1347 | memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); | |
1348 | if ((mf.width != pix->width || mf.height != pix->height) && | |
1349 | pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { | |
1350 | if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0) | |
1351 | dev_dbg(icd->parent, "%s: can't resize\n", __func__); | |
1352 | } | |
1353 | ||
2066930d BS |
1354 | if (mf.code != xlate->code) |
1355 | return -EINVAL; | |
1356 | ||
1357 | pix->width = mf.width; | |
1358 | pix->height = mf.height; | |
1359 | pix->field = mf.field; | |
1360 | pix->colorspace = mf.colorspace; | |
1361 | icd->current_fmt = xlate; | |
1362 | ||
750a6dff JM |
1363 | dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", |
1364 | __func__, pix->width, pix->height); | |
f410991d | 1365 | |
2066930d BS |
1366 | return 0; |
1367 | } | |
1368 | ||
1369 | static int mx2_camera_try_fmt(struct soc_camera_device *icd, | |
1370 | struct v4l2_format *f) | |
1371 | { | |
2066930d BS |
1372 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
1373 | const struct soc_camera_format_xlate *xlate; | |
1374 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1375 | struct v4l2_mbus_framefmt mf; | |
1376 | __u32 pixfmt = pix->pixelformat; | |
750a6dff JM |
1377 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
1378 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d BS |
1379 | unsigned int width_limit; |
1380 | int ret; | |
1381 | ||
750a6dff JM |
1382 | dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", |
1383 | __func__, pix->width, pix->height); | |
1384 | ||
2066930d BS |
1385 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1386 | if (pixfmt && !xlate) { | |
7dfff953 | 1387 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
2066930d BS |
1388 | return -EINVAL; |
1389 | } | |
1390 | ||
1391 | /* FIXME: implement MX27 limits */ | |
1392 | ||
2066930d BS |
1393 | /* limit to MX25 hardware capabilities */ |
1394 | if (cpu_is_mx25()) { | |
1395 | if (xlate->host_fmt->bits_per_sample <= 8) | |
1396 | width_limit = 0xffff * 4; | |
1397 | else | |
1398 | width_limit = 0xffff * 2; | |
1399 | /* CSIIMAG_PARA limit */ | |
1400 | if (pix->width > width_limit) | |
1401 | pix->width = width_limit; | |
1402 | if (pix->height > 0xffff) | |
1403 | pix->height = 0xffff; | |
1404 | ||
1405 | pix->bytesperline = soc_mbus_bytes_per_line(pix->width, | |
1406 | xlate->host_fmt); | |
1407 | if (pix->bytesperline < 0) | |
1408 | return pix->bytesperline; | |
b0a461ff LP |
1409 | pix->sizeimage = soc_mbus_image_size(xlate->host_fmt, |
1410 | pix->bytesperline, pix->height); | |
28281a71 GL |
1411 | /* Check against the CSIRXCNT limit */ |
1412 | if (pix->sizeimage > 4 * 0x3ffff) { | |
1413 | /* Adjust geometry, preserve aspect ratio */ | |
67e86524 GL |
1414 | unsigned int new_height = int_sqrt(div_u64(0x3ffffULL * |
1415 | 4 * pix->height, pix->bytesperline)); | |
28281a71 GL |
1416 | pix->width = new_height * pix->width / pix->height; |
1417 | pix->height = new_height; | |
1418 | pix->bytesperline = soc_mbus_bytes_per_line(pix->width, | |
1419 | xlate->host_fmt); | |
1420 | BUG_ON(pix->bytesperline < 0); | |
b0a461ff LP |
1421 | pix->sizeimage = soc_mbus_image_size(xlate->host_fmt, |
1422 | pix->bytesperline, pix->height); | |
2066930d BS |
1423 | } |
1424 | } | |
1425 | ||
1426 | /* limit to sensor capabilities */ | |
1427 | mf.width = pix->width; | |
1428 | mf.height = pix->height; | |
1429 | mf.field = pix->field; | |
1430 | mf.colorspace = pix->colorspace; | |
1431 | mf.code = xlate->code; | |
1432 | ||
1433 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); | |
1434 | if (ret < 0) | |
1435 | return ret; | |
1436 | ||
750a6dff JM |
1437 | dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", |
1438 | __func__, pcdev->s_width, pcdev->s_height); | |
1439 | ||
1440 | /* If the sensor does not support image size try PrP resizing */ | |
1441 | pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, | |
1442 | xlate->host_fmt->fourcc); | |
1443 | ||
1444 | memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); | |
1445 | if ((mf.width != pix->width || mf.height != pix->height) && | |
1446 | pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { | |
1447 | if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0) | |
1448 | dev_dbg(icd->parent, "%s: can't resize\n", __func__); | |
1449 | } | |
1450 | ||
2066930d BS |
1451 | if (mf.field == V4L2_FIELD_ANY) |
1452 | mf.field = V4L2_FIELD_NONE; | |
f410991d JM |
1453 | /* |
1454 | * Driver supports interlaced images provided they have | |
1455 | * both fields so that they can be processed as if they | |
1456 | * were progressive. | |
1457 | */ | |
1458 | if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) { | |
7dfff953 | 1459 | dev_err(icd->parent, "Field type %d unsupported.\n", |
2066930d BS |
1460 | mf.field); |
1461 | return -EINVAL; | |
1462 | } | |
1463 | ||
1464 | pix->width = mf.width; | |
1465 | pix->height = mf.height; | |
1466 | pix->field = mf.field; | |
1467 | pix->colorspace = mf.colorspace; | |
1468 | ||
750a6dff JM |
1469 | dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", |
1470 | __func__, pix->width, pix->height); | |
1471 | ||
2066930d BS |
1472 | return 0; |
1473 | } | |
1474 | ||
1475 | static int mx2_camera_querycap(struct soc_camera_host *ici, | |
1476 | struct v4l2_capability *cap) | |
1477 | { | |
1478 | /* cap->name is set by the friendly caller:-> */ | |
1479 | strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); | |
2066930d BS |
1480 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
2066930d BS |
1485 | static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) |
1486 | { | |
6b101926 | 1487 | struct soc_camera_device *icd = file->private_data; |
2066930d | 1488 | |
c6a41e32 | 1489 | return vb2_poll(&icd->vb2_vidq, file, pt); |
2066930d BS |
1490 | } |
1491 | ||
1492 | static struct soc_camera_host_ops mx2_soc_camera_host_ops = { | |
1493 | .owner = THIS_MODULE, | |
1494 | .add = mx2_camera_add_device, | |
1495 | .remove = mx2_camera_remove_device, | |
1496 | .set_fmt = mx2_camera_set_fmt, | |
1497 | .set_crop = mx2_camera_set_crop, | |
f410991d | 1498 | .get_formats = mx2_camera_get_formats, |
2066930d | 1499 | .try_fmt = mx2_camera_try_fmt, |
c6a41e32 | 1500 | .init_videobuf2 = mx2_camera_init_videobuf, |
2066930d BS |
1501 | .poll = mx2_camera_poll, |
1502 | .querycap = mx2_camera_querycap, | |
1503 | .set_bus_param = mx2_camera_set_bus_param, | |
1504 | }; | |
1505 | ||
1506 | static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, | |
d84279e6 | 1507 | int bufnum, bool err) |
2066930d | 1508 | { |
8886a881 | 1509 | #ifdef DEBUG |
f410991d | 1510 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; |
8886a881 | 1511 | #endif |
560fab62 | 1512 | struct mx2_buf_internal *ibuf; |
2066930d | 1513 | struct mx2_buffer *buf; |
c6a41e32 | 1514 | struct vb2_buffer *vb; |
2066930d BS |
1515 | unsigned long phys; |
1516 | ||
560fab62 JM |
1517 | ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal, |
1518 | queue); | |
2066930d | 1519 | |
560fab62 | 1520 | BUG_ON(ibuf->bufnum != bufnum); |
2066930d | 1521 | |
560fab62 | 1522 | if (ibuf->discard) { |
cdc9d6f1 JM |
1523 | /* |
1524 | * Discard buffer must not be returned to user space. | |
1525 | * Just return it to the discard queue. | |
1526 | */ | |
1527 | list_move_tail(pcdev->active_bufs.next, &pcdev->discard); | |
1528 | } else { | |
560fab62 JM |
1529 | buf = mx2_ibuf_to_buf(ibuf); |
1530 | ||
2066930d BS |
1531 | vb = &buf->vb; |
1532 | #ifdef DEBUG | |
c6a41e32 | 1533 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); |
f410991d JM |
1534 | if (prp->cfg.channel == 1) { |
1535 | if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + | |
1536 | 4 * bufnum) != phys) { | |
8886a881 JM |
1537 | dev_err(pcdev->dev, "%lx != %x\n", phys, |
1538 | readl(pcdev->base_emma + | |
1539 | PRP_DEST_RGB1_PTR + 4 * bufnum)); | |
f410991d JM |
1540 | } |
1541 | } else { | |
1542 | if (readl(pcdev->base_emma + PRP_DEST_Y_PTR - | |
1543 | 0x14 * bufnum) != phys) { | |
8886a881 JM |
1544 | dev_err(pcdev->dev, "%lx != %x\n", phys, |
1545 | readl(pcdev->base_emma + | |
1546 | PRP_DEST_Y_PTR - 0x14 * bufnum)); | |
f410991d | 1547 | } |
2066930d BS |
1548 | } |
1549 | #endif | |
c6a41e32 JM |
1550 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb, |
1551 | vb2_plane_vaddr(vb, 0), | |
1552 | vb2_get_plane_payload(vb, 0)); | |
2066930d | 1553 | |
560fab62 | 1554 | list_del_init(&buf->internal.queue); |
c6a41e32 | 1555 | do_gettimeofday(&vb->v4l2_buf.timestamp); |
c6a41e32 | 1556 | vb->v4l2_buf.sequence = pcdev->frame_count; |
d84279e6 JM |
1557 | if (err) |
1558 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
1559 | else | |
1560 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
2066930d BS |
1561 | } |
1562 | ||
fb51cbdd JM |
1563 | pcdev->frame_count++; |
1564 | ||
2066930d | 1565 | if (list_empty(&pcdev->capture)) { |
cdc9d6f1 JM |
1566 | if (list_empty(&pcdev->discard)) { |
1567 | dev_warn(pcdev->dev, "%s: trying to access empty discard list\n", | |
1568 | __func__); | |
1569 | return; | |
f410991d | 1570 | } |
cdc9d6f1 | 1571 | |
560fab62 JM |
1572 | ibuf = list_first_entry(&pcdev->discard, |
1573 | struct mx2_buf_internal, queue); | |
1574 | ibuf->bufnum = bufnum; | |
cdc9d6f1 JM |
1575 | |
1576 | list_move_tail(pcdev->discard.next, &pcdev->active_bufs); | |
1577 | mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum); | |
2066930d BS |
1578 | return; |
1579 | } | |
1580 | ||
560fab62 JM |
1581 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
1582 | internal.queue); | |
2066930d | 1583 | |
560fab62 | 1584 | buf->internal.bufnum = bufnum; |
2066930d BS |
1585 | |
1586 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); | |
1587 | ||
1588 | vb = &buf->vb; | |
c6a41e32 | 1589 | buf->state = MX2_STATE_ACTIVE; |
2066930d | 1590 | |
c6a41e32 | 1591 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); |
cdc9d6f1 | 1592 | mx27_update_emma_buf(pcdev, phys, bufnum); |
2066930d BS |
1593 | } |
1594 | ||
1595 | static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) | |
1596 | { | |
1597 | struct mx2_camera_dev *pcdev = data; | |
1598 | unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); | |
560fab62 | 1599 | struct mx2_buf_internal *ibuf; |
cdc9d6f1 | 1600 | |
8636ead8 | 1601 | spin_lock(&pcdev->lock); |
cdc9d6f1 JM |
1602 | |
1603 | if (list_empty(&pcdev->active_bufs)) { | |
1604 | dev_warn(pcdev->dev, "%s: called while active list is empty\n", | |
1605 | __func__); | |
665ad8af JM |
1606 | |
1607 | if (!status) { | |
1608 | spin_unlock(&pcdev->lock); | |
1609 | return IRQ_NONE; | |
1610 | } | |
cdc9d6f1 | 1611 | } |
2066930d BS |
1612 | |
1613 | if (status & (1 << 7)) { /* overflow */ | |
d84279e6 | 1614 | u32 cntl = readl(pcdev->base_emma + PRP_CNTL); |
f410991d JM |
1615 | writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), |
1616 | pcdev->base_emma + PRP_CNTL); | |
2066930d | 1617 | writel(cntl, pcdev->base_emma + PRP_CNTL); |
d84279e6 | 1618 | |
560fab62 JM |
1619 | ibuf = list_first_entry(&pcdev->active_bufs, |
1620 | struct mx2_buf_internal, queue); | |
d84279e6 | 1621 | mx27_camera_frame_done_emma(pcdev, |
560fab62 | 1622 | ibuf->bufnum, true); |
d84279e6 JM |
1623 | |
1624 | status &= ~(1 << 7); | |
1625 | } else if (((status & (3 << 5)) == (3 << 5)) || | |
cdc9d6f1 | 1626 | ((status & (3 << 3)) == (3 << 3))) { |
2066930d BS |
1627 | /* |
1628 | * Both buffers have triggered, process the one we're expecting | |
1629 | * to first | |
1630 | */ | |
560fab62 JM |
1631 | ibuf = list_first_entry(&pcdev->active_bufs, |
1632 | struct mx2_buf_internal, queue); | |
1633 | mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false); | |
1634 | status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */ | |
d84279e6 JM |
1635 | } else if ((status & (1 << 6)) || (status & (1 << 4))) { |
1636 | mx27_camera_frame_done_emma(pcdev, 0, false); | |
1637 | } else if ((status & (1 << 5)) || (status & (1 << 3))) { | |
1638 | mx27_camera_frame_done_emma(pcdev, 1, false); | |
2066930d | 1639 | } |
2066930d | 1640 | |
8636ead8 | 1641 | spin_unlock(&pcdev->lock); |
2066930d BS |
1642 | writel(status, pcdev->base_emma + PRP_INTRSTATUS); |
1643 | ||
1644 | return IRQ_HANDLED; | |
1645 | } | |
1646 | ||
8928b6d1 | 1647 | static int __devinit mx27_camera_emma_init(struct platform_device *pdev) |
2066930d | 1648 | { |
8928b6d1 SG |
1649 | struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev); |
1650 | struct resource *res_emma; | |
1651 | int irq_emma; | |
2066930d BS |
1652 | int err = 0; |
1653 | ||
8928b6d1 SG |
1654 | res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1655 | irq_emma = platform_get_irq(pdev, 1); | |
1656 | if (!res_emma || !irq_emma) { | |
1657 | dev_err(pcdev->dev, "no EMMA resources\n"); | |
2066930d BS |
1658 | goto out; |
1659 | } | |
1660 | ||
8928b6d1 | 1661 | pcdev->base_emma = devm_request_and_ioremap(pcdev->dev, res_emma); |
2066930d | 1662 | if (!pcdev->base_emma) { |
8928b6d1 SG |
1663 | err = -EADDRNOTAVAIL; |
1664 | goto out; | |
2066930d BS |
1665 | } |
1666 | ||
8928b6d1 SG |
1667 | err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0, |
1668 | MX2_CAM_DRV_NAME, pcdev); | |
2066930d BS |
1669 | if (err) { |
1670 | dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); | |
8928b6d1 | 1671 | goto out; |
2066930d BS |
1672 | } |
1673 | ||
8928b6d1 | 1674 | pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg"); |
eb68faaf JM |
1675 | if (IS_ERR(pcdev->clk_emma_ipg)) { |
1676 | err = PTR_ERR(pcdev->clk_emma_ipg); | |
8928b6d1 | 1677 | goto out; |
2066930d BS |
1678 | } |
1679 | ||
eb68faaf JM |
1680 | clk_prepare_enable(pcdev->clk_emma_ipg); |
1681 | ||
8928b6d1 | 1682 | pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb"); |
eb68faaf JM |
1683 | if (IS_ERR(pcdev->clk_emma_ahb)) { |
1684 | err = PTR_ERR(pcdev->clk_emma_ahb); | |
8928b6d1 | 1685 | goto exit_clk_emma_ipg; |
eb68faaf JM |
1686 | } |
1687 | ||
1688 | clk_prepare_enable(pcdev->clk_emma_ahb); | |
2066930d BS |
1689 | |
1690 | err = mx27_camera_emma_prp_reset(pcdev); | |
1691 | if (err) | |
8928b6d1 | 1692 | goto exit_clk_emma_ahb; |
2066930d BS |
1693 | |
1694 | return err; | |
1695 | ||
8928b6d1 | 1696 | exit_clk_emma_ahb: |
eb68faaf | 1697 | clk_disable_unprepare(pcdev->clk_emma_ahb); |
8928b6d1 | 1698 | exit_clk_emma_ipg: |
eb68faaf | 1699 | clk_disable_unprepare(pcdev->clk_emma_ipg); |
2066930d BS |
1700 | out: |
1701 | return err; | |
1702 | } | |
1703 | ||
1704 | static int __devinit mx2_camera_probe(struct platform_device *pdev) | |
1705 | { | |
1706 | struct mx2_camera_dev *pcdev; | |
8928b6d1 SG |
1707 | struct resource *res_csi; |
1708 | int irq_csi; | |
2066930d BS |
1709 | int err = 0; |
1710 | ||
1711 | dev_dbg(&pdev->dev, "initialising\n"); | |
1712 | ||
1713 | res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1714 | irq_csi = platform_get_irq(pdev, 0); | |
1715 | if (res_csi == NULL || irq_csi < 0) { | |
1716 | dev_err(&pdev->dev, "Missing platform resources data\n"); | |
1717 | err = -ENODEV; | |
1718 | goto exit; | |
1719 | } | |
1720 | ||
8928b6d1 | 1721 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
2066930d BS |
1722 | if (!pcdev) { |
1723 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); | |
1724 | err = -ENOMEM; | |
1725 | goto exit; | |
1726 | } | |
1727 | ||
8928b6d1 | 1728 | pcdev->clk_csi = devm_clk_get(&pdev->dev, "ahb"); |
2066930d | 1729 | if (IS_ERR(pcdev->clk_csi)) { |
d867be1c | 1730 | dev_err(&pdev->dev, "Could not get csi clock\n"); |
2066930d | 1731 | err = PTR_ERR(pcdev->clk_csi); |
8928b6d1 | 1732 | goto exit; |
2066930d BS |
1733 | } |
1734 | ||
2066930d BS |
1735 | pcdev->pdata = pdev->dev.platform_data; |
1736 | if (pcdev->pdata) { | |
1737 | long rate; | |
1738 | ||
1739 | pcdev->platform_flags = pcdev->pdata->flags; | |
1740 | ||
1741 | rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); | |
1742 | if (rate <= 0) { | |
1743 | err = -ENODEV; | |
8928b6d1 | 1744 | goto exit; |
2066930d BS |
1745 | } |
1746 | err = clk_set_rate(pcdev->clk_csi, rate); | |
1747 | if (err < 0) | |
8928b6d1 | 1748 | goto exit; |
2066930d BS |
1749 | } |
1750 | ||
1751 | INIT_LIST_HEAD(&pcdev->capture); | |
1752 | INIT_LIST_HEAD(&pcdev->active_bufs); | |
cdc9d6f1 | 1753 | INIT_LIST_HEAD(&pcdev->discard); |
2066930d BS |
1754 | spin_lock_init(&pcdev->lock); |
1755 | ||
8928b6d1 SG |
1756 | pcdev->base_csi = devm_request_and_ioremap(&pdev->dev, res_csi); |
1757 | if (!pcdev->base_csi) { | |
1758 | err = -EADDRNOTAVAIL; | |
1759 | goto exit; | |
2066930d BS |
1760 | } |
1761 | ||
2066930d | 1762 | pcdev->dev = &pdev->dev; |
8928b6d1 | 1763 | platform_set_drvdata(pdev, pcdev); |
2066930d | 1764 | |
2c9ba37d | 1765 | if (cpu_is_mx25()) { |
8928b6d1 SG |
1766 | err = devm_request_irq(&pdev->dev, irq_csi, mx25_camera_irq, 0, |
1767 | MX2_CAM_DRV_NAME, pcdev); | |
2c9ba37d SH |
1768 | if (err) { |
1769 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
8928b6d1 | 1770 | goto exit; |
2c9ba37d | 1771 | } |
2066930d BS |
1772 | } |
1773 | ||
1774 | if (cpu_is_mx27()) { | |
8928b6d1 SG |
1775 | err = mx27_camera_emma_init(pdev); |
1776 | if (err) | |
1777 | goto exit; | |
2066930d BS |
1778 | } |
1779 | ||
8928b6d1 SG |
1780 | /* |
1781 | * We're done with drvdata here. Clear the pointer so that | |
1782 | * v4l2 core can start using drvdata on its purpose. | |
1783 | */ | |
1784 | platform_set_drvdata(pdev, NULL); | |
1785 | ||
2066930d BS |
1786 | pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, |
1787 | pcdev->soc_host.ops = &mx2_soc_camera_host_ops, | |
1788 | pcdev->soc_host.priv = pcdev; | |
1789 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; | |
1790 | pcdev->soc_host.nr = pdev->id; | |
914f05c8 LP |
1791 | if (cpu_is_mx25()) |
1792 | pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE; | |
c6a41e32 JM |
1793 | |
1794 | pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); | |
1795 | if (IS_ERR(pcdev->alloc_ctx)) { | |
1796 | err = PTR_ERR(pcdev->alloc_ctx); | |
1797 | goto eallocctx; | |
1798 | } | |
2066930d BS |
1799 | err = soc_camera_host_register(&pcdev->soc_host); |
1800 | if (err) | |
1801 | goto exit_free_emma; | |
1802 | ||
45f4d4e8 MG |
1803 | dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", |
1804 | clk_get_rate(pcdev->clk_csi)); | |
1805 | ||
2066930d BS |
1806 | return 0; |
1807 | ||
1808 | exit_free_emma: | |
c6a41e32 JM |
1809 | vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); |
1810 | eallocctx: | |
2c9ba37d | 1811 | if (cpu_is_mx27()) { |
eb68faaf | 1812 | clk_disable_unprepare(pcdev->clk_emma_ipg); |
eb68faaf | 1813 | clk_disable_unprepare(pcdev->clk_emma_ahb); |
2066930d | 1814 | } |
2066930d BS |
1815 | exit: |
1816 | return err; | |
1817 | } | |
1818 | ||
1819 | static int __devexit mx2_camera_remove(struct platform_device *pdev) | |
1820 | { | |
1821 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); | |
1822 | struct mx2_camera_dev *pcdev = container_of(soc_host, | |
1823 | struct mx2_camera_dev, soc_host); | |
2066930d BS |
1824 | |
1825 | soc_camera_host_unregister(&pcdev->soc_host); | |
1826 | ||
c6a41e32 JM |
1827 | vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); |
1828 | ||
2c9ba37d | 1829 | if (cpu_is_mx27()) { |
eb68faaf | 1830 | clk_disable_unprepare(pcdev->clk_emma_ipg); |
eb68faaf | 1831 | clk_disable_unprepare(pcdev->clk_emma_ahb); |
2066930d BS |
1832 | } |
1833 | ||
2066930d BS |
1834 | dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); |
1835 | ||
1836 | return 0; | |
1837 | } | |
1838 | ||
1839 | static struct platform_driver mx2_camera_driver = { | |
1840 | .driver = { | |
1841 | .name = MX2_CAM_DRV_NAME, | |
1842 | }, | |
1843 | .remove = __devexit_p(mx2_camera_remove), | |
1844 | }; | |
1845 | ||
1846 | ||
1847 | static int __init mx2_camera_init(void) | |
1848 | { | |
1849 | return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); | |
1850 | } | |
1851 | ||
1852 | static void __exit mx2_camera_exit(void) | |
1853 | { | |
1854 | return platform_driver_unregister(&mx2_camera_driver); | |
1855 | } | |
1856 | ||
1857 | module_init(mx2_camera_init); | |
1858 | module_exit(mx2_camera_exit); | |
1859 | ||
1860 | MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); | |
1861 | MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); | |
1862 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1863 | MODULE_VERSION(MX2_CAM_VERSION); |