Commit | Line | Data |
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4f67130a GL |
1 | /* |
2 | * V4L2 Driver for i.MX3x camera host | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
4f67130a GL |
14 | #include <linux/videodev2.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/interrupt.h> | |
f39c1ab3 | 19 | #include <linux/sched.h> |
b8a6d998 | 20 | #include <linux/dma/ipu-dma.h> |
4f67130a GL |
21 | |
22 | #include <media/v4l2-common.h> | |
23 | #include <media/v4l2-dev.h> | |
379fa5d3 | 24 | #include <media/videobuf2-dma-contig.h> |
4f67130a | 25 | #include <media/soc_camera.h> |
760697be | 26 | #include <media/soc_mediabus.h> |
4f67130a | 27 | |
82906b13 AB |
28 | #include <linux/platform_data/camera-mx3.h> |
29 | #include <linux/platform_data/dma-imx.h> | |
4f67130a GL |
30 | |
31 | #define MX3_CAM_DRV_NAME "mx3-camera" | |
32 | ||
33 | /* CMOS Sensor Interface Registers */ | |
34 | #define CSI_REG_START 0x60 | |
35 | ||
36 | #define CSI_SENS_CONF (0x60 - CSI_REG_START) | |
37 | #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START) | |
38 | #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START) | |
39 | #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START) | |
40 | #define CSI_TST_CTRL (0x70 - CSI_REG_START) | |
41 | #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START) | |
42 | #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START) | |
43 | #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START) | |
44 | #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START) | |
45 | #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START) | |
46 | ||
47 | #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 | |
48 | #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 | |
49 | #define CSI_SENS_CONF_DATA_POL_SHIFT 2 | |
50 | #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 | |
51 | #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 | |
52 | #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7 | |
53 | #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 | |
54 | #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10 | |
55 | #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 | |
56 | #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 | |
57 | ||
58 | #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
59 | #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
60 | #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
61 | ||
62 | #define MAX_VIDEO_MEM 16 | |
63 | ||
64 | struct mx3_camera_buffer { | |
65 | /* common v4l buffer stuff -- must be first */ | |
379fa5d3 | 66 | struct vb2_buffer vb; |
379fa5d3 | 67 | struct list_head queue; |
4f67130a GL |
68 | |
69 | /* One descriptot per scatterlist (per frame) */ | |
70 | struct dma_async_tx_descriptor *txd; | |
71 | ||
72 | /* We have to "build" a scatterlist ourselves - one element per frame */ | |
73 | struct scatterlist sg; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct mx3_camera_dev - i.MX3x camera (CSI) object | |
78 | * @dev: camera device, to which the coherent buffer is attached | |
79 | * @icd: currently attached camera sensor | |
80 | * @clk: pointer to clock | |
81 | * @base: remapped register base address | |
82 | * @pdata: platform data | |
83 | * @platform_flags: platform flags | |
84 | * @mclk: master clock frequency in Hz | |
85 | * @capture: list of capture videobuffers | |
86 | * @lock: protects video buffer lists | |
87 | * @active: active video buffer | |
88 | * @idmac_channel: array of pointers to IPU DMAC DMA channels | |
89 | * @soc_host: embedded soc_host object | |
90 | */ | |
91 | struct mx3_camera_dev { | |
4f67130a GL |
92 | /* |
93 | * i.MX3x is only supposed to handle one camera on its Camera Sensor | |
94 | * Interface. If anyone ever builds hardware to enable more than one | |
95 | * camera _simultaneously_, they will have to modify this driver too | |
96 | */ | |
4f67130a GL |
97 | struct clk *clk; |
98 | ||
99 | void __iomem *base; | |
100 | ||
101 | struct mx3_camera_pdata *pdata; | |
102 | ||
103 | unsigned long platform_flags; | |
104 | unsigned long mclk; | |
579cea03 | 105 | u16 width_flags; /* max 15 bits */ |
4f67130a GL |
106 | |
107 | struct list_head capture; | |
108 | spinlock_t lock; /* Protects video buffer lists */ | |
109 | struct mx3_camera_buffer *active; | |
07f92448 | 110 | size_t buf_total; |
379fa5d3 GL |
111 | struct vb2_alloc_ctx *alloc_ctx; |
112 | enum v4l2_field field; | |
113 | int sequence; | |
4f67130a GL |
114 | |
115 | /* IDMAC / dmaengine interface */ | |
116 | struct idmac_channel *idmac_channel[1]; /* We need one channel */ | |
117 | ||
118 | struct soc_camera_host soc_host; | |
119 | }; | |
120 | ||
121 | struct dma_chan_request { | |
122 | struct mx3_camera_dev *mx3_cam; | |
123 | enum ipu_channel id; | |
124 | }; | |
125 | ||
4f67130a GL |
126 | static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg) |
127 | { | |
128 | return __raw_readl(mx3->base + reg); | |
129 | } | |
130 | ||
131 | static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg) | |
132 | { | |
133 | __raw_writel(value, mx3->base + reg); | |
134 | } | |
135 | ||
379fa5d3 GL |
136 | static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb) |
137 | { | |
138 | return container_of(vb, struct mx3_camera_buffer, vb); | |
139 | } | |
140 | ||
4f67130a GL |
141 | /* Called from the IPU IDMAC ISR */ |
142 | static void mx3_cam_dma_done(void *arg) | |
143 | { | |
144 | struct idmac_tx_desc *desc = to_tx_desc(arg); | |
145 | struct dma_chan *chan = desc->txd.chan; | |
146 | struct idmac_channel *ichannel = to_idmac_chan(chan); | |
147 | struct mx3_camera_dev *mx3_cam = ichannel->client; | |
4f67130a GL |
148 | |
149 | dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", | |
150 | desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0); | |
151 | ||
152 | spin_lock(&mx3_cam->lock); | |
153 | if (mx3_cam->active) { | |
379fa5d3 GL |
154 | struct vb2_buffer *vb = &mx3_cam->active->vb; |
155 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); | |
156 | ||
157 | list_del_init(&buf->queue); | |
8e6057b5 | 158 | v4l2_get_timestamp(&vb->v4l2_buf.timestamp); |
379fa5d3 GL |
159 | vb->v4l2_buf.field = mx3_cam->field; |
160 | vb->v4l2_buf.sequence = mx3_cam->sequence++; | |
161 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
4f67130a GL |
162 | } |
163 | ||
164 | if (list_empty(&mx3_cam->capture)) { | |
165 | mx3_cam->active = NULL; | |
166 | spin_unlock(&mx3_cam->lock); | |
167 | ||
168 | /* | |
169 | * stop capture - without further buffers IPU_CHA_BUF0_RDY will | |
170 | * not get updated | |
171 | */ | |
172 | return; | |
173 | } | |
174 | ||
175 | mx3_cam->active = list_entry(mx3_cam->capture.next, | |
379fa5d3 | 176 | struct mx3_camera_buffer, queue); |
4f67130a GL |
177 | spin_unlock(&mx3_cam->lock); |
178 | } | |
179 | ||
4f67130a GL |
180 | /* |
181 | * Videobuf operations | |
182 | */ | |
183 | ||
184 | /* | |
185 | * Calculate the __buffer__ (not data) size and number of buffers. | |
4f67130a | 186 | */ |
379fa5d3 | 187 | static int mx3_videobuf_setup(struct vb2_queue *vq, |
fc714e70 | 188 | const struct v4l2_format *fmt, |
379fa5d3 | 189 | unsigned int *count, unsigned int *num_planes, |
035aa147 | 190 | unsigned int sizes[], void *alloc_ctxs[]) |
4f67130a | 191 | { |
379fa5d3 | 192 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
7dfff953 | 193 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 194 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a GL |
195 | |
196 | if (!mx3_cam->idmac_channel[0]) | |
197 | return -EINVAL; | |
198 | ||
07f92448 GL |
199 | if (fmt) { |
200 | const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd, | |
201 | fmt->fmt.pix.pixelformat); | |
bed8d803 LP |
202 | unsigned int bytes_per_line; |
203 | int ret; | |
2b61d46e | 204 | |
07f92448 GL |
205 | if (!xlate) |
206 | return -EINVAL; | |
2b61d46e | 207 | |
bed8d803 LP |
208 | ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width, |
209 | xlate->host_fmt); | |
210 | if (ret < 0) | |
211 | return ret; | |
2b61d46e | 212 | |
bed8d803 LP |
213 | bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret); |
214 | ||
215 | ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line, | |
216 | fmt->fmt.pix.height); | |
217 | if (ret < 0) | |
218 | return ret; | |
219 | ||
220 | sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret); | |
07f92448 GL |
221 | } else { |
222 | /* Called from VIDIOC_REQBUFS or in compatibility mode */ | |
2b61d46e | 223 | sizes[0] = icd->sizeimage; |
07f92448 | 224 | } |
4f67130a | 225 | |
07f92448 | 226 | alloc_ctxs[0] = mx3_cam->alloc_ctx; |
4f67130a | 227 | |
07f92448 GL |
228 | if (!vq->num_buffers) |
229 | mx3_cam->sequence = 0; | |
4f67130a | 230 | |
07f92448 GL |
231 | if (!*count) |
232 | *count = 2; | |
4f67130a | 233 | |
07f92448 GL |
234 | /* If *num_planes != 0, we have already verified *count. */ |
235 | if (!*num_planes && | |
236 | sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024) | |
237 | *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) / | |
238 | sizes[0]; | |
4f67130a | 239 | |
07f92448 | 240 | *num_planes = 1; |
4f67130a | 241 | |
379fa5d3 | 242 | return 0; |
4f67130a GL |
243 | } |
244 | ||
245 | static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc) | |
246 | { | |
247 | /* Add more formats as need arises and test possibilities appear... */ | |
248 | switch (fourcc) { | |
4f67130a GL |
249 | case V4L2_PIX_FMT_RGB24: |
250 | return IPU_PIX_FMT_RGB24; | |
a48be1d6 AP |
251 | case V4L2_PIX_FMT_UYVY: |
252 | case V4L2_PIX_FMT_RGB565: | |
4f67130a GL |
253 | default: |
254 | return IPU_PIX_FMT_GENERIC; | |
255 | } | |
256 | } | |
257 | ||
379fa5d3 | 258 | static void mx3_videobuf_queue(struct vb2_buffer *vb) |
4f67130a | 259 | { |
379fa5d3 | 260 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 261 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 262 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 | 263 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 GL |
264 | struct scatterlist *sg = &buf->sg; |
265 | struct dma_async_tx_descriptor *txd; | |
266 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
4f67130a | 267 | struct idmac_video_param *video = &ichan->params.video; |
07f92448 | 268 | const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt; |
07f92448 GL |
269 | dma_cookie_t cookie; |
270 | size_t new_size; | |
271 | ||
2b61d46e | 272 | new_size = icd->sizeimage; |
07f92448 GL |
273 | |
274 | if (vb2_plane_size(vb, 0) < new_size) { | |
275 | dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n", | |
276 | vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size); | |
277 | goto error; | |
278 | } | |
279 | ||
c72f429f | 280 | if (!buf->txd) { |
07f92448 GL |
281 | sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0); |
282 | sg_dma_len(sg) = new_size; | |
283 | ||
16052827 | 284 | txd = dmaengine_prep_slave_sg( |
e0d23ef2 | 285 | &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM, |
07f92448 GL |
286 | DMA_PREP_INTERRUPT); |
287 | if (!txd) | |
288 | goto error; | |
289 | ||
290 | txd->callback_param = txd; | |
291 | txd->callback = mx3_cam_dma_done; | |
292 | ||
07f92448 GL |
293 | buf->txd = txd; |
294 | } else { | |
295 | txd = buf->txd; | |
296 | } | |
297 | ||
298 | vb2_set_plane_payload(vb, 0, new_size); | |
4f67130a GL |
299 | |
300 | /* This is the configuration of one sg-element */ | |
07f92448 | 301 | video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc); |
a48be1d6 AP |
302 | |
303 | if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) { | |
304 | /* | |
07f92448 GL |
305 | * If the IPU DMA channel is configured to transfer generic |
306 | * 8-bit data, we have to set up the geometry parameters | |
307 | * correctly, according to the current pixel format. The DMA | |
308 | * horizontal parameters in this case are expressed in bytes, | |
309 | * not in pixels. | |
a48be1d6 | 310 | */ |
1c0f95ee | 311 | video->out_width = icd->bytesperline; |
a48be1d6 | 312 | video->out_height = icd->user_height; |
1c0f95ee | 313 | video->out_stride = icd->bytesperline; |
a48be1d6 AP |
314 | } else { |
315 | /* | |
316 | * For IPU known formats the pixel unit will be managed | |
317 | * successfully by the IPU code | |
318 | */ | |
319 | video->out_width = icd->user_width; | |
320 | video->out_height = icd->user_height; | |
321 | video->out_stride = icd->user_width; | |
322 | } | |
4f67130a GL |
323 | |
324 | #ifdef DEBUG | |
325 | /* helps to see what DMA actually has written */ | |
379fa5d3 GL |
326 | if (vb2_plane_vaddr(vb, 0)) |
327 | memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0)); | |
4f67130a GL |
328 | #endif |
329 | ||
a7a69197 | 330 | spin_lock_irq(&mx3_cam->lock); |
379fa5d3 | 331 | list_add_tail(&buf->queue, &mx3_cam->capture); |
4f67130a | 332 | |
379fa5d3 | 333 | if (!mx3_cam->active) |
4f67130a | 334 | mx3_cam->active = buf; |
4f67130a | 335 | |
2dd54a54 | 336 | spin_unlock_irq(&mx3_cam->lock); |
4f67130a GL |
337 | |
338 | cookie = txd->tx_submit(txd); | |
7dfff953 | 339 | dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n", |
0166b743 | 340 | cookie, sg_dma_address(&buf->sg)); |
2dd54a54 | 341 | |
4f67130a GL |
342 | if (cookie >= 0) |
343 | return; | |
344 | ||
379fa5d3 | 345 | spin_lock_irq(&mx3_cam->lock); |
4f67130a | 346 | |
379fa5d3 GL |
347 | /* Submit error */ |
348 | list_del_init(&buf->queue); | |
4f67130a GL |
349 | |
350 | if (mx3_cam->active == buf) | |
351 | mx3_cam->active = NULL; | |
379fa5d3 | 352 | |
a7a69197 | 353 | spin_unlock_irq(&mx3_cam->lock); |
07f92448 | 354 | error: |
379fa5d3 | 355 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); |
4f67130a GL |
356 | } |
357 | ||
379fa5d3 | 358 | static void mx3_videobuf_release(struct vb2_buffer *vb) |
4f67130a | 359 | { |
379fa5d3 | 360 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 361 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 362 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 GL |
363 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
364 | struct dma_async_tx_descriptor *txd = buf->txd; | |
4f67130a GL |
365 | unsigned long flags; |
366 | ||
7dfff953 | 367 | dev_dbg(icd->parent, |
379fa5d3 | 368 | "Release%s DMA 0x%08x, queue %sempty\n", |
4f67130a | 369 | mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), |
379fa5d3 GL |
370 | list_empty(&buf->queue) ? "" : "not "); |
371 | ||
4f67130a | 372 | spin_lock_irqsave(&mx3_cam->lock, flags); |
4f67130a | 373 | |
379fa5d3 GL |
374 | if (mx3_cam->active == buf) |
375 | mx3_cam->active = NULL; | |
376 | ||
377 | /* Doesn't hurt also if the list is empty */ | |
378 | list_del_init(&buf->queue); | |
379fa5d3 GL |
379 | |
380 | if (txd) { | |
381 | buf->txd = NULL; | |
382 | if (mx3_cam->idmac_channel[0]) | |
383 | async_tx_ack(txd); | |
4f67130a | 384 | } |
379fa5d3 | 385 | |
4f67130a | 386 | spin_unlock_irqrestore(&mx3_cam->lock, flags); |
07f92448 GL |
387 | |
388 | mx3_cam->buf_total -= vb2_plane_size(vb, 0); | |
4f67130a GL |
389 | } |
390 | ||
379fa5d3 GL |
391 | static int mx3_videobuf_init(struct vb2_buffer *vb) |
392 | { | |
07f92448 GL |
393 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
394 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
395 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 | 396 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 | 397 | |
c72f429f AG |
398 | if (!buf->txd) { |
399 | /* This is for locking debugging only */ | |
400 | INIT_LIST_HEAD(&buf->queue); | |
401 | sg_init_table(&buf->sg, 1); | |
379fa5d3 | 402 | |
c72f429f AG |
403 | mx3_cam->buf_total += vb2_plane_size(vb, 0); |
404 | } | |
379fa5d3 GL |
405 | |
406 | return 0; | |
407 | } | |
408 | ||
e37559b2 | 409 | static void mx3_stop_streaming(struct vb2_queue *q) |
08a31b96 GL |
410 | { |
411 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
7dfff953 | 412 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
08a31b96 GL |
413 | struct mx3_camera_dev *mx3_cam = ici->priv; |
414 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
08a31b96 GL |
415 | struct mx3_camera_buffer *buf, *tmp; |
416 | unsigned long flags; | |
417 | ||
0aae803a VK |
418 | if (ichan) |
419 | dmaengine_pause(&ichan->dma_chan); | |
08a31b96 GL |
420 | |
421 | spin_lock_irqsave(&mx3_cam->lock, flags); | |
422 | ||
423 | mx3_cam->active = NULL; | |
424 | ||
425 | list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) { | |
08a31b96 | 426 | list_del_init(&buf->queue); |
07f92448 | 427 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); |
08a31b96 GL |
428 | } |
429 | ||
430 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
08a31b96 GL |
431 | } |
432 | ||
379fa5d3 GL |
433 | static struct vb2_ops mx3_videobuf_ops = { |
434 | .queue_setup = mx3_videobuf_setup, | |
379fa5d3 GL |
435 | .buf_queue = mx3_videobuf_queue, |
436 | .buf_cleanup = mx3_videobuf_release, | |
437 | .buf_init = mx3_videobuf_init, | |
976036df LP |
438 | .wait_prepare = vb2_ops_wait_prepare, |
439 | .wait_finish = vb2_ops_wait_finish, | |
08a31b96 | 440 | .stop_streaming = mx3_stop_streaming, |
4f67130a GL |
441 | }; |
442 | ||
379fa5d3 | 443 | static int mx3_camera_init_videobuf(struct vb2_queue *q, |
4f67130a GL |
444 | struct soc_camera_device *icd) |
445 | { | |
976036df LP |
446 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
447 | ||
379fa5d3 GL |
448 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
449 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
450 | q->drv_priv = icd; | |
451 | q->ops = &mx3_videobuf_ops; | |
452 | q->mem_ops = &vb2_dma_contig_memops; | |
453 | q->buf_struct_size = sizeof(struct mx3_camera_buffer); | |
ade48681 | 454 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; |
976036df | 455 | q->lock = &ici->host_lock; |
379fa5d3 GL |
456 | |
457 | return vb2_queue_init(q); | |
4f67130a GL |
458 | } |
459 | ||
460 | /* First part of ipu_csi_init_interface() */ | |
663ccaf4 | 461 | static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam) |
4f67130a GL |
462 | { |
463 | u32 conf; | |
464 | long rate; | |
465 | ||
466 | /* Set default size: ipu_csi_set_window_size() */ | |
467 | csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE); | |
468 | /* ...and position to 0:0: ipu_csi_set_window_pos() */ | |
469 | conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
470 | csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL); | |
471 | ||
472 | /* We use only gated clock synchronisation mode so far */ | |
473 | conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT; | |
474 | ||
475 | /* Set generic data, platform-biggest bus-width */ | |
476 | conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
477 | ||
478 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
479 | conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
480 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
481 | conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
482 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
483 | conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
484 | else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/ | |
485 | conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
486 | ||
487 | if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC) | |
488 | conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; | |
489 | if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC) | |
490 | conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT; | |
491 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
492 | conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
493 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
494 | conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
495 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
496 | conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
497 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
498 | conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
499 | ||
500 | /* ipu_csi_init_interface() */ | |
501 | csi_reg_write(mx3_cam, conf, CSI_SENS_CONF); | |
502 | ||
fdf7748b | 503 | clk_prepare_enable(mx3_cam->clk); |
4f67130a | 504 | rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); |
663ccaf4 | 505 | dev_dbg(mx3_cam->soc_host.v4l2_dev.dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate); |
4f67130a GL |
506 | if (rate) |
507 | clk_set_rate(mx3_cam->clk, rate); | |
508 | } | |
509 | ||
4f67130a GL |
510 | static int mx3_camera_add_device(struct soc_camera_device *icd) |
511 | { | |
663ccaf4 GL |
512 | dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n", |
513 | icd->devnum); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static void mx3_camera_remove_device(struct soc_camera_device *icd) | |
519 | { | |
520 | dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n", | |
521 | icd->devnum); | |
522 | } | |
523 | ||
524 | /* Called with .host_lock held */ | |
525 | static int mx3_camera_clock_start(struct soc_camera_host *ici) | |
526 | { | |
4f67130a | 527 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a | 528 | |
663ccaf4 | 529 | mx3_camera_activate(mx3_cam); |
4f67130a | 530 | |
07f92448 | 531 | mx3_cam->buf_total = 0; |
4f67130a | 532 | |
40e2e092 | 533 | return 0; |
4f67130a GL |
534 | } |
535 | ||
dd669e90 | 536 | /* Called with .host_lock held */ |
663ccaf4 | 537 | static void mx3_camera_clock_stop(struct soc_camera_host *ici) |
4f67130a | 538 | { |
4f67130a GL |
539 | struct mx3_camera_dev *mx3_cam = ici->priv; |
540 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
541 | ||
4f67130a GL |
542 | if (*ichan) { |
543 | dma_release_channel(&(*ichan)->dma_chan); | |
544 | *ichan = NULL; | |
545 | } | |
546 | ||
fdf7748b | 547 | clk_disable_unprepare(mx3_cam->clk); |
4f67130a GL |
548 | } |
549 | ||
4f67130a GL |
550 | static int test_platform_param(struct mx3_camera_dev *mx3_cam, |
551 | unsigned char buswidth, unsigned long *flags) | |
552 | { | |
579cea03 GL |
553 | /* |
554 | * If requested data width is supported by the platform, use it or any | |
555 | * possible lower value - i.MX31 is smart enough to shift bits | |
556 | */ | |
557 | if (buswidth > fls(mx3_cam->width_flags)) | |
558 | return -EINVAL; | |
559 | ||
4f67130a GL |
560 | /* |
561 | * Platform specified synchronization and pixel clock polarities are | |
562 | * only a recommendation and are only used during probing. MX3x | |
563 | * camera interface only works in master mode, i.e., uses HSYNC and | |
564 | * VSYNC signals from the sensor | |
565 | */ | |
579cea03 GL |
566 | *flags = V4L2_MBUS_MASTER | |
567 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
568 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
569 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
570 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
571 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
572 | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
573 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
574 | V4L2_MBUS_DATA_ACTIVE_LOW; | |
4f67130a GL |
575 | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static int mx3_camera_try_bus_param(struct soc_camera_device *icd, | |
580 | const unsigned int depth) | |
581 | { | |
579cea03 | 582 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 583 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 584 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 GL |
585 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
586 | unsigned long bus_flags, common_flags; | |
4f67130a GL |
587 | int ret = test_platform_param(mx3_cam, depth, &bus_flags); |
588 | ||
7dfff953 | 589 | dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret); |
4f67130a GL |
590 | |
591 | if (ret < 0) | |
592 | return ret; | |
593 | ||
579cea03 GL |
594 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
595 | if (!ret) { | |
596 | common_flags = soc_mbus_config_compatible(&cfg, | |
597 | bus_flags); | |
598 | if (!common_flags) { | |
599 | dev_warn(icd->parent, | |
600 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
601 | cfg.flags, bus_flags); | |
602 | return -EINVAL; | |
603 | } | |
604 | } else if (ret != -ENOIOCTLCMD) { | |
605 | return ret; | |
606 | } | |
4f67130a | 607 | |
579cea03 | 608 | return 0; |
4f67130a GL |
609 | } |
610 | ||
611 | static bool chan_filter(struct dma_chan *chan, void *arg) | |
612 | { | |
613 | struct dma_chan_request *rq = arg; | |
614 | struct mx3_camera_pdata *pdata; | |
615 | ||
a8de6635 SH |
616 | if (!imx_dma_is_ipu(chan)) |
617 | return false; | |
618 | ||
4f67130a GL |
619 | if (!rq) |
620 | return false; | |
621 | ||
979ea1dd | 622 | pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data; |
4f67130a GL |
623 | |
624 | return rq->id == chan->chan_id && | |
625 | pdata->dma_dev == chan->device->dev; | |
626 | } | |
627 | ||
760697be | 628 | static const struct soc_mbus_pixelfmt mx3_camera_formats[] = { |
4f67130a | 629 | { |
760697be GL |
630 | .fourcc = V4L2_PIX_FMT_SBGGR8, |
631 | .name = "Bayer BGGR (sRGB) 8 bit", | |
632 | .bits_per_sample = 8, | |
633 | .packing = SOC_MBUS_PACKING_NONE, | |
634 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 635 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a | 636 | }, { |
760697be GL |
637 | .fourcc = V4L2_PIX_FMT_GREY, |
638 | .name = "Monochrome 8 bit", | |
639 | .bits_per_sample = 8, | |
640 | .packing = SOC_MBUS_PACKING_NONE, | |
641 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 642 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a GL |
643 | }, |
644 | }; | |
645 | ||
760697be GL |
646 | /* This will be corrected as we get more formats */ |
647 | static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
4f67130a | 648 | { |
760697be GL |
649 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
650 | (fmt->bits_per_sample == 8 && | |
651 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
652 | (fmt->bits_per_sample > 8 && | |
653 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
4f67130a GL |
654 | } |
655 | ||
3805f201 | 656 | static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
4f67130a GL |
657 | struct soc_camera_format_xlate *xlate) |
658 | { | |
760697be | 659 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 660 | struct device *dev = icd->parent; |
760697be | 661 | int formats = 0, ret; |
ebcff5fc HV |
662 | struct v4l2_subdev_mbus_code_enum code = { |
663 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
664 | .index = idx, | |
665 | }; | |
760697be | 666 | const struct soc_mbus_pixelfmt *fmt; |
4f67130a | 667 | |
ebcff5fc | 668 | ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code); |
760697be GL |
669 | if (ret < 0) |
670 | /* No more formats */ | |
671 | return 0; | |
4f67130a | 672 | |
ebcff5fc | 673 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 674 | if (!fmt) { |
7dfff953 | 675 | dev_warn(icd->parent, |
ebcff5fc | 676 | "Unsupported format code #%u: 0x%x\n", idx, code.code); |
4f67130a | 677 | return 0; |
760697be | 678 | } |
4f67130a | 679 | |
760697be GL |
680 | /* This also checks support for the requested bits-per-sample */ |
681 | ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample); | |
4f67130a GL |
682 | if (ret < 0) |
683 | return 0; | |
684 | ||
ebcff5fc | 685 | switch (code.code) { |
27ffaeb0 | 686 | case MEDIA_BUS_FMT_SBGGR10_1X10: |
4f67130a GL |
687 | formats++; |
688 | if (xlate) { | |
760697be | 689 | xlate->host_fmt = &mx3_camera_formats[0]; |
ebcff5fc | 690 | xlate->code = code.code; |
4f67130a | 691 | xlate++; |
2bcccaec | 692 | dev_dbg(dev, "Providing format %s using code 0x%x\n", |
ebcff5fc | 693 | mx3_camera_formats[0].name, code.code); |
4f67130a | 694 | } |
760697be | 695 | break; |
27ffaeb0 | 696 | case MEDIA_BUS_FMT_Y10_1X10: |
4f67130a GL |
697 | formats++; |
698 | if (xlate) { | |
760697be | 699 | xlate->host_fmt = &mx3_camera_formats[1]; |
ebcff5fc | 700 | xlate->code = code.code; |
4f67130a | 701 | xlate++; |
2bcccaec | 702 | dev_dbg(dev, "Providing format %s using code 0x%x\n", |
ebcff5fc | 703 | mx3_camera_formats[1].name, code.code); |
4f67130a | 704 | } |
760697be | 705 | break; |
4f67130a | 706 | default: |
760697be GL |
707 | if (!mx3_camera_packing_supported(fmt)) |
708 | return 0; | |
709 | } | |
710 | ||
711 | /* Generic pass-through */ | |
712 | formats++; | |
713 | if (xlate) { | |
714 | xlate->host_fmt = fmt; | |
ebcff5fc | 715 | xlate->code = code.code; |
a48be1d6 AP |
716 | dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n", |
717 | (fmt->fourcc >> (0*8)) & 0xFF, | |
718 | (fmt->fourcc >> (1*8)) & 0xFF, | |
719 | (fmt->fourcc >> (2*8)) & 0xFF, | |
720 | (fmt->fourcc >> (3*8)) & 0xFF); | |
760697be | 721 | xlate++; |
4f67130a GL |
722 | } |
723 | ||
724 | return formats; | |
725 | } | |
726 | ||
09e231b3 | 727 | static void configure_geometry(struct mx3_camera_dev *mx3_cam, |
a48be1d6 | 728 | unsigned int width, unsigned int height, |
d2dcad49 | 729 | const struct soc_mbus_pixelfmt *fmt) |
4f67130a | 730 | { |
4f67130a | 731 | u32 ctrl, width_field, height_field; |
a48be1d6 AP |
732 | |
733 | if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) { | |
734 | /* | |
735 | * As the CSI will be configured to output BAYER, here | |
736 | * the width parameter count the number of samples to | |
737 | * capture to complete the whole image width. | |
738 | */ | |
cc552b62 GL |
739 | unsigned int num, den; |
740 | int ret = soc_mbus_samples_per_pixel(fmt, &num, &den); | |
741 | BUG_ON(ret < 0); | |
742 | width = width * num / den; | |
a48be1d6 | 743 | } |
4f67130a GL |
744 | |
745 | /* Setup frame size - this cannot be changed on-the-fly... */ | |
6a6c8786 GL |
746 | width_field = width - 1; |
747 | height_field = height - 1; | |
4f67130a GL |
748 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); |
749 | ||
750 | csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); | |
751 | csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2); | |
752 | ||
753 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE); | |
754 | ||
755 | /* ...and position */ | |
756 | ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
757 | /* Sensor does the cropping */ | |
758 | csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); | |
09e231b3 GL |
759 | } |
760 | ||
761 | static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) | |
762 | { | |
763 | dma_cap_mask_t mask; | |
764 | struct dma_chan *chan; | |
765 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
766 | /* We have to use IDMAC_IC_7 for Bayer / generic data */ | |
767 | struct dma_chan_request rq = {.mx3_cam = mx3_cam, | |
768 | .id = IDMAC_IC_7}; | |
769 | ||
09e231b3 GL |
770 | dma_cap_zero(mask); |
771 | dma_cap_set(DMA_SLAVE, mask); | |
772 | dma_cap_set(DMA_PRIVATE, mask); | |
773 | chan = dma_request_channel(mask, chan_filter, &rq); | |
774 | if (!chan) | |
775 | return -EBUSY; | |
776 | ||
777 | *ichan = to_idmac_chan(chan); | |
778 | (*ichan)->client = mx3_cam; | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
6a6c8786 GL |
783 | /* |
784 | * FIXME: learn to use stride != width, then we can keep stride properly aligned | |
785 | * and support arbitrary (even) widths. | |
786 | */ | |
e26b3144 | 787 | static inline void stride_align(__u32 *width) |
6a6c8786 | 788 | { |
d2dcad49 GL |
789 | if (ALIGN(*width, 8) < 4096) |
790 | *width = ALIGN(*width, 8); | |
6a6c8786 GL |
791 | else |
792 | *width = *width & ~7; | |
793 | } | |
794 | ||
795 | /* | |
796 | * As long as we don't implement host-side cropping and scaling, we can use | |
797 | * default g_crop and cropcap from soc_camera.c | |
798 | */ | |
09e231b3 | 799 | static int mx3_camera_set_crop(struct soc_camera_device *icd, |
60cd1ee1 | 800 | const struct v4l2_crop *a) |
09e231b3 | 801 | { |
60cd1ee1 GL |
802 | struct v4l2_crop a_writable = *a; |
803 | struct v4l2_rect *rect = &a_writable.c; | |
7dfff953 | 804 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 805 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 806 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
760697be | 807 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 808 | int ret; |
09e231b3 | 809 | |
6a6c8786 GL |
810 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); |
811 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
812 | ||
813 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
814 | if (ret < 0) | |
815 | return ret; | |
816 | ||
d2dcad49 | 817 | /* The capture device might have changed its output sizes */ |
760697be | 818 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
819 | if (ret < 0) |
820 | return ret; | |
821 | ||
d2dcad49 GL |
822 | if (mf.code != icd->current_fmt->code) |
823 | return -EINVAL; | |
824 | ||
760697be | 825 | if (mf.width & 7) { |
6a6c8786 | 826 | /* Ouch! We can only handle 8-byte aligned width... */ |
760697be GL |
827 | stride_align(&mf.width); |
828 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
09e231b3 GL |
829 | if (ret < 0) |
830 | return ret; | |
831 | } | |
832 | ||
379fa5d3 | 833 | if (mf.width != icd->user_width || mf.height != icd->user_height) |
d2dcad49 GL |
834 | configure_geometry(mx3_cam, mf.width, mf.height, |
835 | icd->current_fmt->host_fmt); | |
6a6c8786 | 836 | |
7dfff953 | 837 | dev_dbg(icd->parent, "Sensor cropped %dx%d\n", |
760697be | 838 | mf.width, mf.height); |
6a6c8786 | 839 | |
760697be GL |
840 | icd->user_width = mf.width; |
841 | icd->user_height = mf.height; | |
6a6c8786 GL |
842 | |
843 | return ret; | |
09e231b3 GL |
844 | } |
845 | ||
846 | static int mx3_camera_set_fmt(struct soc_camera_device *icd, | |
847 | struct v4l2_format *f) | |
848 | { | |
7dfff953 | 849 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 850 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 851 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
852 | const struct soc_camera_format_xlate *xlate; |
853 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 854 | struct v4l2_mbus_framefmt mf; |
09e231b3 GL |
855 | int ret; |
856 | ||
857 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
858 | if (!xlate) { | |
7dfff953 | 859 | dev_warn(icd->parent, "Format %x not found\n", |
0166b743 | 860 | pix->pixelformat); |
09e231b3 GL |
861 | return -EINVAL; |
862 | } | |
863 | ||
6a6c8786 | 864 | stride_align(&pix->width); |
7dfff953 | 865 | dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height); |
6a6c8786 | 866 | |
09e231b3 GL |
867 | /* |
868 | * Might have to perform a complete interface initialisation like in | |
869 | * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider | |
870 | * mxc_v4l2_s_fmt() | |
871 | */ | |
872 | ||
d2dcad49 | 873 | configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt); |
4f67130a | 874 | |
760697be GL |
875 | mf.width = pix->width; |
876 | mf.height = pix->height; | |
877 | mf.field = pix->field; | |
878 | mf.colorspace = pix->colorspace; | |
879 | mf.code = xlate->code; | |
880 | ||
881 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
882 | if (ret < 0) | |
883 | return ret; | |
884 | ||
885 | if (mf.code != xlate->code) | |
886 | return -EINVAL; | |
887 | ||
379fa5d3 GL |
888 | if (!mx3_cam->idmac_channel[0]) { |
889 | ret = acquire_dma_channel(mx3_cam); | |
890 | if (ret < 0) | |
891 | return ret; | |
892 | } | |
893 | ||
760697be GL |
894 | pix->width = mf.width; |
895 | pix->height = mf.height; | |
896 | pix->field = mf.field; | |
379fa5d3 | 897 | mx3_cam->field = mf.field; |
760697be GL |
898 | pix->colorspace = mf.colorspace; |
899 | icd->current_fmt = xlate; | |
4f67130a | 900 | |
7dfff953 | 901 | dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height); |
6a6c8786 | 902 | |
4f67130a GL |
903 | return ret; |
904 | } | |
905 | ||
906 | static int mx3_camera_try_fmt(struct soc_camera_device *icd, | |
907 | struct v4l2_format *f) | |
908 | { | |
c9c1f1c0 | 909 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
4f67130a GL |
910 | const struct soc_camera_format_xlate *xlate; |
911 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 912 | struct v4l2_mbus_framefmt mf; |
4f67130a | 913 | __u32 pixfmt = pix->pixelformat; |
4f67130a GL |
914 | int ret; |
915 | ||
916 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
917 | if (pixfmt && !xlate) { | |
7dfff953 | 918 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
4f67130a GL |
919 | return -EINVAL; |
920 | } | |
921 | ||
922 | /* limit to MX3 hardware capabilities */ | |
923 | if (pix->height > 4096) | |
924 | pix->height = 4096; | |
925 | if (pix->width > 4096) | |
926 | pix->width = 4096; | |
927 | ||
4f67130a | 928 | /* limit to sensor capabilities */ |
760697be GL |
929 | mf.width = pix->width; |
930 | mf.height = pix->height; | |
931 | mf.field = pix->field; | |
932 | mf.colorspace = pix->colorspace; | |
933 | mf.code = xlate->code; | |
4f67130a | 934 | |
760697be GL |
935 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
936 | if (ret < 0) | |
937 | return ret; | |
4f67130a | 938 | |
760697be GL |
939 | pix->width = mf.width; |
940 | pix->height = mf.height; | |
941 | pix->colorspace = mf.colorspace; | |
942 | ||
943 | switch (mf.field) { | |
944 | case V4L2_FIELD_ANY: | |
4f67130a | 945 | pix->field = V4L2_FIELD_NONE; |
760697be GL |
946 | break; |
947 | case V4L2_FIELD_NONE: | |
948 | break; | |
949 | default: | |
7dfff953 | 950 | dev_err(icd->parent, "Field type %d unsupported.\n", |
760697be GL |
951 | mf.field); |
952 | ret = -EINVAL; | |
4f67130a GL |
953 | } |
954 | ||
955 | return ret; | |
956 | } | |
957 | ||
57bee29d | 958 | static int mx3_camera_reqbufs(struct soc_camera_device *icd, |
4f67130a GL |
959 | struct v4l2_requestbuffers *p) |
960 | { | |
961 | return 0; | |
962 | } | |
963 | ||
964 | static unsigned int mx3_camera_poll(struct file *file, poll_table *pt) | |
965 | { | |
57bee29d | 966 | struct soc_camera_device *icd = file->private_data; |
4f67130a | 967 | |
379fa5d3 | 968 | return vb2_poll(&icd->vb2_vidq, file, pt); |
4f67130a GL |
969 | } |
970 | ||
971 | static int mx3_camera_querycap(struct soc_camera_host *ici, | |
972 | struct v4l2_capability *cap) | |
973 | { | |
974 | /* cap->name is set by the firendly caller:-> */ | |
975 | strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card)); | |
7d96c3e4 GL |
976 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
977 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
4f67130a GL |
978 | |
979 | return 0; | |
980 | } | |
981 | ||
8843d119 | 982 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd) |
4f67130a | 983 | { |
579cea03 | 984 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 985 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 986 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 | 987 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 988 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
579cea03 | 989 | unsigned long bus_flags, common_flags; |
4f67130a | 990 | u32 dw, sens_conf; |
760697be GL |
991 | const struct soc_mbus_pixelfmt *fmt; |
992 | int buswidth; | |
993 | int ret; | |
4f67130a | 994 | const struct soc_camera_format_xlate *xlate; |
7dfff953 | 995 | struct device *dev = icd->parent; |
4f67130a | 996 | |
760697be GL |
997 | fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code); |
998 | if (!fmt) | |
999 | return -EINVAL; | |
1000 | ||
4f67130a GL |
1001 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1002 | if (!xlate) { | |
0166b743 | 1003 | dev_warn(dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
1004 | return -EINVAL; |
1005 | } | |
1006 | ||
579cea03 GL |
1007 | buswidth = fmt->bits_per_sample; |
1008 | ret = test_platform_param(mx3_cam, buswidth, &bus_flags); | |
1009 | ||
760697be | 1010 | dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret); |
4f67130a GL |
1011 | |
1012 | if (ret < 0) | |
1013 | return ret; | |
1014 | ||
579cea03 GL |
1015 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1016 | if (!ret) { | |
1017 | common_flags = soc_mbus_config_compatible(&cfg, | |
1018 | bus_flags); | |
1019 | if (!common_flags) { | |
1020 | dev_warn(icd->parent, | |
1021 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1022 | cfg.flags, bus_flags); | |
1023 | return -EINVAL; | |
1024 | } | |
1025 | } else if (ret != -ENOIOCTLCMD) { | |
1026 | return ret; | |
1027 | } else { | |
1028 | common_flags = bus_flags; | |
4f67130a GL |
1029 | } |
1030 | ||
579cea03 GL |
1031 | dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n", |
1032 | cfg.flags, bus_flags, common_flags); | |
1033 | ||
4f67130a | 1034 | /* Make choices, based on platform preferences */ |
579cea03 GL |
1035 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1036 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
4f67130a | 1037 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) |
579cea03 | 1038 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
4f67130a | 1039 | else |
579cea03 | 1040 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
4f67130a GL |
1041 | } |
1042 | ||
579cea03 GL |
1043 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1044 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
4f67130a | 1045 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) |
579cea03 | 1046 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
4f67130a | 1047 | else |
579cea03 | 1048 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
4f67130a GL |
1049 | } |
1050 | ||
579cea03 GL |
1051 | if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) && |
1052 | (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) { | |
4f67130a | 1053 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) |
579cea03 | 1054 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH; |
4f67130a | 1055 | else |
579cea03 | 1056 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW; |
4f67130a GL |
1057 | } |
1058 | ||
579cea03 GL |
1059 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1060 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
4f67130a | 1061 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) |
579cea03 | 1062 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
4f67130a | 1063 | else |
579cea03 | 1064 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
4f67130a GL |
1065 | } |
1066 | ||
579cea03 GL |
1067 | cfg.flags = common_flags; |
1068 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1069 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1070 | dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n", | |
40e2e092 | 1071 | common_flags, ret); |
4f67130a | 1072 | return ret; |
40e2e092 | 1073 | } |
4f67130a GL |
1074 | |
1075 | /* | |
1076 | * So far only gated clock mode is supported. Add a line | |
1077 | * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) | | |
1078 | * below and select the required mode when supporting other | |
1079 | * synchronisation protocols. | |
1080 | */ | |
1081 | sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) & | |
1082 | ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) | | |
1083 | (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) | | |
1084 | (1 << CSI_SENS_CONF_DATA_POL_SHIFT) | | |
1085 | (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) | | |
1086 | (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) | | |
1087 | (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT)); | |
1088 | ||
1089 | /* TODO: Support RGB and YUV formats */ | |
1090 | ||
1091 | /* This has been set in mx3_camera_activate(), but we clear it above */ | |
1092 | sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
1093 | ||
579cea03 | 1094 | if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
4f67130a | 1095 | sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; |
579cea03 | 1096 | if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
4f67130a | 1097 | sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; |
579cea03 | 1098 | if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
4f67130a | 1099 | sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; |
579cea03 | 1100 | if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW) |
4f67130a GL |
1101 | sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; |
1102 | ||
1103 | /* Just do what we're asked to do */ | |
760697be | 1104 | switch (xlate->host_fmt->bits_per_sample) { |
4f67130a GL |
1105 | case 4: |
1106 | dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1107 | break; | |
1108 | case 8: | |
1109 | dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1110 | break; | |
1111 | case 10: | |
1112 | dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1113 | break; | |
1114 | default: | |
1115 | /* | |
1116 | * Actually it can only be 15 now, default is just to silence | |
1117 | * compiler warnings | |
1118 | */ | |
1119 | case 15: | |
1120 | dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1121 | } | |
1122 | ||
1123 | csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); | |
1124 | ||
0166b743 | 1125 | dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw); |
4f67130a GL |
1126 | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static struct soc_camera_host_ops mx3_soc_camera_host_ops = { | |
1131 | .owner = THIS_MODULE, | |
1132 | .add = mx3_camera_add_device, | |
1133 | .remove = mx3_camera_remove_device, | |
663ccaf4 GL |
1134 | .clock_start = mx3_camera_clock_start, |
1135 | .clock_stop = mx3_camera_clock_stop, | |
09e231b3 | 1136 | .set_crop = mx3_camera_set_crop, |
4f67130a GL |
1137 | .set_fmt = mx3_camera_set_fmt, |
1138 | .try_fmt = mx3_camera_try_fmt, | |
1139 | .get_formats = mx3_camera_get_formats, | |
379fa5d3 | 1140 | .init_videobuf2 = mx3_camera_init_videobuf, |
4f67130a GL |
1141 | .reqbufs = mx3_camera_reqbufs, |
1142 | .poll = mx3_camera_poll, | |
1143 | .querycap = mx3_camera_querycap, | |
1144 | .set_bus_param = mx3_camera_set_bus_param, | |
1145 | }; | |
1146 | ||
4c62e976 | 1147 | static int mx3_camera_probe(struct platform_device *pdev) |
4f67130a | 1148 | { |
4dbfd040 | 1149 | struct mx3_camera_pdata *pdata = pdev->dev.platform_data; |
4f67130a GL |
1150 | struct mx3_camera_dev *mx3_cam; |
1151 | struct resource *res; | |
1152 | void __iomem *base; | |
1153 | int err = 0; | |
1154 | struct soc_camera_host *soc_host; | |
1155 | ||
1156 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
72f28744 GL |
1157 | base = devm_ioremap_resource(&pdev->dev, res); |
1158 | if (IS_ERR(base)) | |
1159 | return PTR_ERR(base); | |
4f67130a | 1160 | |
4dbfd040 GL |
1161 | if (!pdata) |
1162 | return -EINVAL; | |
1163 | ||
72f28744 | 1164 | mx3_cam = devm_kzalloc(&pdev->dev, sizeof(*mx3_cam), GFP_KERNEL); |
4f67130a GL |
1165 | if (!mx3_cam) { |
1166 | dev_err(&pdev->dev, "Could not allocate mx3 camera object\n"); | |
72f28744 | 1167 | return -ENOMEM; |
4f67130a | 1168 | } |
4f67130a | 1169 | |
72f28744 GL |
1170 | mx3_cam->clk = devm_clk_get(&pdev->dev, NULL); |
1171 | if (IS_ERR(mx3_cam->clk)) | |
1172 | return PTR_ERR(mx3_cam->clk); | |
4f67130a | 1173 | |
4dbfd040 GL |
1174 | mx3_cam->pdata = pdata; |
1175 | mx3_cam->platform_flags = pdata->flags; | |
c4ede4ce | 1176 | if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) { |
5d28d525 GL |
1177 | /* |
1178 | * Platform hasn't set available data widths. This is bad. | |
1179 | * Warn and use a default. | |
1180 | */ | |
4f67130a GL |
1181 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1182 | "data widths, using default 8 bit\n"); | |
1183 | mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8; | |
1184 | } | |
579cea03 GL |
1185 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4) |
1186 | mx3_cam->width_flags = 1 << 3; | |
1187 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
1188 | mx3_cam->width_flags |= 1 << 7; | |
1189 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
1190 | mx3_cam->width_flags |= 1 << 9; | |
1191 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
1192 | mx3_cam->width_flags |= 1 << 14; | |
4f67130a | 1193 | |
4dbfd040 | 1194 | mx3_cam->mclk = pdata->mclk_10khz * 10000; |
4f67130a GL |
1195 | if (!mx3_cam->mclk) { |
1196 | dev_warn(&pdev->dev, | |
1197 | "mclk_10khz == 0! Please, fix your platform data. " | |
1198 | "Using default 20MHz\n"); | |
1199 | mx3_cam->mclk = 20000000; | |
1200 | } | |
1201 | ||
1202 | /* list of video-buffers */ | |
1203 | INIT_LIST_HEAD(&mx3_cam->capture); | |
1204 | spin_lock_init(&mx3_cam->lock); | |
1205 | ||
4f67130a | 1206 | mx3_cam->base = base; |
4f67130a GL |
1207 | |
1208 | soc_host = &mx3_cam->soc_host; | |
1209 | soc_host->drv_name = MX3_CAM_DRV_NAME; | |
1210 | soc_host->ops = &mx3_soc_camera_host_ops; | |
1211 | soc_host->priv = mx3_cam; | |
979ea1dd | 1212 | soc_host->v4l2_dev.dev = &pdev->dev; |
4f67130a | 1213 | soc_host->nr = pdev->id; |
eff505fa | 1214 | |
379fa5d3 | 1215 | mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
72f28744 GL |
1216 | if (IS_ERR(mx3_cam->alloc_ctx)) |
1217 | return PTR_ERR(mx3_cam->alloc_ctx); | |
379fa5d3 | 1218 | |
4dbfd040 GL |
1219 | if (pdata->asd_sizes) { |
1220 | soc_host->asd = pdata->asd; | |
1221 | soc_host->asd_sizes = pdata->asd_sizes; | |
1222 | } | |
1223 | ||
4f67130a GL |
1224 | err = soc_camera_host_register(soc_host); |
1225 | if (err) | |
1226 | goto ecamhostreg; | |
1227 | ||
1228 | /* IDMAC interface */ | |
1229 | dmaengine_get(); | |
1230 | ||
1231 | return 0; | |
1232 | ||
1233 | ecamhostreg: | |
379fa5d3 | 1234 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
4f67130a GL |
1235 | return err; |
1236 | } | |
1237 | ||
4c62e976 | 1238 | static int mx3_camera_remove(struct platform_device *pdev) |
4f67130a | 1239 | { |
eff505fa GL |
1240 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1241 | struct mx3_camera_dev *mx3_cam = container_of(soc_host, | |
1242 | struct mx3_camera_dev, soc_host); | |
4f67130a | 1243 | |
eff505fa | 1244 | soc_camera_host_unregister(soc_host); |
4f67130a | 1245 | |
4f67130a GL |
1246 | /* |
1247 | * The channel has either not been allocated, | |
1248 | * or should have been released | |
1249 | */ | |
1250 | if (WARN_ON(mx3_cam->idmac_channel[0])) | |
1251 | dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan); | |
1252 | ||
379fa5d3 GL |
1253 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1254 | ||
4f67130a GL |
1255 | dmaengine_put(); |
1256 | ||
4f67130a GL |
1257 | return 0; |
1258 | } | |
1259 | ||
1260 | static struct platform_driver mx3_camera_driver = { | |
0cb29868 | 1261 | .driver = { |
4f67130a GL |
1262 | .name = MX3_CAM_DRV_NAME, |
1263 | }, | |
1264 | .probe = mx3_camera_probe, | |
4c62e976 | 1265 | .remove = mx3_camera_remove, |
4f67130a GL |
1266 | }; |
1267 | ||
1d6629b1 | 1268 | module_platform_driver(mx3_camera_driver); |
4f67130a GL |
1269 | |
1270 | MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); | |
1271 | MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>"); | |
1272 | MODULE_LICENSE("GPL v2"); | |
64dc3c1a | 1273 | MODULE_VERSION("0.2.3"); |
40e2e092 | 1274 | MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME); |