Commit | Line | Data |
---|---|---|
3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
283e4a82 | 6 | * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr> |
3bc43840 GL |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
3bc43840 GL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
7102b773 | 16 | #include <linux/io.h> |
3bc43840 | 17 | #include <linux/delay.h> |
283e4a82 | 18 | #include <linux/device.h> |
3bc43840 | 19 | #include <linux/dma-mapping.h> |
8efdb135 | 20 | #include <linux/err.h> |
3bc43840 GL |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/mm.h> | |
26 | #include <linux/moduleparam.h> | |
283e4a82 | 27 | #include <linux/of.h> |
3bc43840 | 28 | #include <linux/time.h> |
3bc43840 GL |
29 | #include <linux/device.h> |
30 | #include <linux/platform_device.h> | |
3bc43840 | 31 | #include <linux/clk.h> |
d514edac | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1e77d55a RJ |
34 | #include <linux/dmaengine.h> |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/dma/pxa-dma.h> | |
3bc43840 | 37 | |
283e4a82 RJ |
38 | #include <media/v4l2-async.h> |
39 | #include <media/v4l2-clk.h> | |
3bc43840 | 40 | #include <media/v4l2-common.h> |
283e4a82 RJ |
41 | #include <media/v4l2-device.h> |
42 | #include <media/v4l2-ioctl.h> | |
e9a1d94f | 43 | #include <media/v4l2-of.h> |
3bc43840 | 44 | |
283e4a82 RJ |
45 | #include <media/drv-intf/soc_mediabus.h> |
46 | #include <media/videobuf2-dma-sg.h> | |
47 | ||
3bc43840 GL |
48 | #include <linux/videodev2.h> |
49 | ||
a71daaa1 | 50 | #include <linux/platform_data/media/camera-pxa.h> |
3bc43840 | 51 | |
64dc3c1a | 52 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
53 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
54 | ||
283e4a82 RJ |
55 | #define DEFAULT_WIDTH 640 |
56 | #define DEFAULT_HEIGHT 480 | |
57 | ||
5ca11fa3 EM |
58 | /* Camera Interface */ |
59 | #define CICR0 0x0000 | |
60 | #define CICR1 0x0004 | |
61 | #define CICR2 0x0008 | |
62 | #define CICR3 0x000C | |
63 | #define CICR4 0x0010 | |
64 | #define CISR 0x0014 | |
65 | #define CIFR 0x0018 | |
66 | #define CITOR 0x001C | |
67 | #define CIBR0 0x0028 | |
68 | #define CIBR1 0x0030 | |
69 | #define CIBR2 0x0038 | |
70 | ||
71 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
72 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
73 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
74 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
75 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
76 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
77 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
78 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
79 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
80 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
81 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
82 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
83 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
84 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
85 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
86 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
87 | ||
88 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
89 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
90 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
91 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
92 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
93 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
94 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
95 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
96 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
97 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
98 | ||
99 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
100 | wait count mask */ | |
101 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
102 | wait count mask */ | |
103 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
104 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
105 | wait count mask */ | |
106 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
107 | wait count mask */ | |
108 | ||
109 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
110 | wait count mask */ | |
111 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
112 | wait count mask */ | |
113 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
114 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
115 | wait count mask */ | |
116 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
117 | ||
118 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
119 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
120 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
121 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
122 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
123 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
124 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
125 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
126 | ||
127 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
128 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
129 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
130 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
131 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
132 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
133 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
134 | #define CISR_EOL (1 << 8) /* End of line */ | |
135 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
136 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
137 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
138 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
139 | #define CISR_EOF (1 << 3) /* End of frame */ | |
140 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
141 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
142 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
143 | ||
144 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
145 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
146 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
147 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
148 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
149 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
150 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
151 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
152 | ||
7102b773 GL |
153 | #define CICR0_SIM_MP (0 << 24) |
154 | #define CICR0_SIM_SP (1 << 24) | |
155 | #define CICR0_SIM_MS (2 << 24) | |
156 | #define CICR0_SIM_EP (3 << 24) | |
157 | #define CICR0_SIM_ES (4 << 24) | |
158 | ||
159 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
160 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
161 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
162 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
163 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
164 | |
165 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
166 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
167 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
168 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
169 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
170 | ||
171 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
172 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
173 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
174 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
175 | ||
3bc43840 GL |
176 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
177 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
178 | CICR0_EOFM | CICR0_FOM) | |
179 | ||
b36bcbd6 | 180 | #define sensor_call(cam, o, f, args...) \ |
283e4a82 RJ |
181 | v4l2_subdev_call(cam->sensor, o, f, ##args) |
182 | ||
183 | /* | |
184 | * Format handling | |
185 | */ | |
186 | /** | |
187 | * struct soc_camera_format_xlate - match between host and sensor formats | |
188 | * @code: code of a sensor provided format | |
189 | * @host_fmt: host format after host translation from code | |
190 | * | |
191 | * Host and sensor translation structure. Used in table of host and sensor | |
192 | * formats matchings in soc_camera_device. A host can override the generic list | |
193 | * generation by implementing get_formats(), and use it for format checks and | |
194 | * format setup. | |
195 | */ | |
196 | struct soc_camera_format_xlate { | |
197 | u32 code; | |
198 | const struct soc_mbus_pixelfmt *host_fmt; | |
199 | }; | |
b36bcbd6 | 200 | |
3bc43840 GL |
201 | /* |
202 | * Structures | |
203 | */ | |
a5462e5b MR |
204 | enum pxa_camera_active_dma { |
205 | DMA_Y = 0x1, | |
206 | DMA_U = 0x2, | |
207 | DMA_V = 0x4, | |
208 | }; | |
209 | ||
3bc43840 GL |
210 | /* buffer for one video frame */ |
211 | struct pxa_buffer { | |
212 | /* common v4l buffer stuff -- must be first */ | |
e009ebd5 RJ |
213 | struct vb2_v4l2_buffer vbuf; |
214 | struct list_head queue; | |
27ffaeb0 | 215 | u32 code; |
e009ebd5 | 216 | int nb_planes; |
a5462e5b | 217 | /* our descriptor lists for Y, U and V channels */ |
1e77d55a RJ |
218 | struct dma_async_tx_descriptor *descs[3]; |
219 | dma_cookie_t cookie[3]; | |
220 | struct scatterlist *sg[3]; | |
221 | int sg_len[3]; | |
e009ebd5 | 222 | size_t plane_sizes[3]; |
760697be GL |
223 | int inwork; |
224 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
225 | }; |
226 | ||
3bc43840 | 227 | struct pxa_camera_dev { |
283e4a82 RJ |
228 | struct v4l2_device v4l2_dev; |
229 | struct video_device vdev; | |
230 | struct v4l2_async_notifier notifier; | |
231 | struct vb2_queue vb2_vq; | |
232 | struct v4l2_subdev *sensor; | |
233 | struct soc_camera_format_xlate *user_formats; | |
234 | const struct soc_camera_format_xlate *current_fmt; | |
235 | struct v4l2_pix_format current_pix; | |
236 | ||
237 | struct v4l2_async_subdev asd; | |
238 | struct v4l2_async_subdev *asds[1]; | |
239 | ||
5d28d525 GL |
240 | /* |
241 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 242 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
243 | * one camera, they will have to modify this driver too |
244 | */ | |
3bc43840 GL |
245 | struct clk *clk; |
246 | ||
247 | unsigned int irq; | |
248 | void __iomem *base; | |
a5462e5b | 249 | |
e7c50688 | 250 | int channels; |
1e77d55a | 251 | struct dma_chan *dma_chans[3]; |
3bc43840 | 252 | |
3bc43840 GL |
253 | struct pxacamera_platform_data *pdata; |
254 | struct resource *res; | |
255 | unsigned long platform_flags; | |
cf34cba7 GL |
256 | unsigned long ciclk; |
257 | unsigned long mclk; | |
258 | u32 mclk_divisor; | |
283e4a82 | 259 | struct v4l2_clk *mclk_clk; |
679419aa | 260 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
261 | |
262 | struct list_head capture; | |
263 | ||
264 | spinlock_t lock; | |
283e4a82 | 265 | struct mutex mlock; |
61634976 | 266 | unsigned int buf_sequence; |
3bc43840 | 267 | |
3bc43840 | 268 | struct pxa_buffer *active; |
e623ebe6 | 269 | struct tasklet_struct task_eof; |
3f6ac497 RJ |
270 | |
271 | u32 save_cicr[5]; | |
3bc43840 GL |
272 | }; |
273 | ||
6a6c8786 GL |
274 | struct pxa_cam { |
275 | unsigned long flags; | |
276 | }; | |
277 | ||
3bc43840 GL |
278 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
279 | ||
283e4a82 RJ |
280 | /* |
281 | * Format translation functions | |
282 | */ | |
283 | const struct soc_camera_format_xlate *soc_mbus_xlate_by_fourcc( | |
284 | struct soc_camera_format_xlate *user_formats, unsigned int fourcc) | |
285 | { | |
286 | unsigned int i; | |
287 | ||
288 | for (i = 0; user_formats[i].code; i++) | |
289 | if (user_formats[i].host_fmt->fourcc == fourcc) | |
290 | return user_formats + i; | |
291 | return NULL; | |
292 | } | |
293 | ||
294 | static struct soc_camera_format_xlate *soc_mbus_build_fmts_xlate( | |
295 | struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev, | |
296 | int (*get_formats)(struct v4l2_device *, unsigned int, | |
297 | struct soc_camera_format_xlate *xlate)) | |
295ab497 | 298 | { |
283e4a82 RJ |
299 | unsigned int i, fmts = 0, raw_fmts = 0; |
300 | int ret; | |
301 | struct v4l2_subdev_mbus_code_enum code = { | |
302 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
303 | }; | |
304 | struct soc_camera_format_xlate *user_formats; | |
305 | ||
306 | while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) { | |
307 | raw_fmts++; | |
308 | code.index++; | |
309 | } | |
310 | ||
311 | /* | |
312 | * First pass - only count formats this host-sensor | |
313 | * configuration can provide | |
314 | */ | |
315 | for (i = 0; i < raw_fmts; i++) { | |
316 | ret = get_formats(v4l2_dev, i, NULL); | |
317 | if (ret < 0) | |
318 | return ERR_PTR(ret); | |
319 | fmts += ret; | |
320 | } | |
321 | ||
322 | if (!fmts) | |
323 | return ERR_PTR(-ENXIO); | |
295ab497 | 324 | |
283e4a82 RJ |
325 | user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL); |
326 | if (!user_formats) | |
327 | return ERR_PTR(-ENOMEM); | |
328 | ||
329 | /* Second pass - actually fill data formats */ | |
330 | fmts = 0; | |
331 | for (i = 0; i < raw_fmts; i++) { | |
332 | ret = get_formats(v4l2_dev, i, user_formats + fmts); | |
333 | if (ret < 0) | |
334 | goto egfmt; | |
335 | fmts += ret; | |
336 | } | |
337 | user_formats[fmts].code = 0; | |
338 | ||
339 | return user_formats; | |
340 | egfmt: | |
341 | kfree(user_formats); | |
342 | return ERR_PTR(ret); | |
295ab497 RJ |
343 | } |
344 | ||
3bc43840 GL |
345 | /* |
346 | * Videobuf operations | |
347 | */ | |
e009ebd5 | 348 | static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb) |
3bc43840 | 349 | { |
e009ebd5 | 350 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
3bc43840 | 351 | |
e009ebd5 | 352 | return container_of(vbuf, struct pxa_buffer, vbuf); |
3bc43840 GL |
353 | } |
354 | ||
e009ebd5 | 355 | static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev) |
3bc43840 | 356 | { |
283e4a82 RJ |
357 | return pcdev->v4l2_dev.dev; |
358 | } | |
359 | ||
360 | static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev) | |
361 | { | |
362 | return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev); | |
37f5aefd RJ |
363 | } |
364 | ||
1e77d55a | 365 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
e5853918 RJ |
366 | enum pxa_camera_active_dma act_dma); |
367 | ||
1e77d55a | 368 | static void pxa_camera_dma_irq_y(void *data) |
e5853918 RJ |
369 | { |
370 | struct pxa_camera_dev *pcdev = data; | |
371 | ||
1e77d55a | 372 | pxa_camera_dma_irq(pcdev, DMA_Y); |
e5853918 RJ |
373 | } |
374 | ||
1e77d55a | 375 | static void pxa_camera_dma_irq_u(void *data) |
e5853918 RJ |
376 | { |
377 | struct pxa_camera_dev *pcdev = data; | |
378 | ||
1e77d55a | 379 | pxa_camera_dma_irq(pcdev, DMA_U); |
e5853918 RJ |
380 | } |
381 | ||
1e77d55a | 382 | static void pxa_camera_dma_irq_v(void *data) |
e5853918 RJ |
383 | { |
384 | struct pxa_camera_dev *pcdev = data; | |
385 | ||
1e77d55a | 386 | pxa_camera_dma_irq(pcdev, DMA_V); |
e5853918 RJ |
387 | } |
388 | ||
37f5aefd RJ |
389 | /** |
390 | * pxa_init_dma_channel - init dma descriptors | |
391 | * @pcdev: pxa camera device | |
e009ebd5 | 392 | * @vb: videobuffer2 buffer |
37f5aefd RJ |
393 | * @dma: dma video buffer |
394 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
395 | * @cibr: camera Receive Buffer Register | |
37f5aefd RJ |
396 | * |
397 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
37f5aefd | 398 | * |
1e77d55a | 399 | * Returns 0 if success or -ENOMEM if no memory is available |
37f5aefd | 400 | */ |
a5462e5b | 401 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
e009ebd5 RJ |
402 | struct pxa_buffer *buf, int channel, |
403 | struct scatterlist *sg, int sglen) | |
a5462e5b | 404 | { |
1e77d55a | 405 | struct dma_chan *dma_chan = pcdev->dma_chans[channel]; |
1e77d55a RJ |
406 | struct dma_async_tx_descriptor *tx; |
407 | ||
408 | tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM, | |
409 | DMA_PREP_INTERRUPT | DMA_CTRL_REUSE); | |
410 | if (!tx) { | |
e009ebd5 | 411 | dev_err(pcdev_to_dev(pcdev), |
1e77d55a RJ |
412 | "dmaengine_prep_slave_sg failed\n"); |
413 | goto fail; | |
a5462e5b MR |
414 | } |
415 | ||
1e77d55a RJ |
416 | tx->callback_param = pcdev; |
417 | switch (channel) { | |
418 | case 0: | |
419 | tx->callback = pxa_camera_dma_irq_y; | |
420 | break; | |
421 | case 1: | |
422 | tx->callback = pxa_camera_dma_irq_u; | |
423 | break; | |
424 | case 2: | |
425 | tx->callback = pxa_camera_dma_irq_v; | |
426 | break; | |
37f5aefd RJ |
427 | } |
428 | ||
1e77d55a | 429 | buf->descs[channel] = tx; |
a5462e5b | 430 | return 0; |
1e77d55a | 431 | fail: |
e009ebd5 RJ |
432 | dev_dbg(pcdev_to_dev(pcdev), |
433 | "%s (vb=%p) dma_tx=%p\n", | |
434 | __func__, buf, tx); | |
1e77d55a RJ |
435 | |
436 | return -ENOMEM; | |
a5462e5b MR |
437 | } |
438 | ||
256b0233 RJ |
439 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
440 | struct pxa_buffer *buf) | |
441 | { | |
442 | buf->active_dma = DMA_Y; | |
283e4a82 | 443 | if (buf->nb_planes == 3) |
256b0233 RJ |
444 | buf->active_dma |= DMA_U | DMA_V; |
445 | } | |
446 | ||
256b0233 RJ |
447 | /** |
448 | * pxa_dma_start_channels - start DMA channel for active buffer | |
449 | * @pcdev: pxa camera device | |
450 | * | |
451 | * Initialize DMA channels to the beginning of the active video buffer, and | |
452 | * start these channels. | |
453 | */ | |
454 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
455 | { | |
456 | int i; | |
457 | struct pxa_buffer *active; | |
458 | ||
459 | active = pcdev->active; | |
460 | ||
461 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 462 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
463 | "%s (channel=%d)\n", __func__, i); |
464 | dma_async_issue_pending(pcdev->dma_chans[i]); | |
256b0233 RJ |
465 | } |
466 | } | |
467 | ||
468 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
469 | { | |
470 | int i; | |
471 | ||
472 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 473 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 474 | "%s (channel=%d)\n", __func__, i); |
1e77d55a | 475 | dmaengine_terminate_all(pcdev->dma_chans[i]); |
256b0233 RJ |
476 | } |
477 | } | |
478 | ||
256b0233 RJ |
479 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
480 | struct pxa_buffer *buf) | |
481 | { | |
482 | int i; | |
256b0233 RJ |
483 | |
484 | for (i = 0; i < pcdev->channels; i++) { | |
1e77d55a | 485 | buf->cookie[i] = dmaengine_submit(buf->descs[i]); |
e009ebd5 | 486 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
487 | "%s (channel=%d) : submit vb=%p cookie=%d\n", |
488 | __func__, i, buf, buf->descs[i]->cookie); | |
ae7410e7 | 489 | } |
256b0233 RJ |
490 | } |
491 | ||
492 | /** | |
493 | * pxa_camera_start_capture - start video capturing | |
494 | * @pcdev: camera device | |
495 | * | |
496 | * Launch capturing. DMA channels should not be active yet. They should get | |
497 | * activated at the end of frame interrupt, to capture only whole frames, and | |
498 | * never begin the capture of a partial frame. | |
499 | */ | |
500 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
501 | { | |
a47f6be4 | 502 | unsigned long cicr0; |
256b0233 | 503 | |
e009ebd5 | 504 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
e623ebe6 | 505 | __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); |
256b0233 RJ |
506 | /* Enable End-Of-Frame Interrupt */ |
507 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
508 | cicr0 &= ~CICR0_EOFM; | |
509 | __raw_writel(cicr0, pcdev->base + CICR0); | |
510 | } | |
511 | ||
512 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
513 | { | |
514 | unsigned long cicr0; | |
515 | ||
516 | pxa_dma_stop_channels(pcdev); | |
517 | ||
518 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
519 | __raw_writel(cicr0, pcdev->base + CICR0); | |
520 | ||
8c62e221 | 521 | pcdev->active = NULL; |
e009ebd5 | 522 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
3bc43840 GL |
523 | } |
524 | ||
a5462e5b | 525 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
a5462e5b MR |
526 | struct pxa_buffer *buf) |
527 | { | |
e009ebd5 | 528 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; |
61634976 | 529 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
e009ebd5 | 530 | |
a5462e5b | 531 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
e009ebd5 RJ |
532 | list_del_init(&buf->queue); |
533 | vb->timestamp = ktime_get_ns(); | |
61634976 RJ |
534 | vbuf->sequence = pcdev->buf_sequence++; |
535 | vbuf->field = V4L2_FIELD_NONE; | |
e009ebd5 RJ |
536 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); |
537 | dev_dbg(pcdev_to_dev(pcdev), "%s dequeud buffer (buf=0x%p)\n", | |
538 | __func__, buf); | |
a5462e5b MR |
539 | |
540 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 541 | pxa_camera_stop_capture(pcdev); |
a5462e5b MR |
542 | return; |
543 | } | |
544 | ||
545 | pcdev->active = list_entry(pcdev->capture.next, | |
e009ebd5 | 546 | struct pxa_buffer, queue); |
a5462e5b MR |
547 | } |
548 | ||
256b0233 RJ |
549 | /** |
550 | * pxa_camera_check_link_miss - check missed DMA linking | |
551 | * @pcdev: camera device | |
552 | * | |
553 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
554 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 555 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
556 | * This function restarts the capture for this corner case, where : |
557 | * - DADR() == DADDR_STOP | |
558 | * - a videobuffer is queued on the pcdev->capture list | |
559 | * | |
560 | * Please check the "DMA hot chaining timeslice issue" in | |
561 | * Documentation/video4linux/pxa_camera.txt | |
562 | * | |
563 | * Context: should only be called within the dma irq handler | |
564 | */ | |
1e77d55a RJ |
565 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev, |
566 | dma_cookie_t last_submitted, | |
567 | dma_cookie_t last_issued) | |
256b0233 | 568 | { |
1e77d55a | 569 | bool is_dma_stopped = last_submitted != last_issued; |
256b0233 | 570 | |
e009ebd5 | 571 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a | 572 | "%s : top queued buffer=%p, is_dma_stopped=%d\n", |
256b0233 | 573 | __func__, pcdev->active, is_dma_stopped); |
1e77d55a | 574 | |
256b0233 RJ |
575 | if (pcdev->active && is_dma_stopped) |
576 | pxa_camera_start_capture(pcdev); | |
577 | } | |
578 | ||
1e77d55a | 579 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
a5462e5b | 580 | enum pxa_camera_active_dma act_dma) |
3bc43840 | 581 | { |
1e77d55a | 582 | struct pxa_buffer *buf, *last_buf; |
3bc43840 | 583 | unsigned long flags; |
1e77d55a RJ |
584 | u32 camera_status, overrun; |
585 | int chan; | |
1e77d55a RJ |
586 | enum dma_status last_status; |
587 | dma_cookie_t last_issued; | |
3bc43840 GL |
588 | |
589 | spin_lock_irqsave(&pcdev->lock, flags); | |
590 | ||
256b0233 | 591 | camera_status = __raw_readl(pcdev->base + CISR); |
295ab497 | 592 | dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n", |
1e77d55a | 593 | camera_status, act_dma); |
256b0233 RJ |
594 | overrun = CISR_IFO_0; |
595 | if (pcdev->channels == 3) | |
596 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 597 | |
8c62e221 RJ |
598 | /* |
599 | * pcdev->active should not be NULL in DMA irq handler. | |
600 | * | |
601 | * But there is one corner case : if capture was stopped due to an | |
602 | * overrun of channel 1, and at that same channel 2 was completed. | |
603 | * | |
604 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
605 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
606 | * DMA irq handler will already be pending for channel 2. So on entering | |
607 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
608 | * that is normal. | |
609 | */ | |
610 | if (!pcdev->active) | |
3bc43840 | 611 | goto out; |
3bc43840 | 612 | |
e009ebd5 RJ |
613 | buf = pcdev->active; |
614 | WARN_ON(buf->inwork || list_empty(&buf->queue)); | |
3bc43840 | 615 | |
1e77d55a RJ |
616 | /* |
617 | * It's normal if the last frame creates an overrun, as there | |
618 | * are no more DMA descriptors to fetch from QCI fifos | |
619 | */ | |
620 | switch (act_dma) { | |
621 | case DMA_U: | |
622 | chan = 1; | |
623 | break; | |
624 | case DMA_V: | |
625 | chan = 2; | |
626 | break; | |
627 | default: | |
628 | chan = 0; | |
629 | break; | |
630 | } | |
631 | last_buf = list_entry(pcdev->capture.prev, | |
e009ebd5 | 632 | struct pxa_buffer, queue); |
1e77d55a RJ |
633 | last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan], |
634 | last_buf->cookie[chan], | |
635 | NULL, &last_issued); | |
636 | if (camera_status & overrun && | |
637 | last_status != DMA_COMPLETE) { | |
295ab497 | 638 | dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n", |
1e77d55a RJ |
639 | camera_status); |
640 | pxa_camera_stop_capture(pcdev); | |
e009ebd5 | 641 | list_for_each_entry(buf, &pcdev->capture, queue) |
1e77d55a RJ |
642 | pxa_dma_add_tail_buf(pcdev, buf); |
643 | pxa_camera_start_capture(pcdev); | |
644 | goto out; | |
645 | } | |
646 | buf->active_dma &= ~act_dma; | |
647 | if (!buf->active_dma) { | |
e009ebd5 | 648 | pxa_camera_wakeup(pcdev, buf); |
1e77d55a RJ |
649 | pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan], |
650 | last_issued); | |
256b0233 | 651 | } |
3bc43840 GL |
652 | |
653 | out: | |
654 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
655 | } | |
656 | ||
40e2e092 GL |
657 | static u32 mclk_get_divisor(struct platform_device *pdev, |
658 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 659 | { |
cf34cba7 GL |
660 | unsigned long mclk = pcdev->mclk; |
661 | u32 div; | |
3bc43840 GL |
662 | unsigned long lcdclk; |
663 | ||
cf34cba7 GL |
664 | lcdclk = clk_get_rate(pcdev->clk); |
665 | pcdev->ciclk = lcdclk; | |
3bc43840 | 666 | |
cf34cba7 GL |
667 | /* mclk <= ciclk / 4 (27.4.2) */ |
668 | if (mclk > lcdclk / 4) { | |
669 | mclk = lcdclk / 4; | |
295ab497 RJ |
670 | dev_warn(pcdev_to_dev(pcdev), |
671 | "Limiting master clock to %lu\n", mclk); | |
cf34cba7 GL |
672 | } |
673 | ||
674 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
675 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 676 | |
cf34cba7 GL |
677 | /* If we're not supplying MCLK, leave it at 0 */ |
678 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
679 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 680 | |
295ab497 | 681 | dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 682 | lcdclk, mclk, div); |
3bc43840 GL |
683 | |
684 | return div; | |
685 | } | |
686 | ||
cf34cba7 GL |
687 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
688 | unsigned long pclk) | |
689 | { | |
690 | /* We want a timeout > 1 pixel time, not ">=" */ | |
691 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
692 | ||
693 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
694 | } | |
695 | ||
7102b773 | 696 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 697 | { |
3bc43840 GL |
698 | u32 cicr4 = 0; |
699 | ||
5ca11fa3 EM |
700 | /* disable all interrupts */ |
701 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
702 | |
703 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
704 | cicr4 |= CICR4_PCLK_EN; | |
705 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
706 | cicr4 |= CICR4_MCLK_EN; | |
707 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
708 | cicr4 |= CICR4_PCP; | |
709 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
710 | cicr4 |= CICR4_HSP; | |
711 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
712 | cicr4 |= CICR4_VSP; | |
713 | ||
cf34cba7 GL |
714 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
715 | ||
716 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
717 | /* Initialise the timeout under the assumption pclk = mclk */ | |
718 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
719 | else | |
720 | /* "Safe default" - 13MHz */ | |
721 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 722 | |
91acd962 | 723 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
724 | } |
725 | ||
7102b773 | 726 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 727 | { |
91acd962 | 728 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
729 | } |
730 | ||
e623ebe6 | 731 | static void pxa_camera_eof(unsigned long arg) |
3bc43840 | 732 | { |
e623ebe6 RJ |
733 | struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg; |
734 | unsigned long cifr; | |
256b0233 | 735 | struct pxa_buffer *buf; |
3bc43840 | 736 | |
e009ebd5 | 737 | dev_dbg(pcdev_to_dev(pcdev), |
e623ebe6 RJ |
738 | "Camera interrupt status 0x%x\n", |
739 | __raw_readl(pcdev->base + CISR)); | |
740 | ||
741 | /* Reset the FIFOs */ | |
742 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
743 | __raw_writel(cifr, pcdev->base + CIFR); | |
744 | ||
745 | pcdev->active = list_first_entry(&pcdev->capture, | |
e009ebd5 RJ |
746 | struct pxa_buffer, queue); |
747 | buf = pcdev->active; | |
e623ebe6 RJ |
748 | pxa_videobuf_set_actdma(pcdev, buf); |
749 | ||
750 | pxa_dma_start_channels(pcdev); | |
751 | } | |
752 | ||
753 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
754 | { | |
755 | struct pxa_camera_dev *pcdev = data; | |
756 | unsigned long status, cicr0; | |
757 | ||
5ca11fa3 | 758 | status = __raw_readl(pcdev->base + CISR); |
e009ebd5 | 759 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 760 | "Camera interrupt status 0x%lx\n", status); |
3bc43840 | 761 | |
e7c50688 GL |
762 | if (!status) |
763 | return IRQ_NONE; | |
764 | ||
5ca11fa3 | 765 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
766 | |
767 | if (status & CISR_EOF) { | |
5ca11fa3 EM |
768 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
769 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e623ebe6 | 770 | tasklet_schedule(&pcdev->task_eof); |
e7c50688 GL |
771 | } |
772 | ||
3bc43840 GL |
773 | return IRQ_HANDLED; |
774 | } | |
775 | ||
ad5f2e85 GL |
776 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
777 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 778 | { |
ad5f2e85 GL |
779 | /* |
780 | * Platform specified synchronization and pixel clock polarities are | |
781 | * only a recommendation and are only used during probing. The PXA270 | |
782 | * quick capture interface supports both. | |
783 | */ | |
784 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
785 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
786 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
787 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
788 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
789 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
790 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
791 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
792 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
793 | |
794 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
795 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
796 | return 0; | |
ad5f2e85 | 797 | |
679419aa | 798 | return -EINVAL; |
ad5f2e85 GL |
799 | } |
800 | ||
283e4a82 | 801 | static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev, |
6a6c8786 | 802 | unsigned long flags, __u32 pixfmt) |
ad5f2e85 | 803 | { |
6a6c8786 | 804 | unsigned long dw, bpp; |
32536108 | 805 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
b36bcbd6 | 806 | int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top); |
32536108 GL |
807 | |
808 | if (ret < 0) | |
809 | y_skip_top = 0; | |
3bc43840 | 810 | |
5d28d525 GL |
811 | /* |
812 | * Datawidth is now guaranteed to be equal to one of the three values. | |
813 | * We fix bit-per-pixel equal to data-width... | |
814 | */ | |
283e4a82 | 815 | switch (pcdev->current_fmt->host_fmt->bits_per_sample) { |
679419aa | 816 | case 10: |
3bc43840 GL |
817 | dw = 4; |
818 | bpp = 0x40; | |
819 | break; | |
679419aa | 820 | case 9: |
3bc43840 GL |
821 | dw = 3; |
822 | bpp = 0x20; | |
823 | break; | |
824 | default: | |
5d28d525 GL |
825 | /* |
826 | * Actually it can only be 8 now, | |
827 | * default is just to silence compiler warnings | |
828 | */ | |
679419aa | 829 | case 8: |
3bc43840 GL |
830 | dw = 2; |
831 | bpp = 0; | |
832 | } | |
833 | ||
834 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
835 | cicr4 |= CICR4_PCLK_EN; | |
836 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
837 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 838 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 839 | cicr4 |= CICR4_PCP; |
679419aa | 840 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 841 | cicr4 |= CICR4_HSP; |
679419aa | 842 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
843 | cicr4 |= CICR4_VSP; |
844 | ||
5ca11fa3 | 845 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 846 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 847 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 848 | |
283e4a82 | 849 | cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw; |
a5462e5b MR |
850 | |
851 | switch (pixfmt) { | |
852 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 853 | pcdev->channels = 3; |
a5462e5b | 854 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
855 | /* |
856 | * Normally, pxa bus wants as input UYVY format. We allow all | |
857 | * reorderings of the YUV422 format, as no processing is done, | |
858 | * and the YUV stream is just passed through without any | |
859 | * transformation. Note that UYVY is the only format that | |
860 | * should be used if pxa framebuffer Overlay2 is used. | |
861 | */ | |
862 | case V4L2_PIX_FMT_UYVY: | |
863 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 864 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 865 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
866 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
867 | break; | |
868 | case V4L2_PIX_FMT_RGB555: | |
869 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
870 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
871 | break; | |
872 | case V4L2_PIX_FMT_RGB565: | |
873 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
874 | break; | |
875 | } | |
876 | ||
5ca11fa3 | 877 | cicr2 = 0; |
283e4a82 | 878 | cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) | |
32536108 | 879 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 880 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
881 | |
882 | __raw_writel(cicr1, pcdev->base + CICR1); | |
883 | __raw_writel(cicr2, pcdev->base + CICR2); | |
884 | __raw_writel(cicr3, pcdev->base + CICR3); | |
885 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
886 | |
887 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
888 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
889 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
890 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
891 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
892 | } |
893 | ||
6f28435d RJ |
894 | /* |
895 | * Videobuf2 section | |
896 | */ | |
897 | static void pxa_buffer_cleanup(struct pxa_buffer *buf) | |
898 | { | |
899 | int i; | |
900 | ||
901 | for (i = 0; i < 3 && buf->descs[i]; i++) { | |
902 | dmaengine_desc_free(buf->descs[i]); | |
903 | kfree(buf->sg[i]); | |
904 | buf->descs[i] = NULL; | |
905 | buf->sg[i] = NULL; | |
906 | buf->sg_len[i] = 0; | |
907 | buf->plane_sizes[i] = 0; | |
908 | } | |
909 | buf->nb_planes = 0; | |
910 | } | |
911 | ||
912 | static int pxa_buffer_init(struct pxa_camera_dev *pcdev, | |
913 | struct pxa_buffer *buf) | |
914 | { | |
915 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; | |
916 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); | |
917 | int nb_channels = pcdev->channels; | |
918 | int i, ret = 0; | |
919 | unsigned long size = vb2_plane_size(vb, 0); | |
920 | ||
921 | switch (nb_channels) { | |
922 | case 1: | |
923 | buf->plane_sizes[0] = size; | |
924 | break; | |
925 | case 3: | |
926 | buf->plane_sizes[0] = size / 2; | |
927 | buf->plane_sizes[1] = size / 4; | |
928 | buf->plane_sizes[2] = size / 4; | |
929 | break; | |
930 | default: | |
931 | return -EINVAL; | |
932 | }; | |
933 | buf->nb_planes = nb_channels; | |
934 | ||
935 | ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels, | |
936 | buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL); | |
937 | if (ret < 0) { | |
938 | dev_err(pcdev_to_dev(pcdev), | |
939 | "sg_split failed: %d\n", ret); | |
940 | return ret; | |
941 | } | |
942 | for (i = 0; i < nb_channels; i++) { | |
943 | ret = pxa_init_dma_channel(pcdev, buf, i, | |
944 | buf->sg[i], buf->sg_len[i]); | |
945 | if (ret) { | |
946 | pxa_buffer_cleanup(buf); | |
947 | return ret; | |
948 | } | |
949 | } | |
950 | INIT_LIST_HEAD(&buf->queue); | |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
955 | static void pxac_vb2_cleanup(struct vb2_buffer *vb) | |
956 | { | |
957 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
958 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
959 | ||
960 | dev_dbg(pcdev_to_dev(pcdev), | |
961 | "%s(vb=%p)\n", __func__, vb); | |
962 | pxa_buffer_cleanup(buf); | |
963 | } | |
964 | ||
965 | static void pxac_vb2_queue(struct vb2_buffer *vb) | |
966 | { | |
967 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
968 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
969 | ||
970 | dev_dbg(pcdev_to_dev(pcdev), | |
971 | "%s(vb=%p) nb_channels=%d size=%lu active=%p\n", | |
972 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0), | |
973 | pcdev->active); | |
974 | ||
975 | list_add_tail(&buf->queue, &pcdev->capture); | |
976 | ||
977 | pxa_dma_add_tail_buf(pcdev, buf); | |
978 | } | |
979 | ||
980 | /* | |
981 | * Please check the DMA prepared buffer structure in : | |
982 | * Documentation/video4linux/pxa_camera.txt | |
983 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
984 | * modification while DMA chain is running will work anyway. | |
985 | */ | |
986 | static int pxac_vb2_prepare(struct vb2_buffer *vb) | |
987 | { | |
988 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
989 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
6f28435d RJ |
990 | int ret = 0; |
991 | ||
992 | switch (pcdev->channels) { | |
993 | case 1: | |
994 | case 3: | |
283e4a82 | 995 | vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage); |
6f28435d RJ |
996 | break; |
997 | default: | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
1001 | dev_dbg(pcdev_to_dev(pcdev), | |
1002 | "%s (vb=%p) nb_channels=%d size=%lu\n", | |
1003 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0)); | |
1004 | ||
283e4a82 | 1005 | WARN_ON(!pcdev->current_fmt); |
6f28435d RJ |
1006 | |
1007 | #ifdef DEBUG | |
1008 | /* | |
1009 | * This can be useful if you want to see if we actually fill | |
1010 | * the buffer with something | |
1011 | */ | |
1012 | for (i = 0; i < vb->num_planes; i++) | |
1013 | memset((void *)vb2_plane_vaddr(vb, i), | |
1014 | 0xaa, vb2_get_plane_payload(vb, i)); | |
1015 | #endif | |
1016 | ||
1017 | /* | |
1018 | * I think, in buf_prepare you only have to protect global data, | |
1019 | * the actual buffer is yours | |
1020 | */ | |
1021 | buf->inwork = 0; | |
1022 | pxa_videobuf_set_actdma(pcdev, buf); | |
1023 | ||
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | static int pxac_vb2_init(struct vb2_buffer *vb) | |
1028 | { | |
1029 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
1030 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
1031 | ||
1032 | dev_dbg(pcdev_to_dev(pcdev), | |
1033 | "%s(nb_channels=%d)\n", | |
1034 | __func__, pcdev->channels); | |
1035 | ||
1036 | return pxa_buffer_init(pcdev, buf); | |
1037 | } | |
1038 | ||
1039 | static int pxac_vb2_queue_setup(struct vb2_queue *vq, | |
1040 | unsigned int *nbufs, | |
1041 | unsigned int *num_planes, unsigned int sizes[], | |
1042 | struct device *alloc_devs[]) | |
1043 | { | |
1044 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
283e4a82 | 1045 | int size = pcdev->current_pix.sizeimage; |
6f28435d RJ |
1046 | |
1047 | dev_dbg(pcdev_to_dev(pcdev), | |
1048 | "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n", | |
1049 | __func__, vq, *nbufs, *num_planes, size); | |
1050 | /* | |
1051 | * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P | |
1052 | * format, even if there are 3 planes Y, U and V, we reply there is only | |
1053 | * one plane, containing Y, U and V data, one after the other. | |
1054 | */ | |
1055 | if (*num_planes) | |
1056 | return sizes[0] < size ? -EINVAL : 0; | |
1057 | ||
1058 | *num_planes = 1; | |
1059 | switch (pcdev->channels) { | |
1060 | case 1: | |
1061 | case 3: | |
1062 | sizes[0] = size; | |
1063 | break; | |
1064 | default: | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
1068 | if (!*nbufs) | |
1069 | *nbufs = 1; | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count) | |
1075 | { | |
1076 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
1077 | ||
1078 | dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n", | |
1079 | __func__, count, pcdev->active); | |
1080 | ||
61634976 | 1081 | pcdev->buf_sequence = 0; |
6f28435d RJ |
1082 | if (!pcdev->active) |
1083 | pxa_camera_start_capture(pcdev); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static void pxac_vb2_stop_streaming(struct vb2_queue *vq) | |
1089 | { | |
1090 | vb2_wait_for_all_buffers(vq); | |
1091 | } | |
1092 | ||
1093 | static struct vb2_ops pxac_vb2_ops = { | |
1094 | .queue_setup = pxac_vb2_queue_setup, | |
1095 | .buf_init = pxac_vb2_init, | |
1096 | .buf_prepare = pxac_vb2_prepare, | |
1097 | .buf_queue = pxac_vb2_queue, | |
1098 | .buf_cleanup = pxac_vb2_cleanup, | |
1099 | .start_streaming = pxac_vb2_start_streaming, | |
1100 | .stop_streaming = pxac_vb2_stop_streaming, | |
1101 | .wait_prepare = vb2_ops_wait_prepare, | |
1102 | .wait_finish = vb2_ops_wait_finish, | |
1103 | }; | |
1104 | ||
283e4a82 | 1105 | static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev) |
6f28435d | 1106 | { |
6f28435d | 1107 | int ret; |
283e4a82 | 1108 | struct vb2_queue *vq = &pcdev->vb2_vq; |
6f28435d | 1109 | |
283e4a82 | 1110 | memset(vq, 0, sizeof(*vq)); |
6f28435d RJ |
1111 | vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
1112 | vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
1113 | vq->drv_priv = pcdev; | |
1114 | vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
1115 | vq->buf_struct_size = sizeof(struct pxa_buffer); | |
283e4a82 | 1116 | vq->dev = pcdev->v4l2_dev.dev; |
6f28435d RJ |
1117 | |
1118 | vq->ops = &pxac_vb2_ops; | |
1119 | vq->mem_ops = &vb2_dma_sg_memops; | |
283e4a82 | 1120 | vq->lock = &pcdev->mlock; |
6f28435d RJ |
1121 | |
1122 | ret = vb2_queue_init(vq); | |
1123 | dev_dbg(pcdev_to_dev(pcdev), | |
1124 | "vb2_queue_init(vq=%p): %d\n", vq, ret); | |
1125 | ||
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | /* | |
1130 | * Video ioctls section | |
1131 | */ | |
283e4a82 | 1132 | static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev) |
6a6c8786 | 1133 | { |
679419aa | 1134 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
283e4a82 | 1135 | u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc; |
679419aa | 1136 | unsigned long bus_flags, common_flags; |
760697be | 1137 | int ret; |
6a6c8786 | 1138 | |
283e4a82 RJ |
1139 | ret = test_platform_param(pcdev, |
1140 | pcdev->current_fmt->host_fmt->bits_per_sample, | |
d2dcad49 | 1141 | &bus_flags); |
6a6c8786 GL |
1142 | if (ret < 0) |
1143 | return ret; | |
1144 | ||
b36bcbd6 | 1145 | ret = sensor_call(pcdev, video, g_mbus_config, &cfg); |
679419aa GL |
1146 | if (!ret) { |
1147 | common_flags = soc_mbus_config_compatible(&cfg, | |
1148 | bus_flags); | |
1149 | if (!common_flags) { | |
295ab497 | 1150 | dev_warn(pcdev_to_dev(pcdev), |
679419aa GL |
1151 | "Flags incompatible: camera 0x%x, host 0x%lx\n", |
1152 | cfg.flags, bus_flags); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | } else if (ret != -ENOIOCTLCMD) { | |
1156 | return ret; | |
1157 | } else { | |
1158 | common_flags = bus_flags; | |
1159 | } | |
6a6c8786 GL |
1160 | |
1161 | pcdev->channels = 1; | |
1162 | ||
1163 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1164 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1165 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1166 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1167 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1168 | else |
679419aa | 1169 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1170 | } |
1171 | ||
679419aa GL |
1172 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1173 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1174 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1175 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1176 | else |
679419aa | 1177 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1178 | } |
1179 | ||
679419aa GL |
1180 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1181 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1182 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1183 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1184 | else |
679419aa | 1185 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1186 | } |
1187 | ||
679419aa | 1188 | cfg.flags = common_flags; |
b36bcbd6 | 1189 | ret = sensor_call(pcdev, video, s_mbus_config, &cfg); |
679419aa | 1190 | if (ret < 0 && ret != -ENOIOCTLCMD) { |
283e4a82 RJ |
1191 | dev_dbg(pcdev_to_dev(pcdev), |
1192 | "camera s_mbus_config(0x%lx) returned %d\n", | |
679419aa | 1193 | common_flags, ret); |
6a6c8786 | 1194 | return ret; |
679419aa GL |
1195 | } |
1196 | ||
283e4a82 | 1197 | pxa_camera_setup_cicr(pcdev, common_flags, pixfmt); |
3bc43840 GL |
1198 | |
1199 | return 0; | |
1200 | } | |
1201 | ||
283e4a82 | 1202 | static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev, |
2a48fc73 | 1203 | unsigned char buswidth) |
ad5f2e85 | 1204 | { |
679419aa GL |
1205 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1206 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1207 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1208 | |
1209 | if (ret < 0) | |
1210 | return ret; | |
1211 | ||
b36bcbd6 | 1212 | ret = sensor_call(pcdev, video, g_mbus_config, &cfg); |
679419aa GL |
1213 | if (!ret) { |
1214 | common_flags = soc_mbus_config_compatible(&cfg, | |
1215 | bus_flags); | |
1216 | if (!common_flags) { | |
295ab497 | 1217 | dev_warn(pcdev_to_dev(pcdev), |
679419aa GL |
1218 | "Flags incompatible: camera 0x%x, host 0x%lx\n", |
1219 | cfg.flags, bus_flags); | |
1220 | return -EINVAL; | |
1221 | } | |
1222 | } else if (ret == -ENOIOCTLCMD) { | |
1223 | ret = 0; | |
1224 | } | |
ad5f2e85 | 1225 | |
679419aa | 1226 | return ret; |
ad5f2e85 GL |
1227 | } |
1228 | ||
760697be | 1229 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1230 | { |
760697be GL |
1231 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1232 | .name = "Planar YUV422 16 bit", | |
1233 | .bits_per_sample = 8, | |
1234 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1235 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1236 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1237 | }, |
1238 | }; | |
1239 | ||
760697be GL |
1240 | /* This will be corrected as we get more formats */ |
1241 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1242 | { |
760697be GL |
1243 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1244 | (fmt->bits_per_sample == 8 && | |
1245 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1246 | (fmt->bits_per_sample > 8 && | |
1247 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1248 | } |
1249 | ||
283e4a82 RJ |
1250 | static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev, |
1251 | unsigned int idx, | |
2a48fc73 RJ |
1252 | struct soc_camera_format_xlate *xlate) |
1253 | { | |
283e4a82 | 1254 | struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev); |
760697be | 1255 | int formats = 0, ret; |
ebcff5fc HV |
1256 | struct v4l2_subdev_mbus_code_enum code = { |
1257 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1258 | .index = idx, | |
1259 | }; | |
760697be | 1260 | const struct soc_mbus_pixelfmt *fmt; |
2a48fc73 | 1261 | |
b36bcbd6 | 1262 | ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code); |
760697be GL |
1263 | if (ret < 0) |
1264 | /* No more formats */ | |
1265 | return 0; | |
2a48fc73 | 1266 | |
ebcff5fc | 1267 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 1268 | if (!fmt) { |
283e4a82 RJ |
1269 | dev_err(pcdev_to_dev(pcdev), |
1270 | "Invalid format code #%u: %d\n", idx, code.code); | |
2a48fc73 | 1271 | return 0; |
760697be | 1272 | } |
3bc43840 | 1273 | |
760697be | 1274 | /* This also checks support for the requested bits-per-sample */ |
283e4a82 | 1275 | ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample); |
2a48fc73 RJ |
1276 | if (ret < 0) |
1277 | return 0; | |
1278 | ||
ebcff5fc | 1279 | switch (code.code) { |
27ffaeb0 | 1280 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1281 | formats++; |
1282 | if (xlate) { | |
760697be | 1283 | xlate->host_fmt = &pxa_camera_formats[0]; |
ebcff5fc | 1284 | xlate->code = code.code; |
2a48fc73 | 1285 | xlate++; |
295ab497 RJ |
1286 | dev_dbg(pcdev_to_dev(pcdev), |
1287 | "Providing format %s using code %d\n", | |
ebcff5fc | 1288 | pxa_camera_formats[0].name, code.code); |
2a48fc73 | 1289 | } |
27ffaeb0 BB |
1290 | case MEDIA_BUS_FMT_VYUY8_2X8: |
1291 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
1292 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
1293 | case MEDIA_BUS_FMT_RGB565_2X8_LE: | |
1294 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: | |
760697be | 1295 | if (xlate) |
295ab497 RJ |
1296 | dev_dbg(pcdev_to_dev(pcdev), |
1297 | "Providing format %s packed\n", | |
760697be | 1298 | fmt->name); |
2a48fc73 RJ |
1299 | break; |
1300 | default: | |
760697be GL |
1301 | if (!pxa_camera_packing_supported(fmt)) |
1302 | return 0; | |
1303 | if (xlate) | |
295ab497 | 1304 | dev_dbg(pcdev_to_dev(pcdev), |
2a48fc73 | 1305 | "Providing format %s in pass-through mode\n", |
760697be GL |
1306 | fmt->name); |
1307 | } | |
1308 | ||
1309 | /* Generic pass-through */ | |
1310 | formats++; | |
1311 | if (xlate) { | |
1312 | xlate->host_fmt = fmt; | |
ebcff5fc | 1313 | xlate->code = code.code; |
760697be | 1314 | xlate++; |
2a48fc73 RJ |
1315 | } |
1316 | ||
1317 | return formats; | |
1318 | } | |
1319 | ||
283e4a82 RJ |
1320 | static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev) |
1321 | { | |
1322 | struct soc_camera_format_xlate *xlate; | |
1323 | ||
1324 | xlate = soc_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor, | |
1325 | pxa_camera_get_formats); | |
1326 | if (IS_ERR(xlate)) | |
1327 | return PTR_ERR(xlate); | |
1328 | ||
1329 | pcdev->user_formats = xlate; | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev) | |
6a6c8786 | 1334 | { |
283e4a82 | 1335 | kfree(pcdev->user_formats); |
6a6c8786 GL |
1336 | } |
1337 | ||
760697be | 1338 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1339 | { |
1340 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1341 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1342 | (width & 0x01); | |
6a6c8786 GL |
1343 | } |
1344 | ||
283e4a82 RJ |
1345 | static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv, |
1346 | struct v4l2_fmtdesc *f) | |
ad5f2e85 | 1347 | { |
283e4a82 RJ |
1348 | struct pxa_camera_dev *pcdev = video_drvdata(filp); |
1349 | const struct soc_mbus_pixelfmt *format; | |
1350 | unsigned int idx; | |
760697be | 1351 | |
283e4a82 RJ |
1352 | for (idx = 0; pcdev->user_formats[idx].code; idx++); |
1353 | if (f->index >= idx) | |
760697be | 1354 | return -EINVAL; |
2a48fc73 | 1355 | |
283e4a82 RJ |
1356 | format = pcdev->user_formats[f->index].host_fmt; |
1357 | f->pixelformat = format->fourcc; | |
1358 | return 0; | |
1359 | } | |
760697be | 1360 | |
283e4a82 RJ |
1361 | static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv, |
1362 | struct v4l2_format *f) | |
1363 | { | |
1364 | struct pxa_camera_dev *pcdev = video_drvdata(filp); | |
1365 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
25c4d74e | 1366 | |
283e4a82 RJ |
1367 | pix->width = pcdev->current_pix.width; |
1368 | pix->height = pcdev->current_pix.height; | |
1369 | pix->bytesperline = pcdev->current_pix.bytesperline; | |
1370 | pix->sizeimage = pcdev->current_pix.sizeimage; | |
1371 | pix->field = pcdev->current_pix.field; | |
1372 | pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc; | |
1373 | pix->colorspace = pcdev->current_pix.colorspace; | |
1374 | dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n", | |
1375 | pcdev->current_fmt->host_fmt->fourcc); | |
1376 | return 0; | |
ad5f2e85 GL |
1377 | } |
1378 | ||
283e4a82 RJ |
1379 | static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv, |
1380 | struct v4l2_format *f) | |
3bc43840 | 1381 | { |
283e4a82 | 1382 | struct pxa_camera_dev *pcdev = video_drvdata(filp); |
2a48fc73 RJ |
1383 | const struct soc_camera_format_xlate *xlate; |
1384 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
5eab4983 HV |
1385 | struct v4l2_subdev_pad_config pad_cfg; |
1386 | struct v4l2_subdev_format format = { | |
1387 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1388 | }; | |
1389 | struct v4l2_mbus_framefmt *mf = &format.format; | |
2a48fc73 | 1390 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1391 | int ret; |
a2c8c68c | 1392 | |
283e4a82 | 1393 | xlate = soc_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt); |
2a48fc73 | 1394 | if (!xlate) { |
295ab497 | 1395 | dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt); |
25c4d74e | 1396 | return -EINVAL; |
2a48fc73 | 1397 | } |
25c4d74e | 1398 | |
92a8337b | 1399 | /* |
4a6b8df2 TP |
1400 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1401 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1402 | * inserted between Y and U planes, and U and V planes, which violates | |
1403 | * the YUV422P standard. | |
92a8337b | 1404 | */ |
4a6b8df2 TP |
1405 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1406 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1407 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1408 | |
283e4a82 | 1409 | v4l2_fill_mbus_format(mf, pix, xlate->code); |
b36bcbd6 | 1410 | ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format); |
760697be GL |
1411 | if (ret < 0) |
1412 | return ret; | |
06daa1af | 1413 | |
283e4a82 | 1414 | v4l2_fill_pix_format(pix, mf); |
760697be | 1415 | |
283e4a82 | 1416 | /* Only progressive video supported so far */ |
5eab4983 | 1417 | switch (mf->field) { |
760697be GL |
1418 | case V4L2_FIELD_ANY: |
1419 | case V4L2_FIELD_NONE: | |
283e4a82 | 1420 | pix->field = V4L2_FIELD_NONE; |
760697be GL |
1421 | break; |
1422 | default: | |
1423 | /* TODO: support interlaced at least in pass-through mode */ | |
295ab497 | 1424 | dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n", |
5eab4983 | 1425 | mf->field); |
06daa1af GL |
1426 | return -EINVAL; |
1427 | } | |
1428 | ||
283e4a82 RJ |
1429 | ret = soc_mbus_bytes_per_line(pix->width, xlate->host_fmt); |
1430 | if (ret < 0) | |
1431 | return ret; | |
1432 | ||
1433 | pix->bytesperline = ret; | |
1434 | ret = soc_mbus_image_size(xlate->host_fmt, pix->bytesperline, | |
1435 | pix->height); | |
1436 | if (ret < 0) | |
1437 | return ret; | |
1438 | ||
1439 | pix->sizeimage = ret; | |
1440 | return 0; | |
3bc43840 GL |
1441 | } |
1442 | ||
283e4a82 RJ |
1443 | static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv, |
1444 | struct v4l2_format *f) | |
3bc43840 | 1445 | { |
283e4a82 RJ |
1446 | struct pxa_camera_dev *pcdev = video_drvdata(filp); |
1447 | const struct soc_camera_format_xlate *xlate; | |
1448 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1449 | struct v4l2_subdev_format format = { | |
1450 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1451 | }; | |
1452 | unsigned long flags; | |
1453 | int ret, is_busy; | |
1454 | ||
1455 | dev_dbg(pcdev_to_dev(pcdev), | |
1456 | "s_fmt_vid_cap(pix=%dx%d:%x)\n", | |
1457 | pix->width, pix->height, pix->pixelformat); | |
1458 | ||
1459 | spin_lock_irqsave(&pcdev->lock, flags); | |
1460 | is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq); | |
1461 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
1462 | ||
1463 | if (is_busy) | |
1464 | return -EBUSY; | |
1465 | ||
1466 | ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f); | |
1467 | if (ret) | |
1468 | return ret; | |
1469 | ||
1470 | xlate = soc_mbus_xlate_by_fourcc(pcdev->user_formats, | |
1471 | pix->pixelformat); | |
1472 | v4l2_fill_mbus_format(&format.format, pix, xlate->code); | |
1473 | ret = sensor_call(pcdev, pad, set_fmt, NULL, &format); | |
1474 | if (ret < 0) { | |
1475 | dev_warn(pcdev_to_dev(pcdev), | |
1476 | "Failed to configure for format %x\n", | |
1477 | pix->pixelformat); | |
1478 | } else if (pxa_camera_check_frame(pix->width, pix->height)) { | |
1479 | dev_warn(pcdev_to_dev(pcdev), | |
1480 | "Camera driver produced an unsupported frame %dx%d\n", | |
1481 | pix->width, pix->height); | |
1482 | return -EINVAL; | |
1483 | } | |
1484 | ||
1485 | pcdev->current_fmt = xlate; | |
1486 | pcdev->current_pix = *pix; | |
3bc43840 | 1487 | |
283e4a82 RJ |
1488 | ret = pxa_camera_set_bus_param(pcdev); |
1489 | return ret; | |
3bc43840 GL |
1490 | } |
1491 | ||
283e4a82 RJ |
1492 | static int pxac_vidioc_querycap(struct file *file, void *priv, |
1493 | struct v4l2_capability *cap) | |
3bc43840 | 1494 | { |
283e4a82 RJ |
1495 | strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info)); |
1496 | strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver)); | |
3bc43840 | 1497 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); |
7d96c3e4 GL |
1498 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1499 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
3bc43840 GL |
1500 | |
1501 | return 0; | |
1502 | } | |
1503 | ||
283e4a82 RJ |
1504 | static int pxac_vidioc_enum_input(struct file *file, void *priv, |
1505 | struct v4l2_input *i) | |
1506 | { | |
1507 | if (i->index > 0) | |
1508 | return -EINVAL; | |
1509 | ||
1510 | i->type = V4L2_INPUT_TYPE_CAMERA; | |
1511 | strlcpy(i->name, "Camera", sizeof(i->name)); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i) | |
1517 | { | |
1518 | *i = 0; | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i) | |
1524 | { | |
1525 | if (i > 0) | |
1526 | return -EINVAL; | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static int pxac_fops_camera_open(struct file *filp) | |
1532 | { | |
1533 | struct pxa_camera_dev *pcdev = video_drvdata(filp); | |
1534 | int ret; | |
1535 | ||
1536 | mutex_lock(&pcdev->mlock); | |
1537 | ret = v4l2_fh_open(filp); | |
1538 | if (ret < 0) | |
1539 | goto out; | |
1540 | ||
1541 | ret = sensor_call(pcdev, core, s_power, 1); | |
1542 | if (ret) | |
1543 | v4l2_fh_release(filp); | |
1544 | out: | |
1545 | mutex_unlock(&pcdev->mlock); | |
1546 | return ret; | |
1547 | } | |
1548 | ||
1549 | static int pxac_fops_camera_release(struct file *filp) | |
1550 | { | |
1551 | struct pxa_camera_dev *pcdev = video_drvdata(filp); | |
1552 | int ret; | |
1553 | ||
1554 | ret = vb2_fop_release(filp); | |
1555 | if (ret < 0) | |
1556 | return ret; | |
1557 | ||
1558 | mutex_lock(&pcdev->mlock); | |
1559 | ret = sensor_call(pcdev, core, s_power, 0); | |
1560 | mutex_unlock(&pcdev->mlock); | |
1561 | ||
1562 | return ret; | |
1563 | } | |
1564 | ||
1565 | static const struct v4l2_file_operations pxa_camera_fops = { | |
1566 | .owner = THIS_MODULE, | |
1567 | .open = pxac_fops_camera_open, | |
1568 | .release = pxac_fops_camera_release, | |
1569 | .read = vb2_fop_read, | |
1570 | .poll = vb2_fop_poll, | |
1571 | .mmap = vb2_fop_mmap, | |
1572 | .unlocked_ioctl = video_ioctl2, | |
1573 | }; | |
1574 | ||
1575 | static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = { | |
1576 | .vidioc_querycap = pxac_vidioc_querycap, | |
1577 | ||
1578 | .vidioc_enum_input = pxac_vidioc_enum_input, | |
1579 | .vidioc_g_input = pxac_vidioc_g_input, | |
1580 | .vidioc_s_input = pxac_vidioc_s_input, | |
1581 | ||
1582 | .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap, | |
1583 | .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap, | |
1584 | .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap, | |
1585 | .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap, | |
1586 | ||
1587 | .vidioc_reqbufs = vb2_ioctl_reqbufs, | |
1588 | .vidioc_create_bufs = vb2_ioctl_create_bufs, | |
1589 | .vidioc_querybuf = vb2_ioctl_querybuf, | |
1590 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
1591 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
1592 | .vidioc_expbuf = vb2_ioctl_expbuf, | |
1593 | .vidioc_streamon = vb2_ioctl_streamon, | |
1594 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
1595 | }; | |
1596 | ||
1597 | static struct v4l2_clk_ops pxa_camera_mclk_ops = { | |
1598 | }; | |
1599 | ||
1600 | static const struct video_device pxa_camera_videodev_template = { | |
1601 | .name = "pxa-camera", | |
1602 | .minor = -1, | |
1603 | .fops = &pxa_camera_fops, | |
1604 | .ioctl_ops = &pxa_camera_ioctl_ops, | |
1605 | .release = video_device_release_empty, | |
1606 | .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING, | |
1607 | }; | |
1608 | ||
1609 | static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier, | |
1610 | struct v4l2_subdev *subdev, | |
1611 | struct v4l2_async_subdev *asd) | |
1612 | { | |
1613 | int err; | |
1614 | struct v4l2_device *v4l2_dev = notifier->v4l2_dev; | |
1615 | struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev); | |
1616 | struct video_device *vdev = &pcdev->vdev; | |
1617 | struct v4l2_pix_format *pix = &pcdev->current_pix; | |
1618 | struct v4l2_subdev_format format = { | |
1619 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1620 | }; | |
1621 | struct v4l2_mbus_framefmt *mf = &format.format; | |
1622 | ||
1623 | dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n", | |
1624 | __func__); | |
1625 | mutex_lock(&pcdev->mlock); | |
1626 | *vdev = pxa_camera_videodev_template; | |
1627 | vdev->v4l2_dev = v4l2_dev; | |
1628 | vdev->lock = &pcdev->mlock; | |
1629 | pcdev->sensor = subdev; | |
1630 | pcdev->vdev.queue = &pcdev->vb2_vq; | |
1631 | pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev; | |
1632 | pcdev->vdev.ctrl_handler = subdev->ctrl_handler; | |
1633 | video_set_drvdata(&pcdev->vdev, pcdev); | |
1634 | ||
1635 | err = pxa_camera_build_formats(pcdev); | |
1636 | if (err) { | |
1637 | dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n", | |
1638 | err); | |
1639 | goto out; | |
1640 | } | |
1641 | ||
1642 | pcdev->current_fmt = pcdev->user_formats; | |
1643 | pix->field = V4L2_FIELD_NONE; | |
1644 | pix->width = DEFAULT_WIDTH; | |
1645 | pix->height = DEFAULT_HEIGHT; | |
1646 | pix->bytesperline = | |
1647 | soc_mbus_bytes_per_line(pix->width, | |
1648 | pcdev->current_fmt->host_fmt); | |
1649 | pix->sizeimage = | |
1650 | soc_mbus_image_size(pcdev->current_fmt->host_fmt, | |
1651 | pix->bytesperline, pix->height); | |
1652 | pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc; | |
1653 | v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code); | |
1654 | err = sensor_call(pcdev, pad, set_fmt, NULL, &format); | |
1655 | if (err) | |
1656 | goto out; | |
1657 | ||
1658 | v4l2_fill_pix_format(pix, mf); | |
1659 | pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n", | |
1660 | __func__, pix->colorspace, pix->pixelformat); | |
1661 | ||
1662 | err = pxa_camera_init_videobuf2(pcdev); | |
1663 | if (err) | |
1664 | goto out; | |
1665 | ||
1666 | err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1); | |
1667 | if (err) { | |
1668 | v4l2_err(v4l2_dev, "register video device failed: %d\n", err); | |
1669 | pcdev->sensor = NULL; | |
1670 | } else { | |
1671 | dev_info(pcdev_to_dev(pcdev), | |
1672 | "PXA Camera driver attached to camera %s\n", | |
1673 | subdev->name); | |
1674 | } | |
1675 | out: | |
1676 | mutex_unlock(&pcdev->mlock); | |
1677 | return err; | |
1678 | } | |
1679 | ||
1680 | static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier, | |
1681 | struct v4l2_subdev *subdev, | |
1682 | struct v4l2_async_subdev *asd) | |
1683 | { | |
1684 | struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev); | |
1685 | ||
1686 | mutex_lock(&pcdev->mlock); | |
1687 | dev_info(pcdev_to_dev(pcdev), | |
1688 | "PXA Camera driver detached from camera %s\n", | |
1689 | subdev->name); | |
1690 | ||
1691 | /* disable capture, disable interrupts */ | |
1692 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
1693 | ||
1694 | /* Stop DMA engine */ | |
1695 | pxa_dma_stop_channels(pcdev); | |
1696 | ||
1697 | pxa_camera_destroy_formats(pcdev); | |
1698 | video_unregister_device(&pcdev->vdev); | |
1699 | pcdev->sensor = NULL; | |
1700 | ||
1701 | mutex_unlock(&pcdev->mlock); | |
1702 | } | |
1703 | ||
6f28435d RJ |
1704 | /* |
1705 | * Driver probe, remove, suspend and resume operations | |
1706 | */ | |
7254026c | 1707 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1708 | { |
283e4a82 | 1709 | struct pxa_camera_dev *pcdev = dev_get_drvdata(dev); |
3f6ac497 RJ |
1710 | int i = 0, ret = 0; |
1711 | ||
5ca11fa3 EM |
1712 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1713 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1714 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1715 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1716 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1717 | |
283e4a82 | 1718 | if (pcdev->sensor) { |
b36bcbd6 | 1719 | ret = sensor_call(pcdev, core, s_power, 0); |
497833c6 GL |
1720 | if (ret == -ENOIOCTLCMD) |
1721 | ret = 0; | |
1722 | } | |
3f6ac497 RJ |
1723 | |
1724 | return ret; | |
1725 | } | |
1726 | ||
7254026c | 1727 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1728 | { |
283e4a82 | 1729 | struct pxa_camera_dev *pcdev = dev_get_drvdata(dev); |
3f6ac497 RJ |
1730 | int i = 0, ret = 0; |
1731 | ||
5ca11fa3 EM |
1732 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1733 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1734 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1735 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1736 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1737 | |
283e4a82 | 1738 | if (pcdev->sensor) { |
b36bcbd6 | 1739 | ret = sensor_call(pcdev, core, s_power, 1); |
497833c6 GL |
1740 | if (ret == -ENOIOCTLCMD) |
1741 | ret = 0; | |
1742 | } | |
3f6ac497 RJ |
1743 | |
1744 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1745 | if (!ret && pcdev->active) |
1746 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1747 | |
1748 | return ret; | |
1749 | } | |
1750 | ||
e9a1d94f | 1751 | static int pxa_camera_pdata_from_dt(struct device *dev, |
283e4a82 RJ |
1752 | struct pxa_camera_dev *pcdev, |
1753 | struct v4l2_async_subdev *asd) | |
e9a1d94f RJ |
1754 | { |
1755 | u32 mclk_rate; | |
283e4a82 | 1756 | struct device_node *remote, *np = dev->of_node; |
e9a1d94f RJ |
1757 | struct v4l2_of_endpoint ep; |
1758 | int err = of_property_read_u32(np, "clock-frequency", | |
1759 | &mclk_rate); | |
1760 | if (!err) { | |
1761 | pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; | |
1762 | pcdev->mclk = mclk_rate; | |
1763 | } | |
1764 | ||
1765 | np = of_graph_get_next_endpoint(np, NULL); | |
1766 | if (!np) { | |
283e4a82 | 1767 | dev_err(dev, "could not find endpoint\n"); |
e9a1d94f RJ |
1768 | return -EINVAL; |
1769 | } | |
1770 | ||
1771 | err = v4l2_of_parse_endpoint(np, &ep); | |
1772 | if (err) { | |
283e4a82 | 1773 | dev_err(dev, "could not parse endpoint\n"); |
e9a1d94f RJ |
1774 | goto out; |
1775 | } | |
1776 | ||
1777 | switch (ep.bus.parallel.bus_width) { | |
1778 | case 4: | |
1779 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; | |
1780 | break; | |
1781 | case 5: | |
1782 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; | |
1783 | break; | |
1784 | case 8: | |
1785 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; | |
1786 | break; | |
1787 | case 9: | |
1788 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; | |
1789 | break; | |
1790 | case 10: | |
1791 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1792 | break; | |
1793 | default: | |
1794 | break; | |
c611c908 | 1795 | } |
e9a1d94f RJ |
1796 | |
1797 | if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) | |
1798 | pcdev->platform_flags |= PXA_CAMERA_MASTER; | |
1799 | if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
1800 | pcdev->platform_flags |= PXA_CAMERA_HSP; | |
1801 | if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
1802 | pcdev->platform_flags |= PXA_CAMERA_VSP; | |
1803 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
1804 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; | |
1805 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
1806 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; | |
1807 | ||
283e4a82 RJ |
1808 | asd->match_type = V4L2_ASYNC_MATCH_OF; |
1809 | remote = of_graph_get_remote_port(np); | |
1810 | if (remote) { | |
1811 | asd->match.of.node = remote; | |
1812 | of_node_put(remote); | |
1813 | } else { | |
1814 | dev_notice(dev, "no remote for %s\n", of_node_full_name(np)); | |
1815 | } | |
1816 | ||
e9a1d94f RJ |
1817 | out: |
1818 | of_node_put(np); | |
1819 | ||
1820 | return err; | |
1821 | } | |
1822 | ||
4c62e976 | 1823 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1824 | { |
1825 | struct pxa_camera_dev *pcdev; | |
1826 | struct resource *res; | |
1827 | void __iomem *base; | |
1e77d55a RJ |
1828 | struct dma_slave_config config = { |
1829 | .src_addr_width = 0, | |
1830 | .src_maxburst = 8, | |
1831 | .direction = DMA_DEV_TO_MEM, | |
1832 | }; | |
1833 | dma_cap_mask_t mask; | |
1834 | struct pxad_param params; | |
283e4a82 | 1835 | char clk_name[V4L2_CLK_NAME_SIZE]; |
02da4659 | 1836 | int irq; |
1e77d55a | 1837 | int err = 0, i; |
3bc43840 GL |
1838 | |
1839 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1840 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1841 | if (!res || irq < 0) |
1842 | return -ENODEV; | |
3bc43840 | 1843 | |
47de201c | 1844 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1845 | if (!pcdev) { |
7102b773 | 1846 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1847 | return -ENOMEM; |
3bc43840 GL |
1848 | } |
1849 | ||
47de201c JL |
1850 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1851 | if (IS_ERR(pcdev->clk)) | |
1852 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1853 | |
3bc43840 GL |
1854 | pcdev->res = res; |
1855 | ||
1856 | pcdev->pdata = pdev->dev.platform_data; | |
e9a1d94f | 1857 | if (&pdev->dev.of_node && !pcdev->pdata) { |
283e4a82 | 1858 | err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd); |
e9a1d94f RJ |
1859 | } else { |
1860 | pcdev->platform_flags = pcdev->pdata->flags; | |
1861 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
283e4a82 RJ |
1862 | pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C; |
1863 | pcdev->asd.match.i2c.adapter_id = | |
1864 | pcdev->pdata->sensor_i2c_adapter_id; | |
1865 | pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address; | |
e9a1d94f RJ |
1866 | } |
1867 | if (err < 0) | |
1868 | return err; | |
1869 | ||
ad5f2e85 GL |
1870 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1871 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1872 | /* |
1873 | * Platform hasn't set available data widths. This is bad. | |
1874 | * Warn and use a default. | |
1875 | */ | |
3bc43840 GL |
1876 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1877 | "data widths, using default 10 bit\n"); | |
1878 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1879 | } | |
679419aa GL |
1880 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1881 | pcdev->width_flags = 1 << 7; | |
1882 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1883 | pcdev->width_flags |= 1 << 8; | |
1884 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1885 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 | 1886 | if (!pcdev->mclk) { |
3bc43840 | 1887 | dev_warn(&pdev->dev, |
cf34cba7 | 1888 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1889 | "Using default 20MHz\n"); |
cf34cba7 | 1890 | pcdev->mclk = 20000000; |
3bc43840 GL |
1891 | } |
1892 | ||
40e2e092 | 1893 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1894 | |
3bc43840 GL |
1895 | INIT_LIST_HEAD(&pcdev->capture); |
1896 | spin_lock_init(&pcdev->lock); | |
283e4a82 | 1897 | mutex_init(&pcdev->mlock); |
3bc43840 GL |
1898 | |
1899 | /* | |
1900 | * Request the regions. | |
1901 | */ | |
8efdb135 SK |
1902 | base = devm_ioremap_resource(&pdev->dev, res); |
1903 | if (IS_ERR(base)) | |
1904 | return PTR_ERR(base); | |
1905 | ||
3bc43840 GL |
1906 | pcdev->irq = irq; |
1907 | pcdev->base = base; | |
3bc43840 GL |
1908 | |
1909 | /* request dma */ | |
1e77d55a RJ |
1910 | dma_cap_zero(mask); |
1911 | dma_cap_set(DMA_SLAVE, mask); | |
1912 | dma_cap_set(DMA_PRIVATE, mask); | |
1913 | ||
1914 | params.prio = 0; | |
1915 | params.drcmr = 68; | |
1916 | pcdev->dma_chans[0] = | |
1917 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1918 | ¶ms, &pdev->dev, "CI_Y"); | |
1919 | if (!pcdev->dma_chans[0]) { | |
eff505fa | 1920 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
1e77d55a | 1921 | return -ENODEV; |
3bc43840 | 1922 | } |
a5462e5b | 1923 | |
1e77d55a RJ |
1924 | params.drcmr = 69; |
1925 | pcdev->dma_chans[1] = | |
1926 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1927 | ¶ms, &pdev->dev, "CI_U"); | |
1928 | if (!pcdev->dma_chans[1]) { | |
1929 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); | |
a5462e5b MR |
1930 | goto exit_free_dma_y; |
1931 | } | |
a5462e5b | 1932 | |
1e77d55a RJ |
1933 | params.drcmr = 70; |
1934 | pcdev->dma_chans[2] = | |
1935 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1936 | ¶ms, &pdev->dev, "CI_V"); | |
1937 | if (!pcdev->dma_chans[2]) { | |
eff505fa | 1938 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1939 | goto exit_free_dma_u; |
1940 | } | |
3bc43840 | 1941 | |
1e77d55a RJ |
1942 | for (i = 0; i < 3; i++) { |
1943 | config.src_addr = pcdev->res->start + CIBR0 + i * 8; | |
1944 | err = dmaengine_slave_config(pcdev->dma_chans[i], &config); | |
1945 | if (err < 0) { | |
1946 | dev_err(&pdev->dev, "dma slave config failed: %d\n", | |
1947 | err); | |
1948 | goto exit_free_dma; | |
1949 | } | |
1950 | } | |
3bc43840 GL |
1951 | |
1952 | /* request irq */ | |
47de201c JL |
1953 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1954 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1955 | if (err) { |
47de201c | 1956 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1957 | goto exit_free_dma; |
1958 | } | |
1959 | ||
e623ebe6 | 1960 | tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev); |
eff505fa | 1961 | |
283e4a82 RJ |
1962 | pxa_camera_activate(pcdev); |
1963 | ||
1964 | dev_set_drvdata(&pdev->dev, pcdev); | |
1965 | err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev); | |
3bc43840 | 1966 | if (err) |
47de201c | 1967 | goto exit_free_dma; |
3bc43840 | 1968 | |
283e4a82 RJ |
1969 | pcdev->asds[0] = &pcdev->asd; |
1970 | pcdev->notifier.subdevs = pcdev->asds; | |
1971 | pcdev->notifier.num_subdevs = 1; | |
1972 | pcdev->notifier.bound = pxa_camera_sensor_bound; | |
1973 | pcdev->notifier.unbind = pxa_camera_sensor_unbind; | |
1974 | ||
1975 | if (!of_have_populated_dt()) | |
1976 | pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C; | |
1977 | ||
1978 | err = pxa_camera_init_videobuf2(pcdev); | |
1979 | if (err) | |
1980 | goto exit_free_v4l2dev; | |
3bc43840 | 1981 | |
283e4a82 RJ |
1982 | if (pcdev->mclk) { |
1983 | v4l2_clk_name_i2c(clk_name, sizeof(clk_name), | |
1984 | pcdev->asd.match.i2c.adapter_id, | |
1985 | pcdev->asd.match.i2c.address); | |
1986 | ||
1987 | pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops, | |
1988 | clk_name, NULL); | |
1989 | if (IS_ERR(pcdev->mclk_clk)) | |
1990 | return PTR_ERR(pcdev->mclk_clk); | |
1991 | } | |
1992 | ||
1993 | err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier); | |
1994 | if (err) | |
1995 | goto exit_free_clk; | |
1996 | ||
1997 | return 0; | |
1998 | exit_free_clk: | |
1999 | v4l2_clk_unregister(pcdev->mclk_clk); | |
2000 | exit_free_v4l2dev: | |
2001 | v4l2_device_unregister(&pcdev->v4l2_dev); | |
3bc43840 | 2002 | exit_free_dma: |
1e77d55a | 2003 | dma_release_channel(pcdev->dma_chans[2]); |
a5462e5b | 2004 | exit_free_dma_u: |
1e77d55a | 2005 | dma_release_channel(pcdev->dma_chans[1]); |
a5462e5b | 2006 | exit_free_dma_y: |
1e77d55a | 2007 | dma_release_channel(pcdev->dma_chans[0]); |
3bc43840 GL |
2008 | return err; |
2009 | } | |
2010 | ||
4c62e976 | 2011 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 2012 | { |
283e4a82 | 2013 | struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev); |
3bc43840 | 2014 | |
283e4a82 | 2015 | pxa_camera_deactivate(pcdev); |
1e77d55a RJ |
2016 | dma_release_channel(pcdev->dma_chans[0]); |
2017 | dma_release_channel(pcdev->dma_chans[1]); | |
2018 | dma_release_channel(pcdev->dma_chans[2]); | |
3bc43840 | 2019 | |
283e4a82 RJ |
2020 | v4l2_clk_unregister(pcdev->mclk_clk); |
2021 | v4l2_device_unregister(&pcdev->v4l2_dev); | |
3bc43840 | 2022 | |
7102b773 | 2023 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 2024 | |
3bc43840 GL |
2025 | return 0; |
2026 | } | |
2027 | ||
56a49194 | 2028 | static const struct dev_pm_ops pxa_camera_pm = { |
7254026c GL |
2029 | .suspend = pxa_camera_suspend, |
2030 | .resume = pxa_camera_resume, | |
2031 | }; | |
2032 | ||
e9a1d94f RJ |
2033 | static const struct of_device_id pxa_camera_of_match[] = { |
2034 | { .compatible = "marvell,pxa270-qci", }, | |
2035 | {}, | |
2036 | }; | |
2037 | MODULE_DEVICE_TABLE(of, pxa_camera_of_match); | |
2038 | ||
3bc43840 | 2039 | static struct platform_driver pxa_camera_driver = { |
6003b2ad | 2040 | .driver = { |
3bc43840 | 2041 | .name = PXA_CAM_DRV_NAME, |
7254026c | 2042 | .pm = &pxa_camera_pm, |
e9a1d94f | 2043 | .of_match_table = of_match_ptr(pxa_camera_of_match), |
3bc43840 GL |
2044 | }, |
2045 | .probe = pxa_camera_probe, | |
4c62e976 | 2046 | .remove = pxa_camera_remove, |
3bc43840 GL |
2047 | }; |
2048 | ||
1d6629b1 | 2049 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
2050 | |
2051 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
2052 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
2053 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 2054 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 2055 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |