Commit | Line | Data |
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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
8efdb135 | 18 | #include <linux/err.h> |
3bc43840 GL |
19 | #include <linux/errno.h> |
20 | #include <linux/fs.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/time.h> | |
3bc43840 GL |
26 | #include <linux/device.h> |
27 | #include <linux/platform_device.h> | |
3bc43840 | 28 | #include <linux/clk.h> |
d514edac | 29 | #include <linux/sched.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1e77d55a RJ |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/dma/pxa-dma.h> | |
3bc43840 GL |
34 | |
35 | #include <media/v4l2-common.h> | |
36 | #include <media/v4l2-dev.h> | |
e009ebd5 | 37 | #include <media/videobuf2-dma-sg.h> |
3bc43840 | 38 | #include <media/soc_camera.h> |
d647f0b7 | 39 | #include <media/drv-intf/soc_mediabus.h> |
e9a1d94f | 40 | #include <media/v4l2-of.h> |
3bc43840 GL |
41 | |
42 | #include <linux/videodev2.h> | |
43 | ||
a71daaa1 | 44 | #include <linux/platform_data/media/camera-pxa.h> |
3bc43840 | 45 | |
64dc3c1a | 46 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
47 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
48 | ||
5ca11fa3 EM |
49 | /* Camera Interface */ |
50 | #define CICR0 0x0000 | |
51 | #define CICR1 0x0004 | |
52 | #define CICR2 0x0008 | |
53 | #define CICR3 0x000C | |
54 | #define CICR4 0x0010 | |
55 | #define CISR 0x0014 | |
56 | #define CIFR 0x0018 | |
57 | #define CITOR 0x001C | |
58 | #define CIBR0 0x0028 | |
59 | #define CIBR1 0x0030 | |
60 | #define CIBR2 0x0038 | |
61 | ||
62 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
63 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
64 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
65 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
66 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
67 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
68 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
69 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
70 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
71 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
72 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
73 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
74 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
75 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
76 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
77 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
78 | ||
79 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
80 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
81 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
82 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
83 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
84 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
85 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
86 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
87 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
88 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
89 | ||
90 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
91 | wait count mask */ | |
92 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
93 | wait count mask */ | |
94 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
95 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
96 | wait count mask */ | |
97 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
98 | wait count mask */ | |
99 | ||
100 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
101 | wait count mask */ | |
102 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
103 | wait count mask */ | |
104 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
105 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
106 | wait count mask */ | |
107 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
108 | ||
109 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
110 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
111 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
112 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
113 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
114 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
115 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
116 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
117 | ||
118 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
119 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
120 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
121 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
122 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
123 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
124 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
125 | #define CISR_EOL (1 << 8) /* End of line */ | |
126 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
127 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
128 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
129 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
130 | #define CISR_EOF (1 << 3) /* End of frame */ | |
131 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
132 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
133 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
134 | ||
135 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
136 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
137 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
138 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
139 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
140 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
141 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
142 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
143 | ||
7102b773 GL |
144 | #define CICR0_SIM_MP (0 << 24) |
145 | #define CICR0_SIM_SP (1 << 24) | |
146 | #define CICR0_SIM_MS (2 << 24) | |
147 | #define CICR0_SIM_EP (3 << 24) | |
148 | #define CICR0_SIM_ES (4 << 24) | |
149 | ||
150 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
151 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
152 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
153 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
154 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
155 | |
156 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
157 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
158 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
159 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
160 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
161 | ||
162 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
163 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
164 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
165 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
166 | ||
3bc43840 GL |
167 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
168 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
169 | CICR0_EOFM | CICR0_FOM) | |
170 | ||
b36bcbd6 RJ |
171 | #define sensor_call(cam, o, f, args...) \ |
172 | v4l2_subdev_call(sd, o, f, ##args) | |
173 | ||
3bc43840 GL |
174 | /* |
175 | * Structures | |
176 | */ | |
a5462e5b MR |
177 | enum pxa_camera_active_dma { |
178 | DMA_Y = 0x1, | |
179 | DMA_U = 0x2, | |
180 | DMA_V = 0x4, | |
181 | }; | |
182 | ||
3bc43840 GL |
183 | /* buffer for one video frame */ |
184 | struct pxa_buffer { | |
185 | /* common v4l buffer stuff -- must be first */ | |
e009ebd5 RJ |
186 | struct vb2_v4l2_buffer vbuf; |
187 | struct list_head queue; | |
27ffaeb0 | 188 | u32 code; |
e009ebd5 | 189 | int nb_planes; |
a5462e5b | 190 | /* our descriptor lists for Y, U and V channels */ |
1e77d55a RJ |
191 | struct dma_async_tx_descriptor *descs[3]; |
192 | dma_cookie_t cookie[3]; | |
193 | struct scatterlist *sg[3]; | |
194 | int sg_len[3]; | |
e009ebd5 | 195 | size_t plane_sizes[3]; |
760697be GL |
196 | int inwork; |
197 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
198 | }; |
199 | ||
3bc43840 | 200 | struct pxa_camera_dev { |
eb6c8558 | 201 | struct soc_camera_host soc_host; |
5d28d525 GL |
202 | /* |
203 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 204 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
205 | * one camera, they will have to modify this driver too |
206 | */ | |
3bc43840 GL |
207 | struct clk *clk; |
208 | ||
209 | unsigned int irq; | |
210 | void __iomem *base; | |
a5462e5b | 211 | |
e7c50688 | 212 | int channels; |
1e77d55a | 213 | struct dma_chan *dma_chans[3]; |
3bc43840 | 214 | |
3bc43840 GL |
215 | struct pxacamera_platform_data *pdata; |
216 | struct resource *res; | |
217 | unsigned long platform_flags; | |
cf34cba7 GL |
218 | unsigned long ciclk; |
219 | unsigned long mclk; | |
220 | u32 mclk_divisor; | |
679419aa | 221 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
222 | |
223 | struct list_head capture; | |
224 | ||
225 | spinlock_t lock; | |
226 | ||
3bc43840 | 227 | struct pxa_buffer *active; |
e623ebe6 | 228 | struct tasklet_struct task_eof; |
3f6ac497 RJ |
229 | |
230 | u32 save_cicr[5]; | |
3bc43840 GL |
231 | }; |
232 | ||
6a6c8786 GL |
233 | struct pxa_cam { |
234 | unsigned long flags; | |
235 | }; | |
236 | ||
3bc43840 GL |
237 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
238 | ||
295ab497 RJ |
239 | static struct pxa_camera_dev *icd_to_pcdev(struct soc_camera_device *icd) |
240 | { | |
241 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
242 | struct pxa_camera_dev *pcdev = ici->priv; | |
243 | ||
244 | return pcdev; | |
245 | } | |
246 | ||
3bc43840 GL |
247 | /* |
248 | * Videobuf operations | |
249 | */ | |
e009ebd5 | 250 | static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb) |
3bc43840 | 251 | { |
e009ebd5 | 252 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
3bc43840 | 253 | |
e009ebd5 | 254 | return container_of(vbuf, struct pxa_buffer, vbuf); |
3bc43840 GL |
255 | } |
256 | ||
e009ebd5 | 257 | static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev) |
3bc43840 | 258 | { |
e009ebd5 | 259 | return pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
260 | } |
261 | ||
1e77d55a | 262 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
e5853918 RJ |
263 | enum pxa_camera_active_dma act_dma); |
264 | ||
1e77d55a | 265 | static void pxa_camera_dma_irq_y(void *data) |
e5853918 RJ |
266 | { |
267 | struct pxa_camera_dev *pcdev = data; | |
268 | ||
1e77d55a | 269 | pxa_camera_dma_irq(pcdev, DMA_Y); |
e5853918 RJ |
270 | } |
271 | ||
1e77d55a | 272 | static void pxa_camera_dma_irq_u(void *data) |
e5853918 RJ |
273 | { |
274 | struct pxa_camera_dev *pcdev = data; | |
275 | ||
1e77d55a | 276 | pxa_camera_dma_irq(pcdev, DMA_U); |
e5853918 RJ |
277 | } |
278 | ||
1e77d55a | 279 | static void pxa_camera_dma_irq_v(void *data) |
e5853918 RJ |
280 | { |
281 | struct pxa_camera_dev *pcdev = data; | |
282 | ||
1e77d55a | 283 | pxa_camera_dma_irq(pcdev, DMA_V); |
e5853918 RJ |
284 | } |
285 | ||
37f5aefd RJ |
286 | /** |
287 | * pxa_init_dma_channel - init dma descriptors | |
288 | * @pcdev: pxa camera device | |
e009ebd5 | 289 | * @vb: videobuffer2 buffer |
37f5aefd RJ |
290 | * @dma: dma video buffer |
291 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
292 | * @cibr: camera Receive Buffer Register | |
37f5aefd RJ |
293 | * |
294 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
37f5aefd | 295 | * |
1e77d55a | 296 | * Returns 0 if success or -ENOMEM if no memory is available |
37f5aefd | 297 | */ |
a5462e5b | 298 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
e009ebd5 RJ |
299 | struct pxa_buffer *buf, int channel, |
300 | struct scatterlist *sg, int sglen) | |
a5462e5b | 301 | { |
1e77d55a | 302 | struct dma_chan *dma_chan = pcdev->dma_chans[channel]; |
1e77d55a RJ |
303 | struct dma_async_tx_descriptor *tx; |
304 | ||
305 | tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM, | |
306 | DMA_PREP_INTERRUPT | DMA_CTRL_REUSE); | |
307 | if (!tx) { | |
e009ebd5 | 308 | dev_err(pcdev_to_dev(pcdev), |
1e77d55a RJ |
309 | "dmaengine_prep_slave_sg failed\n"); |
310 | goto fail; | |
a5462e5b MR |
311 | } |
312 | ||
1e77d55a RJ |
313 | tx->callback_param = pcdev; |
314 | switch (channel) { | |
315 | case 0: | |
316 | tx->callback = pxa_camera_dma_irq_y; | |
317 | break; | |
318 | case 1: | |
319 | tx->callback = pxa_camera_dma_irq_u; | |
320 | break; | |
321 | case 2: | |
322 | tx->callback = pxa_camera_dma_irq_v; | |
323 | break; | |
37f5aefd RJ |
324 | } |
325 | ||
1e77d55a | 326 | buf->descs[channel] = tx; |
a5462e5b | 327 | return 0; |
1e77d55a | 328 | fail: |
e009ebd5 RJ |
329 | dev_dbg(pcdev_to_dev(pcdev), |
330 | "%s (vb=%p) dma_tx=%p\n", | |
331 | __func__, buf, tx); | |
1e77d55a RJ |
332 | |
333 | return -ENOMEM; | |
a5462e5b MR |
334 | } |
335 | ||
256b0233 RJ |
336 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
337 | struct pxa_buffer *buf) | |
338 | { | |
339 | buf->active_dma = DMA_Y; | |
340 | if (pcdev->channels == 3) | |
341 | buf->active_dma |= DMA_U | DMA_V; | |
342 | } | |
343 | ||
256b0233 RJ |
344 | /** |
345 | * pxa_dma_start_channels - start DMA channel for active buffer | |
346 | * @pcdev: pxa camera device | |
347 | * | |
348 | * Initialize DMA channels to the beginning of the active video buffer, and | |
349 | * start these channels. | |
350 | */ | |
351 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
352 | { | |
353 | int i; | |
354 | struct pxa_buffer *active; | |
355 | ||
356 | active = pcdev->active; | |
357 | ||
358 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 359 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
360 | "%s (channel=%d)\n", __func__, i); |
361 | dma_async_issue_pending(pcdev->dma_chans[i]); | |
256b0233 RJ |
362 | } |
363 | } | |
364 | ||
365 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
366 | { | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 370 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 371 | "%s (channel=%d)\n", __func__, i); |
1e77d55a | 372 | dmaengine_terminate_all(pcdev->dma_chans[i]); |
256b0233 RJ |
373 | } |
374 | } | |
375 | ||
256b0233 RJ |
376 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
377 | struct pxa_buffer *buf) | |
378 | { | |
379 | int i; | |
256b0233 RJ |
380 | |
381 | for (i = 0; i < pcdev->channels; i++) { | |
1e77d55a | 382 | buf->cookie[i] = dmaengine_submit(buf->descs[i]); |
e009ebd5 | 383 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
384 | "%s (channel=%d) : submit vb=%p cookie=%d\n", |
385 | __func__, i, buf, buf->descs[i]->cookie); | |
ae7410e7 | 386 | } |
256b0233 RJ |
387 | } |
388 | ||
389 | /** | |
390 | * pxa_camera_start_capture - start video capturing | |
391 | * @pcdev: camera device | |
392 | * | |
393 | * Launch capturing. DMA channels should not be active yet. They should get | |
394 | * activated at the end of frame interrupt, to capture only whole frames, and | |
395 | * never begin the capture of a partial frame. | |
396 | */ | |
397 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
398 | { | |
a47f6be4 | 399 | unsigned long cicr0; |
256b0233 | 400 | |
e009ebd5 | 401 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
e623ebe6 | 402 | __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); |
256b0233 RJ |
403 | /* Enable End-Of-Frame Interrupt */ |
404 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
405 | cicr0 &= ~CICR0_EOFM; | |
406 | __raw_writel(cicr0, pcdev->base + CICR0); | |
407 | } | |
408 | ||
409 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
410 | { | |
411 | unsigned long cicr0; | |
412 | ||
413 | pxa_dma_stop_channels(pcdev); | |
414 | ||
415 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
416 | __raw_writel(cicr0, pcdev->base + CICR0); | |
417 | ||
8c62e221 | 418 | pcdev->active = NULL; |
e009ebd5 | 419 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
3bc43840 GL |
420 | } |
421 | ||
a5462e5b | 422 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
a5462e5b MR |
423 | struct pxa_buffer *buf) |
424 | { | |
e009ebd5 RJ |
425 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; |
426 | ||
a5462e5b | 427 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
e009ebd5 RJ |
428 | list_del_init(&buf->queue); |
429 | vb->timestamp = ktime_get_ns(); | |
430 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
431 | dev_dbg(pcdev_to_dev(pcdev), "%s dequeud buffer (buf=0x%p)\n", | |
432 | __func__, buf); | |
a5462e5b MR |
433 | |
434 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 435 | pxa_camera_stop_capture(pcdev); |
a5462e5b MR |
436 | return; |
437 | } | |
438 | ||
439 | pcdev->active = list_entry(pcdev->capture.next, | |
e009ebd5 | 440 | struct pxa_buffer, queue); |
a5462e5b MR |
441 | } |
442 | ||
256b0233 RJ |
443 | /** |
444 | * pxa_camera_check_link_miss - check missed DMA linking | |
445 | * @pcdev: camera device | |
446 | * | |
447 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
448 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 449 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
450 | * This function restarts the capture for this corner case, where : |
451 | * - DADR() == DADDR_STOP | |
452 | * - a videobuffer is queued on the pcdev->capture list | |
453 | * | |
454 | * Please check the "DMA hot chaining timeslice issue" in | |
455 | * Documentation/video4linux/pxa_camera.txt | |
456 | * | |
457 | * Context: should only be called within the dma irq handler | |
458 | */ | |
1e77d55a RJ |
459 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev, |
460 | dma_cookie_t last_submitted, | |
461 | dma_cookie_t last_issued) | |
256b0233 | 462 | { |
1e77d55a | 463 | bool is_dma_stopped = last_submitted != last_issued; |
256b0233 | 464 | |
e009ebd5 | 465 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a | 466 | "%s : top queued buffer=%p, is_dma_stopped=%d\n", |
256b0233 | 467 | __func__, pcdev->active, is_dma_stopped); |
1e77d55a | 468 | |
256b0233 RJ |
469 | if (pcdev->active && is_dma_stopped) |
470 | pxa_camera_start_capture(pcdev); | |
471 | } | |
472 | ||
1e77d55a | 473 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
a5462e5b | 474 | enum pxa_camera_active_dma act_dma) |
3bc43840 | 475 | { |
1e77d55a | 476 | struct pxa_buffer *buf, *last_buf; |
3bc43840 | 477 | unsigned long flags; |
1e77d55a RJ |
478 | u32 camera_status, overrun; |
479 | int chan; | |
1e77d55a RJ |
480 | enum dma_status last_status; |
481 | dma_cookie_t last_issued; | |
3bc43840 GL |
482 | |
483 | spin_lock_irqsave(&pcdev->lock, flags); | |
484 | ||
256b0233 | 485 | camera_status = __raw_readl(pcdev->base + CISR); |
295ab497 | 486 | dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n", |
1e77d55a | 487 | camera_status, act_dma); |
256b0233 RJ |
488 | overrun = CISR_IFO_0; |
489 | if (pcdev->channels == 3) | |
490 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 491 | |
8c62e221 RJ |
492 | /* |
493 | * pcdev->active should not be NULL in DMA irq handler. | |
494 | * | |
495 | * But there is one corner case : if capture was stopped due to an | |
496 | * overrun of channel 1, and at that same channel 2 was completed. | |
497 | * | |
498 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
499 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
500 | * DMA irq handler will already be pending for channel 2. So on entering | |
501 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
502 | * that is normal. | |
503 | */ | |
504 | if (!pcdev->active) | |
3bc43840 | 505 | goto out; |
3bc43840 | 506 | |
e009ebd5 RJ |
507 | buf = pcdev->active; |
508 | WARN_ON(buf->inwork || list_empty(&buf->queue)); | |
3bc43840 | 509 | |
1e77d55a RJ |
510 | /* |
511 | * It's normal if the last frame creates an overrun, as there | |
512 | * are no more DMA descriptors to fetch from QCI fifos | |
513 | */ | |
514 | switch (act_dma) { | |
515 | case DMA_U: | |
516 | chan = 1; | |
517 | break; | |
518 | case DMA_V: | |
519 | chan = 2; | |
520 | break; | |
521 | default: | |
522 | chan = 0; | |
523 | break; | |
524 | } | |
525 | last_buf = list_entry(pcdev->capture.prev, | |
e009ebd5 | 526 | struct pxa_buffer, queue); |
1e77d55a RJ |
527 | last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan], |
528 | last_buf->cookie[chan], | |
529 | NULL, &last_issued); | |
530 | if (camera_status & overrun && | |
531 | last_status != DMA_COMPLETE) { | |
295ab497 | 532 | dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n", |
1e77d55a RJ |
533 | camera_status); |
534 | pxa_camera_stop_capture(pcdev); | |
e009ebd5 | 535 | list_for_each_entry(buf, &pcdev->capture, queue) |
1e77d55a RJ |
536 | pxa_dma_add_tail_buf(pcdev, buf); |
537 | pxa_camera_start_capture(pcdev); | |
538 | goto out; | |
539 | } | |
540 | buf->active_dma &= ~act_dma; | |
541 | if (!buf->active_dma) { | |
e009ebd5 | 542 | pxa_camera_wakeup(pcdev, buf); |
1e77d55a RJ |
543 | pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan], |
544 | last_issued); | |
256b0233 | 545 | } |
3bc43840 GL |
546 | |
547 | out: | |
548 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
549 | } | |
550 | ||
40e2e092 GL |
551 | static u32 mclk_get_divisor(struct platform_device *pdev, |
552 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 553 | { |
cf34cba7 GL |
554 | unsigned long mclk = pcdev->mclk; |
555 | u32 div; | |
3bc43840 GL |
556 | unsigned long lcdclk; |
557 | ||
cf34cba7 GL |
558 | lcdclk = clk_get_rate(pcdev->clk); |
559 | pcdev->ciclk = lcdclk; | |
3bc43840 | 560 | |
cf34cba7 GL |
561 | /* mclk <= ciclk / 4 (27.4.2) */ |
562 | if (mclk > lcdclk / 4) { | |
563 | mclk = lcdclk / 4; | |
295ab497 RJ |
564 | dev_warn(pcdev_to_dev(pcdev), |
565 | "Limiting master clock to %lu\n", mclk); | |
cf34cba7 GL |
566 | } |
567 | ||
568 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
569 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 570 | |
cf34cba7 GL |
571 | /* If we're not supplying MCLK, leave it at 0 */ |
572 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
573 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 574 | |
295ab497 | 575 | dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 576 | lcdclk, mclk, div); |
3bc43840 GL |
577 | |
578 | return div; | |
579 | } | |
580 | ||
cf34cba7 GL |
581 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
582 | unsigned long pclk) | |
583 | { | |
584 | /* We want a timeout > 1 pixel time, not ">=" */ | |
585 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
586 | ||
587 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
588 | } | |
589 | ||
7102b773 | 590 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 591 | { |
3bc43840 GL |
592 | u32 cicr4 = 0; |
593 | ||
5ca11fa3 EM |
594 | /* disable all interrupts */ |
595 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
596 | |
597 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
598 | cicr4 |= CICR4_PCLK_EN; | |
599 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
600 | cicr4 |= CICR4_MCLK_EN; | |
601 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
602 | cicr4 |= CICR4_PCP; | |
603 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
604 | cicr4 |= CICR4_HSP; | |
605 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
606 | cicr4 |= CICR4_VSP; | |
607 | ||
cf34cba7 GL |
608 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
609 | ||
610 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
611 | /* Initialise the timeout under the assumption pclk = mclk */ | |
612 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
613 | else | |
614 | /* "Safe default" - 13MHz */ | |
615 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 616 | |
91acd962 | 617 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
618 | } |
619 | ||
7102b773 | 620 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 621 | { |
91acd962 | 622 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
623 | } |
624 | ||
e623ebe6 | 625 | static void pxa_camera_eof(unsigned long arg) |
3bc43840 | 626 | { |
e623ebe6 RJ |
627 | struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg; |
628 | unsigned long cifr; | |
256b0233 | 629 | struct pxa_buffer *buf; |
3bc43840 | 630 | |
e009ebd5 | 631 | dev_dbg(pcdev_to_dev(pcdev), |
e623ebe6 RJ |
632 | "Camera interrupt status 0x%x\n", |
633 | __raw_readl(pcdev->base + CISR)); | |
634 | ||
635 | /* Reset the FIFOs */ | |
636 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
637 | __raw_writel(cifr, pcdev->base + CIFR); | |
638 | ||
639 | pcdev->active = list_first_entry(&pcdev->capture, | |
e009ebd5 RJ |
640 | struct pxa_buffer, queue); |
641 | buf = pcdev->active; | |
e623ebe6 RJ |
642 | pxa_videobuf_set_actdma(pcdev, buf); |
643 | ||
644 | pxa_dma_start_channels(pcdev); | |
645 | } | |
646 | ||
647 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
648 | { | |
649 | struct pxa_camera_dev *pcdev = data; | |
650 | unsigned long status, cicr0; | |
651 | ||
5ca11fa3 | 652 | status = __raw_readl(pcdev->base + CISR); |
e009ebd5 | 653 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 654 | "Camera interrupt status 0x%lx\n", status); |
3bc43840 | 655 | |
e7c50688 GL |
656 | if (!status) |
657 | return IRQ_NONE; | |
658 | ||
5ca11fa3 | 659 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
660 | |
661 | if (status & CISR_EOF) { | |
5ca11fa3 EM |
662 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
663 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e623ebe6 | 664 | tasklet_schedule(&pcdev->task_eof); |
e7c50688 GL |
665 | } |
666 | ||
3bc43840 GL |
667 | return IRQ_HANDLED; |
668 | } | |
669 | ||
39b553db GL |
670 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
671 | { | |
295ab497 RJ |
672 | struct pxa_camera_dev *pcdev = icd_to_pcdev(icd); |
673 | ||
674 | dev_info(pcdev_to_dev(pcdev), "PXA Camera driver attached to camera %d\n", | |
39b553db GL |
675 | icd->devnum); |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | static void pxa_camera_remove_device(struct soc_camera_device *icd) | |
681 | { | |
295ab497 RJ |
682 | struct pxa_camera_dev *pcdev = icd_to_pcdev(icd); |
683 | ||
684 | dev_info(pcdev_to_dev(pcdev), "PXA Camera driver detached from camera %d\n", | |
39b553db GL |
685 | icd->devnum); |
686 | } | |
687 | ||
1c3bb743 GL |
688 | /* |
689 | * The following two functions absolutely depend on the fact, that | |
690 | * there can be only one camera on PXA quick capture interface | |
dd669e90 | 691 | * Called with .host_lock held |
1c3bb743 | 692 | */ |
39b553db | 693 | static int pxa_camera_clock_start(struct soc_camera_host *ici) |
3bc43840 | 694 | { |
3bc43840 | 695 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 | 696 | |
7102b773 | 697 | pxa_camera_activate(pcdev); |
40e2e092 | 698 | |
40e2e092 | 699 | return 0; |
3bc43840 GL |
700 | } |
701 | ||
dd669e90 | 702 | /* Called with .host_lock held */ |
39b553db | 703 | static void pxa_camera_clock_stop(struct soc_camera_host *ici) |
3bc43840 | 704 | { |
3bc43840 GL |
705 | struct pxa_camera_dev *pcdev = ici->priv; |
706 | ||
3bc43840 | 707 | /* disable capture, disable interrupts */ |
5ca11fa3 | 708 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 709 | |
3bc43840 | 710 | /* Stop DMA engine */ |
1e77d55a | 711 | pxa_dma_stop_channels(pcdev); |
7102b773 | 712 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
713 | } |
714 | ||
ad5f2e85 GL |
715 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
716 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 717 | { |
ad5f2e85 GL |
718 | /* |
719 | * Platform specified synchronization and pixel clock polarities are | |
720 | * only a recommendation and are only used during probing. The PXA270 | |
721 | * quick capture interface supports both. | |
722 | */ | |
723 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
724 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
725 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
726 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
727 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
728 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
729 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
730 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
731 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
732 | |
733 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
734 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
735 | return 0; | |
ad5f2e85 | 736 | |
679419aa | 737 | return -EINVAL; |
ad5f2e85 GL |
738 | } |
739 | ||
6a6c8786 GL |
740 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
741 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 742 | { |
7dfff953 | 743 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 744 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 745 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 746 | unsigned long dw, bpp; |
32536108 | 747 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
b36bcbd6 | 748 | int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top); |
32536108 GL |
749 | |
750 | if (ret < 0) | |
751 | y_skip_top = 0; | |
3bc43840 | 752 | |
5d28d525 GL |
753 | /* |
754 | * Datawidth is now guaranteed to be equal to one of the three values. | |
755 | * We fix bit-per-pixel equal to data-width... | |
756 | */ | |
679419aa GL |
757 | switch (icd->current_fmt->host_fmt->bits_per_sample) { |
758 | case 10: | |
3bc43840 GL |
759 | dw = 4; |
760 | bpp = 0x40; | |
761 | break; | |
679419aa | 762 | case 9: |
3bc43840 GL |
763 | dw = 3; |
764 | bpp = 0x20; | |
765 | break; | |
766 | default: | |
5d28d525 GL |
767 | /* |
768 | * Actually it can only be 8 now, | |
769 | * default is just to silence compiler warnings | |
770 | */ | |
679419aa | 771 | case 8: |
3bc43840 GL |
772 | dw = 2; |
773 | bpp = 0; | |
774 | } | |
775 | ||
776 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
777 | cicr4 |= CICR4_PCLK_EN; | |
778 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
779 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 780 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 781 | cicr4 |= CICR4_PCP; |
679419aa | 782 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 783 | cicr4 |= CICR4_HSP; |
679419aa | 784 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
785 | cicr4 |= CICR4_VSP; |
786 | ||
5ca11fa3 | 787 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 788 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 789 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 790 | |
6a6c8786 | 791 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
792 | |
793 | switch (pixfmt) { | |
794 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 795 | pcdev->channels = 3; |
a5462e5b | 796 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
797 | /* |
798 | * Normally, pxa bus wants as input UYVY format. We allow all | |
799 | * reorderings of the YUV422 format, as no processing is done, | |
800 | * and the YUV stream is just passed through without any | |
801 | * transformation. Note that UYVY is the only format that | |
802 | * should be used if pxa framebuffer Overlay2 is used. | |
803 | */ | |
804 | case V4L2_PIX_FMT_UYVY: | |
805 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 806 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 807 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
808 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
809 | break; | |
810 | case V4L2_PIX_FMT_RGB555: | |
811 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
812 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
813 | break; | |
814 | case V4L2_PIX_FMT_RGB565: | |
815 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
816 | break; | |
817 | } | |
818 | ||
5ca11fa3 | 819 | cicr2 = 0; |
6a6c8786 | 820 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 821 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 822 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
823 | |
824 | __raw_writel(cicr1, pcdev->base + CICR1); | |
825 | __raw_writel(cicr2, pcdev->base + CICR2); | |
826 | __raw_writel(cicr3, pcdev->base + CICR3); | |
827 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
828 | |
829 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
830 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
831 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
832 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
833 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
834 | } |
835 | ||
6f28435d RJ |
836 | /* |
837 | * Videobuf2 section | |
838 | */ | |
839 | static void pxa_buffer_cleanup(struct pxa_buffer *buf) | |
840 | { | |
841 | int i; | |
842 | ||
843 | for (i = 0; i < 3 && buf->descs[i]; i++) { | |
844 | dmaengine_desc_free(buf->descs[i]); | |
845 | kfree(buf->sg[i]); | |
846 | buf->descs[i] = NULL; | |
847 | buf->sg[i] = NULL; | |
848 | buf->sg_len[i] = 0; | |
849 | buf->plane_sizes[i] = 0; | |
850 | } | |
851 | buf->nb_planes = 0; | |
852 | } | |
853 | ||
854 | static int pxa_buffer_init(struct pxa_camera_dev *pcdev, | |
855 | struct pxa_buffer *buf) | |
856 | { | |
857 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; | |
858 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); | |
859 | int nb_channels = pcdev->channels; | |
860 | int i, ret = 0; | |
861 | unsigned long size = vb2_plane_size(vb, 0); | |
862 | ||
863 | switch (nb_channels) { | |
864 | case 1: | |
865 | buf->plane_sizes[0] = size; | |
866 | break; | |
867 | case 3: | |
868 | buf->plane_sizes[0] = size / 2; | |
869 | buf->plane_sizes[1] = size / 4; | |
870 | buf->plane_sizes[2] = size / 4; | |
871 | break; | |
872 | default: | |
873 | return -EINVAL; | |
874 | }; | |
875 | buf->nb_planes = nb_channels; | |
876 | ||
877 | ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels, | |
878 | buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL); | |
879 | if (ret < 0) { | |
880 | dev_err(pcdev_to_dev(pcdev), | |
881 | "sg_split failed: %d\n", ret); | |
882 | return ret; | |
883 | } | |
884 | for (i = 0; i < nb_channels; i++) { | |
885 | ret = pxa_init_dma_channel(pcdev, buf, i, | |
886 | buf->sg[i], buf->sg_len[i]); | |
887 | if (ret) { | |
888 | pxa_buffer_cleanup(buf); | |
889 | return ret; | |
890 | } | |
891 | } | |
892 | INIT_LIST_HEAD(&buf->queue); | |
893 | ||
894 | return ret; | |
895 | } | |
896 | ||
897 | static void pxac_vb2_cleanup(struct vb2_buffer *vb) | |
898 | { | |
899 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
900 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
901 | ||
902 | dev_dbg(pcdev_to_dev(pcdev), | |
903 | "%s(vb=%p)\n", __func__, vb); | |
904 | pxa_buffer_cleanup(buf); | |
905 | } | |
906 | ||
907 | static void pxac_vb2_queue(struct vb2_buffer *vb) | |
908 | { | |
909 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
910 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
911 | ||
912 | dev_dbg(pcdev_to_dev(pcdev), | |
913 | "%s(vb=%p) nb_channels=%d size=%lu active=%p\n", | |
914 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0), | |
915 | pcdev->active); | |
916 | ||
917 | list_add_tail(&buf->queue, &pcdev->capture); | |
918 | ||
919 | pxa_dma_add_tail_buf(pcdev, buf); | |
920 | } | |
921 | ||
922 | /* | |
923 | * Please check the DMA prepared buffer structure in : | |
924 | * Documentation/video4linux/pxa_camera.txt | |
925 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
926 | * modification while DMA chain is running will work anyway. | |
927 | */ | |
928 | static int pxac_vb2_prepare(struct vb2_buffer *vb) | |
929 | { | |
930 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
931 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
932 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); | |
933 | int ret = 0; | |
934 | ||
935 | switch (pcdev->channels) { | |
936 | case 1: | |
937 | case 3: | |
938 | vb2_set_plane_payload(vb, 0, icd->sizeimage); | |
939 | break; | |
940 | default: | |
941 | return -EINVAL; | |
942 | } | |
943 | ||
944 | dev_dbg(pcdev_to_dev(pcdev), | |
945 | "%s (vb=%p) nb_channels=%d size=%lu\n", | |
946 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0)); | |
947 | ||
948 | WARN_ON(!icd->current_fmt); | |
949 | ||
950 | #ifdef DEBUG | |
951 | /* | |
952 | * This can be useful if you want to see if we actually fill | |
953 | * the buffer with something | |
954 | */ | |
955 | for (i = 0; i < vb->num_planes; i++) | |
956 | memset((void *)vb2_plane_vaddr(vb, i), | |
957 | 0xaa, vb2_get_plane_payload(vb, i)); | |
958 | #endif | |
959 | ||
960 | /* | |
961 | * I think, in buf_prepare you only have to protect global data, | |
962 | * the actual buffer is yours | |
963 | */ | |
964 | buf->inwork = 0; | |
965 | pxa_videobuf_set_actdma(pcdev, buf); | |
966 | ||
967 | return ret; | |
968 | } | |
969 | ||
970 | static int pxac_vb2_init(struct vb2_buffer *vb) | |
971 | { | |
972 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
973 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
974 | ||
975 | dev_dbg(pcdev_to_dev(pcdev), | |
976 | "%s(nb_channels=%d)\n", | |
977 | __func__, pcdev->channels); | |
978 | ||
979 | return pxa_buffer_init(pcdev, buf); | |
980 | } | |
981 | ||
982 | static int pxac_vb2_queue_setup(struct vb2_queue *vq, | |
983 | unsigned int *nbufs, | |
984 | unsigned int *num_planes, unsigned int sizes[], | |
985 | struct device *alloc_devs[]) | |
986 | { | |
987 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
988 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); | |
989 | int size = icd->sizeimage; | |
990 | ||
991 | dev_dbg(pcdev_to_dev(pcdev), | |
992 | "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n", | |
993 | __func__, vq, *nbufs, *num_planes, size); | |
994 | /* | |
995 | * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P | |
996 | * format, even if there are 3 planes Y, U and V, we reply there is only | |
997 | * one plane, containing Y, U and V data, one after the other. | |
998 | */ | |
999 | if (*num_planes) | |
1000 | return sizes[0] < size ? -EINVAL : 0; | |
1001 | ||
1002 | *num_planes = 1; | |
1003 | switch (pcdev->channels) { | |
1004 | case 1: | |
1005 | case 3: | |
1006 | sizes[0] = size; | |
1007 | break; | |
1008 | default: | |
1009 | return -EINVAL; | |
1010 | } | |
1011 | ||
1012 | if (!*nbufs) | |
1013 | *nbufs = 1; | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count) | |
1019 | { | |
1020 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
1021 | ||
1022 | dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n", | |
1023 | __func__, count, pcdev->active); | |
1024 | ||
1025 | if (!pcdev->active) | |
1026 | pxa_camera_start_capture(pcdev); | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | static void pxac_vb2_stop_streaming(struct vb2_queue *vq) | |
1032 | { | |
1033 | vb2_wait_for_all_buffers(vq); | |
1034 | } | |
1035 | ||
1036 | static struct vb2_ops pxac_vb2_ops = { | |
1037 | .queue_setup = pxac_vb2_queue_setup, | |
1038 | .buf_init = pxac_vb2_init, | |
1039 | .buf_prepare = pxac_vb2_prepare, | |
1040 | .buf_queue = pxac_vb2_queue, | |
1041 | .buf_cleanup = pxac_vb2_cleanup, | |
1042 | .start_streaming = pxac_vb2_start_streaming, | |
1043 | .stop_streaming = pxac_vb2_stop_streaming, | |
1044 | .wait_prepare = vb2_ops_wait_prepare, | |
1045 | .wait_finish = vb2_ops_wait_finish, | |
1046 | }; | |
1047 | ||
1048 | static int pxa_camera_init_videobuf2(struct vb2_queue *vq, | |
1049 | struct soc_camera_device *icd) | |
1050 | { | |
1051 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
1052 | struct pxa_camera_dev *pcdev = ici->priv; | |
1053 | int ret; | |
1054 | ||
1055 | vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
1056 | vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
1057 | vq->drv_priv = pcdev; | |
1058 | vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
1059 | vq->buf_struct_size = sizeof(struct pxa_buffer); | |
1060 | ||
1061 | vq->ops = &pxac_vb2_ops; | |
1062 | vq->mem_ops = &vb2_dma_sg_memops; | |
1063 | ||
1064 | ret = vb2_queue_init(vq); | |
1065 | dev_dbg(pcdev_to_dev(pcdev), | |
1066 | "vb2_queue_init(vq=%p): %d\n", vq, ret); | |
1067 | ||
1068 | return ret; | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * Video ioctls section | |
1073 | */ | |
8843d119 | 1074 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) |
6a6c8786 | 1075 | { |
679419aa | 1076 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1077 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
6a6c8786 | 1078 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa | 1079 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 1080 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
679419aa | 1081 | unsigned long bus_flags, common_flags; |
760697be | 1082 | int ret; |
6a6c8786 GL |
1083 | struct pxa_cam *cam = icd->host_priv; |
1084 | ||
d2dcad49 GL |
1085 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1086 | &bus_flags); | |
6a6c8786 GL |
1087 | if (ret < 0) |
1088 | return ret; | |
1089 | ||
b36bcbd6 | 1090 | ret = sensor_call(pcdev, video, g_mbus_config, &cfg); |
679419aa GL |
1091 | if (!ret) { |
1092 | common_flags = soc_mbus_config_compatible(&cfg, | |
1093 | bus_flags); | |
1094 | if (!common_flags) { | |
295ab497 | 1095 | dev_warn(pcdev_to_dev(pcdev), |
679419aa GL |
1096 | "Flags incompatible: camera 0x%x, host 0x%lx\n", |
1097 | cfg.flags, bus_flags); | |
1098 | return -EINVAL; | |
1099 | } | |
1100 | } else if (ret != -ENOIOCTLCMD) { | |
1101 | return ret; | |
1102 | } else { | |
1103 | common_flags = bus_flags; | |
1104 | } | |
6a6c8786 GL |
1105 | |
1106 | pcdev->channels = 1; | |
1107 | ||
1108 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1109 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1110 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1111 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1112 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1113 | else |
679419aa | 1114 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1115 | } |
1116 | ||
679419aa GL |
1117 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1118 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1119 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1120 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1121 | else |
679419aa | 1122 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1123 | } |
1124 | ||
679419aa GL |
1125 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1126 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1127 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1128 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1129 | else |
679419aa | 1130 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1131 | } |
1132 | ||
679419aa | 1133 | cfg.flags = common_flags; |
b36bcbd6 | 1134 | ret = sensor_call(pcdev, video, s_mbus_config, &cfg); |
679419aa | 1135 | if (ret < 0 && ret != -ENOIOCTLCMD) { |
295ab497 | 1136 | dev_dbg(pcdev_to_dev(pcdev), "camera s_mbus_config(0x%lx) returned %d\n", |
679419aa | 1137 | common_flags, ret); |
6a6c8786 | 1138 | return ret; |
679419aa GL |
1139 | } |
1140 | ||
1141 | cam->flags = common_flags; | |
6a6c8786 GL |
1142 | |
1143 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1144 | |
1145 | return 0; | |
1146 | } | |
1147 | ||
2a48fc73 RJ |
1148 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1149 | unsigned char buswidth) | |
ad5f2e85 | 1150 | { |
679419aa | 1151 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1152 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1153 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa GL |
1154 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1155 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1156 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1157 | |
1158 | if (ret < 0) | |
1159 | return ret; | |
1160 | ||
b36bcbd6 | 1161 | ret = sensor_call(pcdev, video, g_mbus_config, &cfg); |
679419aa GL |
1162 | if (!ret) { |
1163 | common_flags = soc_mbus_config_compatible(&cfg, | |
1164 | bus_flags); | |
1165 | if (!common_flags) { | |
295ab497 | 1166 | dev_warn(pcdev_to_dev(pcdev), |
679419aa GL |
1167 | "Flags incompatible: camera 0x%x, host 0x%lx\n", |
1168 | cfg.flags, bus_flags); | |
1169 | return -EINVAL; | |
1170 | } | |
1171 | } else if (ret == -ENOIOCTLCMD) { | |
1172 | ret = 0; | |
1173 | } | |
ad5f2e85 | 1174 | |
679419aa | 1175 | return ret; |
ad5f2e85 GL |
1176 | } |
1177 | ||
760697be | 1178 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1179 | { |
760697be GL |
1180 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1181 | .name = "Planar YUV422 16 bit", | |
1182 | .bits_per_sample = 8, | |
1183 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1184 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1185 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1186 | }, |
1187 | }; | |
1188 | ||
760697be GL |
1189 | /* This will be corrected as we get more formats */ |
1190 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1191 | { |
760697be GL |
1192 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1193 | (fmt->bits_per_sample == 8 && | |
1194 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1195 | (fmt->bits_per_sample > 8 && | |
1196 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1197 | } |
1198 | ||
3805f201 | 1199 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1200 | struct soc_camera_format_xlate *xlate) |
1201 | { | |
760697be | 1202 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
295ab497 | 1203 | struct pxa_camera_dev *pcdev = icd_to_pcdev(icd); |
760697be | 1204 | int formats = 0, ret; |
6a6c8786 | 1205 | struct pxa_cam *cam; |
ebcff5fc HV |
1206 | struct v4l2_subdev_mbus_code_enum code = { |
1207 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1208 | .index = idx, | |
1209 | }; | |
760697be | 1210 | const struct soc_mbus_pixelfmt *fmt; |
2a48fc73 | 1211 | |
b36bcbd6 | 1212 | ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code); |
760697be GL |
1213 | if (ret < 0) |
1214 | /* No more formats */ | |
1215 | return 0; | |
2a48fc73 | 1216 | |
ebcff5fc | 1217 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 1218 | if (!fmt) { |
295ab497 | 1219 | dev_err(pcdev_to_dev(pcdev), "Invalid format code #%u: %d\n", idx, code.code); |
2a48fc73 | 1220 | return 0; |
760697be | 1221 | } |
3bc43840 | 1222 | |
760697be GL |
1223 | /* This also checks support for the requested bits-per-sample */ |
1224 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1225 | if (ret < 0) |
1226 | return 0; | |
1227 | ||
6a6c8786 GL |
1228 | if (!icd->host_priv) { |
1229 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1230 | if (!cam) | |
1231 | return -ENOMEM; | |
1232 | ||
1233 | icd->host_priv = cam; | |
1234 | } else { | |
1235 | cam = icd->host_priv; | |
1236 | } | |
1237 | ||
ebcff5fc | 1238 | switch (code.code) { |
27ffaeb0 | 1239 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1240 | formats++; |
1241 | if (xlate) { | |
760697be | 1242 | xlate->host_fmt = &pxa_camera_formats[0]; |
ebcff5fc | 1243 | xlate->code = code.code; |
2a48fc73 | 1244 | xlate++; |
295ab497 RJ |
1245 | dev_dbg(pcdev_to_dev(pcdev), |
1246 | "Providing format %s using code %d\n", | |
ebcff5fc | 1247 | pxa_camera_formats[0].name, code.code); |
2a48fc73 | 1248 | } |
27ffaeb0 BB |
1249 | case MEDIA_BUS_FMT_VYUY8_2X8: |
1250 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
1251 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
1252 | case MEDIA_BUS_FMT_RGB565_2X8_LE: | |
1253 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: | |
760697be | 1254 | if (xlate) |
295ab497 RJ |
1255 | dev_dbg(pcdev_to_dev(pcdev), |
1256 | "Providing format %s packed\n", | |
760697be | 1257 | fmt->name); |
2a48fc73 RJ |
1258 | break; |
1259 | default: | |
760697be GL |
1260 | if (!pxa_camera_packing_supported(fmt)) |
1261 | return 0; | |
1262 | if (xlate) | |
295ab497 | 1263 | dev_dbg(pcdev_to_dev(pcdev), |
2a48fc73 | 1264 | "Providing format %s in pass-through mode\n", |
760697be GL |
1265 | fmt->name); |
1266 | } | |
1267 | ||
1268 | /* Generic pass-through */ | |
1269 | formats++; | |
1270 | if (xlate) { | |
1271 | xlate->host_fmt = fmt; | |
ebcff5fc | 1272 | xlate->code = code.code; |
760697be | 1273 | xlate++; |
2a48fc73 RJ |
1274 | } |
1275 | ||
1276 | return formats; | |
1277 | } | |
1278 | ||
6a6c8786 GL |
1279 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1280 | { | |
1281 | kfree(icd->host_priv); | |
1282 | icd->host_priv = NULL; | |
1283 | } | |
1284 | ||
760697be | 1285 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1286 | { |
1287 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1288 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1289 | (width & 0x01); | |
6a6c8786 GL |
1290 | } |
1291 | ||
10d5509c HV |
1292 | static int pxa_camera_set_selection(struct soc_camera_device *icd, |
1293 | struct v4l2_selection *sel) | |
09e231b3 | 1294 | { |
10d5509c | 1295 | const struct v4l2_rect *rect = &sel->r; |
7dfff953 GL |
1296 | struct device *dev = icd->parent; |
1297 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
09e231b3 | 1298 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1299 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1300 | struct soc_camera_sense sense = { |
1301 | .master_clock = pcdev->mclk, | |
1302 | .pixel_clock_max = pcdev->ciclk / 4, | |
1303 | }; | |
da298c6d HV |
1304 | struct v4l2_subdev_format fmt = { |
1305 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1306 | }; | |
1307 | struct v4l2_mbus_framefmt *mf = &fmt.format; | |
6a6c8786 | 1308 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1309 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
10d5509c HV |
1310 | struct v4l2_subdev_selection sdsel = { |
1311 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1312 | .target = sel->target, | |
1313 | .flags = sel->flags, | |
1314 | .r = sel->r, | |
1315 | }; | |
09e231b3 GL |
1316 | int ret; |
1317 | ||
1318 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1319 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1320 | icd->sense = &sense; | |
1321 | ||
b36bcbd6 | 1322 | ret = sensor_call(pcdev, pad, set_selection, NULL, &sdsel); |
09e231b3 GL |
1323 | |
1324 | icd->sense = NULL; | |
1325 | ||
1326 | if (ret < 0) { | |
295ab497 | 1327 | dev_warn(pcdev_to_dev(pcdev), "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1328 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1329 | return ret; |
1330 | } | |
10d5509c | 1331 | sel->r = sdsel.r; |
6a6c8786 | 1332 | |
b36bcbd6 | 1333 | ret = sensor_call(pcdev, pad, get_fmt, NULL, &fmt); |
6a6c8786 GL |
1334 | if (ret < 0) |
1335 | return ret; | |
1336 | ||
da298c6d | 1337 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1338 | /* |
1339 | * Camera cropping produced a frame beyond our capabilities. | |
1340 | * FIXME: just extract a subframe, that we can process. | |
1341 | */ | |
da298c6d HV |
1342 | v4l_bound_align_image(&mf->width, 48, 2048, 1, |
1343 | &mf->height, 32, 2048, 0, | |
760697be | 1344 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
b36bcbd6 | 1345 | ret = sensor_call(pcdev, pad, set_fmt, NULL, &fmt); |
6a6c8786 GL |
1346 | if (ret < 0) |
1347 | return ret; | |
1348 | ||
da298c6d | 1349 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
295ab497 | 1350 | dev_warn(pcdev_to_dev(pcdev), |
6a6c8786 GL |
1351 | "Inconsistent state. Use S_FMT to repair\n"); |
1352 | return -EINVAL; | |
1353 | } | |
1354 | } | |
1355 | ||
1356 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1357 | if (sense.pixel_clock > sense.pixel_clock_max) { |
295ab497 | 1358 | dev_err(pcdev_to_dev(pcdev), |
09e231b3 GL |
1359 | "pixel clock %lu set by the camera too high!", |
1360 | sense.pixel_clock); | |
1361 | return -EIO; | |
1362 | } | |
1363 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1364 | } | |
1365 | ||
da298c6d HV |
1366 | icd->user_width = mf->width; |
1367 | icd->user_height = mf->height; | |
6a6c8786 | 1368 | |
760697be | 1369 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1370 | |
09e231b3 GL |
1371 | return ret; |
1372 | } | |
1373 | ||
d8fac217 | 1374 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1375 | struct v4l2_format *f) |
ad5f2e85 | 1376 | { |
7dfff953 GL |
1377 | struct device *dev = icd->parent; |
1378 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
cf34cba7 | 1379 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1380 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1381 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1382 | struct soc_camera_sense sense = { |
1383 | .master_clock = pcdev->mclk, | |
1384 | .pixel_clock_max = pcdev->ciclk / 4, | |
1385 | }; | |
09e231b3 | 1386 | struct v4l2_pix_format *pix = &f->fmt.pix; |
ebf984bb HV |
1387 | struct v4l2_subdev_format format = { |
1388 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1389 | }; | |
1390 | struct v4l2_mbus_framefmt *mf = &format.format; | |
0ad675eb | 1391 | int ret; |
25c4d74e | 1392 | |
09e231b3 GL |
1393 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1394 | if (!xlate) { | |
295ab497 RJ |
1395 | dev_warn(pcdev_to_dev(pcdev), |
1396 | "Format %x not found\n", pix->pixelformat); | |
09e231b3 | 1397 | return -EINVAL; |
0ad675eb | 1398 | } |
2a48fc73 | 1399 | |
cf34cba7 GL |
1400 | /* If PCLK is used to latch data from the sensor, check sense */ |
1401 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1402 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1403 | icd->sense = &sense; |
1404 | ||
ebf984bb HV |
1405 | mf->width = pix->width; |
1406 | mf->height = pix->height; | |
1407 | mf->field = pix->field; | |
1408 | mf->colorspace = pix->colorspace; | |
1409 | mf->code = xlate->code; | |
760697be | 1410 | |
b36bcbd6 | 1411 | ret = sensor_call(pcdev, pad, set_fmt, NULL, &format); |
760697be | 1412 | |
ebf984bb | 1413 | if (mf->code != xlate->code) |
760697be | 1414 | return -EINVAL; |
2a48fc73 | 1415 | |
cf34cba7 GL |
1416 | icd->sense = NULL; |
1417 | ||
1418 | if (ret < 0) { | |
295ab497 RJ |
1419 | dev_warn(pcdev_to_dev(pcdev), |
1420 | "Failed to configure for format %x\n", | |
09e231b3 | 1421 | pix->pixelformat); |
ebf984bb | 1422 | } else if (pxa_camera_check_frame(mf->width, mf->height)) { |
295ab497 | 1423 | dev_warn(pcdev_to_dev(pcdev), |
6a6c8786 | 1424 | "Camera driver produced an unsupported frame %dx%d\n", |
ebf984bb | 1425 | mf->width, mf->height); |
6a6c8786 | 1426 | ret = -EINVAL; |
cf34cba7 GL |
1427 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1428 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
295ab497 | 1429 | dev_err(pcdev_to_dev(pcdev), |
cf34cba7 GL |
1430 | "pixel clock %lu set by the camera too high!", |
1431 | sense.pixel_clock); | |
1432 | return -EIO; | |
1433 | } | |
1434 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1435 | } | |
2a48fc73 | 1436 | |
760697be GL |
1437 | if (ret < 0) |
1438 | return ret; | |
1439 | ||
ebf984bb HV |
1440 | pix->width = mf->width; |
1441 | pix->height = mf->height; | |
1442 | pix->field = mf->field; | |
1443 | pix->colorspace = mf->colorspace; | |
760697be | 1444 | icd->current_fmt = xlate; |
25c4d74e GL |
1445 | |
1446 | return ret; | |
ad5f2e85 GL |
1447 | } |
1448 | ||
d8fac217 GL |
1449 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1450 | struct v4l2_format *f) | |
3bc43840 | 1451 | { |
c9c1f1c0 | 1452 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
295ab497 | 1453 | struct pxa_camera_dev *pcdev = icd_to_pcdev(icd); |
2a48fc73 RJ |
1454 | const struct soc_camera_format_xlate *xlate; |
1455 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
5eab4983 HV |
1456 | struct v4l2_subdev_pad_config pad_cfg; |
1457 | struct v4l2_subdev_format format = { | |
1458 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1459 | }; | |
1460 | struct v4l2_mbus_framefmt *mf = &format.format; | |
2a48fc73 | 1461 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1462 | int ret; |
a2c8c68c | 1463 | |
2a48fc73 RJ |
1464 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1465 | if (!xlate) { | |
295ab497 | 1466 | dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt); |
25c4d74e | 1467 | return -EINVAL; |
2a48fc73 | 1468 | } |
25c4d74e | 1469 | |
92a8337b | 1470 | /* |
4a6b8df2 TP |
1471 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1472 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1473 | * inserted between Y and U planes, and U and V planes, which violates | |
1474 | * the YUV422P standard. | |
92a8337b | 1475 | */ |
4a6b8df2 TP |
1476 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1477 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1478 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1479 | |
ad5f2e85 | 1480 | /* limit to sensor capabilities */ |
5eab4983 HV |
1481 | mf->width = pix->width; |
1482 | mf->height = pix->height; | |
91401219 | 1483 | /* Only progressive video supported so far */ |
5eab4983 HV |
1484 | mf->field = V4L2_FIELD_NONE; |
1485 | mf->colorspace = pix->colorspace; | |
1486 | mf->code = xlate->code; | |
bf507158 | 1487 | |
b36bcbd6 | 1488 | ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format); |
760697be GL |
1489 | if (ret < 0) |
1490 | return ret; | |
06daa1af | 1491 | |
5eab4983 HV |
1492 | pix->width = mf->width; |
1493 | pix->height = mf->height; | |
1494 | pix->colorspace = mf->colorspace; | |
760697be | 1495 | |
5eab4983 | 1496 | switch (mf->field) { |
760697be GL |
1497 | case V4L2_FIELD_ANY: |
1498 | case V4L2_FIELD_NONE: | |
1499 | pix->field = V4L2_FIELD_NONE; | |
1500 | break; | |
1501 | default: | |
1502 | /* TODO: support interlaced at least in pass-through mode */ | |
295ab497 | 1503 | dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n", |
5eab4983 | 1504 | mf->field); |
06daa1af GL |
1505 | return -EINVAL; |
1506 | } | |
1507 | ||
bf507158 | 1508 | return ret; |
3bc43840 GL |
1509 | } |
1510 | ||
7102b773 | 1511 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1512 | { |
57bee29d | 1513 | struct soc_camera_device *icd = file->private_data; |
3bc43840 | 1514 | |
e009ebd5 | 1515 | return vb2_poll(&icd->vb2_vidq, file, pt); |
3bc43840 GL |
1516 | } |
1517 | ||
7102b773 GL |
1518 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1519 | struct v4l2_capability *cap) | |
3bc43840 GL |
1520 | { |
1521 | /* cap->name is set by the firendly caller:-> */ | |
1522 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
7d96c3e4 GL |
1523 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1524 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
3bc43840 GL |
1525 | |
1526 | return 0; | |
1527 | } | |
1528 | ||
6f28435d RJ |
1529 | /* |
1530 | * Driver probe, remove, suspend and resume operations | |
1531 | */ | |
7254026c | 1532 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1533 | { |
7254026c | 1534 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1535 | struct pxa_camera_dev *pcdev = ici->priv; |
1536 | int i = 0, ret = 0; | |
1537 | ||
5ca11fa3 EM |
1538 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1539 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1540 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1541 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1542 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1543 | |
f7f6ce2d GL |
1544 | if (pcdev->soc_host.icd) { |
1545 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
b36bcbd6 | 1546 | ret = sensor_call(pcdev, core, s_power, 0); |
497833c6 GL |
1547 | if (ret == -ENOIOCTLCMD) |
1548 | ret = 0; | |
1549 | } | |
3f6ac497 RJ |
1550 | |
1551 | return ret; | |
1552 | } | |
1553 | ||
7254026c | 1554 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1555 | { |
7254026c | 1556 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1557 | struct pxa_camera_dev *pcdev = ici->priv; |
1558 | int i = 0, ret = 0; | |
1559 | ||
5ca11fa3 EM |
1560 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1561 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1562 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1563 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1564 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1565 | |
f7f6ce2d GL |
1566 | if (pcdev->soc_host.icd) { |
1567 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
b36bcbd6 | 1568 | ret = sensor_call(pcdev, core, s_power, 1); |
497833c6 GL |
1569 | if (ret == -ENOIOCTLCMD) |
1570 | ret = 0; | |
1571 | } | |
3f6ac497 RJ |
1572 | |
1573 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1574 | if (!ret && pcdev->active) |
1575 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1576 | |
1577 | return ret; | |
1578 | } | |
1579 | ||
b8d9904c GL |
1580 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1581 | .owner = THIS_MODULE, | |
1582 | .add = pxa_camera_add_device, | |
1583 | .remove = pxa_camera_remove_device, | |
39b553db GL |
1584 | .clock_start = pxa_camera_clock_start, |
1585 | .clock_stop = pxa_camera_clock_stop, | |
10d5509c | 1586 | .set_selection = pxa_camera_set_selection, |
2a48fc73 | 1587 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1588 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1589 | .set_fmt = pxa_camera_set_fmt, |
1590 | .try_fmt = pxa_camera_try_fmt, | |
e009ebd5 | 1591 | .init_videobuf2 = pxa_camera_init_videobuf2, |
b8d9904c GL |
1592 | .poll = pxa_camera_poll, |
1593 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1594 | .set_bus_param = pxa_camera_set_bus_param, |
1595 | }; | |
1596 | ||
e9a1d94f RJ |
1597 | static int pxa_camera_pdata_from_dt(struct device *dev, |
1598 | struct pxa_camera_dev *pcdev) | |
1599 | { | |
1600 | u32 mclk_rate; | |
1601 | struct device_node *np = dev->of_node; | |
1602 | struct v4l2_of_endpoint ep; | |
1603 | int err = of_property_read_u32(np, "clock-frequency", | |
1604 | &mclk_rate); | |
1605 | if (!err) { | |
1606 | pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; | |
1607 | pcdev->mclk = mclk_rate; | |
1608 | } | |
1609 | ||
1610 | np = of_graph_get_next_endpoint(np, NULL); | |
1611 | if (!np) { | |
295ab497 | 1612 | dev_err(pcdev_to_dev(pcdev), "could not find endpoint\n"); |
e9a1d94f RJ |
1613 | return -EINVAL; |
1614 | } | |
1615 | ||
1616 | err = v4l2_of_parse_endpoint(np, &ep); | |
1617 | if (err) { | |
295ab497 | 1618 | dev_err(pcdev_to_dev(pcdev), "could not parse endpoint\n"); |
e9a1d94f RJ |
1619 | goto out; |
1620 | } | |
1621 | ||
1622 | switch (ep.bus.parallel.bus_width) { | |
1623 | case 4: | |
1624 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; | |
1625 | break; | |
1626 | case 5: | |
1627 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; | |
1628 | break; | |
1629 | case 8: | |
1630 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; | |
1631 | break; | |
1632 | case 9: | |
1633 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; | |
1634 | break; | |
1635 | case 10: | |
1636 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1637 | break; | |
1638 | default: | |
1639 | break; | |
c611c908 | 1640 | } |
e9a1d94f RJ |
1641 | |
1642 | if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) | |
1643 | pcdev->platform_flags |= PXA_CAMERA_MASTER; | |
1644 | if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
1645 | pcdev->platform_flags |= PXA_CAMERA_HSP; | |
1646 | if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
1647 | pcdev->platform_flags |= PXA_CAMERA_VSP; | |
1648 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
1649 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; | |
1650 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
1651 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; | |
1652 | ||
1653 | out: | |
1654 | of_node_put(np); | |
1655 | ||
1656 | return err; | |
1657 | } | |
1658 | ||
4c62e976 | 1659 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1660 | { |
1661 | struct pxa_camera_dev *pcdev; | |
1662 | struct resource *res; | |
1663 | void __iomem *base; | |
1e77d55a RJ |
1664 | struct dma_slave_config config = { |
1665 | .src_addr_width = 0, | |
1666 | .src_maxburst = 8, | |
1667 | .direction = DMA_DEV_TO_MEM, | |
1668 | }; | |
1669 | dma_cap_mask_t mask; | |
1670 | struct pxad_param params; | |
02da4659 | 1671 | int irq; |
1e77d55a | 1672 | int err = 0, i; |
3bc43840 GL |
1673 | |
1674 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1675 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1676 | if (!res || irq < 0) |
1677 | return -ENODEV; | |
3bc43840 | 1678 | |
47de201c | 1679 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1680 | if (!pcdev) { |
7102b773 | 1681 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1682 | return -ENOMEM; |
3bc43840 GL |
1683 | } |
1684 | ||
47de201c JL |
1685 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1686 | if (IS_ERR(pcdev->clk)) | |
1687 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1688 | |
3bc43840 GL |
1689 | pcdev->res = res; |
1690 | ||
1691 | pcdev->pdata = pdev->dev.platform_data; | |
e9a1d94f RJ |
1692 | if (&pdev->dev.of_node && !pcdev->pdata) { |
1693 | err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); | |
1694 | } else { | |
1695 | pcdev->platform_flags = pcdev->pdata->flags; | |
1696 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
1697 | } | |
1698 | if (err < 0) | |
1699 | return err; | |
1700 | ||
ad5f2e85 GL |
1701 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1702 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1703 | /* |
1704 | * Platform hasn't set available data widths. This is bad. | |
1705 | * Warn and use a default. | |
1706 | */ | |
3bc43840 GL |
1707 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1708 | "data widths, using default 10 bit\n"); | |
1709 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1710 | } | |
679419aa GL |
1711 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1712 | pcdev->width_flags = 1 << 7; | |
1713 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1714 | pcdev->width_flags |= 1 << 8; | |
1715 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1716 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 | 1717 | if (!pcdev->mclk) { |
3bc43840 | 1718 | dev_warn(&pdev->dev, |
cf34cba7 | 1719 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1720 | "Using default 20MHz\n"); |
cf34cba7 | 1721 | pcdev->mclk = 20000000; |
3bc43840 GL |
1722 | } |
1723 | ||
40e2e092 | 1724 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1725 | |
3bc43840 GL |
1726 | INIT_LIST_HEAD(&pcdev->capture); |
1727 | spin_lock_init(&pcdev->lock); | |
1728 | ||
1729 | /* | |
1730 | * Request the regions. | |
1731 | */ | |
8efdb135 SK |
1732 | base = devm_ioremap_resource(&pdev->dev, res); |
1733 | if (IS_ERR(base)) | |
1734 | return PTR_ERR(base); | |
1735 | ||
3bc43840 GL |
1736 | pcdev->irq = irq; |
1737 | pcdev->base = base; | |
3bc43840 GL |
1738 | |
1739 | /* request dma */ | |
1e77d55a RJ |
1740 | dma_cap_zero(mask); |
1741 | dma_cap_set(DMA_SLAVE, mask); | |
1742 | dma_cap_set(DMA_PRIVATE, mask); | |
1743 | ||
1744 | params.prio = 0; | |
1745 | params.drcmr = 68; | |
1746 | pcdev->dma_chans[0] = | |
1747 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1748 | ¶ms, &pdev->dev, "CI_Y"); | |
1749 | if (!pcdev->dma_chans[0]) { | |
eff505fa | 1750 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
1e77d55a | 1751 | return -ENODEV; |
3bc43840 | 1752 | } |
a5462e5b | 1753 | |
1e77d55a RJ |
1754 | params.drcmr = 69; |
1755 | pcdev->dma_chans[1] = | |
1756 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1757 | ¶ms, &pdev->dev, "CI_U"); | |
1758 | if (!pcdev->dma_chans[1]) { | |
1759 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); | |
a5462e5b MR |
1760 | goto exit_free_dma_y; |
1761 | } | |
a5462e5b | 1762 | |
1e77d55a RJ |
1763 | params.drcmr = 70; |
1764 | pcdev->dma_chans[2] = | |
1765 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1766 | ¶ms, &pdev->dev, "CI_V"); | |
1767 | if (!pcdev->dma_chans[2]) { | |
eff505fa | 1768 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1769 | goto exit_free_dma_u; |
1770 | } | |
3bc43840 | 1771 | |
1e77d55a RJ |
1772 | for (i = 0; i < 3; i++) { |
1773 | config.src_addr = pcdev->res->start + CIBR0 + i * 8; | |
1774 | err = dmaengine_slave_config(pcdev->dma_chans[i], &config); | |
1775 | if (err < 0) { | |
1776 | dev_err(&pdev->dev, "dma slave config failed: %d\n", | |
1777 | err); | |
1778 | goto exit_free_dma; | |
1779 | } | |
1780 | } | |
3bc43840 GL |
1781 | |
1782 | /* request irq */ | |
47de201c JL |
1783 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1784 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1785 | if (err) { |
47de201c | 1786 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1787 | goto exit_free_dma; |
1788 | } | |
1789 | ||
eb6c8558 GL |
1790 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1791 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1792 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1793 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1794 | pcdev->soc_host.nr = pdev->id; |
e623ebe6 | 1795 | tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev); |
eff505fa | 1796 | |
eb6c8558 | 1797 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 | 1798 | if (err) |
47de201c | 1799 | goto exit_free_dma; |
3bc43840 GL |
1800 | |
1801 | return 0; | |
1802 | ||
3bc43840 | 1803 | exit_free_dma: |
1e77d55a | 1804 | dma_release_channel(pcdev->dma_chans[2]); |
a5462e5b | 1805 | exit_free_dma_u: |
1e77d55a | 1806 | dma_release_channel(pcdev->dma_chans[1]); |
a5462e5b | 1807 | exit_free_dma_y: |
1e77d55a | 1808 | dma_release_channel(pcdev->dma_chans[0]); |
3bc43840 GL |
1809 | return err; |
1810 | } | |
1811 | ||
4c62e976 | 1812 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 1813 | { |
eff505fa GL |
1814 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1815 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1816 | struct pxa_camera_dev, soc_host); | |
3bc43840 | 1817 | |
1e77d55a RJ |
1818 | dma_release_channel(pcdev->dma_chans[0]); |
1819 | dma_release_channel(pcdev->dma_chans[1]); | |
1820 | dma_release_channel(pcdev->dma_chans[2]); | |
3bc43840 | 1821 | |
eff505fa | 1822 | soc_camera_host_unregister(soc_host); |
3bc43840 | 1823 | |
7102b773 | 1824 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1825 | |
3bc43840 GL |
1826 | return 0; |
1827 | } | |
1828 | ||
56a49194 | 1829 | static const struct dev_pm_ops pxa_camera_pm = { |
7254026c GL |
1830 | .suspend = pxa_camera_suspend, |
1831 | .resume = pxa_camera_resume, | |
1832 | }; | |
1833 | ||
e9a1d94f RJ |
1834 | static const struct of_device_id pxa_camera_of_match[] = { |
1835 | { .compatible = "marvell,pxa270-qci", }, | |
1836 | {}, | |
1837 | }; | |
1838 | MODULE_DEVICE_TABLE(of, pxa_camera_of_match); | |
1839 | ||
3bc43840 | 1840 | static struct platform_driver pxa_camera_driver = { |
6003b2ad | 1841 | .driver = { |
3bc43840 | 1842 | .name = PXA_CAM_DRV_NAME, |
7254026c | 1843 | .pm = &pxa_camera_pm, |
e9a1d94f | 1844 | .of_match_table = of_match_ptr(pxa_camera_of_match), |
3bc43840 GL |
1845 | }, |
1846 | .probe = pxa_camera_probe, | |
4c62e976 | 1847 | .remove = pxa_camera_remove, |
3bc43840 GL |
1848 | }; |
1849 | ||
1d6629b1 | 1850 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
1851 | |
1852 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1853 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1854 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1855 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1856 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |