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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
3bc43840 GL |
25 | #include <linux/device.h> |
26 | #include <linux/platform_device.h> | |
3bc43840 | 27 | #include <linux/clk.h> |
d514edac | 28 | #include <linux/sched.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
3bc43840 GL |
30 | |
31 | #include <media/v4l2-common.h> | |
32 | #include <media/v4l2-dev.h> | |
092d3921 | 33 | #include <media/videobuf-dma-sg.h> |
3bc43840 | 34 | #include <media/soc_camera.h> |
760697be | 35 | #include <media/soc_mediabus.h> |
3bc43840 GL |
36 | |
37 | #include <linux/videodev2.h> | |
38 | ||
cfbaf4df | 39 | #include <mach/dma.h> |
293b2da1 | 40 | #include <linux/platform_data/camera-pxa.h> |
3bc43840 | 41 | |
64dc3c1a | 42 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
43 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
44 | ||
5ca11fa3 EM |
45 | /* Camera Interface */ |
46 | #define CICR0 0x0000 | |
47 | #define CICR1 0x0004 | |
48 | #define CICR2 0x0008 | |
49 | #define CICR3 0x000C | |
50 | #define CICR4 0x0010 | |
51 | #define CISR 0x0014 | |
52 | #define CIFR 0x0018 | |
53 | #define CITOR 0x001C | |
54 | #define CIBR0 0x0028 | |
55 | #define CIBR1 0x0030 | |
56 | #define CIBR2 0x0038 | |
57 | ||
58 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
59 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
60 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
61 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
62 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
63 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
64 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
65 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
66 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
67 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
68 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
69 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
70 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
71 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
72 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
73 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
74 | ||
75 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
76 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
77 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
78 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
79 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
80 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
81 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
82 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
83 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
84 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
85 | ||
86 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
89 | wait count mask */ | |
90 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
91 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
92 | wait count mask */ | |
93 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
94 | wait count mask */ | |
95 | ||
96 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
99 | wait count mask */ | |
100 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
101 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
102 | wait count mask */ | |
103 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
104 | ||
105 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
106 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
107 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
108 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
109 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
110 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
111 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
112 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
113 | ||
114 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
115 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
116 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
117 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
118 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
119 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
120 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
121 | #define CISR_EOL (1 << 8) /* End of line */ | |
122 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
123 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
124 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
125 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
126 | #define CISR_EOF (1 << 3) /* End of frame */ | |
127 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
128 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
129 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
130 | ||
131 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
132 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
133 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
134 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
135 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
136 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
137 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
138 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
139 | ||
7102b773 GL |
140 | #define CICR0_SIM_MP (0 << 24) |
141 | #define CICR0_SIM_SP (1 << 24) | |
142 | #define CICR0_SIM_MS (2 << 24) | |
143 | #define CICR0_SIM_EP (3 << 24) | |
144 | #define CICR0_SIM_ES (4 << 24) | |
145 | ||
146 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
147 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
148 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
149 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
150 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
151 | |
152 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
153 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
154 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
155 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
156 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
157 | ||
158 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
159 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
160 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
161 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
162 | ||
3bc43840 GL |
163 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
164 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
165 | CICR0_EOFM | CICR0_FOM) | |
166 | ||
3bc43840 GL |
167 | /* |
168 | * Structures | |
169 | */ | |
a5462e5b MR |
170 | enum pxa_camera_active_dma { |
171 | DMA_Y = 0x1, | |
172 | DMA_U = 0x2, | |
173 | DMA_V = 0x4, | |
174 | }; | |
175 | ||
176 | /* descriptor needed for the PXA DMA engine */ | |
177 | struct pxa_cam_dma { | |
178 | dma_addr_t sg_dma; | |
179 | struct pxa_dma_desc *sg_cpu; | |
180 | size_t sg_size; | |
181 | int sglen; | |
182 | }; | |
3bc43840 GL |
183 | |
184 | /* buffer for one video frame */ | |
185 | struct pxa_buffer { | |
186 | /* common v4l buffer stuff -- must be first */ | |
760697be GL |
187 | struct videobuf_buffer vb; |
188 | enum v4l2_mbus_pixelcode code; | |
a5462e5b | 189 | /* our descriptor lists for Y, U and V channels */ |
760697be GL |
190 | struct pxa_cam_dma dmas[3]; |
191 | int inwork; | |
192 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
193 | }; |
194 | ||
3bc43840 | 195 | struct pxa_camera_dev { |
eb6c8558 | 196 | struct soc_camera_host soc_host; |
5d28d525 GL |
197 | /* |
198 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 199 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
200 | * one camera, they will have to modify this driver too |
201 | */ | |
3bc43840 GL |
202 | struct soc_camera_device *icd; |
203 | struct clk *clk; | |
204 | ||
205 | unsigned int irq; | |
206 | void __iomem *base; | |
a5462e5b | 207 | |
e7c50688 | 208 | int channels; |
a5462e5b | 209 | unsigned int dma_chans[3]; |
3bc43840 | 210 | |
3bc43840 GL |
211 | struct pxacamera_platform_data *pdata; |
212 | struct resource *res; | |
213 | unsigned long platform_flags; | |
cf34cba7 GL |
214 | unsigned long ciclk; |
215 | unsigned long mclk; | |
216 | u32 mclk_divisor; | |
679419aa | 217 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
218 | |
219 | struct list_head capture; | |
220 | ||
221 | spinlock_t lock; | |
222 | ||
3bc43840 | 223 | struct pxa_buffer *active; |
5aa2110f | 224 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
225 | |
226 | u32 save_cicr[5]; | |
3bc43840 GL |
227 | }; |
228 | ||
6a6c8786 GL |
229 | struct pxa_cam { |
230 | unsigned long flags; | |
231 | }; | |
232 | ||
3bc43840 GL |
233 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
234 | ||
235 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
236 | ||
237 | /* | |
238 | * Videobuf operations | |
239 | */ | |
7102b773 GL |
240 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
241 | unsigned int *size) | |
3bc43840 GL |
242 | { |
243 | struct soc_camera_device *icd = vq->priv_data; | |
244 | ||
7dfff953 | 245 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); |
3bc43840 | 246 | |
2b61d46e | 247 | *size = icd->sizeimage; |
3bc43840 GL |
248 | |
249 | if (0 == *count) | |
250 | *count = 32; | |
dab7e310 AB |
251 | if (*size * *count > vid_limit * 1024 * 1024) |
252 | *count = (vid_limit * 1024 * 1024) / *size; | |
3bc43840 GL |
253 | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
258 | { | |
259 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 260 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 261 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); |
a5462e5b | 262 | int i; |
3bc43840 GL |
263 | |
264 | BUG_ON(in_interrupt()); | |
265 | ||
7dfff953 | 266 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
267 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
268 | ||
5d28d525 GL |
269 | /* |
270 | * This waits until this buffer is out of danger, i.e., until it is no | |
271 | * longer in STATE_QUEUED or STATE_ACTIVE | |
272 | */ | |
0e0809a5 | 273 | videobuf_waiton(vq, &buf->vb, 0, 0); |
95268403 | 274 | videobuf_dma_unmap(vq->dev, dma); |
3bc43840 GL |
275 | videobuf_dma_free(dma); |
276 | ||
a5462e5b MR |
277 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
278 | if (buf->dmas[i].sg_cpu) | |
96c75399 GL |
279 | dma_free_coherent(ici->v4l2_dev.dev, |
280 | buf->dmas[i].sg_size, | |
a5462e5b MR |
281 | buf->dmas[i].sg_cpu, |
282 | buf->dmas[i].sg_dma); | |
283 | buf->dmas[i].sg_cpu = NULL; | |
284 | } | |
3bc43840 GL |
285 | |
286 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
287 | } | |
288 | ||
37f5aefd RJ |
289 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, |
290 | int sg_first_ofs, int size) | |
291 | { | |
292 | int i, offset, dma_len, xfer_len; | |
293 | struct scatterlist *sg; | |
294 | ||
295 | offset = sg_first_ofs; | |
296 | for_each_sg(sglist, sg, sglen, i) { | |
297 | dma_len = sg_dma_len(sg); | |
298 | ||
299 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
300 | xfer_len = roundup(min(dma_len - offset, size), 8); | |
301 | ||
302 | size = max(0, size - xfer_len); | |
303 | offset = 0; | |
304 | if (size == 0) | |
305 | break; | |
306 | } | |
307 | ||
308 | BUG_ON(size != 0); | |
309 | return i + 1; | |
310 | } | |
311 | ||
312 | /** | |
313 | * pxa_init_dma_channel - init dma descriptors | |
314 | * @pcdev: pxa camera device | |
315 | * @buf: pxa buffer to find pxa dma channel | |
316 | * @dma: dma video buffer | |
317 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
318 | * @cibr: camera Receive Buffer Register | |
319 | * @size: bytes to transfer | |
320 | * @sg_first: first element of sg_list | |
321 | * @sg_first_ofs: offset in first element of sg_list | |
322 | * | |
323 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
324 | * Beware sg_first and sg_first_ofs are both input and output parameters. | |
325 | * | |
326 | * Returns 0 or -ENOMEM if no coherent memory is available | |
327 | */ | |
a5462e5b MR |
328 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
329 | struct pxa_buffer *buf, | |
330 | struct videobuf_dmabuf *dma, int channel, | |
37f5aefd RJ |
331 | int cibr, int size, |
332 | struct scatterlist **sg_first, int *sg_first_ofs) | |
a5462e5b MR |
333 | { |
334 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
979ea1dd | 335 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
336 | struct scatterlist *sg; |
337 | int i, offset, sglen; | |
338 | int dma_len = 0, xfer_len = 0; | |
a5462e5b MR |
339 | |
340 | if (pxa_dma->sg_cpu) | |
979ea1dd | 341 | dma_free_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
342 | pxa_dma->sg_cpu, pxa_dma->sg_dma); |
343 | ||
37f5aefd RJ |
344 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, |
345 | *sg_first_ofs, size); | |
346 | ||
a5462e5b | 347 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); |
979ea1dd | 348 | pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
349 | &pxa_dma->sg_dma, GFP_KERNEL); |
350 | if (!pxa_dma->sg_cpu) | |
351 | return -ENOMEM; | |
352 | ||
353 | pxa_dma->sglen = sglen; | |
37f5aefd | 354 | offset = *sg_first_ofs; |
a5462e5b | 355 | |
979ea1dd | 356 | dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", |
37f5aefd | 357 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); |
a5462e5b | 358 | |
37f5aefd RJ |
359 | |
360 | for_each_sg(*sg_first, sg, sglen, i) { | |
361 | dma_len = sg_dma_len(sg); | |
a5462e5b MR |
362 | |
363 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
37f5aefd | 364 | xfer_len = roundup(min(dma_len - offset, size), 8); |
a5462e5b | 365 | |
37f5aefd RJ |
366 | size = max(0, size - xfer_len); |
367 | ||
368 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
369 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | |
a5462e5b MR |
370 | pxa_dma->sg_cpu[i].dcmd = |
371 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
256b0233 RJ |
372 | #ifdef DEBUG |
373 | if (!i) | |
374 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | |
375 | #endif | |
a5462e5b MR |
376 | pxa_dma->sg_cpu[i].ddadr = |
377 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
37f5aefd | 378 | |
979ea1dd | 379 | dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", |
37f5aefd RJ |
380 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), |
381 | sg_dma_address(sg) + offset, xfer_len); | |
382 | offset = 0; | |
383 | ||
384 | if (size == 0) | |
385 | break; | |
a5462e5b MR |
386 | } |
387 | ||
256b0233 RJ |
388 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; |
389 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | |
a5462e5b | 390 | |
37f5aefd RJ |
391 | /* |
392 | * Handle 1 special case : | |
393 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | |
394 | * to dma_len (end on PAGE boundary). In this case, the sg element | |
395 | * for next plane should be the next after the last used to store the | |
396 | * last scatter gather RAM page | |
397 | */ | |
398 | if (xfer_len >= dma_len) { | |
399 | *sg_first_ofs = xfer_len - dma_len; | |
400 | *sg_first = sg_next(sg); | |
401 | } else { | |
402 | *sg_first_ofs = xfer_len; | |
403 | *sg_first = sg; | |
404 | } | |
405 | ||
a5462e5b MR |
406 | return 0; |
407 | } | |
408 | ||
256b0233 RJ |
409 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
410 | struct pxa_buffer *buf) | |
411 | { | |
412 | buf->active_dma = DMA_Y; | |
413 | if (pcdev->channels == 3) | |
414 | buf->active_dma |= DMA_U | DMA_V; | |
415 | } | |
416 | ||
417 | /* | |
418 | * Please check the DMA prepared buffer structure in : | |
419 | * Documentation/video4linux/pxa_camera.txt | |
420 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
421 | * modification while DMA chain is running will work anyway. | |
422 | */ | |
7102b773 GL |
423 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
424 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
425 | { |
426 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 427 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 428 | struct pxa_camera_dev *pcdev = ici->priv; |
979ea1dd | 429 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 | 430 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); |
a5462e5b | 431 | int ret; |
a5462e5b | 432 | int size_y, size_u = 0, size_v = 0; |
3bc43840 | 433 | |
979ea1dd | 434 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
435 | vb, vb->baddr, vb->bsize); |
436 | ||
437 | /* Added list head initialization on alloc */ | |
438 | WARN_ON(!list_empty(&vb->queue)); | |
439 | ||
440 | #ifdef DEBUG | |
5d28d525 GL |
441 | /* |
442 | * This can be useful if you want to see if we actually fill | |
443 | * the buffer with something | |
444 | */ | |
3bc43840 GL |
445 | memset((void *)vb->baddr, 0xaa, vb->bsize); |
446 | #endif | |
447 | ||
448 | BUG_ON(NULL == icd->current_fmt); | |
449 | ||
5d28d525 GL |
450 | /* |
451 | * I think, in buf_prepare you only have to protect global data, | |
452 | * the actual buffer is yours | |
453 | */ | |
3bc43840 GL |
454 | buf->inwork = 1; |
455 | ||
760697be | 456 | if (buf->code != icd->current_fmt->code || |
6a6c8786 GL |
457 | vb->width != icd->user_width || |
458 | vb->height != icd->user_height || | |
3bc43840 | 459 | vb->field != field) { |
760697be | 460 | buf->code = icd->current_fmt->code; |
6a6c8786 GL |
461 | vb->width = icd->user_width; |
462 | vb->height = icd->user_height; | |
3bc43840 GL |
463 | vb->field = field; |
464 | vb->state = VIDEOBUF_NEEDS_INIT; | |
465 | } | |
466 | ||
2b61d46e | 467 | vb->size = icd->sizeimage; |
3bc43840 GL |
468 | if (0 != vb->baddr && vb->bsize < vb->size) { |
469 | ret = -EINVAL; | |
470 | goto out; | |
471 | } | |
472 | ||
473 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd RJ |
474 | int size = vb->size; |
475 | int next_ofs = 0; | |
3bc43840 | 476 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
37f5aefd | 477 | struct scatterlist *sg; |
3bc43840 GL |
478 | |
479 | ret = videobuf_iolock(vq, vb, NULL); | |
480 | if (ret) | |
481 | goto fail; | |
482 | ||
5aa2110f | 483 | if (pcdev->channels == 3) { |
a5462e5b MR |
484 | size_y = size / 2; |
485 | size_u = size_v = size / 4; | |
486 | } else { | |
a5462e5b MR |
487 | size_y = size; |
488 | } | |
489 | ||
37f5aefd | 490 | sg = dma->sglist; |
3bc43840 | 491 | |
37f5aefd RJ |
492 | /* init DMA for Y channel */ |
493 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | |
494 | &sg, &next_ofs); | |
a5462e5b | 495 | if (ret) { |
979ea1dd | 496 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); |
3bc43840 GL |
497 | goto fail; |
498 | } | |
499 | ||
37f5aefd RJ |
500 | /* init DMA for U channel */ |
501 | if (size_u) | |
502 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
503 | size_u, &sg, &next_ofs); | |
504 | if (ret) { | |
979ea1dd | 505 | dev_err(dev, "DMA initialization for U failed\n"); |
37f5aefd RJ |
506 | goto fail_u; |
507 | } | |
508 | ||
509 | /* init DMA for V channel */ | |
510 | if (size_v) | |
511 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
512 | size_v, &sg, &next_ofs); | |
513 | if (ret) { | |
979ea1dd | 514 | dev_err(dev, "DMA initialization for V failed\n"); |
37f5aefd | 515 | goto fail_v; |
3bc43840 | 516 | } |
3bc43840 GL |
517 | |
518 | vb->state = VIDEOBUF_PREPARED; | |
519 | } | |
520 | ||
521 | buf->inwork = 0; | |
256b0233 | 522 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
523 | |
524 | return 0; | |
525 | ||
a5462e5b | 526 | fail_v: |
979ea1dd | 527 | dma_free_coherent(dev, buf->dmas[1].sg_size, |
a5462e5b MR |
528 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); |
529 | fail_u: | |
979ea1dd | 530 | dma_free_coherent(dev, buf->dmas[0].sg_size, |
a5462e5b | 531 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); |
3bc43840 GL |
532 | fail: |
533 | free_buffer(vq, buf); | |
534 | out: | |
535 | buf->inwork = 0; | |
536 | return ret; | |
537 | } | |
538 | ||
256b0233 RJ |
539 | /** |
540 | * pxa_dma_start_channels - start DMA channel for active buffer | |
541 | * @pcdev: pxa camera device | |
542 | * | |
543 | * Initialize DMA channels to the beginning of the active video buffer, and | |
544 | * start these channels. | |
545 | */ | |
546 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
547 | { | |
548 | int i; | |
549 | struct pxa_buffer *active; | |
550 | ||
551 | active = pcdev->active; | |
552 | ||
553 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
554 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
555 | "%s (channel=%d) ddadr=%08x\n", __func__, | |
256b0233 RJ |
556 | i, active->dmas[i].sg_dma); |
557 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | |
558 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
559 | } | |
560 | } | |
561 | ||
562 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
563 | { | |
564 | int i; | |
565 | ||
566 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
567 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
568 | "%s (channel=%d)\n", __func__, i); | |
256b0233 RJ |
569 | DCSR(pcdev->dma_chans[i]) = 0; |
570 | } | |
571 | } | |
572 | ||
256b0233 RJ |
573 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
574 | struct pxa_buffer *buf) | |
575 | { | |
576 | int i; | |
577 | struct pxa_dma_desc *buf_last_desc; | |
578 | ||
579 | for (i = 0; i < pcdev->channels; i++) { | |
580 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | |
581 | buf_last_desc->ddadr = DDADR_STOP; | |
582 | ||
ae7410e7 GL |
583 | if (pcdev->sg_tail[i]) |
584 | /* Link the new buffer to the old tail */ | |
585 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | |
256b0233 | 586 | |
ae7410e7 GL |
587 | /* Update the channel tail */ |
588 | pcdev->sg_tail[i] = buf_last_desc; | |
589 | } | |
256b0233 RJ |
590 | } |
591 | ||
592 | /** | |
593 | * pxa_camera_start_capture - start video capturing | |
594 | * @pcdev: camera device | |
595 | * | |
596 | * Launch capturing. DMA channels should not be active yet. They should get | |
597 | * activated at the end of frame interrupt, to capture only whole frames, and | |
598 | * never begin the capture of a partial frame. | |
599 | */ | |
600 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
601 | { | |
a47f6be4 | 602 | unsigned long cicr0; |
256b0233 | 603 | |
979ea1dd | 604 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
605 | /* Enable End-Of-Frame Interrupt */ |
606 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
607 | cicr0 &= ~CICR0_EOFM; | |
608 | __raw_writel(cicr0, pcdev->base + CICR0); | |
609 | } | |
610 | ||
611 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
612 | { | |
613 | unsigned long cicr0; | |
614 | ||
615 | pxa_dma_stop_channels(pcdev); | |
616 | ||
617 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
618 | __raw_writel(cicr0, pcdev->base + CICR0); | |
619 | ||
8c62e221 | 620 | pcdev->active = NULL; |
979ea1dd | 621 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
622 | } |
623 | ||
2dd54a54 | 624 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ |
7102b773 GL |
625 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
626 | struct videobuf_buffer *vb) | |
3bc43840 GL |
627 | { |
628 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 629 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 GL |
630 | struct pxa_camera_dev *pcdev = ici->priv; |
631 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 | 632 | |
7dfff953 | 633 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", |
0166b743 | 634 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); |
256b0233 | 635 | |
3bc43840 GL |
636 | list_add_tail(&vb->queue, &pcdev->capture); |
637 | ||
638 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 639 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 640 | |
256b0233 RJ |
641 | if (!pcdev->active) |
642 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
643 | } |
644 | ||
645 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
646 | struct videobuf_buffer *vb) | |
647 | { | |
648 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
649 | #ifdef DEBUG | |
650 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 651 | struct device *dev = icd->parent; |
3bc43840 | 652 | |
0166b743 | 653 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
654 | vb, vb->baddr, vb->bsize); |
655 | ||
656 | switch (vb->state) { | |
657 | case VIDEOBUF_ACTIVE: | |
0166b743 | 658 | dev_dbg(dev, "%s (active)\n", __func__); |
3bc43840 GL |
659 | break; |
660 | case VIDEOBUF_QUEUED: | |
0166b743 | 661 | dev_dbg(dev, "%s (queued)\n", __func__); |
3bc43840 GL |
662 | break; |
663 | case VIDEOBUF_PREPARED: | |
0166b743 | 664 | dev_dbg(dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
665 | break; |
666 | default: | |
0166b743 | 667 | dev_dbg(dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
668 | break; |
669 | } | |
670 | #endif | |
671 | ||
672 | free_buffer(vq, buf); | |
673 | } | |
674 | ||
a5462e5b MR |
675 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
676 | struct videobuf_buffer *vb, | |
677 | struct pxa_buffer *buf) | |
678 | { | |
256b0233 | 679 | int i; |
5ca11fa3 | 680 | |
a5462e5b MR |
681 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
682 | list_del_init(&vb->queue); | |
683 | vb->state = VIDEOBUF_DONE; | |
8e6057b5 | 684 | v4l2_get_timestamp(&vb->ts); |
a5462e5b MR |
685 | vb->field_count++; |
686 | wake_up(&vb->done); | |
979ea1dd GL |
687 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", |
688 | __func__, vb); | |
a5462e5b MR |
689 | |
690 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 691 | pxa_camera_stop_capture(pcdev); |
256b0233 RJ |
692 | for (i = 0; i < pcdev->channels; i++) |
693 | pcdev->sg_tail[i] = NULL; | |
a5462e5b MR |
694 | return; |
695 | } | |
696 | ||
697 | pcdev->active = list_entry(pcdev->capture.next, | |
698 | struct pxa_buffer, vb.queue); | |
699 | } | |
700 | ||
256b0233 RJ |
701 | /** |
702 | * pxa_camera_check_link_miss - check missed DMA linking | |
703 | * @pcdev: camera device | |
704 | * | |
705 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
706 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 707 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
708 | * This function restarts the capture for this corner case, where : |
709 | * - DADR() == DADDR_STOP | |
710 | * - a videobuffer is queued on the pcdev->capture list | |
711 | * | |
712 | * Please check the "DMA hot chaining timeslice issue" in | |
713 | * Documentation/video4linux/pxa_camera.txt | |
714 | * | |
715 | * Context: should only be called within the dma irq handler | |
716 | */ | |
717 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | |
718 | { | |
719 | int i, is_dma_stopped = 1; | |
720 | ||
721 | for (i = 0; i < pcdev->channels; i++) | |
722 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | |
723 | is_dma_stopped = 0; | |
979ea1dd GL |
724 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
725 | "%s : top queued buffer=%p, dma_stopped=%d\n", | |
256b0233 RJ |
726 | __func__, pcdev->active, is_dma_stopped); |
727 | if (pcdev->active && is_dma_stopped) | |
728 | pxa_camera_start_capture(pcdev); | |
729 | } | |
730 | ||
a5462e5b MR |
731 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, |
732 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 733 | { |
979ea1dd | 734 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 GL |
735 | struct pxa_buffer *buf; |
736 | unsigned long flags; | |
e7c50688 | 737 | u32 status, camera_status, overrun; |
3bc43840 GL |
738 | struct videobuf_buffer *vb; |
739 | ||
740 | spin_lock_irqsave(&pcdev->lock, flags); | |
741 | ||
a5462e5b | 742 | status = DCSR(channel); |
256b0233 RJ |
743 | DCSR(channel) = status; |
744 | ||
745 | camera_status = __raw_readl(pcdev->base + CISR); | |
746 | overrun = CISR_IFO_0; | |
747 | if (pcdev->channels == 3) | |
748 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 749 | |
3bc43840 | 750 | if (status & DCSR_BUSERR) { |
979ea1dd | 751 | dev_err(dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
752 | goto out; |
753 | } | |
754 | ||
256b0233 | 755 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { |
979ea1dd GL |
756 | dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", |
757 | status); | |
3bc43840 GL |
758 | goto out; |
759 | } | |
760 | ||
8c62e221 RJ |
761 | /* |
762 | * pcdev->active should not be NULL in DMA irq handler. | |
763 | * | |
764 | * But there is one corner case : if capture was stopped due to an | |
765 | * overrun of channel 1, and at that same channel 2 was completed. | |
766 | * | |
767 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
768 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
769 | * DMA irq handler will already be pending for channel 2. So on entering | |
770 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
771 | * that is normal. | |
772 | */ | |
773 | if (!pcdev->active) | |
3bc43840 | 774 | goto out; |
3bc43840 GL |
775 | |
776 | vb = &pcdev->active->vb; | |
777 | buf = container_of(vb, struct pxa_buffer, vb); | |
778 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 779 | |
979ea1dd | 780 | dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", |
256b0233 RJ |
781 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", |
782 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | |
783 | ||
784 | if (status & DCSR_ENDINTR) { | |
8c62e221 RJ |
785 | /* |
786 | * It's normal if the last frame creates an overrun, as there | |
787 | * are no more DMA descriptors to fetch from QCI fifos | |
788 | */ | |
789 | if (camera_status & overrun && | |
790 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | |
979ea1dd | 791 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", |
256b0233 RJ |
792 | camera_status); |
793 | pxa_camera_stop_capture(pcdev); | |
794 | pxa_camera_start_capture(pcdev); | |
795 | goto out; | |
796 | } | |
797 | buf->active_dma &= ~act_dma; | |
798 | if (!buf->active_dma) { | |
799 | pxa_camera_wakeup(pcdev, vb, buf); | |
800 | pxa_camera_check_link_miss(pcdev); | |
801 | } | |
802 | } | |
3bc43840 GL |
803 | |
804 | out: | |
805 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
806 | } | |
807 | ||
a5462e5b MR |
808 | static void pxa_camera_dma_irq_y(int channel, void *data) |
809 | { | |
810 | struct pxa_camera_dev *pcdev = data; | |
811 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
812 | } | |
813 | ||
814 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
815 | { | |
816 | struct pxa_camera_dev *pcdev = data; | |
817 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
818 | } | |
819 | ||
820 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
821 | { | |
822 | struct pxa_camera_dev *pcdev = data; | |
823 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
824 | } | |
825 | ||
7102b773 | 826 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
827 | .buf_setup = pxa_videobuf_setup, |
828 | .buf_prepare = pxa_videobuf_prepare, | |
829 | .buf_queue = pxa_videobuf_queue, | |
830 | .buf_release = pxa_videobuf_release, | |
831 | }; | |
832 | ||
a034d1b7 | 833 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
834 | struct soc_camera_device *icd) |
835 | { | |
7dfff953 | 836 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
a034d1b7 MD |
837 | struct pxa_camera_dev *pcdev = ici->priv; |
838 | ||
5d28d525 GL |
839 | /* |
840 | * We must pass NULL as dev pointer, then all pci_* dma operations | |
841 | * transform to normal dma_* ones. | |
842 | */ | |
a034d1b7 | 843 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 | 844 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
47ebe3f9 | 845 | sizeof(struct pxa_buffer), icd, &ici->host_lock); |
092d3921 PZ |
846 | } |
847 | ||
40e2e092 GL |
848 | static u32 mclk_get_divisor(struct platform_device *pdev, |
849 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 850 | { |
cf34cba7 | 851 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 852 | struct device *dev = &pdev->dev; |
cf34cba7 | 853 | u32 div; |
3bc43840 GL |
854 | unsigned long lcdclk; |
855 | ||
cf34cba7 GL |
856 | lcdclk = clk_get_rate(pcdev->clk); |
857 | pcdev->ciclk = lcdclk; | |
3bc43840 | 858 | |
cf34cba7 GL |
859 | /* mclk <= ciclk / 4 (27.4.2) */ |
860 | if (mclk > lcdclk / 4) { | |
861 | mclk = lcdclk / 4; | |
979ea1dd | 862 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
863 | } |
864 | ||
865 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
866 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 867 | |
cf34cba7 GL |
868 | /* If we're not supplying MCLK, leave it at 0 */ |
869 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
870 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 871 | |
979ea1dd | 872 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 873 | lcdclk, mclk, div); |
3bc43840 GL |
874 | |
875 | return div; | |
876 | } | |
877 | ||
cf34cba7 GL |
878 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
879 | unsigned long pclk) | |
880 | { | |
881 | /* We want a timeout > 1 pixel time, not ">=" */ | |
882 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
883 | ||
884 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
885 | } | |
886 | ||
7102b773 | 887 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 888 | { |
3bc43840 GL |
889 | u32 cicr4 = 0; |
890 | ||
5ca11fa3 EM |
891 | /* disable all interrupts */ |
892 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
893 | |
894 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
895 | cicr4 |= CICR4_PCLK_EN; | |
896 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
897 | cicr4 |= CICR4_MCLK_EN; | |
898 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
899 | cicr4 |= CICR4_PCP; | |
900 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
901 | cicr4 |= CICR4_HSP; | |
902 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
903 | cicr4 |= CICR4_VSP; | |
904 | ||
cf34cba7 GL |
905 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
906 | ||
907 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
908 | /* Initialise the timeout under the assumption pclk = mclk */ | |
909 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
910 | else | |
911 | /* "Safe default" - 13MHz */ | |
912 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 913 | |
91acd962 | 914 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
915 | } |
916 | ||
7102b773 | 917 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 918 | { |
91acd962 | 919 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
920 | } |
921 | ||
922 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
923 | { | |
924 | struct pxa_camera_dev *pcdev = data; | |
a47f6be4 | 925 | unsigned long status, cifr, cicr0; |
256b0233 RJ |
926 | struct pxa_buffer *buf; |
927 | struct videobuf_buffer *vb; | |
3bc43840 | 928 | |
5ca11fa3 | 929 | status = __raw_readl(pcdev->base + CISR); |
0166b743 GL |
930 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
931 | "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 932 | |
e7c50688 GL |
933 | if (!status) |
934 | return IRQ_NONE; | |
935 | ||
5ca11fa3 | 936 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
937 | |
938 | if (status & CISR_EOF) { | |
a47f6be4 SH |
939 | /* Reset the FIFOs */ |
940 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
941 | __raw_writel(cifr, pcdev->base + CIFR); | |
942 | ||
256b0233 RJ |
943 | pcdev->active = list_first_entry(&pcdev->capture, |
944 | struct pxa_buffer, vb.queue); | |
945 | vb = &pcdev->active->vb; | |
946 | buf = container_of(vb, struct pxa_buffer, vb); | |
947 | pxa_videobuf_set_actdma(pcdev, buf); | |
948 | ||
949 | pxa_dma_start_channels(pcdev); | |
950 | ||
5ca11fa3 EM |
951 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
952 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
953 | } |
954 | ||
3bc43840 GL |
955 | return IRQ_HANDLED; |
956 | } | |
957 | ||
1c3bb743 GL |
958 | /* |
959 | * The following two functions absolutely depend on the fact, that | |
960 | * there can be only one camera on PXA quick capture interface | |
dd669e90 | 961 | * Called with .host_lock held |
1c3bb743 | 962 | */ |
7102b773 | 963 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 | 964 | { |
7dfff953 | 965 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 966 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 | 967 | |
979ea1dd GL |
968 | if (pcdev->icd) |
969 | return -EBUSY; | |
3bc43840 | 970 | |
7102b773 | 971 | pxa_camera_activate(pcdev); |
40e2e092 GL |
972 | |
973 | pcdev->icd = icd; | |
3bc43840 | 974 | |
7dfff953 | 975 | dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", |
40e2e092 | 976 | icd->devnum); |
3bc43840 | 977 | |
40e2e092 | 978 | return 0; |
3bc43840 GL |
979 | } |
980 | ||
dd669e90 | 981 | /* Called with .host_lock held */ |
7102b773 | 982 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 | 983 | { |
7dfff953 | 984 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 GL |
985 | struct pxa_camera_dev *pcdev = ici->priv; |
986 | ||
987 | BUG_ON(icd != pcdev->icd); | |
988 | ||
7dfff953 | 989 | dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", |
3bc43840 GL |
990 | icd->devnum); |
991 | ||
992 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 993 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 994 | |
3bc43840 | 995 | /* Stop DMA engine */ |
a5462e5b MR |
996 | DCSR(pcdev->dma_chans[0]) = 0; |
997 | DCSR(pcdev->dma_chans[1]) = 0; | |
998 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 | 999 | |
7102b773 | 1000 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
1001 | |
1002 | pcdev->icd = NULL; | |
1003 | } | |
1004 | ||
ad5f2e85 GL |
1005 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
1006 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 1007 | { |
ad5f2e85 GL |
1008 | /* |
1009 | * Platform specified synchronization and pixel clock polarities are | |
1010 | * only a recommendation and are only used during probing. The PXA270 | |
1011 | * quick capture interface supports both. | |
1012 | */ | |
1013 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
1014 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
1015 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
1016 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
1017 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
1018 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
1019 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
1020 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
1021 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
1022 | |
1023 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
1024 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
1025 | return 0; | |
ad5f2e85 | 1026 | |
679419aa | 1027 | return -EINVAL; |
ad5f2e85 GL |
1028 | } |
1029 | ||
6a6c8786 GL |
1030 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
1031 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 1032 | { |
7dfff953 | 1033 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1034 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 1035 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 1036 | unsigned long dw, bpp; |
32536108 GL |
1037 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
1038 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
1039 | ||
1040 | if (ret < 0) | |
1041 | y_skip_top = 0; | |
3bc43840 | 1042 | |
5d28d525 GL |
1043 | /* |
1044 | * Datawidth is now guaranteed to be equal to one of the three values. | |
1045 | * We fix bit-per-pixel equal to data-width... | |
1046 | */ | |
679419aa GL |
1047 | switch (icd->current_fmt->host_fmt->bits_per_sample) { |
1048 | case 10: | |
3bc43840 GL |
1049 | dw = 4; |
1050 | bpp = 0x40; | |
1051 | break; | |
679419aa | 1052 | case 9: |
3bc43840 GL |
1053 | dw = 3; |
1054 | bpp = 0x20; | |
1055 | break; | |
1056 | default: | |
5d28d525 GL |
1057 | /* |
1058 | * Actually it can only be 8 now, | |
1059 | * default is just to silence compiler warnings | |
1060 | */ | |
679419aa | 1061 | case 8: |
3bc43840 GL |
1062 | dw = 2; |
1063 | bpp = 0; | |
1064 | } | |
1065 | ||
1066 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1067 | cicr4 |= CICR4_PCLK_EN; | |
1068 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1069 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 1070 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 1071 | cicr4 |= CICR4_PCP; |
679419aa | 1072 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 1073 | cicr4 |= CICR4_HSP; |
679419aa | 1074 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1075 | cicr4 |= CICR4_VSP; |
1076 | ||
5ca11fa3 | 1077 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1078 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1079 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1080 | |
6a6c8786 | 1081 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1082 | |
1083 | switch (pixfmt) { | |
1084 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1085 | pcdev->channels = 3; |
a5462e5b | 1086 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1087 | /* |
1088 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1089 | * reorderings of the YUV422 format, as no processing is done, | |
1090 | * and the YUV stream is just passed through without any | |
1091 | * transformation. Note that UYVY is the only format that | |
1092 | * should be used if pxa framebuffer Overlay2 is used. | |
1093 | */ | |
1094 | case V4L2_PIX_FMT_UYVY: | |
1095 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1096 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1097 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1098 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1099 | break; | |
1100 | case V4L2_PIX_FMT_RGB555: | |
1101 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1102 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1103 | break; | |
1104 | case V4L2_PIX_FMT_RGB565: | |
1105 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1106 | break; | |
1107 | } | |
1108 | ||
5ca11fa3 | 1109 | cicr2 = 0; |
6a6c8786 | 1110 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1111 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1112 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1113 | |
1114 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1115 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1116 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1117 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1118 | |
1119 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1120 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1121 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1122 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1123 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1124 | } |
1125 | ||
8843d119 | 1126 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) |
6a6c8786 | 1127 | { |
679419aa | 1128 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1129 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
6a6c8786 | 1130 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa | 1131 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 1132 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
679419aa | 1133 | unsigned long bus_flags, common_flags; |
760697be | 1134 | int ret; |
6a6c8786 GL |
1135 | struct pxa_cam *cam = icd->host_priv; |
1136 | ||
d2dcad49 GL |
1137 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1138 | &bus_flags); | |
6a6c8786 GL |
1139 | if (ret < 0) |
1140 | return ret; | |
1141 | ||
679419aa GL |
1142 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1143 | if (!ret) { | |
1144 | common_flags = soc_mbus_config_compatible(&cfg, | |
1145 | bus_flags); | |
1146 | if (!common_flags) { | |
1147 | dev_warn(icd->parent, | |
1148 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1149 | cfg.flags, bus_flags); | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | } else if (ret != -ENOIOCTLCMD) { | |
1153 | return ret; | |
1154 | } else { | |
1155 | common_flags = bus_flags; | |
1156 | } | |
6a6c8786 GL |
1157 | |
1158 | pcdev->channels = 1; | |
1159 | ||
1160 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1161 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1162 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1163 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1164 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1165 | else |
679419aa | 1166 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1167 | } |
1168 | ||
679419aa GL |
1169 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1170 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1171 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1172 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1173 | else |
679419aa | 1174 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1175 | } |
1176 | ||
679419aa GL |
1177 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1178 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1179 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1180 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1181 | else |
679419aa | 1182 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1183 | } |
1184 | ||
679419aa GL |
1185 | cfg.flags = common_flags; |
1186 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1187 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1188 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1189 | common_flags, ret); | |
6a6c8786 | 1190 | return ret; |
679419aa GL |
1191 | } |
1192 | ||
1193 | cam->flags = common_flags; | |
6a6c8786 GL |
1194 | |
1195 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1196 | |
1197 | return 0; | |
1198 | } | |
1199 | ||
2a48fc73 RJ |
1200 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1201 | unsigned char buswidth) | |
ad5f2e85 | 1202 | { |
679419aa | 1203 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1204 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1205 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa GL |
1206 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1207 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1208 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1209 | |
1210 | if (ret < 0) | |
1211 | return ret; | |
1212 | ||
679419aa GL |
1213 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1214 | if (!ret) { | |
1215 | common_flags = soc_mbus_config_compatible(&cfg, | |
1216 | bus_flags); | |
1217 | if (!common_flags) { | |
1218 | dev_warn(icd->parent, | |
1219 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1220 | cfg.flags, bus_flags); | |
1221 | return -EINVAL; | |
1222 | } | |
1223 | } else if (ret == -ENOIOCTLCMD) { | |
1224 | ret = 0; | |
1225 | } | |
ad5f2e85 | 1226 | |
679419aa | 1227 | return ret; |
ad5f2e85 GL |
1228 | } |
1229 | ||
760697be | 1230 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1231 | { |
760697be GL |
1232 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1233 | .name = "Planar YUV422 16 bit", | |
1234 | .bits_per_sample = 8, | |
1235 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1236 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1237 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1238 | }, |
1239 | }; | |
1240 | ||
760697be GL |
1241 | /* This will be corrected as we get more formats */ |
1242 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1243 | { |
760697be GL |
1244 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1245 | (fmt->bits_per_sample == 8 && | |
1246 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1247 | (fmt->bits_per_sample > 8 && | |
1248 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1249 | } |
1250 | ||
3805f201 | 1251 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1252 | struct soc_camera_format_xlate *xlate) |
1253 | { | |
760697be | 1254 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1255 | struct device *dev = icd->parent; |
760697be | 1256 | int formats = 0, ret; |
6a6c8786 | 1257 | struct pxa_cam *cam; |
760697be GL |
1258 | enum v4l2_mbus_pixelcode code; |
1259 | const struct soc_mbus_pixelfmt *fmt; | |
2a48fc73 | 1260 | |
760697be GL |
1261 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
1262 | if (ret < 0) | |
1263 | /* No more formats */ | |
1264 | return 0; | |
2a48fc73 | 1265 | |
760697be GL |
1266 | fmt = soc_mbus_get_fmtdesc(code); |
1267 | if (!fmt) { | |
3805f201 | 1268 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code); |
2a48fc73 | 1269 | return 0; |
760697be | 1270 | } |
3bc43840 | 1271 | |
760697be GL |
1272 | /* This also checks support for the requested bits-per-sample */ |
1273 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1274 | if (ret < 0) |
1275 | return 0; | |
1276 | ||
6a6c8786 GL |
1277 | if (!icd->host_priv) { |
1278 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1279 | if (!cam) | |
1280 | return -ENOMEM; | |
1281 | ||
1282 | icd->host_priv = cam; | |
1283 | } else { | |
1284 | cam = icd->host_priv; | |
1285 | } | |
1286 | ||
760697be | 1287 | switch (code) { |
ace6e979 | 1288 | case V4L2_MBUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1289 | formats++; |
1290 | if (xlate) { | |
760697be GL |
1291 | xlate->host_fmt = &pxa_camera_formats[0]; |
1292 | xlate->code = code; | |
2a48fc73 | 1293 | xlate++; |
760697be GL |
1294 | dev_dbg(dev, "Providing format %s using code %d\n", |
1295 | pxa_camera_formats[0].name, code); | |
2a48fc73 | 1296 | } |
ace6e979 GL |
1297 | case V4L2_MBUS_FMT_VYUY8_2X8: |
1298 | case V4L2_MBUS_FMT_YUYV8_2X8: | |
1299 | case V4L2_MBUS_FMT_YVYU8_2X8: | |
760697be GL |
1300 | case V4L2_MBUS_FMT_RGB565_2X8_LE: |
1301 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: | |
1302 | if (xlate) | |
0166b743 | 1303 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1304 | fmt->name); |
2a48fc73 RJ |
1305 | break; |
1306 | default: | |
760697be GL |
1307 | if (!pxa_camera_packing_supported(fmt)) |
1308 | return 0; | |
1309 | if (xlate) | |
0166b743 | 1310 | dev_dbg(dev, |
2a48fc73 | 1311 | "Providing format %s in pass-through mode\n", |
760697be GL |
1312 | fmt->name); |
1313 | } | |
1314 | ||
1315 | /* Generic pass-through */ | |
1316 | formats++; | |
1317 | if (xlate) { | |
1318 | xlate->host_fmt = fmt; | |
1319 | xlate->code = code; | |
1320 | xlate++; | |
2a48fc73 RJ |
1321 | } |
1322 | ||
1323 | return formats; | |
1324 | } | |
1325 | ||
6a6c8786 GL |
1326 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1327 | { | |
1328 | kfree(icd->host_priv); | |
1329 | icd->host_priv = NULL; | |
1330 | } | |
1331 | ||
760697be | 1332 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1333 | { |
1334 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1335 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1336 | (width & 0x01); | |
6a6c8786 GL |
1337 | } |
1338 | ||
09e231b3 | 1339 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
448a61f0 | 1340 | const struct v4l2_crop *a) |
09e231b3 | 1341 | { |
448a61f0 | 1342 | const struct v4l2_rect *rect = &a->c; |
7dfff953 GL |
1343 | struct device *dev = icd->parent; |
1344 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
09e231b3 | 1345 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1346 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1347 | struct soc_camera_sense sense = { |
1348 | .master_clock = pcdev->mclk, | |
1349 | .pixel_clock_max = pcdev->ciclk / 4, | |
1350 | }; | |
760697be | 1351 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 1352 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1353 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
09e231b3 GL |
1354 | int ret; |
1355 | ||
1356 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1357 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1358 | icd->sense = &sense; | |
1359 | ||
08590b96 | 1360 | ret = v4l2_subdev_call(sd, video, s_crop, a); |
09e231b3 GL |
1361 | |
1362 | icd->sense = NULL; | |
1363 | ||
1364 | if (ret < 0) { | |
0166b743 | 1365 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1366 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1367 | return ret; |
1368 | } | |
1369 | ||
760697be | 1370 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
1371 | if (ret < 0) |
1372 | return ret; | |
1373 | ||
760697be | 1374 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1375 | /* |
1376 | * Camera cropping produced a frame beyond our capabilities. | |
1377 | * FIXME: just extract a subframe, that we can process. | |
1378 | */ | |
760697be GL |
1379 | v4l_bound_align_image(&mf.width, 48, 2048, 1, |
1380 | &mf.height, 32, 2048, 0, | |
1381 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); | |
1382 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
6a6c8786 GL |
1383 | if (ret < 0) |
1384 | return ret; | |
1385 | ||
760697be | 1386 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
7dfff953 | 1387 | dev_warn(icd->parent, |
6a6c8786 GL |
1388 | "Inconsistent state. Use S_FMT to repair\n"); |
1389 | return -EINVAL; | |
1390 | } | |
1391 | } | |
1392 | ||
1393 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1394 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1395 | dev_err(dev, |
09e231b3 GL |
1396 | "pixel clock %lu set by the camera too high!", |
1397 | sense.pixel_clock); | |
1398 | return -EIO; | |
1399 | } | |
1400 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1401 | } | |
1402 | ||
760697be GL |
1403 | icd->user_width = mf.width; |
1404 | icd->user_height = mf.height; | |
6a6c8786 | 1405 | |
760697be | 1406 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1407 | |
09e231b3 GL |
1408 | return ret; |
1409 | } | |
1410 | ||
d8fac217 | 1411 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1412 | struct v4l2_format *f) |
ad5f2e85 | 1413 | { |
7dfff953 GL |
1414 | struct device *dev = icd->parent; |
1415 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
cf34cba7 | 1416 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1417 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1418 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1419 | struct soc_camera_sense sense = { |
1420 | .master_clock = pcdev->mclk, | |
1421 | .pixel_clock_max = pcdev->ciclk / 4, | |
1422 | }; | |
09e231b3 | 1423 | struct v4l2_pix_format *pix = &f->fmt.pix; |
760697be | 1424 | struct v4l2_mbus_framefmt mf; |
0ad675eb | 1425 | int ret; |
25c4d74e | 1426 | |
09e231b3 GL |
1427 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1428 | if (!xlate) { | |
0166b743 | 1429 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1430 | return -EINVAL; |
0ad675eb | 1431 | } |
2a48fc73 | 1432 | |
cf34cba7 GL |
1433 | /* If PCLK is used to latch data from the sensor, check sense */ |
1434 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1435 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1436 | icd->sense = &sense; |
1437 | ||
760697be GL |
1438 | mf.width = pix->width; |
1439 | mf.height = pix->height; | |
1440 | mf.field = pix->field; | |
1441 | mf.colorspace = pix->colorspace; | |
1442 | mf.code = xlate->code; | |
1443 | ||
1444 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
1445 | ||
1446 | if (mf.code != xlate->code) | |
1447 | return -EINVAL; | |
2a48fc73 | 1448 | |
cf34cba7 GL |
1449 | icd->sense = NULL; |
1450 | ||
1451 | if (ret < 0) { | |
0166b743 | 1452 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1453 | pix->pixelformat); |
760697be | 1454 | } else if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1455 | dev_warn(dev, |
1456 | "Camera driver produced an unsupported frame %dx%d\n", | |
760697be | 1457 | mf.width, mf.height); |
6a6c8786 | 1458 | ret = -EINVAL; |
cf34cba7 GL |
1459 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1460 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1461 | dev_err(dev, |
cf34cba7 GL |
1462 | "pixel clock %lu set by the camera too high!", |
1463 | sense.pixel_clock); | |
1464 | return -EIO; | |
1465 | } | |
1466 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1467 | } | |
2a48fc73 | 1468 | |
760697be GL |
1469 | if (ret < 0) |
1470 | return ret; | |
1471 | ||
1472 | pix->width = mf.width; | |
1473 | pix->height = mf.height; | |
1474 | pix->field = mf.field; | |
1475 | pix->colorspace = mf.colorspace; | |
1476 | icd->current_fmt = xlate; | |
25c4d74e GL |
1477 | |
1478 | return ret; | |
ad5f2e85 GL |
1479 | } |
1480 | ||
d8fac217 GL |
1481 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1482 | struct v4l2_format *f) | |
3bc43840 | 1483 | { |
c9c1f1c0 | 1484 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1485 | const struct soc_camera_format_xlate *xlate; |
1486 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 1487 | struct v4l2_mbus_framefmt mf; |
2a48fc73 | 1488 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1489 | int ret; |
a2c8c68c | 1490 | |
2a48fc73 RJ |
1491 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1492 | if (!xlate) { | |
7dfff953 | 1493 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1494 | return -EINVAL; |
2a48fc73 | 1495 | } |
25c4d74e | 1496 | |
92a8337b | 1497 | /* |
4a6b8df2 TP |
1498 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1499 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1500 | * inserted between Y and U planes, and U and V planes, which violates | |
1501 | * the YUV422P standard. | |
92a8337b | 1502 | */ |
4a6b8df2 TP |
1503 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1504 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1505 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1506 | |
ad5f2e85 | 1507 | /* limit to sensor capabilities */ |
760697be GL |
1508 | mf.width = pix->width; |
1509 | mf.height = pix->height; | |
91401219 GL |
1510 | /* Only progressive video supported so far */ |
1511 | mf.field = V4L2_FIELD_NONE; | |
760697be GL |
1512 | mf.colorspace = pix->colorspace; |
1513 | mf.code = xlate->code; | |
bf507158 | 1514 | |
760697be GL |
1515 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
1516 | if (ret < 0) | |
1517 | return ret; | |
06daa1af | 1518 | |
760697be GL |
1519 | pix->width = mf.width; |
1520 | pix->height = mf.height; | |
1521 | pix->colorspace = mf.colorspace; | |
1522 | ||
1523 | switch (mf.field) { | |
1524 | case V4L2_FIELD_ANY: | |
1525 | case V4L2_FIELD_NONE: | |
1526 | pix->field = V4L2_FIELD_NONE; | |
1527 | break; | |
1528 | default: | |
1529 | /* TODO: support interlaced at least in pass-through mode */ | |
7dfff953 | 1530 | dev_err(icd->parent, "Field type %d unsupported.\n", |
760697be | 1531 | mf.field); |
06daa1af GL |
1532 | return -EINVAL; |
1533 | } | |
1534 | ||
bf507158 | 1535 | return ret; |
3bc43840 GL |
1536 | } |
1537 | ||
57bee29d | 1538 | static int pxa_camera_reqbufs(struct soc_camera_device *icd, |
7102b773 | 1539 | struct v4l2_requestbuffers *p) |
3bc43840 GL |
1540 | { |
1541 | int i; | |
1542 | ||
5d28d525 GL |
1543 | /* |
1544 | * This is for locking debugging only. I removed spinlocks and now I | |
3bc43840 GL |
1545 | * check whether .prepare is ever called on a linked buffer, or whether |
1546 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
5d28d525 GL |
1547 | * it hadn't triggered |
1548 | */ | |
3bc43840 | 1549 | for (i = 0; i < p->count; i++) { |
57bee29d | 1550 | struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], |
3bc43840 GL |
1551 | struct pxa_buffer, vb); |
1552 | buf->inwork = 0; | |
1553 | INIT_LIST_HEAD(&buf->vb.queue); | |
1554 | } | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
7102b773 | 1559 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1560 | { |
57bee29d | 1561 | struct soc_camera_device *icd = file->private_data; |
3bc43840 GL |
1562 | struct pxa_buffer *buf; |
1563 | ||
57bee29d | 1564 | buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, |
3bc43840 GL |
1565 | vb.stream); |
1566 | ||
1567 | poll_wait(file, &buf->vb.done, pt); | |
1568 | ||
1569 | if (buf->vb.state == VIDEOBUF_DONE || | |
1570 | buf->vb.state == VIDEOBUF_ERROR) | |
1571 | return POLLIN|POLLRDNORM; | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
7102b773 GL |
1576 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1577 | struct v4l2_capability *cap) | |
3bc43840 GL |
1578 | { |
1579 | /* cap->name is set by the firendly caller:-> */ | |
1580 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
3bc43840 GL |
1581 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
7254026c | 1586 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1587 | { |
7254026c | 1588 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1589 | struct pxa_camera_dev *pcdev = ici->priv; |
1590 | int i = 0, ret = 0; | |
1591 | ||
5ca11fa3 EM |
1592 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1593 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1594 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1595 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1596 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1597 | |
497833c6 | 1598 | if (pcdev->icd) { |
7254026c | 1599 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); |
497833c6 GL |
1600 | ret = v4l2_subdev_call(sd, core, s_power, 0); |
1601 | if (ret == -ENOIOCTLCMD) | |
1602 | ret = 0; | |
1603 | } | |
3f6ac497 RJ |
1604 | |
1605 | return ret; | |
1606 | } | |
1607 | ||
7254026c | 1608 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1609 | { |
7254026c | 1610 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1611 | struct pxa_camera_dev *pcdev = ici->priv; |
1612 | int i = 0, ret = 0; | |
1613 | ||
87f3dd77 EM |
1614 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1615 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1616 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1617 | |
5ca11fa3 EM |
1618 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1619 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1620 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1621 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1622 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1623 | |
497833c6 | 1624 | if (pcdev->icd) { |
7254026c | 1625 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd); |
497833c6 GL |
1626 | ret = v4l2_subdev_call(sd, core, s_power, 1); |
1627 | if (ret == -ENOIOCTLCMD) | |
1628 | ret = 0; | |
1629 | } | |
3f6ac497 RJ |
1630 | |
1631 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1632 | if (!ret && pcdev->active) |
1633 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1634 | |
1635 | return ret; | |
1636 | } | |
1637 | ||
b8d9904c GL |
1638 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1639 | .owner = THIS_MODULE, | |
1640 | .add = pxa_camera_add_device, | |
1641 | .remove = pxa_camera_remove_device, | |
09e231b3 | 1642 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1643 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1644 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1645 | .set_fmt = pxa_camera_set_fmt, |
1646 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1647 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1648 | .reqbufs = pxa_camera_reqbufs, |
1649 | .poll = pxa_camera_poll, | |
1650 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1651 | .set_bus_param = pxa_camera_set_bus_param, |
1652 | }; | |
1653 | ||
4c62e976 | 1654 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1655 | { |
1656 | struct pxa_camera_dev *pcdev; | |
1657 | struct resource *res; | |
1658 | void __iomem *base; | |
02da4659 | 1659 | int irq; |
3bc43840 GL |
1660 | int err = 0; |
1661 | ||
1662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1663 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1664 | if (!res || irq < 0) |
1665 | return -ENODEV; | |
3bc43840 | 1666 | |
47de201c | 1667 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1668 | if (!pcdev) { |
7102b773 | 1669 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1670 | return -ENOMEM; |
3bc43840 GL |
1671 | } |
1672 | ||
47de201c JL |
1673 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1674 | if (IS_ERR(pcdev->clk)) | |
1675 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1676 | |
3bc43840 GL |
1677 | pcdev->res = res; |
1678 | ||
1679 | pcdev->pdata = pdev->dev.platform_data; | |
1680 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1681 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1682 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1683 | /* |
1684 | * Platform hasn't set available data widths. This is bad. | |
1685 | * Warn and use a default. | |
1686 | */ | |
3bc43840 GL |
1687 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1688 | "data widths, using default 10 bit\n"); | |
1689 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1690 | } | |
679419aa GL |
1691 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1692 | pcdev->width_flags = 1 << 7; | |
1693 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1694 | pcdev->width_flags |= 1 << 8; | |
1695 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1696 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 GL |
1697 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1698 | if (!pcdev->mclk) { | |
3bc43840 | 1699 | dev_warn(&pdev->dev, |
cf34cba7 | 1700 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1701 | "Using default 20MHz\n"); |
cf34cba7 | 1702 | pcdev->mclk = 20000000; |
3bc43840 GL |
1703 | } |
1704 | ||
40e2e092 | 1705 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1706 | |
3bc43840 GL |
1707 | INIT_LIST_HEAD(&pcdev->capture); |
1708 | spin_lock_init(&pcdev->lock); | |
1709 | ||
1710 | /* | |
1711 | * Request the regions. | |
1712 | */ | |
47de201c JL |
1713 | base = devm_request_and_ioremap(&pdev->dev, res); |
1714 | if (!base) | |
1715 | return -ENOMEM; | |
3bc43840 GL |
1716 | pcdev->irq = irq; |
1717 | pcdev->base = base; | |
3bc43840 GL |
1718 | |
1719 | /* request dma */ | |
de3e3b82 | 1720 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1721 | pxa_camera_dma_irq_y, pcdev); | |
1722 | if (err < 0) { | |
eff505fa | 1723 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
47de201c | 1724 | return err; |
3bc43840 | 1725 | } |
de3e3b82 | 1726 | pcdev->dma_chans[0] = err; |
eff505fa | 1727 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
a5462e5b | 1728 | |
de3e3b82 | 1729 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1730 | pxa_camera_dma_irq_u, pcdev); | |
1731 | if (err < 0) { | |
eff505fa | 1732 | dev_err(&pdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1733 | goto exit_free_dma_y; |
1734 | } | |
de3e3b82 | 1735 | pcdev->dma_chans[1] = err; |
eff505fa | 1736 | dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
a5462e5b | 1737 | |
de3e3b82 | 1738 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1739 | pxa_camera_dma_irq_v, pcdev); | |
1740 | if (err < 0) { | |
eff505fa | 1741 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1742 | goto exit_free_dma_u; |
1743 | } | |
de3e3b82 | 1744 | pcdev->dma_chans[2] = err; |
eff505fa | 1745 | dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1746 | |
87f3dd77 EM |
1747 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1748 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1749 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1750 | |
1751 | /* request irq */ | |
47de201c JL |
1752 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1753 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1754 | if (err) { |
47de201c | 1755 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1756 | goto exit_free_dma; |
1757 | } | |
1758 | ||
eb6c8558 GL |
1759 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1760 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1761 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1762 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1763 | pcdev->soc_host.nr = pdev->id; |
eff505fa | 1764 | |
eb6c8558 | 1765 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 | 1766 | if (err) |
47de201c | 1767 | goto exit_free_dma; |
3bc43840 GL |
1768 | |
1769 | return 0; | |
1770 | ||
3bc43840 | 1771 | exit_free_dma: |
a5462e5b MR |
1772 | pxa_free_dma(pcdev->dma_chans[2]); |
1773 | exit_free_dma_u: | |
1774 | pxa_free_dma(pcdev->dma_chans[1]); | |
1775 | exit_free_dma_y: | |
1776 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1777 | return err; |
1778 | } | |
1779 | ||
4c62e976 | 1780 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 1781 | { |
eff505fa GL |
1782 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1783 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1784 | struct pxa_camera_dev, soc_host); | |
3bc43840 | 1785 | |
a5462e5b MR |
1786 | pxa_free_dma(pcdev->dma_chans[0]); |
1787 | pxa_free_dma(pcdev->dma_chans[1]); | |
1788 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 | 1789 | |
eff505fa | 1790 | soc_camera_host_unregister(soc_host); |
3bc43840 | 1791 | |
7102b773 | 1792 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1793 | |
3bc43840 GL |
1794 | return 0; |
1795 | } | |
1796 | ||
7254026c GL |
1797 | static struct dev_pm_ops pxa_camera_pm = { |
1798 | .suspend = pxa_camera_suspend, | |
1799 | .resume = pxa_camera_resume, | |
1800 | }; | |
1801 | ||
3bc43840 GL |
1802 | static struct platform_driver pxa_camera_driver = { |
1803 | .driver = { | |
1804 | .name = PXA_CAM_DRV_NAME, | |
7254026c | 1805 | .pm = &pxa_camera_pm, |
3bc43840 GL |
1806 | }, |
1807 | .probe = pxa_camera_probe, | |
4c62e976 | 1808 | .remove = pxa_camera_remove, |
3bc43840 GL |
1809 | }; |
1810 | ||
1d6629b1 | 1811 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
1812 | |
1813 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1814 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1815 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1816 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1817 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |