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[media] v4l2: replace s_mbus_fmt by set_fmt
[deliverable/linux.git] / drivers / media / platform / soc_camera / pxa_camera.c
CommitLineData
3bc43840
GL		 1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
3bc43840
GL		 13#include <linux/init.h>
14#include <linux/module.h>
7102b773 15#include <linux/io.h>
3bc43840
GL		 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
8efdb135 18#include <linux/err.h>
3bc43840
GL		 19#include <linux/errno.h>
20#include <linux/fs.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/moduleparam.h>
25#include <linux/time.h>
3bc43840
GL		 26#include <linux/device.h>
27#include <linux/platform_device.h>
3bc43840 28#include <linux/clk.h>
d514edac 29#include <linux/sched.h>
5a0e3ad6 30#include <linux/slab.h>
3bc43840
GL		 31
32#include <media/v4l2-common.h>
33#include <media/v4l2-dev.h>
092d3921 34#include <media/videobuf-dma-sg.h>
3bc43840 35#include <media/soc_camera.h>
760697be 36#include <media/soc_mediabus.h>
e9a1d94f 37#include <media/v4l2-of.h>
3bc43840
GL		 38
39#include <linux/videodev2.h>
40
cfbaf4df 41#include <mach/dma.h>
293b2da1 42#include <linux/platform_data/camera-pxa.h>
3bc43840 43
64dc3c1a 44#define PXA_CAM_VERSION "0.0.6"
3bc43840
GL		 45#define PXA_CAM_DRV_NAME "pxa27x-camera"
46
5ca11fa3
EM		 47/* Camera Interface */
48#define CICR0 0x0000
49#define CICR1 0x0004
50#define CICR2 0x0008
51#define CICR3 0x000C
52#define CICR4 0x0010
53#define CISR 0x0014
54#define CIFR 0x0018
55#define CITOR 0x001C
56#define CIBR0 0x0028
57#define CIBR1 0x0030
58#define CIBR2 0x0038
59
60#define CICR0_DMAEN (1 << 31) /* DMA request enable */
61#define CICR0_PAR_EN (1 << 30) /* Parity enable */
62#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
63#define CICR0_ENB (1 << 28) /* Camera interface enable */
64#define CICR0_DIS (1 << 27) /* Camera interface disable */
65#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
66#define CICR0_TOM (1 << 9) /* Time-out mask */
67#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
68#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
69#define CICR0_EOLM (1 << 6) /* End-of-line mask */
70#define CICR0_PERRM (1 << 5) /* Parity-error mask */
71#define CICR0_QDM (1 << 4) /* Quick-disable mask */
72#define CICR0_CDM (1 << 3) /* Disable-done mask */
73#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
74#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
75#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
76
77#define CICR1_TBIT (1 << 31) /* Transparency bit */
78#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
79#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
80#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
81#define CICR1_RGB_F (1 << 11) /* RGB format */
82#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
83#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
84#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
85#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
86#define CICR1_DW (0x7 << 0) /* Data width mask */
87
88#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
89 wait count mask */
90#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
91 wait count mask */
92#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
93#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
94 wait count mask */
95#define CICR2_FSW (0x7 << 0) /* Frame stabilization
96 wait count mask */
97
98#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
99 wait count mask */
100#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
101 wait count mask */
102#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
103#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
104 wait count mask */
105#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
106
107#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
108#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
109#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
110#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
111#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
112#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
113#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
114#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
115
116#define CISR_FTO (1 << 15) /* FIFO time-out */
117#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
118#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
119#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
120#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
121#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
122#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
123#define CISR_EOL (1 << 8) /* End of line */
124#define CISR_PAR_ERR (1 << 7) /* Parity error */
125#define CISR_CQD (1 << 6) /* Camera interface quick disable */
126#define CISR_CDD (1 << 5) /* Camera interface disable done */
127#define CISR_SOF (1 << 4) /* Start of frame */
128#define CISR_EOF (1 << 3) /* End of frame */
129#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
130#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
131#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
132
133#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
134#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
135#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
136#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
137#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
138#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
139#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
140#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
141
7102b773
GL		 142#define CICR0_SIM_MP (0 << 24)
143#define CICR0_SIM_SP (1 << 24)
144#define CICR0_SIM_MS (2 << 24)
145#define CICR0_SIM_EP (3 << 24)
146#define CICR0_SIM_ES (4 << 24)
147
148#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
149#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
a5462e5b
MR		 150#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
151#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
152#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
7102b773
GL		 153
154#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
155#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
156#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
157#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
158#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
159
160#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
161#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
162#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
163#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
164
3bc43840
GL		 165#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
166 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
167 CICR0_EOFM | CICR0_FOM)
168
3bc43840
GL		 169/*
170 * Structures
171 */
a5462e5b
MR		 172enum pxa_camera_active_dma {
173 DMA_Y = 0x1,
174 DMA_U = 0x2,
175 DMA_V = 0x4,
176};
177
178/* descriptor needed for the PXA DMA engine */
179struct pxa_cam_dma {
180 dma_addr_t sg_dma;
181 struct pxa_dma_desc *sg_cpu;
182 size_t sg_size;
183 int sglen;
184};
3bc43840
GL		 185
186/* buffer for one video frame */
187struct pxa_buffer {
188 /* common v4l buffer stuff -- must be first */
760697be 189 struct videobuf_buffer vb;
27ffaeb0 190 u32 code;
a5462e5b 191 /* our descriptor lists for Y, U and V channels */
760697be
GL		 192 struct pxa_cam_dma dmas[3];
193 int inwork;
194 enum pxa_camera_active_dma active_dma;
3bc43840
GL		 195};
196
3bc43840 197struct pxa_camera_dev {
eb6c8558 198 struct soc_camera_host soc_host;
5d28d525
GL		 199 /*
200 * PXA27x is only supposed to handle one camera on its Quick Capture
3bc43840 201 * interface. If anyone ever builds hardware to enable more than
5d28d525
GL		 202 * one camera, they will have to modify this driver too
203 */
3bc43840
GL		 204 struct clk *clk;
205
206 unsigned int irq;
207 void __iomem *base;
a5462e5b 208
e7c50688 209 int channels;
a5462e5b 210 unsigned int dma_chans[3];
3bc43840 211
3bc43840
GL		 212 struct pxacamera_platform_data *pdata;
213 struct resource *res;
214 unsigned long platform_flags;
cf34cba7
GL		 215 unsigned long ciclk;
216 unsigned long mclk;
217 u32 mclk_divisor;
679419aa 218 u16 width_flags; /* max 10 bits */
3bc43840
GL		 219
220 struct list_head capture;
221
222 spinlock_t lock;
223
3bc43840 224 struct pxa_buffer *active;
5aa2110f 225 struct pxa_dma_desc *sg_tail[3];
3f6ac497
RJ		 226
227 u32 save_cicr[5];
3bc43840
GL		 228};
229
6a6c8786
GL		 230struct pxa_cam {
231 unsigned long flags;
232};
233
3bc43840
GL		 234static const char *pxa_cam_driver_description = "PXA_Camera";
235
236static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
237
238/*
239 * Videobuf operations
240 */
7102b773
GL		 241static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
242 unsigned int *size)
3bc43840
GL		 243{
244 struct soc_camera_device *icd = vq->priv_data;
245
7dfff953 246 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
3bc43840 247
2b61d46e 248 *size = icd->sizeimage;
3bc43840
GL		 249
250 if (0 == *count)
251 *count = 32;
dab7e310
AB		 252 if (*size * *count > vid_limit * 1024 * 1024)
253 *count = (vid_limit * 1024 * 1024) / *size;
3bc43840
GL		 254
255 return 0;
256}
257
258static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
259{
260 struct soc_camera_device *icd = vq->priv_data;
7dfff953 261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
3bc43840 262 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
a5462e5b 263 int i;
3bc43840
GL		 264
265 BUG_ON(in_interrupt());
266
7dfff953 267 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 268 &buf->vb, buf->vb.baddr, buf->vb.bsize);
269
5d28d525
GL		 270 /*
271 * This waits until this buffer is out of danger, i.e., until it is no
272 * longer in STATE_QUEUED or STATE_ACTIVE
273 */
0e0809a5 274 videobuf_waiton(vq, &buf->vb, 0, 0);
95268403 275 videobuf_dma_unmap(vq->dev, dma);
3bc43840
GL		 276 videobuf_dma_free(dma);
277
a5462e5b
MR		 278 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
279 if (buf->dmas[i].sg_cpu)
96c75399
GL		 280 dma_free_coherent(ici->v4l2_dev.dev,
281 buf->dmas[i].sg_size,
a5462e5b
MR		 282 buf->dmas[i].sg_cpu,
283 buf->dmas[i].sg_dma);
284 buf->dmas[i].sg_cpu = NULL;
285 }
3bc43840
GL		 286
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
288}
289
37f5aefd
RJ		 290static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
292{
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
295
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
299
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
302
303 size = max(0, size - xfer_len);
304 offset = 0;
305 if (size == 0)
306 break;
307 }
308
309 BUG_ON(size != 0);
310 return i + 1;
311}
312
313/**
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
323 *
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
326 *
327 * Returns 0 or -ENOMEM if no coherent memory is available
328 */
a5462e5b
MR		 329static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
37f5aefd
RJ		 332 int cibr, int size,
333 struct scatterlist **sg_first, int *sg_first_ofs)
a5462e5b
MR		 334{
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
979ea1dd 336 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
37f5aefd
RJ		 337 struct scatterlist *sg;
338 int i, offset, sglen;
339 int dma_len = 0, xfer_len = 0;
a5462e5b
MR		 340
341 if (pxa_dma->sg_cpu)
979ea1dd 342 dma_free_coherent(dev, pxa_dma->sg_size,
a5462e5b
MR		 343 pxa_dma->sg_cpu, pxa_dma->sg_dma);
344
37f5aefd
RJ		 345 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
346 *sg_first_ofs, size);
347
a5462e5b 348 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
979ea1dd 349 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
a5462e5b
MR		 350 &pxa_dma->sg_dma, GFP_KERNEL);
351 if (!pxa_dma->sg_cpu)
352 return -ENOMEM;
353
354 pxa_dma->sglen = sglen;
37f5aefd 355 offset = *sg_first_ofs;
a5462e5b 356
979ea1dd 357 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
37f5aefd 358 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
a5462e5b 359
37f5aefd
RJ		 360
361 for_each_sg(*sg_first, sg, sglen, i) {
362 dma_len = sg_dma_len(sg);
a5462e5b
MR		 363
364 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
37f5aefd 365 xfer_len = roundup(min(dma_len - offset, size), 8);
a5462e5b 366
37f5aefd
RJ		 367 size = max(0, size - xfer_len);
368
369 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
370 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
a5462e5b
MR		 371 pxa_dma->sg_cpu[i].dcmd =
372 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
256b0233
RJ		 373#ifdef DEBUG
374 if (!i)
375 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
376#endif
a5462e5b
MR		 377 pxa_dma->sg_cpu[i].ddadr =
378 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
37f5aefd 379
979ea1dd 380 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
37f5aefd
RJ		 381 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
382 sg_dma_address(sg) + offset, xfer_len);
383 offset = 0;
384
385 if (size == 0)
386 break;
a5462e5b
MR		 387 }
388
256b0233
RJ		 389 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
390 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
a5462e5b 391
37f5aefd
RJ		 392 /*
393 * Handle 1 special case :
394 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
395 * to dma_len (end on PAGE boundary). In this case, the sg element
396 * for next plane should be the next after the last used to store the
397 * last scatter gather RAM page
398 */
399 if (xfer_len >= dma_len) {
400 *sg_first_ofs = xfer_len - dma_len;
401 *sg_first = sg_next(sg);
402 } else {
403 *sg_first_ofs = xfer_len;
404 *sg_first = sg;
405 }
406
a5462e5b
MR		 407 return 0;
408}
409
256b0233
RJ		 410static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
411 struct pxa_buffer *buf)
412{
413 buf->active_dma = DMA_Y;
414 if (pcdev->channels == 3)
415 buf->active_dma |= DMA_U | DMA_V;
416}
417
418/*
419 * Please check the DMA prepared buffer structure in :
420 * Documentation/video4linux/pxa_camera.txt
421 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
422 * modification while DMA chain is running will work anyway.
423 */
7102b773
GL		 424static int pxa_videobuf_prepare(struct videobuf_queue *vq,
425 struct videobuf_buffer *vb, enum v4l2_field field)
3bc43840
GL		 426{
427 struct soc_camera_device *icd = vq->priv_data;
7dfff953 428 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
3bc43840 429 struct pxa_camera_dev *pcdev = ici->priv;
979ea1dd 430 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
3bc43840 431 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
a5462e5b 432 int ret;
a5462e5b 433 int size_y, size_u = 0, size_v = 0;
3bc43840 434
979ea1dd 435 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 436 vb, vb->baddr, vb->bsize);
437
438 /* Added list head initialization on alloc */
439 WARN_ON(!list_empty(&vb->queue));
440
441#ifdef DEBUG
5d28d525
GL		 442 /*
443 * This can be useful if you want to see if we actually fill
444 * the buffer with something
445 */
3bc43840
GL		 446 memset((void *)vb->baddr, 0xaa, vb->bsize);
447#endif
448
449 BUG_ON(NULL == icd->current_fmt);
450
5d28d525
GL		 451 /*
452 * I think, in buf_prepare you only have to protect global data,
453 * the actual buffer is yours
454 */
3bc43840
GL		 455 buf->inwork = 1;
456
760697be 457 if (buf->code != icd->current_fmt->code ||
6a6c8786
GL		 458 vb->width != icd->user_width ||
459 vb->height != icd->user_height ||
3bc43840 460 vb->field != field) {
760697be 461 buf->code = icd->current_fmt->code;
6a6c8786
GL		 462 vb->width = icd->user_width;
463 vb->height = icd->user_height;
3bc43840
GL		 464 vb->field = field;
465 vb->state = VIDEOBUF_NEEDS_INIT;
466 }
467
2b61d46e 468 vb->size = icd->sizeimage;
3bc43840
GL		 469 if (0 != vb->baddr && vb->bsize < vb->size) {
470 ret = -EINVAL;
471 goto out;
472 }
473
474 if (vb->state == VIDEOBUF_NEEDS_INIT) {
37f5aefd
RJ		 475 int size = vb->size;
476 int next_ofs = 0;
3bc43840 477 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
37f5aefd 478 struct scatterlist *sg;
3bc43840
GL		 479
480 ret = videobuf_iolock(vq, vb, NULL);
481 if (ret)
482 goto fail;
483
5aa2110f 484 if (pcdev->channels == 3) {
a5462e5b
MR		 485 size_y = size / 2;
486 size_u = size_v = size / 4;
487 } else {
a5462e5b
MR		 488 size_y = size;
489 }
490
37f5aefd 491 sg = dma->sglist;
3bc43840 492
37f5aefd
RJ		 493 /* init DMA for Y channel */
494 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
495 &sg, &next_ofs);
a5462e5b 496 if (ret) {
979ea1dd 497 dev_err(dev, "DMA initialization for Y/RGB failed\n");
3bc43840
GL		 498 goto fail;
499 }
500
37f5aefd
RJ		 501 /* init DMA for U channel */
502 if (size_u)
503 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
504 size_u, &sg, &next_ofs);
505 if (ret) {
979ea1dd 506 dev_err(dev, "DMA initialization for U failed\n");
37f5aefd
RJ		 507 goto fail_u;
508 }
509
510 /* init DMA for V channel */
511 if (size_v)
512 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
513 size_v, &sg, &next_ofs);
514 if (ret) {
979ea1dd 515 dev_err(dev, "DMA initialization for V failed\n");
37f5aefd 516 goto fail_v;
3bc43840 517 }
3bc43840
GL		 518
519 vb->state = VIDEOBUF_PREPARED;
520 }
521
522 buf->inwork = 0;
256b0233 523 pxa_videobuf_set_actdma(pcdev, buf);
3bc43840
GL		 524
525 return 0;
526
a5462e5b 527fail_v:
979ea1dd 528 dma_free_coherent(dev, buf->dmas[1].sg_size,
a5462e5b
MR		 529 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
530fail_u:
979ea1dd 531 dma_free_coherent(dev, buf->dmas[0].sg_size,
a5462e5b 532 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
3bc43840
GL		 533fail:
534 free_buffer(vq, buf);
535out:
536 buf->inwork = 0;
537 return ret;
538}
539
256b0233
RJ		 540/**
541 * pxa_dma_start_channels - start DMA channel for active buffer
542 * @pcdev: pxa camera device
543 *
544 * Initialize DMA channels to the beginning of the active video buffer, and
545 * start these channels.
546 */
547static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
548{
549 int i;
550 struct pxa_buffer *active;
551
552 active = pcdev->active;
553
554 for (i = 0; i < pcdev->channels; i++) {
0166b743
GL		 555 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
556 "%s (channel=%d) ddadr=%08x\n", __func__,
256b0233
RJ		 557 i, active->dmas[i].sg_dma);
558 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
559 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
560 }
561}
562
563static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
564{
565 int i;
566
567 for (i = 0; i < pcdev->channels; i++) {
0166b743
GL		 568 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
569 "%s (channel=%d)\n", __func__, i);
256b0233
RJ		 570 DCSR(pcdev->dma_chans[i]) = 0;
571 }
572}
573
256b0233
RJ		 574static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
575 struct pxa_buffer *buf)
576{
577 int i;
578 struct pxa_dma_desc *buf_last_desc;
579
580 for (i = 0; i < pcdev->channels; i++) {
581 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
582 buf_last_desc->ddadr = DDADR_STOP;
583
ae7410e7
GL		 584 if (pcdev->sg_tail[i])
585 /* Link the new buffer to the old tail */
586 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
256b0233 587
ae7410e7
GL		 588 /* Update the channel tail */
589 pcdev->sg_tail[i] = buf_last_desc;
590 }
256b0233
RJ		 591}
592
593/**
594 * pxa_camera_start_capture - start video capturing
595 * @pcdev: camera device
596 *
597 * Launch capturing. DMA channels should not be active yet. They should get
598 * activated at the end of frame interrupt, to capture only whole frames, and
599 * never begin the capture of a partial frame.
600 */
601static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
602{
a47f6be4 603 unsigned long cicr0;
256b0233 604
979ea1dd 605 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
256b0233
RJ		 606 /* Enable End-Of-Frame Interrupt */
607 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
608 cicr0 &= ~CICR0_EOFM;
609 __raw_writel(cicr0, pcdev->base + CICR0);
610}
611
612static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
613{
614 unsigned long cicr0;
615
616 pxa_dma_stop_channels(pcdev);
617
618 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
619 __raw_writel(cicr0, pcdev->base + CICR0);
620
8c62e221 621 pcdev->active = NULL;
979ea1dd 622 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
256b0233
RJ		 623}
624
2dd54a54 625/* Called under spinlock_irqsave(&pcdev->lock, ...) */
7102b773
GL		 626static void pxa_videobuf_queue(struct videobuf_queue *vq,
627 struct videobuf_buffer *vb)
3bc43840
GL		 628{
629 struct soc_camera_device *icd = vq->priv_data;
7dfff953 630 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
3bc43840
GL		 631 struct pxa_camera_dev *pcdev = ici->priv;
632 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
3bc43840 633
7dfff953 634 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
0166b743 635 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
256b0233 636
3bc43840
GL		 637 list_add_tail(&vb->queue, &pcdev->capture);
638
639 vb->state = VIDEOBUF_ACTIVE;
256b0233 640 pxa_dma_add_tail_buf(pcdev, buf);
3bc43840 641
256b0233
RJ		 642 if (!pcdev->active)
643 pxa_camera_start_capture(pcdev);
3bc43840
GL		 644}
645
646static void pxa_videobuf_release(struct videobuf_queue *vq,
647 struct videobuf_buffer *vb)
648{
649 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
650#ifdef DEBUG
651 struct soc_camera_device *icd = vq->priv_data;
7dfff953 652 struct device *dev = icd->parent;
3bc43840 653
0166b743 654 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 655 vb, vb->baddr, vb->bsize);
656
657 switch (vb->state) {
658 case VIDEOBUF_ACTIVE:
0166b743 659 dev_dbg(dev, "%s (active)\n", __func__);
3bc43840
GL		 660 break;
661 case VIDEOBUF_QUEUED:
0166b743 662 dev_dbg(dev, "%s (queued)\n", __func__);
3bc43840
GL		 663 break;
664 case VIDEOBUF_PREPARED:
0166b743 665 dev_dbg(dev, "%s (prepared)\n", __func__);
3bc43840
GL		 666 break;
667 default:
0166b743 668 dev_dbg(dev, "%s (unknown)\n", __func__);
3bc43840
GL		 669 break;
670 }
671#endif
672
673 free_buffer(vq, buf);
674}
675
a5462e5b
MR		 676static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
677 struct videobuf_buffer *vb,
678 struct pxa_buffer *buf)
679{
256b0233 680 int i;
5ca11fa3 681
a5462e5b
MR		 682 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
683 list_del_init(&vb->queue);
684 vb->state = VIDEOBUF_DONE;
8e6057b5 685 v4l2_get_timestamp(&vb->ts);
a5462e5b
MR		 686 vb->field_count++;
687 wake_up(&vb->done);
979ea1dd
GL		 688 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
689 __func__, vb);
a5462e5b
MR		 690
691 if (list_empty(&pcdev->capture)) {
256b0233 692 pxa_camera_stop_capture(pcdev);
256b0233
RJ		 693 for (i = 0; i < pcdev->channels; i++)
694 pcdev->sg_tail[i] = NULL;
a5462e5b
MR		 695 return;
696 }
697
698 pcdev->active = list_entry(pcdev->capture.next,
699 struct pxa_buffer, vb.queue);
700}
701
256b0233
RJ		 702/**
703 * pxa_camera_check_link_miss - check missed DMA linking
704 * @pcdev: camera device
705 *
706 * The DMA chaining is done with DMA running. This means a tiny temporal window
707 * remains, where a buffer is queued on the chain, while the chain is already
25985edc 708 * stopped. This means the tailed buffer would never be transferred by DMA.
256b0233
RJ		 709 * This function restarts the capture for this corner case, where :
710 * - DADR() == DADDR_STOP
711 * - a videobuffer is queued on the pcdev->capture list
712 *
713 * Please check the "DMA hot chaining timeslice issue" in
714 * Documentation/video4linux/pxa_camera.txt
715 *
716 * Context: should only be called within the dma irq handler
717 */
718static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
719{
720 int i, is_dma_stopped = 1;
721
722 for (i = 0; i < pcdev->channels; i++)
723 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
724 is_dma_stopped = 0;
979ea1dd
GL		 725 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
726 "%s : top queued buffer=%p, dma_stopped=%d\n",
256b0233
RJ		 727 __func__, pcdev->active, is_dma_stopped);
728 if (pcdev->active && is_dma_stopped)
729 pxa_camera_start_capture(pcdev);
730}
731
a5462e5b
MR		 732static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
733 enum pxa_camera_active_dma act_dma)
3bc43840 734{
979ea1dd 735 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
3bc43840
GL		 736 struct pxa_buffer *buf;
737 unsigned long flags;
e7c50688 738 u32 status, camera_status, overrun;
3bc43840
GL		 739 struct videobuf_buffer *vb;
740
741 spin_lock_irqsave(&pcdev->lock, flags);
742
a5462e5b 743 status = DCSR(channel);
256b0233
RJ		 744 DCSR(channel) = status;
745
746 camera_status = __raw_readl(pcdev->base + CISR);
747 overrun = CISR_IFO_0;
748 if (pcdev->channels == 3)
749 overrun |= CISR_IFO_1 | CISR_IFO_2;
7102b773 750
3bc43840 751 if (status & DCSR_BUSERR) {
979ea1dd 752 dev_err(dev, "DMA Bus Error IRQ!\n");
3bc43840
GL		 753 goto out;
754 }
755
256b0233 756 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
979ea1dd
GL		 757 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
758 status);
3bc43840
GL		 759 goto out;
760 }
761
8c62e221
RJ		 762 /*
763 * pcdev->active should not be NULL in DMA irq handler.
764 *
765 * But there is one corner case : if capture was stopped due to an
766 * overrun of channel 1, and at that same channel 2 was completed.
767 *
768 * When handling the overrun in DMA irq for channel 1, we'll stop the
769 * capture and restart it (and thus set pcdev->active to NULL). But the
770 * DMA irq handler will already be pending for channel 2. So on entering
771 * the DMA irq handler for channel 2 there will be no active buffer, yet
772 * that is normal.
773 */
774 if (!pcdev->active)
3bc43840 775 goto out;
3bc43840
GL		 776
777 vb = &pcdev->active->vb;
778 buf = container_of(vb, struct pxa_buffer, vb);
779 WARN_ON(buf->inwork || list_empty(&vb->queue));
3bc43840 780
979ea1dd 781 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
256b0233
RJ		 782 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
783 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
784
785 if (status & DCSR_ENDINTR) {
8c62e221
RJ		 786 /*
787 * It's normal if the last frame creates an overrun, as there
788 * are no more DMA descriptors to fetch from QCI fifos
789 */
790 if (camera_status & overrun &&
791 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
979ea1dd 792 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
256b0233
RJ		 793 camera_status);
794 pxa_camera_stop_capture(pcdev);
795 pxa_camera_start_capture(pcdev);
796 goto out;
797 }
798 buf->active_dma &= ~act_dma;
799 if (!buf->active_dma) {
800 pxa_camera_wakeup(pcdev, vb, buf);
801 pxa_camera_check_link_miss(pcdev);
802 }
803 }
3bc43840
GL		 804
805out:
806 spin_unlock_irqrestore(&pcdev->lock, flags);
807}
808
a5462e5b
MR		 809static void pxa_camera_dma_irq_y(int channel, void *data)
810{
811 struct pxa_camera_dev *pcdev = data;
812 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
813}
814
815static void pxa_camera_dma_irq_u(int channel, void *data)
816{
817 struct pxa_camera_dev *pcdev = data;
818 pxa_camera_dma_irq(channel, pcdev, DMA_U);
819}
820
821static void pxa_camera_dma_irq_v(int channel, void *data)
822{
823 struct pxa_camera_dev *pcdev = data;
824 pxa_camera_dma_irq(channel, pcdev, DMA_V);
825}
826
7102b773 827static struct videobuf_queue_ops pxa_videobuf_ops = {
3bc43840
GL		 828 .buf_setup = pxa_videobuf_setup,
829 .buf_prepare = pxa_videobuf_prepare,
830 .buf_queue = pxa_videobuf_queue,
831 .buf_release = pxa_videobuf_release,
832};
833
a034d1b7 834static void pxa_camera_init_videobuf(struct videobuf_queue *q,
092d3921
PZ		 835 struct soc_camera_device *icd)
836{
7dfff953 837 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
a034d1b7
MD		 838 struct pxa_camera_dev *pcdev = ici->priv;
839
5d28d525
GL		 840 /*
841 * We must pass NULL as dev pointer, then all pci_* dma operations
842 * transform to normal dma_* ones.
843 */
a034d1b7 844 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
092d3921 845 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
47ebe3f9 846 sizeof(struct pxa_buffer), icd, &ici->host_lock);
092d3921
PZ		 847}
848
40e2e092
GL		 849static u32 mclk_get_divisor(struct platform_device *pdev,
850 struct pxa_camera_dev *pcdev)
3bc43840 851{
cf34cba7 852 unsigned long mclk = pcdev->mclk;
6a6c8786 853 struct device *dev = &pdev->dev;
cf34cba7 854 u32 div;
3bc43840
GL		 855 unsigned long lcdclk;
856
cf34cba7
GL		 857 lcdclk = clk_get_rate(pcdev->clk);
858 pcdev->ciclk = lcdclk;
3bc43840 859
cf34cba7
GL		 860 /* mclk <= ciclk / 4 (27.4.2) */
861 if (mclk > lcdclk / 4) {
862 mclk = lcdclk / 4;
979ea1dd 863 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
cf34cba7
GL		 864 }
865
866 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
867 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
3bc43840 868
cf34cba7
GL		 869 /* If we're not supplying MCLK, leave it at 0 */
870 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
871 pcdev->mclk = lcdclk / (2 * (div + 1));
3bc43840 872
979ea1dd 873 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
40e2e092 874 lcdclk, mclk, div);
3bc43840
GL		 875
876 return div;
877}
878
cf34cba7
GL		 879static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
880 unsigned long pclk)
881{
882 /* We want a timeout > 1 pixel time, not ">=" */
883 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
884
885 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
886}
887
7102b773 888static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
3bc43840 889{
3bc43840
GL		 890 u32 cicr4 = 0;
891
5ca11fa3
EM		 892 /* disable all interrupts */
893 __raw_writel(0x3ff, pcdev->base + CICR0);
3bc43840
GL		 894
895 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
896 cicr4 |= CICR4_PCLK_EN;
897 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
898 cicr4 |= CICR4_MCLK_EN;
899 if (pcdev->platform_flags & PXA_CAMERA_PCP)
900 cicr4 |= CICR4_PCP;
901 if (pcdev->platform_flags & PXA_CAMERA_HSP)
902 cicr4 |= CICR4_HSP;
903 if (pcdev->platform_flags & PXA_CAMERA_VSP)
904 cicr4 |= CICR4_VSP;
905
cf34cba7
GL		 906 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
907
908 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
909 /* Initialise the timeout under the assumption pclk = mclk */
910 recalculate_fifo_timeout(pcdev, pcdev->mclk);
911 else
912 /* "Safe default" - 13MHz */
913 recalculate_fifo_timeout(pcdev, 13000000);
3bc43840 914
91acd962 915 clk_prepare_enable(pcdev->clk);
3bc43840
GL		 916}
917
7102b773 918static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
3bc43840 919{
91acd962 920 clk_disable_unprepare(pcdev->clk);
3bc43840
GL		 921}
922
923static irqreturn_t pxa_camera_irq(int irq, void *data)
924{
925 struct pxa_camera_dev *pcdev = data;
a47f6be4 926 unsigned long status, cifr, cicr0;
256b0233
RJ		 927 struct pxa_buffer *buf;
928 struct videobuf_buffer *vb;
3bc43840 929
5ca11fa3 930 status = __raw_readl(pcdev->base + CISR);
0166b743
GL		 931 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
932 "Camera interrupt status 0x%lx\n", status);
3bc43840 933
e7c50688
GL		 934 if (!status)
935 return IRQ_NONE;
936
5ca11fa3 937 __raw_writel(status, pcdev->base + CISR);
e7c50688
GL		 938
939 if (status & CISR_EOF) {
a47f6be4
SH		 940 /* Reset the FIFOs */
941 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
942 __raw_writel(cifr, pcdev->base + CIFR);
943
256b0233
RJ		 944 pcdev->active = list_first_entry(&pcdev->capture,
945 struct pxa_buffer, vb.queue);
946 vb = &pcdev->active->vb;
947 buf = container_of(vb, struct pxa_buffer, vb);
948 pxa_videobuf_set_actdma(pcdev, buf);
949
950 pxa_dma_start_channels(pcdev);
951
5ca11fa3
EM		 952 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
953 __raw_writel(cicr0, pcdev->base + CICR0);
e7c50688
GL		 954 }
955
3bc43840
GL		 956 return IRQ_HANDLED;
957}
958
39b553db
GL		 959static int pxa_camera_add_device(struct soc_camera_device *icd)
960{
961 dev_info(icd->parent, "PXA Camera driver attached to camera %d\n",
962 icd->devnum);
963
964 return 0;
965}
966
967static void pxa_camera_remove_device(struct soc_camera_device *icd)
968{
969 dev_info(icd->parent, "PXA Camera driver detached from camera %d\n",
970 icd->devnum);
971}
972
1c3bb743
GL		 973/*
974 * The following two functions absolutely depend on the fact, that
975 * there can be only one camera on PXA quick capture interface
dd669e90 976 * Called with .host_lock held
1c3bb743 977 */
39b553db 978static int pxa_camera_clock_start(struct soc_camera_host *ici)
3bc43840 979{
3bc43840 980 struct pxa_camera_dev *pcdev = ici->priv;
3bc43840 981
7102b773 982 pxa_camera_activate(pcdev);
40e2e092 983
40e2e092 984 return 0;
3bc43840
GL		 985}
986
dd669e90 987/* Called with .host_lock held */
39b553db 988static void pxa_camera_clock_stop(struct soc_camera_host *ici)
3bc43840 989{
3bc43840
GL		 990 struct pxa_camera_dev *pcdev = ici->priv;
991
3bc43840 992 /* disable capture, disable interrupts */
5ca11fa3 993 __raw_writel(0x3ff, pcdev->base + CICR0);
a5462e5b 994
3bc43840 995 /* Stop DMA engine */
a5462e5b
MR		 996 DCSR(pcdev->dma_chans[0]) = 0;
997 DCSR(pcdev->dma_chans[1]) = 0;
998 DCSR(pcdev->dma_chans[2]) = 0;
3bc43840 999
7102b773 1000 pxa_camera_deactivate(pcdev);
3bc43840
GL		 1001}
1002
ad5f2e85
GL		 1003static int test_platform_param(struct pxa_camera_dev *pcdev,
1004 unsigned char buswidth, unsigned long *flags)
3bc43840 1005{
ad5f2e85
GL		 1006 /*
1007 * Platform specified synchronization and pixel clock polarities are
1008 * only a recommendation and are only used during probing. The PXA270
1009 * quick capture interface supports both.
1010 */
1011 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
679419aa
GL		 1012 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1013 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1014 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1015 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1016 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1017 V4L2_MBUS_DATA_ACTIVE_HIGH |
1018 V4L2_MBUS_PCLK_SAMPLE_RISING |
1019 V4L2_MBUS_PCLK_SAMPLE_FALLING;
3bc43840
GL		 1020
1021 /* If requested data width is supported by the platform, use it */
679419aa
GL		 1022 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1023 return 0;
ad5f2e85 1024
679419aa 1025 return -EINVAL;
ad5f2e85
GL		 1026}
1027
6a6c8786
GL		 1028static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1029 unsigned long flags, __u32 pixfmt)
ad5f2e85 1030{
7dfff953 1031 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
ad5f2e85 1032 struct pxa_camera_dev *pcdev = ici->priv;
32536108 1033 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
6a6c8786 1034 unsigned long dw, bpp;
32536108
GL		 1035 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1036 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1037
1038 if (ret < 0)
1039 y_skip_top = 0;
3bc43840 1040
5d28d525
GL		 1041 /*
1042 * Datawidth is now guaranteed to be equal to one of the three values.
1043 * We fix bit-per-pixel equal to data-width...
1044 */
679419aa
GL		 1045 switch (icd->current_fmt->host_fmt->bits_per_sample) {
1046 case 10:
3bc43840
GL		 1047 dw = 4;
1048 bpp = 0x40;
1049 break;
679419aa 1050 case 9:
3bc43840
GL		 1051 dw = 3;
1052 bpp = 0x20;
1053 break;
1054 default:
5d28d525
GL		 1055 /*
1056 * Actually it can only be 8 now,
1057 * default is just to silence compiler warnings
1058 */
679419aa 1059 case 8:
3bc43840
GL		 1060 dw = 2;
1061 bpp = 0;
1062 }
1063
1064 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1065 cicr4 |= CICR4_PCLK_EN;
1066 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1067 cicr4 |= CICR4_MCLK_EN;
679419aa 1068 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
3bc43840 1069 cicr4 |= CICR4_PCP;
679419aa 1070 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
3bc43840 1071 cicr4 |= CICR4_HSP;
679419aa 1072 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
3bc43840
GL		 1073 cicr4 |= CICR4_VSP;
1074
5ca11fa3 1075 cicr0 = __raw_readl(pcdev->base + CICR0);
3bc43840 1076 if (cicr0 & CICR0_ENB)
5ca11fa3 1077 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
a5462e5b 1078
6a6c8786 1079 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
a5462e5b
MR		 1080
1081 switch (pixfmt) {
1082 case V4L2_PIX_FMT_YUV422P:
e7c50688 1083 pcdev->channels = 3;
a5462e5b 1084 cicr1 |= CICR1_YCBCR_F;
2a48fc73
RJ		 1085 /*
1086 * Normally, pxa bus wants as input UYVY format. We allow all
1087 * reorderings of the YUV422 format, as no processing is done,
1088 * and the YUV stream is just passed through without any
1089 * transformation. Note that UYVY is the only format that
1090 * should be used if pxa framebuffer Overlay2 is used.
1091 */
1092 case V4L2_PIX_FMT_UYVY:
1093 case V4L2_PIX_FMT_VYUY:
a5462e5b 1094 case V4L2_PIX_FMT_YUYV:
2a48fc73 1095 case V4L2_PIX_FMT_YVYU:
a5462e5b
MR		 1096 cicr1 |= CICR1_COLOR_SP_VAL(2);
1097 break;
1098 case V4L2_PIX_FMT_RGB555:
1099 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1100 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1101 break;
1102 case V4L2_PIX_FMT_RGB565:
1103 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1104 break;
1105 }
1106
5ca11fa3 1107 cicr2 = 0;
6a6c8786 1108 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
32536108 1109 CICR3_BFW_VAL(min((u32)255, y_skip_top));
cf34cba7 1110 cicr4 |= pcdev->mclk_divisor;
5ca11fa3
EM		 1111
1112 __raw_writel(cicr1, pcdev->base + CICR1);
1113 __raw_writel(cicr2, pcdev->base + CICR2);
1114 __raw_writel(cicr3, pcdev->base + CICR3);
1115 __raw_writel(cicr4, pcdev->base + CICR4);
3bc43840
GL		 1116
1117 /* CIF interrupts are not used, only DMA */
5ca11fa3
EM		 1118 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1119 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1120 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1121 __raw_writel(cicr0, pcdev->base + CICR0);
6a6c8786
GL		 1122}
1123
8843d119 1124static int pxa_camera_set_bus_param(struct soc_camera_device *icd)
6a6c8786 1125{
679419aa 1126 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
7dfff953 1127 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
6a6c8786 1128 struct pxa_camera_dev *pcdev = ici->priv;
679419aa 1129 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
8843d119 1130 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
679419aa 1131 unsigned long bus_flags, common_flags;
760697be 1132 int ret;
6a6c8786
GL		 1133 struct pxa_cam *cam = icd->host_priv;
1134
d2dcad49
GL		 1135 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1136 &bus_flags);
6a6c8786
GL		 1137 if (ret < 0)
1138 return ret;
1139
679419aa
GL		 1140 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1141 if (!ret) {
1142 common_flags = soc_mbus_config_compatible(&cfg,
1143 bus_flags);
1144 if (!common_flags) {
1145 dev_warn(icd->parent,
1146 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1147 cfg.flags, bus_flags);
1148 return -EINVAL;
1149 }
1150 } else if (ret != -ENOIOCTLCMD) {
1151 return ret;
1152 } else {
1153 common_flags = bus_flags;
1154 }
6a6c8786
GL		 1155
1156 pcdev->channels = 1;
1157
1158 /* Make choises, based on platform preferences */
679419aa
GL		 1159 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1160 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
6a6c8786 1161 if (pcdev->platform_flags & PXA_CAMERA_HSP)
679419aa 1162 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
6a6c8786 1163 else
679419aa 1164 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
6a6c8786
GL		 1165 }
1166
679419aa
GL		 1167 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1168 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
6a6c8786 1169 if (pcdev->platform_flags & PXA_CAMERA_VSP)
679419aa 1170 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
6a6c8786 1171 else
679419aa 1172 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
6a6c8786
GL		 1173 }
1174
679419aa
GL		 1175 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1176 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
6a6c8786 1177 if (pcdev->platform_flags & PXA_CAMERA_PCP)
679419aa 1178 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
6a6c8786 1179 else
679419aa 1180 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
6a6c8786
GL		 1181 }
1182
679419aa
GL		 1183 cfg.flags = common_flags;
1184 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1185 if (ret < 0 && ret != -ENOIOCTLCMD) {
1186 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1187 common_flags, ret);
6a6c8786 1188 return ret;
679419aa
GL		 1189 }
1190
1191 cam->flags = common_flags;
6a6c8786
GL		 1192
1193 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
3bc43840
GL		 1194
1195 return 0;
1196}
1197
2a48fc73
RJ		 1198static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1199 unsigned char buswidth)
ad5f2e85 1200{
679419aa 1201 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
7dfff953 1202 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
ad5f2e85 1203 struct pxa_camera_dev *pcdev = ici->priv;
679419aa
GL		 1204 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1205 unsigned long bus_flags, common_flags;
2a48fc73 1206 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
ad5f2e85
GL		 1207
1208 if (ret < 0)
1209 return ret;
1210
679419aa
GL		 1211 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1212 if (!ret) {
1213 common_flags = soc_mbus_config_compatible(&cfg,
1214 bus_flags);
1215 if (!common_flags) {
1216 dev_warn(icd->parent,
1217 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1218 cfg.flags, bus_flags);
1219 return -EINVAL;
1220 }
1221 } else if (ret == -ENOIOCTLCMD) {
1222 ret = 0;
1223 }
ad5f2e85 1224
679419aa 1225 return ret;
ad5f2e85
GL		 1226}
1227
760697be 1228static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
2a48fc73 1229 {
760697be
GL		 1230 .fourcc = V4L2_PIX_FMT_YUV422P,
1231 .name = "Planar YUV422 16 bit",
1232 .bits_per_sample = 8,
1233 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1234 .order = SOC_MBUS_ORDER_LE,
ad3b81fa 1235 .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V,
2a48fc73
RJ		 1236 },
1237};
1238
760697be
GL		 1239/* This will be corrected as we get more formats */
1240static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
ad5f2e85 1241{
760697be
GL		 1242 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1243 (fmt->bits_per_sample == 8 &&
1244 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1245 (fmt->bits_per_sample > 8 &&
1246 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
2a48fc73
RJ		 1247}
1248
3805f201 1249static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
2a48fc73
RJ		 1250 struct soc_camera_format_xlate *xlate)
1251{
760697be 1252 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
7dfff953 1253 struct device *dev = icd->parent;
760697be 1254 int formats = 0, ret;
6a6c8786 1255 struct pxa_cam *cam;
ebcff5fc
HV		 1256 struct v4l2_subdev_mbus_code_enum code = {
1257 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1258 .index = idx,
1259 };
760697be 1260 const struct soc_mbus_pixelfmt *fmt;
2a48fc73 1261
ebcff5fc 1262 ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
760697be
GL		 1263 if (ret < 0)
1264 /* No more formats */
1265 return 0;
2a48fc73 1266
ebcff5fc 1267 fmt = soc_mbus_get_fmtdesc(code.code);
760697be 1268 if (!fmt) {
ebcff5fc 1269 dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code);
2a48fc73 1270 return 0;
760697be 1271 }
3bc43840 1272
760697be
GL		 1273 /* This also checks support for the requested bits-per-sample */
1274 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
2a48fc73
RJ		 1275 if (ret < 0)
1276 return 0;
1277
6a6c8786
GL		 1278 if (!icd->host_priv) {
1279 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1280 if (!cam)
1281 return -ENOMEM;
1282
1283 icd->host_priv = cam;
1284 } else {
1285 cam = icd->host_priv;
1286 }
1287
ebcff5fc 1288 switch (code.code) {
27ffaeb0 1289 case MEDIA_BUS_FMT_UYVY8_2X8:
2a48fc73
RJ		 1290 formats++;
1291 if (xlate) {
760697be 1292 xlate->host_fmt = &pxa_camera_formats[0];
ebcff5fc 1293 xlate->code = code.code;
2a48fc73 1294 xlate++;
760697be 1295 dev_dbg(dev, "Providing format %s using code %d\n",
ebcff5fc 1296 pxa_camera_formats[0].name, code.code);
2a48fc73 1297 }
27ffaeb0
BB		 1298 case MEDIA_BUS_FMT_VYUY8_2X8:
1299 case MEDIA_BUS_FMT_YUYV8_2X8:
1300 case MEDIA_BUS_FMT_YVYU8_2X8:
1301 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1302 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
760697be 1303 if (xlate)
0166b743 1304 dev_dbg(dev, "Providing format %s packed\n",
760697be 1305 fmt->name);
2a48fc73
RJ		 1306 break;
1307 default:
760697be
GL		 1308 if (!pxa_camera_packing_supported(fmt))
1309 return 0;
1310 if (xlate)
0166b743 1311 dev_dbg(dev,
2a48fc73 1312 "Providing format %s in pass-through mode\n",
760697be
GL		 1313 fmt->name);
1314 }
1315
1316 /* Generic pass-through */
1317 formats++;
1318 if (xlate) {
1319 xlate->host_fmt = fmt;
ebcff5fc 1320 xlate->code = code.code;
760697be 1321 xlate++;
2a48fc73
RJ		 1322 }
1323
1324 return formats;
1325}
1326
6a6c8786
GL		 1327static void pxa_camera_put_formats(struct soc_camera_device *icd)
1328{
1329 kfree(icd->host_priv);
1330 icd->host_priv = NULL;
1331}
1332
760697be 1333static int pxa_camera_check_frame(u32 width, u32 height)
6a6c8786
GL		 1334{
1335 /* limit to pxa hardware capabilities */
760697be
GL		 1336 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1337 (width & 0x01);
6a6c8786
GL		 1338}
1339
09e231b3 1340static int pxa_camera_set_crop(struct soc_camera_device *icd,
448a61f0 1341 const struct v4l2_crop *a)
09e231b3 1342{
448a61f0 1343 const struct v4l2_rect *rect = &a->c;
7dfff953
GL		 1344 struct device *dev = icd->parent;
1345 struct soc_camera_host *ici = to_soc_camera_host(dev);
09e231b3 1346 struct pxa_camera_dev *pcdev = ici->priv;
c9c1f1c0 1347 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
09e231b3
GL		 1348 struct soc_camera_sense sense = {
1349 .master_clock = pcdev->mclk,
1350 .pixel_clock_max = pcdev->ciclk / 4,
1351 };
da298c6d
HV		 1352 struct v4l2_subdev_format fmt = {
1353 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1354 };
1355 struct v4l2_mbus_framefmt *mf = &fmt.format;
6a6c8786 1356 struct pxa_cam *cam = icd->host_priv;
760697be 1357 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
09e231b3
GL		 1358 int ret;
1359
1360 /* If PCLK is used to latch data from the sensor, check sense */
1361 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1362 icd->sense = &sense;
1363
08590b96 1364 ret = v4l2_subdev_call(sd, video, s_crop, a);
09e231b3
GL		 1365
1366 icd->sense = NULL;
1367
1368 if (ret < 0) {
0166b743 1369 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
09e231b3 1370 rect->width, rect->height, rect->left, rect->top);
6a6c8786
GL		 1371 return ret;
1372 }
1373
da298c6d 1374 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
6a6c8786
GL		 1375 if (ret < 0)
1376 return ret;
1377
da298c6d 1378 if (pxa_camera_check_frame(mf->width, mf->height)) {
6a6c8786
GL		 1379 /*
1380 * Camera cropping produced a frame beyond our capabilities.
1381 * FIXME: just extract a subframe, that we can process.
1382 */
da298c6d
HV		 1383 v4l_bound_align_image(&mf->width, 48, 2048, 1,
1384 &mf->height, 32, 2048, 0,
760697be 1385 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
da298c6d 1386 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, mf);
6a6c8786
GL		 1387 if (ret < 0)
1388 return ret;
1389
da298c6d 1390 if (pxa_camera_check_frame(mf->width, mf->height)) {
7dfff953 1391 dev_warn(icd->parent,
6a6c8786
GL		 1392 "Inconsistent state. Use S_FMT to repair\n");
1393 return -EINVAL;
1394 }
1395 }
1396
1397 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
09e231b3 1398 if (sense.pixel_clock > sense.pixel_clock_max) {
0166b743 1399 dev_err(dev,
09e231b3
GL		 1400 "pixel clock %lu set by the camera too high!",
1401 sense.pixel_clock);
1402 return -EIO;
1403 }
1404 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1405 }
1406
da298c6d
HV		 1407 icd->user_width = mf->width;
1408 icd->user_height = mf->height;
6a6c8786 1409
760697be 1410 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
6a6c8786 1411
09e231b3
GL		 1412 return ret;
1413}
1414
d8fac217 1415static int pxa_camera_set_fmt(struct soc_camera_device *icd,
09e231b3 1416 struct v4l2_format *f)
ad5f2e85 1417{
7dfff953
GL		 1418 struct device *dev = icd->parent;
1419 struct soc_camera_host *ici = to_soc_camera_host(dev);
cf34cba7 1420 struct pxa_camera_dev *pcdev = ici->priv;
c9c1f1c0 1421 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
0ad675eb 1422 const struct soc_camera_format_xlate *xlate = NULL;
cf34cba7
GL		 1423 struct soc_camera_sense sense = {
1424 .master_clock = pcdev->mclk,
1425 .pixel_clock_max = pcdev->ciclk / 4,
1426 };
09e231b3 1427 struct v4l2_pix_format *pix = &f->fmt.pix;
760697be 1428 struct v4l2_mbus_framefmt mf;
0ad675eb 1429 int ret;
25c4d74e 1430
09e231b3
GL		 1431 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1432 if (!xlate) {
0166b743 1433 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
09e231b3 1434 return -EINVAL;
0ad675eb 1435 }
2a48fc73 1436
cf34cba7
GL		 1437 /* If PCLK is used to latch data from the sensor, check sense */
1438 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
760697be 1439 /* The caller holds a mutex. */
cf34cba7
GL		 1440 icd->sense = &sense;
1441
760697be
GL		 1442 mf.width = pix->width;
1443 mf.height = pix->height;
1444 mf.field = pix->field;
1445 mf.colorspace = pix->colorspace;
1446 mf.code = xlate->code;
1447
1448 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1449
1450 if (mf.code != xlate->code)
1451 return -EINVAL;
2a48fc73 1452
cf34cba7
GL		 1453 icd->sense = NULL;
1454
1455 if (ret < 0) {
0166b743 1456 dev_warn(dev, "Failed to configure for format %x\n",
09e231b3 1457 pix->pixelformat);
760697be 1458 } else if (pxa_camera_check_frame(mf.width, mf.height)) {
6a6c8786
GL		 1459 dev_warn(dev,
1460 "Camera driver produced an unsupported frame %dx%d\n",
760697be 1461 mf.width, mf.height);
6a6c8786 1462 ret = -EINVAL;
cf34cba7
GL		 1463 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1464 if (sense.pixel_clock > sense.pixel_clock_max) {
0166b743 1465 dev_err(dev,
cf34cba7
GL		 1466 "pixel clock %lu set by the camera too high!",
1467 sense.pixel_clock);
1468 return -EIO;
1469 }
1470 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1471 }
2a48fc73 1472
760697be
GL		 1473 if (ret < 0)
1474 return ret;
1475
1476 pix->width = mf.width;
1477 pix->height = mf.height;
1478 pix->field = mf.field;
1479 pix->colorspace = mf.colorspace;
1480 icd->current_fmt = xlate;
25c4d74e
GL		 1481
1482 return ret;
ad5f2e85
GL		 1483}
1484
d8fac217
GL		 1485static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1486 struct v4l2_format *f)
3bc43840 1487{
c9c1f1c0 1488 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
2a48fc73
RJ		 1489 const struct soc_camera_format_xlate *xlate;
1490 struct v4l2_pix_format *pix = &f->fmt.pix;
760697be 1491 struct v4l2_mbus_framefmt mf;
2a48fc73 1492 __u32 pixfmt = pix->pixelformat;
bf507158 1493 int ret;
a2c8c68c 1494
2a48fc73
RJ		 1495 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1496 if (!xlate) {
7dfff953 1497 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
25c4d74e 1498 return -EINVAL;
2a48fc73 1499 }
25c4d74e 1500
92a8337b 1501 /*
4a6b8df2
TP		 1502 * Limit to pxa hardware capabilities. YUV422P planar format requires
1503 * images size to be a multiple of 16 bytes. If not, zeros will be
1504 * inserted between Y and U planes, and U and V planes, which violates
1505 * the YUV422P standard.
92a8337b 1506 */
4a6b8df2
TP		 1507 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1508 &pix->height, 32, 2048, 0,
6a6c8786 1509 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
92a8337b 1510
ad5f2e85 1511 /* limit to sensor capabilities */
760697be
GL		 1512 mf.width = pix->width;
1513 mf.height = pix->height;
91401219
GL		 1514 /* Only progressive video supported so far */
1515 mf.field = V4L2_FIELD_NONE;
760697be
GL		 1516 mf.colorspace = pix->colorspace;
1517 mf.code = xlate->code;
bf507158 1518
760697be
GL		 1519 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1520 if (ret < 0)
1521 return ret;
06daa1af 1522
760697be
GL		 1523 pix->width = mf.width;
1524 pix->height = mf.height;
1525 pix->colorspace = mf.colorspace;
1526
1527 switch (mf.field) {
1528 case V4L2_FIELD_ANY:
1529 case V4L2_FIELD_NONE:
1530 pix->field = V4L2_FIELD_NONE;
1531 break;
1532 default:
1533 /* TODO: support interlaced at least in pass-through mode */
7dfff953 1534 dev_err(icd->parent, "Field type %d unsupported.\n",
760697be 1535 mf.field);
06daa1af
GL		 1536 return -EINVAL;
1537 }
1538
bf507158 1539 return ret;
3bc43840
GL		 1540}
1541
57bee29d 1542static int pxa_camera_reqbufs(struct soc_camera_device *icd,
7102b773 1543 struct v4l2_requestbuffers *p)
3bc43840
GL		 1544{
1545 int i;
1546
5d28d525
GL		 1547 /*
1548 * This is for locking debugging only. I removed spinlocks and now I
3bc43840
GL		 1549 * check whether .prepare is ever called on a linked buffer, or whether
1550 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
5d28d525
GL		 1551 * it hadn't triggered
1552 */
3bc43840 1553 for (i = 0; i < p->count; i++) {
57bee29d 1554 struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i],
3bc43840
GL		 1555 struct pxa_buffer, vb);
1556 buf->inwork = 0;
1557 INIT_LIST_HEAD(&buf->vb.queue);
1558 }
1559
1560 return 0;
1561}
1562
7102b773 1563static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
3bc43840 1564{
57bee29d 1565 struct soc_camera_device *icd = file->private_data;
3bc43840
GL		 1566 struct pxa_buffer *buf;
1567
57bee29d 1568 buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer,
3bc43840
GL		 1569 vb.stream);
1570
1571 poll_wait(file, &buf->vb.done, pt);
1572
1573 if (buf->vb.state == VIDEOBUF_DONE ||
1574 buf->vb.state == VIDEOBUF_ERROR)
1575 return POLLIN|POLLRDNORM;
1576
1577 return 0;
1578}
1579
7102b773
GL		 1580static int pxa_camera_querycap(struct soc_camera_host *ici,
1581 struct v4l2_capability *cap)
3bc43840
GL		 1582{
1583 /* cap->name is set by the firendly caller:-> */
1584 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
7d96c3e4
GL		 1585 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1586 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
3bc43840
GL		 1587
1588 return 0;
1589}
1590
7254026c 1591static int pxa_camera_suspend(struct device *dev)
3f6ac497 1592{
7254026c 1593 struct soc_camera_host *ici = to_soc_camera_host(dev);
3f6ac497
RJ		 1594 struct pxa_camera_dev *pcdev = ici->priv;
1595 int i = 0, ret = 0;
1596
5ca11fa3
EM		 1597 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1598 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1599 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1600 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1601 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
3f6ac497 1602
f7f6ce2d
GL		 1603 if (pcdev->soc_host.icd) {
1604 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
497833c6
GL		 1605 ret = v4l2_subdev_call(sd, core, s_power, 0);
1606 if (ret == -ENOIOCTLCMD)
1607 ret = 0;
1608 }
3f6ac497
RJ		 1609
1610 return ret;
1611}
1612
7254026c 1613static int pxa_camera_resume(struct device *dev)
3f6ac497 1614{
7254026c 1615 struct soc_camera_host *ici = to_soc_camera_host(dev);
3f6ac497
RJ		 1616 struct pxa_camera_dev *pcdev = ici->priv;
1617 int i = 0, ret = 0;
1618
87f3dd77
EM		 1619 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1620 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1621 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3f6ac497 1622
5ca11fa3
EM		 1623 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1624 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1625 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1626 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1627 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
3f6ac497 1628
f7f6ce2d
GL		 1629 if (pcdev->soc_host.icd) {
1630 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
497833c6
GL		 1631 ret = v4l2_subdev_call(sd, core, s_power, 1);
1632 if (ret == -ENOIOCTLCMD)
1633 ret = 0;
1634 }
3f6ac497
RJ		 1635
1636 /* Restart frame capture if active buffer exists */
256b0233
RJ		 1637 if (!ret && pcdev->active)
1638 pxa_camera_start_capture(pcdev);
3f6ac497
RJ		 1639
1640 return ret;
1641}
1642
b8d9904c
GL		 1643static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1644 .owner = THIS_MODULE,
1645 .add = pxa_camera_add_device,
1646 .remove = pxa_camera_remove_device,
39b553db
GL		 1647 .clock_start = pxa_camera_clock_start,
1648 .clock_stop = pxa_camera_clock_stop,
09e231b3 1649 .set_crop = pxa_camera_set_crop,
2a48fc73 1650 .get_formats = pxa_camera_get_formats,
6a6c8786 1651 .put_formats = pxa_camera_put_formats,
d8fac217
GL		 1652 .set_fmt = pxa_camera_set_fmt,
1653 .try_fmt = pxa_camera_try_fmt,
092d3921 1654 .init_videobuf = pxa_camera_init_videobuf,
b8d9904c
GL		 1655 .reqbufs = pxa_camera_reqbufs,
1656 .poll = pxa_camera_poll,
1657 .querycap = pxa_camera_querycap,
b8d9904c
GL		 1658 .set_bus_param = pxa_camera_set_bus_param,
1659};
1660
e9a1d94f
RJ		 1661static int pxa_camera_pdata_from_dt(struct device *dev,
1662 struct pxa_camera_dev *pcdev)
1663{
1664 u32 mclk_rate;
1665 struct device_node *np = dev->of_node;
1666 struct v4l2_of_endpoint ep;
1667 int err = of_property_read_u32(np, "clock-frequency",
1668 &mclk_rate);
1669 if (!err) {
1670 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
1671 pcdev->mclk = mclk_rate;
1672 }
1673
1674 np = of_graph_get_next_endpoint(np, NULL);
1675 if (!np) {
1676 dev_err(dev, "could not find endpoint\n");
1677 return -EINVAL;
1678 }
1679
1680 err = v4l2_of_parse_endpoint(np, &ep);
1681 if (err) {
1682 dev_err(dev, "could not parse endpoint\n");
1683 goto out;
1684 }
1685
1686 switch (ep.bus.parallel.bus_width) {
1687 case 4:
1688 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
1689 break;
1690 case 5:
1691 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
1692 break;
1693 case 8:
1694 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
1695 break;
1696 case 9:
1697 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
1698 break;
1699 case 10:
1700 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1701 break;
1702 default:
1703 break;
c611c908 1704 }
e9a1d94f
RJ		 1705
1706 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
1707 pcdev->platform_flags |= PXA_CAMERA_MASTER;
1708 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1709 pcdev->platform_flags |= PXA_CAMERA_HSP;
1710 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1711 pcdev->platform_flags |= PXA_CAMERA_VSP;
1712 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1713 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
1714 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1715 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
1716
1717out:
1718 of_node_put(np);
1719
1720 return err;
1721}
1722
4c62e976 1723static int pxa_camera_probe(struct platform_device *pdev)
3bc43840
GL		 1724{
1725 struct pxa_camera_dev *pcdev;
1726 struct resource *res;
1727 void __iomem *base;
02da4659 1728 int irq;
3bc43840
GL		 1729 int err = 0;
1730
1731 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1732 irq = platform_get_irq(pdev, 0);
47de201c
JL		 1733 if (!res || irq < 0)
1734 return -ENODEV;
3bc43840 1735
47de201c 1736 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
3bc43840 1737 if (!pcdev) {
7102b773 1738 dev_err(&pdev->dev, "Could not allocate pcdev\n");
47de201c 1739 return -ENOMEM;
3bc43840
GL		 1740 }
1741
47de201c
JL		 1742 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
1743 if (IS_ERR(pcdev->clk))
1744 return PTR_ERR(pcdev->clk);
3bc43840 1745
3bc43840
GL		 1746 pcdev->res = res;
1747
1748 pcdev->pdata = pdev->dev.platform_data;
e9a1d94f
RJ		 1749 if (&pdev->dev.of_node && !pcdev->pdata) {
1750 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
1751 } else {
1752 pcdev->platform_flags = pcdev->pdata->flags;
1753 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1754 }
1755 if (err < 0)
1756 return err;
1757
ad5f2e85
GL		 1758 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1759 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
5d28d525
GL		 1760 /*
1761 * Platform hasn't set available data widths. This is bad.
1762 * Warn and use a default.
1763 */
3bc43840
GL		 1764 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1765 "data widths, using default 10 bit\n");
1766 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1767 }
679419aa
GL		 1768 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1769 pcdev->width_flags = 1 << 7;
1770 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1771 pcdev->width_flags |= 1 << 8;
1772 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1773 pcdev->width_flags |= 1 << 9;
cf34cba7 1774 if (!pcdev->mclk) {
3bc43840 1775 dev_warn(&pdev->dev,
cf34cba7 1776 "mclk == 0! Please, fix your platform data. "
3bc43840 1777 "Using default 20MHz\n");
cf34cba7 1778 pcdev->mclk = 20000000;
3bc43840
GL		 1779 }
1780
40e2e092 1781 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
cf34cba7 1782
3bc43840
GL		 1783 INIT_LIST_HEAD(&pcdev->capture);
1784 spin_lock_init(&pcdev->lock);
1785
1786 /*
1787 * Request the regions.
1788 */
8efdb135
SK		 1789 base = devm_ioremap_resource(&pdev->dev, res);
1790 if (IS_ERR(base))
1791 return PTR_ERR(base);
1792
3bc43840
GL		 1793 pcdev->irq = irq;
1794 pcdev->base = base;
3bc43840
GL		 1795
1796 /* request dma */
de3e3b82 1797 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1798 pxa_camera_dma_irq_y, pcdev);
1799 if (err < 0) {
eff505fa 1800 dev_err(&pdev->dev, "Can't request DMA for Y\n");
47de201c 1801 return err;
3bc43840 1802 }
de3e3b82 1803 pcdev->dma_chans[0] = err;
eff505fa 1804 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
a5462e5b 1805
de3e3b82 1806 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1807 pxa_camera_dma_irq_u, pcdev);
1808 if (err < 0) {
eff505fa 1809 dev_err(&pdev->dev, "Can't request DMA for U\n");
a5462e5b
MR		 1810 goto exit_free_dma_y;
1811 }
de3e3b82 1812 pcdev->dma_chans[1] = err;
eff505fa 1813 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
a5462e5b 1814
de3e3b82 1815 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1816 pxa_camera_dma_irq_v, pcdev);
1817 if (err < 0) {
eff505fa 1818 dev_err(&pdev->dev, "Can't request DMA for V\n");
a5462e5b
MR		 1819 goto exit_free_dma_u;
1820 }
de3e3b82 1821 pcdev->dma_chans[2] = err;
eff505fa 1822 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
3bc43840 1823
87f3dd77
EM		 1824 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1825 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1826 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3bc43840
GL		 1827
1828 /* request irq */
47de201c
JL		 1829 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
1830 PXA_CAM_DRV_NAME, pcdev);
3bc43840 1831 if (err) {
47de201c 1832 dev_err(&pdev->dev, "Camera interrupt register failed\n");
3bc43840
GL		 1833 goto exit_free_dma;
1834 }
1835
eb6c8558
GL		 1836 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1837 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1838 pcdev->soc_host.priv = pcdev;
979ea1dd 1839 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
eb6c8558 1840 pcdev->soc_host.nr = pdev->id;
eff505fa 1841
eb6c8558 1842 err = soc_camera_host_register(&pcdev->soc_host);
3bc43840 1843 if (err)
47de201c 1844 goto exit_free_dma;
3bc43840
GL		 1845
1846 return 0;
1847
3bc43840 1848exit_free_dma:
a5462e5b
MR		 1849 pxa_free_dma(pcdev->dma_chans[2]);
1850exit_free_dma_u:
1851 pxa_free_dma(pcdev->dma_chans[1]);
1852exit_free_dma_y:
1853 pxa_free_dma(pcdev->dma_chans[0]);
3bc43840
GL		 1854 return err;
1855}
1856
4c62e976 1857static int pxa_camera_remove(struct platform_device *pdev)
3bc43840 1858{
eff505fa
GL		 1859 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1860 struct pxa_camera_dev *pcdev = container_of(soc_host,
1861 struct pxa_camera_dev, soc_host);
3bc43840 1862
a5462e5b
MR		 1863 pxa_free_dma(pcdev->dma_chans[0]);
1864 pxa_free_dma(pcdev->dma_chans[1]);
1865 pxa_free_dma(pcdev->dma_chans[2]);
3bc43840 1866
eff505fa 1867 soc_camera_host_unregister(soc_host);
3bc43840 1868
7102b773 1869 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
3bc43840 1870
3bc43840
GL		 1871 return 0;
1872}
1873
56a49194 1874static const struct dev_pm_ops pxa_camera_pm = {
7254026c
GL		 1875 .suspend = pxa_camera_suspend,
1876 .resume = pxa_camera_resume,
1877};
1878
e9a1d94f
RJ		 1879static const struct of_device_id pxa_camera_of_match[] = {
1880 { .compatible = "marvell,pxa270-qci", },
1881 {},
1882};
1883MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
1884
3bc43840 1885static struct platform_driver pxa_camera_driver = {
6003b2ad 1886 .driver = {
3bc43840 1887 .name = PXA_CAM_DRV_NAME,
7254026c 1888 .pm = &pxa_camera_pm,
e9a1d94f 1889 .of_match_table = of_match_ptr(pxa_camera_of_match),
3bc43840
GL		 1890 },
1891 .probe = pxa_camera_probe,
4c62e976 1892 .remove = pxa_camera_remove,
3bc43840
GL		 1893};
1894
1d6629b1 1895module_platform_driver(pxa_camera_driver);
3bc43840
GL		 1896
1897MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1898MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1899MODULE_LICENSE("GPL");
64dc3c1a 1900MODULE_VERSION(PXA_CAM_VERSION);
40e2e092 1901MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux kernel - Deliverables
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