Commit | Line | Data |
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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
8efdb135 | 18 | #include <linux/err.h> |
3bc43840 GL |
19 | #include <linux/errno.h> |
20 | #include <linux/fs.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/time.h> | |
3bc43840 GL |
26 | #include <linux/device.h> |
27 | #include <linux/platform_device.h> | |
3bc43840 | 28 | #include <linux/clk.h> |
d514edac | 29 | #include <linux/sched.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1e77d55a RJ |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/dma/pxa-dma.h> | |
3bc43840 GL |
34 | |
35 | #include <media/v4l2-common.h> | |
36 | #include <media/v4l2-dev.h> | |
e009ebd5 | 37 | #include <media/videobuf2-dma-sg.h> |
3bc43840 | 38 | #include <media/soc_camera.h> |
d647f0b7 | 39 | #include <media/drv-intf/soc_mediabus.h> |
e9a1d94f | 40 | #include <media/v4l2-of.h> |
3bc43840 GL |
41 | |
42 | #include <linux/videodev2.h> | |
43 | ||
a71daaa1 | 44 | #include <linux/platform_data/media/camera-pxa.h> |
3bc43840 | 45 | |
64dc3c1a | 46 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
47 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
48 | ||
5ca11fa3 EM |
49 | /* Camera Interface */ |
50 | #define CICR0 0x0000 | |
51 | #define CICR1 0x0004 | |
52 | #define CICR2 0x0008 | |
53 | #define CICR3 0x000C | |
54 | #define CICR4 0x0010 | |
55 | #define CISR 0x0014 | |
56 | #define CIFR 0x0018 | |
57 | #define CITOR 0x001C | |
58 | #define CIBR0 0x0028 | |
59 | #define CIBR1 0x0030 | |
60 | #define CIBR2 0x0038 | |
61 | ||
62 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
63 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
64 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
65 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
66 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
67 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
68 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
69 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
70 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
71 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
72 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
73 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
74 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
75 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
76 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
77 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
78 | ||
79 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
80 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
81 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
82 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
83 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
84 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
85 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
86 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
87 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
88 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
89 | ||
90 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
91 | wait count mask */ | |
92 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
93 | wait count mask */ | |
94 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
95 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
96 | wait count mask */ | |
97 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
98 | wait count mask */ | |
99 | ||
100 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
101 | wait count mask */ | |
102 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
103 | wait count mask */ | |
104 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
105 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
106 | wait count mask */ | |
107 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
108 | ||
109 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
110 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
111 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
112 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
113 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
114 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
115 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
116 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
117 | ||
118 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
119 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
120 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
121 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
122 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
123 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
124 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
125 | #define CISR_EOL (1 << 8) /* End of line */ | |
126 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
127 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
128 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
129 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
130 | #define CISR_EOF (1 << 3) /* End of frame */ | |
131 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
132 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
133 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
134 | ||
135 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
136 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
137 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
138 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
139 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
140 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
141 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
142 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
143 | ||
7102b773 GL |
144 | #define CICR0_SIM_MP (0 << 24) |
145 | #define CICR0_SIM_SP (1 << 24) | |
146 | #define CICR0_SIM_MS (2 << 24) | |
147 | #define CICR0_SIM_EP (3 << 24) | |
148 | #define CICR0_SIM_ES (4 << 24) | |
149 | ||
150 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
151 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
152 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
153 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
154 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
155 | |
156 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
157 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
158 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
159 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
160 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
161 | ||
162 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
163 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
164 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
165 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
166 | ||
3bc43840 GL |
167 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
168 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
169 | CICR0_EOFM | CICR0_FOM) | |
170 | ||
3bc43840 GL |
171 | /* |
172 | * Structures | |
173 | */ | |
a5462e5b MR |
174 | enum pxa_camera_active_dma { |
175 | DMA_Y = 0x1, | |
176 | DMA_U = 0x2, | |
177 | DMA_V = 0x4, | |
178 | }; | |
179 | ||
3bc43840 GL |
180 | /* buffer for one video frame */ |
181 | struct pxa_buffer { | |
182 | /* common v4l buffer stuff -- must be first */ | |
e009ebd5 RJ |
183 | struct vb2_v4l2_buffer vbuf; |
184 | struct list_head queue; | |
27ffaeb0 | 185 | u32 code; |
e009ebd5 | 186 | int nb_planes; |
a5462e5b | 187 | /* our descriptor lists for Y, U and V channels */ |
1e77d55a RJ |
188 | struct dma_async_tx_descriptor *descs[3]; |
189 | dma_cookie_t cookie[3]; | |
190 | struct scatterlist *sg[3]; | |
191 | int sg_len[3]; | |
e009ebd5 | 192 | size_t plane_sizes[3]; |
760697be GL |
193 | int inwork; |
194 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
195 | }; |
196 | ||
3bc43840 | 197 | struct pxa_camera_dev { |
eb6c8558 | 198 | struct soc_camera_host soc_host; |
5d28d525 GL |
199 | /* |
200 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 201 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
202 | * one camera, they will have to modify this driver too |
203 | */ | |
3bc43840 GL |
204 | struct clk *clk; |
205 | ||
206 | unsigned int irq; | |
207 | void __iomem *base; | |
a5462e5b | 208 | |
e7c50688 | 209 | int channels; |
1e77d55a | 210 | struct dma_chan *dma_chans[3]; |
3bc43840 | 211 | |
3bc43840 GL |
212 | struct pxacamera_platform_data *pdata; |
213 | struct resource *res; | |
214 | unsigned long platform_flags; | |
cf34cba7 GL |
215 | unsigned long ciclk; |
216 | unsigned long mclk; | |
217 | u32 mclk_divisor; | |
679419aa | 218 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
219 | |
220 | struct list_head capture; | |
221 | ||
222 | spinlock_t lock; | |
223 | ||
3bc43840 | 224 | struct pxa_buffer *active; |
e623ebe6 | 225 | struct tasklet_struct task_eof; |
3f6ac497 RJ |
226 | |
227 | u32 save_cicr[5]; | |
3bc43840 GL |
228 | }; |
229 | ||
6a6c8786 GL |
230 | struct pxa_cam { |
231 | unsigned long flags; | |
232 | }; | |
233 | ||
3bc43840 GL |
234 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
235 | ||
3bc43840 GL |
236 | /* |
237 | * Videobuf operations | |
238 | */ | |
e009ebd5 | 239 | static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb) |
3bc43840 | 240 | { |
e009ebd5 | 241 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
3bc43840 | 242 | |
e009ebd5 | 243 | return container_of(vbuf, struct pxa_buffer, vbuf); |
3bc43840 GL |
244 | } |
245 | ||
e009ebd5 | 246 | static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev) |
3bc43840 | 247 | { |
e009ebd5 | 248 | return pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
249 | } |
250 | ||
1e77d55a | 251 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
e5853918 RJ |
252 | enum pxa_camera_active_dma act_dma); |
253 | ||
1e77d55a | 254 | static void pxa_camera_dma_irq_y(void *data) |
e5853918 RJ |
255 | { |
256 | struct pxa_camera_dev *pcdev = data; | |
257 | ||
1e77d55a | 258 | pxa_camera_dma_irq(pcdev, DMA_Y); |
e5853918 RJ |
259 | } |
260 | ||
1e77d55a | 261 | static void pxa_camera_dma_irq_u(void *data) |
e5853918 RJ |
262 | { |
263 | struct pxa_camera_dev *pcdev = data; | |
264 | ||
1e77d55a | 265 | pxa_camera_dma_irq(pcdev, DMA_U); |
e5853918 RJ |
266 | } |
267 | ||
1e77d55a | 268 | static void pxa_camera_dma_irq_v(void *data) |
e5853918 RJ |
269 | { |
270 | struct pxa_camera_dev *pcdev = data; | |
271 | ||
1e77d55a | 272 | pxa_camera_dma_irq(pcdev, DMA_V); |
e5853918 RJ |
273 | } |
274 | ||
37f5aefd RJ |
275 | /** |
276 | * pxa_init_dma_channel - init dma descriptors | |
277 | * @pcdev: pxa camera device | |
e009ebd5 | 278 | * @vb: videobuffer2 buffer |
37f5aefd RJ |
279 | * @dma: dma video buffer |
280 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
281 | * @cibr: camera Receive Buffer Register | |
37f5aefd RJ |
282 | * |
283 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
37f5aefd | 284 | * |
1e77d55a | 285 | * Returns 0 if success or -ENOMEM if no memory is available |
37f5aefd | 286 | */ |
a5462e5b | 287 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
e009ebd5 RJ |
288 | struct pxa_buffer *buf, int channel, |
289 | struct scatterlist *sg, int sglen) | |
a5462e5b | 290 | { |
1e77d55a | 291 | struct dma_chan *dma_chan = pcdev->dma_chans[channel]; |
1e77d55a RJ |
292 | struct dma_async_tx_descriptor *tx; |
293 | ||
294 | tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM, | |
295 | DMA_PREP_INTERRUPT | DMA_CTRL_REUSE); | |
296 | if (!tx) { | |
e009ebd5 | 297 | dev_err(pcdev_to_dev(pcdev), |
1e77d55a RJ |
298 | "dmaengine_prep_slave_sg failed\n"); |
299 | goto fail; | |
a5462e5b MR |
300 | } |
301 | ||
1e77d55a RJ |
302 | tx->callback_param = pcdev; |
303 | switch (channel) { | |
304 | case 0: | |
305 | tx->callback = pxa_camera_dma_irq_y; | |
306 | break; | |
307 | case 1: | |
308 | tx->callback = pxa_camera_dma_irq_u; | |
309 | break; | |
310 | case 2: | |
311 | tx->callback = pxa_camera_dma_irq_v; | |
312 | break; | |
37f5aefd RJ |
313 | } |
314 | ||
1e77d55a | 315 | buf->descs[channel] = tx; |
a5462e5b | 316 | return 0; |
1e77d55a | 317 | fail: |
e009ebd5 RJ |
318 | dev_dbg(pcdev_to_dev(pcdev), |
319 | "%s (vb=%p) dma_tx=%p\n", | |
320 | __func__, buf, tx); | |
1e77d55a RJ |
321 | |
322 | return -ENOMEM; | |
a5462e5b MR |
323 | } |
324 | ||
256b0233 RJ |
325 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
326 | struct pxa_buffer *buf) | |
327 | { | |
328 | buf->active_dma = DMA_Y; | |
329 | if (pcdev->channels == 3) | |
330 | buf->active_dma |= DMA_U | DMA_V; | |
331 | } | |
332 | ||
256b0233 RJ |
333 | /** |
334 | * pxa_dma_start_channels - start DMA channel for active buffer | |
335 | * @pcdev: pxa camera device | |
336 | * | |
337 | * Initialize DMA channels to the beginning of the active video buffer, and | |
338 | * start these channels. | |
339 | */ | |
340 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
341 | { | |
342 | int i; | |
343 | struct pxa_buffer *active; | |
344 | ||
345 | active = pcdev->active; | |
346 | ||
347 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 348 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
349 | "%s (channel=%d)\n", __func__, i); |
350 | dma_async_issue_pending(pcdev->dma_chans[i]); | |
256b0233 RJ |
351 | } |
352 | } | |
353 | ||
354 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
355 | { | |
356 | int i; | |
357 | ||
358 | for (i = 0; i < pcdev->channels; i++) { | |
e009ebd5 | 359 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 360 | "%s (channel=%d)\n", __func__, i); |
1e77d55a | 361 | dmaengine_terminate_all(pcdev->dma_chans[i]); |
256b0233 RJ |
362 | } |
363 | } | |
364 | ||
256b0233 RJ |
365 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
366 | struct pxa_buffer *buf) | |
367 | { | |
368 | int i; | |
256b0233 RJ |
369 | |
370 | for (i = 0; i < pcdev->channels; i++) { | |
1e77d55a | 371 | buf->cookie[i] = dmaengine_submit(buf->descs[i]); |
e009ebd5 | 372 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a RJ |
373 | "%s (channel=%d) : submit vb=%p cookie=%d\n", |
374 | __func__, i, buf, buf->descs[i]->cookie); | |
ae7410e7 | 375 | } |
256b0233 RJ |
376 | } |
377 | ||
378 | /** | |
379 | * pxa_camera_start_capture - start video capturing | |
380 | * @pcdev: camera device | |
381 | * | |
382 | * Launch capturing. DMA channels should not be active yet. They should get | |
383 | * activated at the end of frame interrupt, to capture only whole frames, and | |
384 | * never begin the capture of a partial frame. | |
385 | */ | |
386 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
387 | { | |
a47f6be4 | 388 | unsigned long cicr0; |
256b0233 | 389 | |
e009ebd5 | 390 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
e623ebe6 | 391 | __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); |
256b0233 RJ |
392 | /* Enable End-Of-Frame Interrupt */ |
393 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
394 | cicr0 &= ~CICR0_EOFM; | |
395 | __raw_writel(cicr0, pcdev->base + CICR0); | |
396 | } | |
397 | ||
398 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
399 | { | |
400 | unsigned long cicr0; | |
401 | ||
402 | pxa_dma_stop_channels(pcdev); | |
403 | ||
404 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
405 | __raw_writel(cicr0, pcdev->base + CICR0); | |
406 | ||
8c62e221 | 407 | pcdev->active = NULL; |
e009ebd5 | 408 | dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); |
3bc43840 GL |
409 | } |
410 | ||
a5462e5b | 411 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
a5462e5b MR |
412 | struct pxa_buffer *buf) |
413 | { | |
e009ebd5 RJ |
414 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; |
415 | ||
a5462e5b | 416 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
e009ebd5 RJ |
417 | list_del_init(&buf->queue); |
418 | vb->timestamp = ktime_get_ns(); | |
419 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
420 | dev_dbg(pcdev_to_dev(pcdev), "%s dequeud buffer (buf=0x%p)\n", | |
421 | __func__, buf); | |
a5462e5b MR |
422 | |
423 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 424 | pxa_camera_stop_capture(pcdev); |
a5462e5b MR |
425 | return; |
426 | } | |
427 | ||
428 | pcdev->active = list_entry(pcdev->capture.next, | |
e009ebd5 | 429 | struct pxa_buffer, queue); |
a5462e5b MR |
430 | } |
431 | ||
256b0233 RJ |
432 | /** |
433 | * pxa_camera_check_link_miss - check missed DMA linking | |
434 | * @pcdev: camera device | |
435 | * | |
436 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
437 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 438 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
439 | * This function restarts the capture for this corner case, where : |
440 | * - DADR() == DADDR_STOP | |
441 | * - a videobuffer is queued on the pcdev->capture list | |
442 | * | |
443 | * Please check the "DMA hot chaining timeslice issue" in | |
444 | * Documentation/video4linux/pxa_camera.txt | |
445 | * | |
446 | * Context: should only be called within the dma irq handler | |
447 | */ | |
1e77d55a RJ |
448 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev, |
449 | dma_cookie_t last_submitted, | |
450 | dma_cookie_t last_issued) | |
256b0233 | 451 | { |
1e77d55a | 452 | bool is_dma_stopped = last_submitted != last_issued; |
256b0233 | 453 | |
e009ebd5 | 454 | dev_dbg(pcdev_to_dev(pcdev), |
1e77d55a | 455 | "%s : top queued buffer=%p, is_dma_stopped=%d\n", |
256b0233 | 456 | __func__, pcdev->active, is_dma_stopped); |
1e77d55a | 457 | |
256b0233 RJ |
458 | if (pcdev->active && is_dma_stopped) |
459 | pxa_camera_start_capture(pcdev); | |
460 | } | |
461 | ||
1e77d55a | 462 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
a5462e5b | 463 | enum pxa_camera_active_dma act_dma) |
3bc43840 | 464 | { |
e009ebd5 | 465 | struct device *dev = pcdev_to_dev(pcdev); |
1e77d55a | 466 | struct pxa_buffer *buf, *last_buf; |
3bc43840 | 467 | unsigned long flags; |
1e77d55a RJ |
468 | u32 camera_status, overrun; |
469 | int chan; | |
1e77d55a RJ |
470 | enum dma_status last_status; |
471 | dma_cookie_t last_issued; | |
3bc43840 GL |
472 | |
473 | spin_lock_irqsave(&pcdev->lock, flags); | |
474 | ||
256b0233 | 475 | camera_status = __raw_readl(pcdev->base + CISR); |
1e77d55a RJ |
476 | dev_dbg(dev, "camera dma irq, cisr=0x%x dma=%d\n", |
477 | camera_status, act_dma); | |
256b0233 RJ |
478 | overrun = CISR_IFO_0; |
479 | if (pcdev->channels == 3) | |
480 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 481 | |
8c62e221 RJ |
482 | /* |
483 | * pcdev->active should not be NULL in DMA irq handler. | |
484 | * | |
485 | * But there is one corner case : if capture was stopped due to an | |
486 | * overrun of channel 1, and at that same channel 2 was completed. | |
487 | * | |
488 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
489 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
490 | * DMA irq handler will already be pending for channel 2. So on entering | |
491 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
492 | * that is normal. | |
493 | */ | |
494 | if (!pcdev->active) | |
3bc43840 | 495 | goto out; |
3bc43840 | 496 | |
e009ebd5 RJ |
497 | buf = pcdev->active; |
498 | WARN_ON(buf->inwork || list_empty(&buf->queue)); | |
3bc43840 | 499 | |
1e77d55a RJ |
500 | /* |
501 | * It's normal if the last frame creates an overrun, as there | |
502 | * are no more DMA descriptors to fetch from QCI fifos | |
503 | */ | |
504 | switch (act_dma) { | |
505 | case DMA_U: | |
506 | chan = 1; | |
507 | break; | |
508 | case DMA_V: | |
509 | chan = 2; | |
510 | break; | |
511 | default: | |
512 | chan = 0; | |
513 | break; | |
514 | } | |
515 | last_buf = list_entry(pcdev->capture.prev, | |
e009ebd5 | 516 | struct pxa_buffer, queue); |
1e77d55a RJ |
517 | last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan], |
518 | last_buf->cookie[chan], | |
519 | NULL, &last_issued); | |
520 | if (camera_status & overrun && | |
521 | last_status != DMA_COMPLETE) { | |
522 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", | |
523 | camera_status); | |
524 | pxa_camera_stop_capture(pcdev); | |
e009ebd5 | 525 | list_for_each_entry(buf, &pcdev->capture, queue) |
1e77d55a RJ |
526 | pxa_dma_add_tail_buf(pcdev, buf); |
527 | pxa_camera_start_capture(pcdev); | |
528 | goto out; | |
529 | } | |
530 | buf->active_dma &= ~act_dma; | |
531 | if (!buf->active_dma) { | |
e009ebd5 | 532 | pxa_camera_wakeup(pcdev, buf); |
1e77d55a RJ |
533 | pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan], |
534 | last_issued); | |
256b0233 | 535 | } |
3bc43840 GL |
536 | |
537 | out: | |
538 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
539 | } | |
540 | ||
e009ebd5 RJ |
541 | static void pxa_buffer_cleanup(struct pxa_buffer *buf) |
542 | { | |
543 | int i; | |
544 | ||
545 | for (i = 0; i < 3 && buf->descs[i]; i++) { | |
546 | dmaengine_desc_free(buf->descs[i]); | |
547 | kfree(buf->sg[i]); | |
548 | buf->descs[i] = NULL; | |
549 | buf->sg[i] = NULL; | |
550 | buf->sg_len[i] = 0; | |
551 | buf->plane_sizes[i] = 0; | |
552 | } | |
553 | buf->nb_planes = 0; | |
554 | } | |
555 | ||
556 | static int pxa_buffer_init(struct pxa_camera_dev *pcdev, | |
557 | struct pxa_buffer *buf) | |
558 | { | |
559 | struct vb2_buffer *vb = &buf->vbuf.vb2_buf; | |
560 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); | |
561 | int nb_channels = pcdev->channels; | |
562 | int i, ret = 0; | |
563 | unsigned long size = vb2_plane_size(vb, 0); | |
564 | ||
565 | switch (nb_channels) { | |
566 | case 1: | |
567 | buf->plane_sizes[0] = size; | |
568 | break; | |
569 | case 3: | |
570 | buf->plane_sizes[0] = size / 2; | |
571 | buf->plane_sizes[1] = size / 4; | |
572 | buf->plane_sizes[2] = size / 4; | |
573 | break; | |
574 | default: | |
575 | return -EINVAL; | |
576 | }; | |
577 | buf->nb_planes = nb_channels; | |
578 | ||
579 | ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels, | |
580 | buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL); | |
581 | if (ret < 0) { | |
582 | dev_err(pcdev_to_dev(pcdev), | |
583 | "sg_split failed: %d\n", ret); | |
584 | return ret; | |
585 | } | |
586 | for (i = 0; i < nb_channels; i++) { | |
587 | ret = pxa_init_dma_channel(pcdev, buf, i, | |
588 | buf->sg[i], buf->sg_len[i]); | |
589 | if (ret) { | |
590 | pxa_buffer_cleanup(buf); | |
591 | return ret; | |
592 | } | |
593 | } | |
594 | INIT_LIST_HEAD(&buf->queue); | |
595 | ||
596 | return ret; | |
597 | } | |
598 | ||
599 | static void pxac_vb2_cleanup(struct vb2_buffer *vb) | |
600 | { | |
601 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
602 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
603 | ||
604 | dev_dbg(pcdev_to_dev(pcdev), | |
605 | "%s(vb=%p)\n", __func__, vb); | |
606 | pxa_buffer_cleanup(buf); | |
607 | } | |
608 | ||
609 | static void pxac_vb2_queue(struct vb2_buffer *vb) | |
610 | { | |
611 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
612 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
613 | ||
614 | dev_dbg(pcdev_to_dev(pcdev), | |
615 | "%s(vb=%p) nb_channels=%d size=%lu active=%p\n", | |
616 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0), | |
617 | pcdev->active); | |
618 | ||
619 | list_add_tail(&buf->queue, &pcdev->capture); | |
620 | ||
621 | pxa_dma_add_tail_buf(pcdev, buf); | |
622 | } | |
623 | ||
624 | /* | |
625 | * Please check the DMA prepared buffer structure in : | |
626 | * Documentation/video4linux/pxa_camera.txt | |
627 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
628 | * modification while DMA chain is running will work anyway. | |
629 | */ | |
630 | static int pxac_vb2_prepare(struct vb2_buffer *vb) | |
631 | { | |
632 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
633 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
634 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); | |
635 | int ret = 0; | |
636 | ||
637 | switch (pcdev->channels) { | |
638 | case 1: | |
639 | case 3: | |
640 | vb2_set_plane_payload(vb, 0, icd->sizeimage); | |
641 | break; | |
642 | default: | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
646 | dev_dbg(pcdev_to_dev(pcdev), | |
647 | "%s (vb=%p) nb_channels=%d size=%lu\n", | |
648 | __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0)); | |
649 | ||
650 | WARN_ON(!icd->current_fmt); | |
651 | ||
652 | #ifdef DEBUG | |
653 | /* | |
654 | * This can be useful if you want to see if we actually fill | |
655 | * the buffer with something | |
656 | */ | |
657 | for (i = 0; i < vb->num_planes; i++) | |
658 | memset((void *)vb2_plane_vaddr(vb, i), | |
659 | 0xaa, vb2_get_plane_payload(vb, i)); | |
660 | #endif | |
661 | ||
662 | /* | |
663 | * I think, in buf_prepare you only have to protect global data, | |
664 | * the actual buffer is yours | |
665 | */ | |
666 | buf->inwork = 0; | |
667 | pxa_videobuf_set_actdma(pcdev, buf); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
672 | static int pxac_vb2_init(struct vb2_buffer *vb) | |
673 | { | |
674 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); | |
675 | struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); | |
676 | ||
677 | dev_dbg(pcdev_to_dev(pcdev), | |
678 | "%s(nb_channels=%d)\n", | |
679 | __func__, pcdev->channels); | |
680 | ||
681 | return pxa_buffer_init(pcdev, buf); | |
682 | } | |
683 | ||
684 | static int pxac_vb2_queue_setup(struct vb2_queue *vq, | |
685 | unsigned int *nbufs, | |
686 | unsigned int *num_planes, unsigned int sizes[], | |
687 | struct device *alloc_devs[]) | |
688 | { | |
689 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
690 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); | |
691 | int size = icd->sizeimage; | |
692 | ||
693 | dev_dbg(pcdev_to_dev(pcdev), | |
694 | "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n", | |
695 | __func__, vq, *nbufs, *num_planes, size); | |
696 | /* | |
697 | * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P | |
698 | * format, even if there are 3 planes Y, U and V, we reply there is only | |
699 | * one plane, containing Y, U and V data, one after the other. | |
700 | */ | |
701 | if (*num_planes) | |
702 | return sizes[0] < size ? -EINVAL : 0; | |
703 | ||
704 | *num_planes = 1; | |
705 | switch (pcdev->channels) { | |
706 | case 1: | |
707 | case 3: | |
708 | sizes[0] = size; | |
709 | break; | |
710 | default: | |
711 | return -EINVAL; | |
712 | } | |
713 | ||
714 | if (!*nbufs) | |
715 | *nbufs = 1; | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count) | |
721 | { | |
722 | struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); | |
723 | ||
724 | dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n", | |
725 | __func__, count, pcdev->active); | |
726 | ||
727 | if (!pcdev->active) | |
728 | pxa_camera_start_capture(pcdev); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static void pxac_vb2_stop_streaming(struct vb2_queue *vq) | |
734 | { | |
735 | vb2_wait_for_all_buffers(vq); | |
736 | } | |
737 | ||
738 | static struct vb2_ops pxac_vb2_ops = { | |
739 | .queue_setup = pxac_vb2_queue_setup, | |
740 | .buf_init = pxac_vb2_init, | |
741 | .buf_prepare = pxac_vb2_prepare, | |
742 | .buf_queue = pxac_vb2_queue, | |
743 | .buf_cleanup = pxac_vb2_cleanup, | |
744 | .start_streaming = pxac_vb2_start_streaming, | |
745 | .stop_streaming = pxac_vb2_stop_streaming, | |
746 | .wait_prepare = vb2_ops_wait_prepare, | |
747 | .wait_finish = vb2_ops_wait_finish, | |
3bc43840 GL |
748 | }; |
749 | ||
e009ebd5 RJ |
750 | static int pxa_camera_init_videobuf2(struct vb2_queue *vq, |
751 | struct soc_camera_device *icd) | |
092d3921 | 752 | { |
7dfff953 | 753 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
a034d1b7 | 754 | struct pxa_camera_dev *pcdev = ici->priv; |
e009ebd5 | 755 | int ret; |
a034d1b7 | 756 | |
e009ebd5 RJ |
757 | vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
758 | vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
759 | vq->drv_priv = pcdev; | |
760 | vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
761 | vq->buf_struct_size = sizeof(struct pxa_buffer); | |
762 | ||
763 | vq->ops = &pxac_vb2_ops; | |
764 | vq->mem_ops = &vb2_dma_sg_memops; | |
765 | ||
766 | ret = vb2_queue_init(vq); | |
767 | dev_dbg(pcdev_to_dev(pcdev), | |
768 | "vb2_queue_init(vq=%p): %d\n", vq, ret); | |
769 | ||
770 | return ret; | |
092d3921 PZ |
771 | } |
772 | ||
40e2e092 GL |
773 | static u32 mclk_get_divisor(struct platform_device *pdev, |
774 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 775 | { |
cf34cba7 | 776 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 777 | struct device *dev = &pdev->dev; |
cf34cba7 | 778 | u32 div; |
3bc43840 GL |
779 | unsigned long lcdclk; |
780 | ||
cf34cba7 GL |
781 | lcdclk = clk_get_rate(pcdev->clk); |
782 | pcdev->ciclk = lcdclk; | |
3bc43840 | 783 | |
cf34cba7 GL |
784 | /* mclk <= ciclk / 4 (27.4.2) */ |
785 | if (mclk > lcdclk / 4) { | |
786 | mclk = lcdclk / 4; | |
979ea1dd | 787 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
788 | } |
789 | ||
790 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
791 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 792 | |
cf34cba7 GL |
793 | /* If we're not supplying MCLK, leave it at 0 */ |
794 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
795 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 796 | |
979ea1dd | 797 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 798 | lcdclk, mclk, div); |
3bc43840 GL |
799 | |
800 | return div; | |
801 | } | |
802 | ||
cf34cba7 GL |
803 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
804 | unsigned long pclk) | |
805 | { | |
806 | /* We want a timeout > 1 pixel time, not ">=" */ | |
807 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
808 | ||
809 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
810 | } | |
811 | ||
7102b773 | 812 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 813 | { |
3bc43840 GL |
814 | u32 cicr4 = 0; |
815 | ||
5ca11fa3 EM |
816 | /* disable all interrupts */ |
817 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
818 | |
819 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
820 | cicr4 |= CICR4_PCLK_EN; | |
821 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
822 | cicr4 |= CICR4_MCLK_EN; | |
823 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
824 | cicr4 |= CICR4_PCP; | |
825 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
826 | cicr4 |= CICR4_HSP; | |
827 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
828 | cicr4 |= CICR4_VSP; | |
829 | ||
cf34cba7 GL |
830 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
831 | ||
832 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
833 | /* Initialise the timeout under the assumption pclk = mclk */ | |
834 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
835 | else | |
836 | /* "Safe default" - 13MHz */ | |
837 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 838 | |
91acd962 | 839 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
840 | } |
841 | ||
7102b773 | 842 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 843 | { |
91acd962 | 844 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
845 | } |
846 | ||
e623ebe6 | 847 | static void pxa_camera_eof(unsigned long arg) |
3bc43840 | 848 | { |
e623ebe6 RJ |
849 | struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg; |
850 | unsigned long cifr; | |
256b0233 | 851 | struct pxa_buffer *buf; |
3bc43840 | 852 | |
e009ebd5 | 853 | dev_dbg(pcdev_to_dev(pcdev), |
e623ebe6 RJ |
854 | "Camera interrupt status 0x%x\n", |
855 | __raw_readl(pcdev->base + CISR)); | |
856 | ||
857 | /* Reset the FIFOs */ | |
858 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
859 | __raw_writel(cifr, pcdev->base + CIFR); | |
860 | ||
861 | pcdev->active = list_first_entry(&pcdev->capture, | |
e009ebd5 RJ |
862 | struct pxa_buffer, queue); |
863 | buf = pcdev->active; | |
e623ebe6 RJ |
864 | pxa_videobuf_set_actdma(pcdev, buf); |
865 | ||
866 | pxa_dma_start_channels(pcdev); | |
867 | } | |
868 | ||
869 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
870 | { | |
871 | struct pxa_camera_dev *pcdev = data; | |
872 | unsigned long status, cicr0; | |
873 | ||
5ca11fa3 | 874 | status = __raw_readl(pcdev->base + CISR); |
e009ebd5 | 875 | dev_dbg(pcdev_to_dev(pcdev), |
0166b743 | 876 | "Camera interrupt status 0x%lx\n", status); |
3bc43840 | 877 | |
e7c50688 GL |
878 | if (!status) |
879 | return IRQ_NONE; | |
880 | ||
5ca11fa3 | 881 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
882 | |
883 | if (status & CISR_EOF) { | |
5ca11fa3 EM |
884 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
885 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e623ebe6 | 886 | tasklet_schedule(&pcdev->task_eof); |
e7c50688 GL |
887 | } |
888 | ||
3bc43840 GL |
889 | return IRQ_HANDLED; |
890 | } | |
891 | ||
39b553db GL |
892 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
893 | { | |
894 | dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", | |
895 | icd->devnum); | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static void pxa_camera_remove_device(struct soc_camera_device *icd) | |
901 | { | |
902 | dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", | |
903 | icd->devnum); | |
904 | } | |
905 | ||
1c3bb743 GL |
906 | /* |
907 | * The following two functions absolutely depend on the fact, that | |
908 | * there can be only one camera on PXA quick capture interface | |
dd669e90 | 909 | * Called with .host_lock held |
1c3bb743 | 910 | */ |
39b553db | 911 | static int pxa_camera_clock_start(struct soc_camera_host *ici) |
3bc43840 | 912 | { |
3bc43840 | 913 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 | 914 | |
7102b773 | 915 | pxa_camera_activate(pcdev); |
40e2e092 | 916 | |
40e2e092 | 917 | return 0; |
3bc43840 GL |
918 | } |
919 | ||
dd669e90 | 920 | /* Called with .host_lock held */ |
39b553db | 921 | static void pxa_camera_clock_stop(struct soc_camera_host *ici) |
3bc43840 | 922 | { |
3bc43840 GL |
923 | struct pxa_camera_dev *pcdev = ici->priv; |
924 | ||
3bc43840 | 925 | /* disable capture, disable interrupts */ |
5ca11fa3 | 926 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 927 | |
3bc43840 | 928 | /* Stop DMA engine */ |
1e77d55a | 929 | pxa_dma_stop_channels(pcdev); |
7102b773 | 930 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
931 | } |
932 | ||
ad5f2e85 GL |
933 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
934 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 935 | { |
ad5f2e85 GL |
936 | /* |
937 | * Platform specified synchronization and pixel clock polarities are | |
938 | * only a recommendation and are only used during probing. The PXA270 | |
939 | * quick capture interface supports both. | |
940 | */ | |
941 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
942 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
943 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
944 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
945 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
946 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
947 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
948 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
949 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
950 | |
951 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
952 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
953 | return 0; | |
ad5f2e85 | 954 | |
679419aa | 955 | return -EINVAL; |
ad5f2e85 GL |
956 | } |
957 | ||
6a6c8786 GL |
958 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
959 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 960 | { |
7dfff953 | 961 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 962 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 963 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 964 | unsigned long dw, bpp; |
32536108 GL |
965 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
966 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
967 | ||
968 | if (ret < 0) | |
969 | y_skip_top = 0; | |
3bc43840 | 970 | |
5d28d525 GL |
971 | /* |
972 | * Datawidth is now guaranteed to be equal to one of the three values. | |
973 | * We fix bit-per-pixel equal to data-width... | |
974 | */ | |
679419aa GL |
975 | switch (icd->current_fmt->host_fmt->bits_per_sample) { |
976 | case 10: | |
3bc43840 GL |
977 | dw = 4; |
978 | bpp = 0x40; | |
979 | break; | |
679419aa | 980 | case 9: |
3bc43840 GL |
981 | dw = 3; |
982 | bpp = 0x20; | |
983 | break; | |
984 | default: | |
5d28d525 GL |
985 | /* |
986 | * Actually it can only be 8 now, | |
987 | * default is just to silence compiler warnings | |
988 | */ | |
679419aa | 989 | case 8: |
3bc43840 GL |
990 | dw = 2; |
991 | bpp = 0; | |
992 | } | |
993 | ||
994 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
995 | cicr4 |= CICR4_PCLK_EN; | |
996 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
997 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 998 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 999 | cicr4 |= CICR4_PCP; |
679419aa | 1000 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 1001 | cicr4 |= CICR4_HSP; |
679419aa | 1002 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1003 | cicr4 |= CICR4_VSP; |
1004 | ||
5ca11fa3 | 1005 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1006 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1007 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1008 | |
6a6c8786 | 1009 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1010 | |
1011 | switch (pixfmt) { | |
1012 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1013 | pcdev->channels = 3; |
a5462e5b | 1014 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1015 | /* |
1016 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1017 | * reorderings of the YUV422 format, as no processing is done, | |
1018 | * and the YUV stream is just passed through without any | |
1019 | * transformation. Note that UYVY is the only format that | |
1020 | * should be used if pxa framebuffer Overlay2 is used. | |
1021 | */ | |
1022 | case V4L2_PIX_FMT_UYVY: | |
1023 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1024 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1025 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1026 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1027 | break; | |
1028 | case V4L2_PIX_FMT_RGB555: | |
1029 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1030 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1031 | break; | |
1032 | case V4L2_PIX_FMT_RGB565: | |
1033 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1034 | break; | |
1035 | } | |
1036 | ||
5ca11fa3 | 1037 | cicr2 = 0; |
6a6c8786 | 1038 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1039 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1040 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1041 | |
1042 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1043 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1044 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1045 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1046 | |
1047 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1048 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1049 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1050 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1051 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1052 | } |
1053 | ||
8843d119 | 1054 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) |
6a6c8786 | 1055 | { |
679419aa | 1056 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1057 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
6a6c8786 | 1058 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa | 1059 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 1060 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
679419aa | 1061 | unsigned long bus_flags, common_flags; |
760697be | 1062 | int ret; |
6a6c8786 GL |
1063 | struct pxa_cam *cam = icd->host_priv; |
1064 | ||
d2dcad49 GL |
1065 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1066 | &bus_flags); | |
6a6c8786 GL |
1067 | if (ret < 0) |
1068 | return ret; | |
1069 | ||
679419aa GL |
1070 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1071 | if (!ret) { | |
1072 | common_flags = soc_mbus_config_compatible(&cfg, | |
1073 | bus_flags); | |
1074 | if (!common_flags) { | |
1075 | dev_warn(icd->parent, | |
1076 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1077 | cfg.flags, bus_flags); | |
1078 | return -EINVAL; | |
1079 | } | |
1080 | } else if (ret != -ENOIOCTLCMD) { | |
1081 | return ret; | |
1082 | } else { | |
1083 | common_flags = bus_flags; | |
1084 | } | |
6a6c8786 GL |
1085 | |
1086 | pcdev->channels = 1; | |
1087 | ||
1088 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1089 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1090 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1091 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1092 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1093 | else |
679419aa | 1094 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1095 | } |
1096 | ||
679419aa GL |
1097 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1098 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1099 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1100 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1101 | else |
679419aa | 1102 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1103 | } |
1104 | ||
679419aa GL |
1105 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1106 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1107 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1108 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1109 | else |
679419aa | 1110 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1111 | } |
1112 | ||
679419aa GL |
1113 | cfg.flags = common_flags; |
1114 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1115 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1116 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1117 | common_flags, ret); | |
6a6c8786 | 1118 | return ret; |
679419aa GL |
1119 | } |
1120 | ||
1121 | cam->flags = common_flags; | |
6a6c8786 GL |
1122 | |
1123 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1124 | |
1125 | return 0; | |
1126 | } | |
1127 | ||
2a48fc73 RJ |
1128 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1129 | unsigned char buswidth) | |
ad5f2e85 | 1130 | { |
679419aa | 1131 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1132 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1133 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa GL |
1134 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1135 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1136 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1137 | |
1138 | if (ret < 0) | |
1139 | return ret; | |
1140 | ||
679419aa GL |
1141 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1142 | if (!ret) { | |
1143 | common_flags = soc_mbus_config_compatible(&cfg, | |
1144 | bus_flags); | |
1145 | if (!common_flags) { | |
1146 | dev_warn(icd->parent, | |
1147 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1148 | cfg.flags, bus_flags); | |
1149 | return -EINVAL; | |
1150 | } | |
1151 | } else if (ret == -ENOIOCTLCMD) { | |
1152 | ret = 0; | |
1153 | } | |
ad5f2e85 | 1154 | |
679419aa | 1155 | return ret; |
ad5f2e85 GL |
1156 | } |
1157 | ||
760697be | 1158 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1159 | { |
760697be GL |
1160 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1161 | .name = "Planar YUV422 16 bit", | |
1162 | .bits_per_sample = 8, | |
1163 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1164 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1165 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1166 | }, |
1167 | }; | |
1168 | ||
760697be GL |
1169 | /* This will be corrected as we get more formats */ |
1170 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1171 | { |
760697be GL |
1172 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1173 | (fmt->bits_per_sample == 8 && | |
1174 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1175 | (fmt->bits_per_sample > 8 && | |
1176 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1177 | } |
1178 | ||
3805f201 | 1179 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1180 | struct soc_camera_format_xlate *xlate) |
1181 | { | |
760697be | 1182 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1183 | struct device *dev = icd->parent; |
760697be | 1184 | int formats = 0, ret; |
6a6c8786 | 1185 | struct pxa_cam *cam; |
ebcff5fc HV |
1186 | struct v4l2_subdev_mbus_code_enum code = { |
1187 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1188 | .index = idx, | |
1189 | }; | |
760697be | 1190 | const struct soc_mbus_pixelfmt *fmt; |
2a48fc73 | 1191 | |
ebcff5fc | 1192 | ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code); |
760697be GL |
1193 | if (ret < 0) |
1194 | /* No more formats */ | |
1195 | return 0; | |
2a48fc73 | 1196 | |
ebcff5fc | 1197 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 1198 | if (!fmt) { |
ebcff5fc | 1199 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code); |
2a48fc73 | 1200 | return 0; |
760697be | 1201 | } |
3bc43840 | 1202 | |
760697be GL |
1203 | /* This also checks support for the requested bits-per-sample */ |
1204 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1205 | if (ret < 0) |
1206 | return 0; | |
1207 | ||
6a6c8786 GL |
1208 | if (!icd->host_priv) { |
1209 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1210 | if (!cam) | |
1211 | return -ENOMEM; | |
1212 | ||
1213 | icd->host_priv = cam; | |
1214 | } else { | |
1215 | cam = icd->host_priv; | |
1216 | } | |
1217 | ||
ebcff5fc | 1218 | switch (code.code) { |
27ffaeb0 | 1219 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1220 | formats++; |
1221 | if (xlate) { | |
760697be | 1222 | xlate->host_fmt = &pxa_camera_formats[0]; |
ebcff5fc | 1223 | xlate->code = code.code; |
2a48fc73 | 1224 | xlate++; |
760697be | 1225 | dev_dbg(dev, "Providing format %s using code %d\n", |
ebcff5fc | 1226 | pxa_camera_formats[0].name, code.code); |
2a48fc73 | 1227 | } |
27ffaeb0 BB |
1228 | case MEDIA_BUS_FMT_VYUY8_2X8: |
1229 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
1230 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
1231 | case MEDIA_BUS_FMT_RGB565_2X8_LE: | |
1232 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: | |
760697be | 1233 | if (xlate) |
0166b743 | 1234 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1235 | fmt->name); |
2a48fc73 RJ |
1236 | break; |
1237 | default: | |
760697be GL |
1238 | if (!pxa_camera_packing_supported(fmt)) |
1239 | return 0; | |
1240 | if (xlate) | |
0166b743 | 1241 | dev_dbg(dev, |
2a48fc73 | 1242 | "Providing format %s in pass-through mode\n", |
760697be GL |
1243 | fmt->name); |
1244 | } | |
1245 | ||
1246 | /* Generic pass-through */ | |
1247 | formats++; | |
1248 | if (xlate) { | |
1249 | xlate->host_fmt = fmt; | |
ebcff5fc | 1250 | xlate->code = code.code; |
760697be | 1251 | xlate++; |
2a48fc73 RJ |
1252 | } |
1253 | ||
1254 | return formats; | |
1255 | } | |
1256 | ||
6a6c8786 GL |
1257 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1258 | { | |
1259 | kfree(icd->host_priv); | |
1260 | icd->host_priv = NULL; | |
1261 | } | |
1262 | ||
760697be | 1263 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1264 | { |
1265 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1266 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1267 | (width & 0x01); | |
6a6c8786 GL |
1268 | } |
1269 | ||
10d5509c HV |
1270 | static int pxa_camera_set_selection(struct soc_camera_device *icd, |
1271 | struct v4l2_selection *sel) | |
09e231b3 | 1272 | { |
10d5509c | 1273 | const struct v4l2_rect *rect = &sel->r; |
7dfff953 GL |
1274 | struct device *dev = icd->parent; |
1275 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
09e231b3 | 1276 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1277 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1278 | struct soc_camera_sense sense = { |
1279 | .master_clock = pcdev->mclk, | |
1280 | .pixel_clock_max = pcdev->ciclk / 4, | |
1281 | }; | |
da298c6d HV |
1282 | struct v4l2_subdev_format fmt = { |
1283 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1284 | }; | |
1285 | struct v4l2_mbus_framefmt *mf = &fmt.format; | |
6a6c8786 | 1286 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1287 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
10d5509c HV |
1288 | struct v4l2_subdev_selection sdsel = { |
1289 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1290 | .target = sel->target, | |
1291 | .flags = sel->flags, | |
1292 | .r = sel->r, | |
1293 | }; | |
09e231b3 GL |
1294 | int ret; |
1295 | ||
1296 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1297 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1298 | icd->sense = &sense; | |
1299 | ||
10d5509c | 1300 | ret = v4l2_subdev_call(sd, pad, set_selection, NULL, &sdsel); |
09e231b3 GL |
1301 | |
1302 | icd->sense = NULL; | |
1303 | ||
1304 | if (ret < 0) { | |
0166b743 | 1305 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1306 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1307 | return ret; |
1308 | } | |
10d5509c | 1309 | sel->r = sdsel.r; |
6a6c8786 | 1310 | |
da298c6d | 1311 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); |
6a6c8786 GL |
1312 | if (ret < 0) |
1313 | return ret; | |
1314 | ||
da298c6d | 1315 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1316 | /* |
1317 | * Camera cropping produced a frame beyond our capabilities. | |
1318 | * FIXME: just extract a subframe, that we can process. | |
1319 | */ | |
da298c6d HV |
1320 | v4l_bound_align_image(&mf->width, 48, 2048, 1, |
1321 | &mf->height, 32, 2048, 0, | |
760697be | 1322 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
ebf984bb | 1323 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt); |
6a6c8786 GL |
1324 | if (ret < 0) |
1325 | return ret; | |
1326 | ||
da298c6d | 1327 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
7dfff953 | 1328 | dev_warn(icd->parent, |
6a6c8786 GL |
1329 | "Inconsistent state. Use S_FMT to repair\n"); |
1330 | return -EINVAL; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1335 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1336 | dev_err(dev, |
09e231b3 GL |
1337 | "pixel clock %lu set by the camera too high!", |
1338 | sense.pixel_clock); | |
1339 | return -EIO; | |
1340 | } | |
1341 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1342 | } | |
1343 | ||
da298c6d HV |
1344 | icd->user_width = mf->width; |
1345 | icd->user_height = mf->height; | |
6a6c8786 | 1346 | |
760697be | 1347 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1348 | |
09e231b3 GL |
1349 | return ret; |
1350 | } | |
1351 | ||
d8fac217 | 1352 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1353 | struct v4l2_format *f) |
ad5f2e85 | 1354 | { |
7dfff953 GL |
1355 | struct device *dev = icd->parent; |
1356 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
cf34cba7 | 1357 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1358 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1359 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1360 | struct soc_camera_sense sense = { |
1361 | .master_clock = pcdev->mclk, | |
1362 | .pixel_clock_max = pcdev->ciclk / 4, | |
1363 | }; | |
09e231b3 | 1364 | struct v4l2_pix_format *pix = &f->fmt.pix; |
ebf984bb HV |
1365 | struct v4l2_subdev_format format = { |
1366 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1367 | }; | |
1368 | struct v4l2_mbus_framefmt *mf = &format.format; | |
0ad675eb | 1369 | int ret; |
25c4d74e | 1370 | |
09e231b3 GL |
1371 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1372 | if (!xlate) { | |
0166b743 | 1373 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1374 | return -EINVAL; |
0ad675eb | 1375 | } |
2a48fc73 | 1376 | |
cf34cba7 GL |
1377 | /* If PCLK is used to latch data from the sensor, check sense */ |
1378 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1379 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1380 | icd->sense = &sense; |
1381 | ||
ebf984bb HV |
1382 | mf->width = pix->width; |
1383 | mf->height = pix->height; | |
1384 | mf->field = pix->field; | |
1385 | mf->colorspace = pix->colorspace; | |
1386 | mf->code = xlate->code; | |
760697be | 1387 | |
ebf984bb | 1388 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format); |
760697be | 1389 | |
ebf984bb | 1390 | if (mf->code != xlate->code) |
760697be | 1391 | return -EINVAL; |
2a48fc73 | 1392 | |
cf34cba7 GL |
1393 | icd->sense = NULL; |
1394 | ||
1395 | if (ret < 0) { | |
0166b743 | 1396 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1397 | pix->pixelformat); |
ebf984bb | 1398 | } else if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1399 | dev_warn(dev, |
1400 | "Camera driver produced an unsupported frame %dx%d\n", | |
ebf984bb | 1401 | mf->width, mf->height); |
6a6c8786 | 1402 | ret = -EINVAL; |
cf34cba7 GL |
1403 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1404 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1405 | dev_err(dev, |
cf34cba7 GL |
1406 | "pixel clock %lu set by the camera too high!", |
1407 | sense.pixel_clock); | |
1408 | return -EIO; | |
1409 | } | |
1410 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1411 | } | |
2a48fc73 | 1412 | |
760697be GL |
1413 | if (ret < 0) |
1414 | return ret; | |
1415 | ||
ebf984bb HV |
1416 | pix->width = mf->width; |
1417 | pix->height = mf->height; | |
1418 | pix->field = mf->field; | |
1419 | pix->colorspace = mf->colorspace; | |
760697be | 1420 | icd->current_fmt = xlate; |
25c4d74e GL |
1421 | |
1422 | return ret; | |
ad5f2e85 GL |
1423 | } |
1424 | ||
d8fac217 GL |
1425 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1426 | struct v4l2_format *f) | |
3bc43840 | 1427 | { |
c9c1f1c0 | 1428 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1429 | const struct soc_camera_format_xlate *xlate; |
1430 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
5eab4983 HV |
1431 | struct v4l2_subdev_pad_config pad_cfg; |
1432 | struct v4l2_subdev_format format = { | |
1433 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1434 | }; | |
1435 | struct v4l2_mbus_framefmt *mf = &format.format; | |
2a48fc73 | 1436 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1437 | int ret; |
a2c8c68c | 1438 | |
2a48fc73 RJ |
1439 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1440 | if (!xlate) { | |
7dfff953 | 1441 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1442 | return -EINVAL; |
2a48fc73 | 1443 | } |
25c4d74e | 1444 | |
92a8337b | 1445 | /* |
4a6b8df2 TP |
1446 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1447 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1448 | * inserted between Y and U planes, and U and V planes, which violates | |
1449 | * the YUV422P standard. | |
92a8337b | 1450 | */ |
4a6b8df2 TP |
1451 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1452 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1453 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1454 | |
ad5f2e85 | 1455 | /* limit to sensor capabilities */ |
5eab4983 HV |
1456 | mf->width = pix->width; |
1457 | mf->height = pix->height; | |
91401219 | 1458 | /* Only progressive video supported so far */ |
5eab4983 HV |
1459 | mf->field = V4L2_FIELD_NONE; |
1460 | mf->colorspace = pix->colorspace; | |
1461 | mf->code = xlate->code; | |
bf507158 | 1462 | |
5eab4983 | 1463 | ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format); |
760697be GL |
1464 | if (ret < 0) |
1465 | return ret; | |
06daa1af | 1466 | |
5eab4983 HV |
1467 | pix->width = mf->width; |
1468 | pix->height = mf->height; | |
1469 | pix->colorspace = mf->colorspace; | |
760697be | 1470 | |
5eab4983 | 1471 | switch (mf->field) { |
760697be GL |
1472 | case V4L2_FIELD_ANY: |
1473 | case V4L2_FIELD_NONE: | |
1474 | pix->field = V4L2_FIELD_NONE; | |
1475 | break; | |
1476 | default: | |
1477 | /* TODO: support interlaced at least in pass-through mode */ | |
7dfff953 | 1478 | dev_err(icd->parent, "Field type %d unsupported.\n", |
5eab4983 | 1479 | mf->field); |
06daa1af GL |
1480 | return -EINVAL; |
1481 | } | |
1482 | ||
bf507158 | 1483 | return ret; |
3bc43840 GL |
1484 | } |
1485 | ||
7102b773 | 1486 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1487 | { |
57bee29d | 1488 | struct soc_camera_device *icd = file->private_data; |
3bc43840 | 1489 | |
e009ebd5 | 1490 | return vb2_poll(&icd->vb2_vidq, file, pt); |
3bc43840 GL |
1491 | } |
1492 | ||
7102b773 GL |
1493 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1494 | struct v4l2_capability *cap) | |
3bc43840 GL |
1495 | { |
1496 | /* cap->name is set by the firendly caller:-> */ | |
1497 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
7d96c3e4 GL |
1498 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1499 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
3bc43840 GL |
1500 | |
1501 | return 0; | |
1502 | } | |
1503 | ||
7254026c | 1504 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1505 | { |
7254026c | 1506 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1507 | struct pxa_camera_dev *pcdev = ici->priv; |
1508 | int i = 0, ret = 0; | |
1509 | ||
5ca11fa3 EM |
1510 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1511 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1512 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1513 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1514 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1515 | |
f7f6ce2d GL |
1516 | if (pcdev->soc_host.icd) { |
1517 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1518 | ret = v4l2_subdev_call(sd, core, s_power, 0); |
1519 | if (ret == -ENOIOCTLCMD) | |
1520 | ret = 0; | |
1521 | } | |
3f6ac497 RJ |
1522 | |
1523 | return ret; | |
1524 | } | |
1525 | ||
7254026c | 1526 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1527 | { |
7254026c | 1528 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1529 | struct pxa_camera_dev *pcdev = ici->priv; |
1530 | int i = 0, ret = 0; | |
1531 | ||
5ca11fa3 EM |
1532 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1533 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1534 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1535 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1536 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1537 | |
f7f6ce2d GL |
1538 | if (pcdev->soc_host.icd) { |
1539 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1540 | ret = v4l2_subdev_call(sd, core, s_power, 1); |
1541 | if (ret == -ENOIOCTLCMD) | |
1542 | ret = 0; | |
1543 | } | |
3f6ac497 RJ |
1544 | |
1545 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1546 | if (!ret && pcdev->active) |
1547 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1548 | |
1549 | return ret; | |
1550 | } | |
1551 | ||
b8d9904c GL |
1552 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1553 | .owner = THIS_MODULE, | |
1554 | .add = pxa_camera_add_device, | |
1555 | .remove = pxa_camera_remove_device, | |
39b553db GL |
1556 | .clock_start = pxa_camera_clock_start, |
1557 | .clock_stop = pxa_camera_clock_stop, | |
10d5509c | 1558 | .set_selection = pxa_camera_set_selection, |
2a48fc73 | 1559 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1560 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1561 | .set_fmt = pxa_camera_set_fmt, |
1562 | .try_fmt = pxa_camera_try_fmt, | |
e009ebd5 | 1563 | .init_videobuf2 = pxa_camera_init_videobuf2, |
b8d9904c GL |
1564 | .poll = pxa_camera_poll, |
1565 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1566 | .set_bus_param = pxa_camera_set_bus_param, |
1567 | }; | |
1568 | ||
e9a1d94f RJ |
1569 | static int pxa_camera_pdata_from_dt(struct device *dev, |
1570 | struct pxa_camera_dev *pcdev) | |
1571 | { | |
1572 | u32 mclk_rate; | |
1573 | struct device_node *np = dev->of_node; | |
1574 | struct v4l2_of_endpoint ep; | |
1575 | int err = of_property_read_u32(np, "clock-frequency", | |
1576 | &mclk_rate); | |
1577 | if (!err) { | |
1578 | pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; | |
1579 | pcdev->mclk = mclk_rate; | |
1580 | } | |
1581 | ||
1582 | np = of_graph_get_next_endpoint(np, NULL); | |
1583 | if (!np) { | |
1584 | dev_err(dev, "could not find endpoint\n"); | |
1585 | return -EINVAL; | |
1586 | } | |
1587 | ||
1588 | err = v4l2_of_parse_endpoint(np, &ep); | |
1589 | if (err) { | |
1590 | dev_err(dev, "could not parse endpoint\n"); | |
1591 | goto out; | |
1592 | } | |
1593 | ||
1594 | switch (ep.bus.parallel.bus_width) { | |
1595 | case 4: | |
1596 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; | |
1597 | break; | |
1598 | case 5: | |
1599 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; | |
1600 | break; | |
1601 | case 8: | |
1602 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; | |
1603 | break; | |
1604 | case 9: | |
1605 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; | |
1606 | break; | |
1607 | case 10: | |
1608 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1609 | break; | |
1610 | default: | |
1611 | break; | |
c611c908 | 1612 | } |
e9a1d94f RJ |
1613 | |
1614 | if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) | |
1615 | pcdev->platform_flags |= PXA_CAMERA_MASTER; | |
1616 | if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
1617 | pcdev->platform_flags |= PXA_CAMERA_HSP; | |
1618 | if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
1619 | pcdev->platform_flags |= PXA_CAMERA_VSP; | |
1620 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
1621 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; | |
1622 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
1623 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; | |
1624 | ||
1625 | out: | |
1626 | of_node_put(np); | |
1627 | ||
1628 | return err; | |
1629 | } | |
1630 | ||
4c62e976 | 1631 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1632 | { |
1633 | struct pxa_camera_dev *pcdev; | |
1634 | struct resource *res; | |
1635 | void __iomem *base; | |
1e77d55a RJ |
1636 | struct dma_slave_config config = { |
1637 | .src_addr_width = 0, | |
1638 | .src_maxburst = 8, | |
1639 | .direction = DMA_DEV_TO_MEM, | |
1640 | }; | |
1641 | dma_cap_mask_t mask; | |
1642 | struct pxad_param params; | |
02da4659 | 1643 | int irq; |
1e77d55a | 1644 | int err = 0, i; |
3bc43840 GL |
1645 | |
1646 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1647 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1648 | if (!res || irq < 0) |
1649 | return -ENODEV; | |
3bc43840 | 1650 | |
47de201c | 1651 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1652 | if (!pcdev) { |
7102b773 | 1653 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1654 | return -ENOMEM; |
3bc43840 GL |
1655 | } |
1656 | ||
47de201c JL |
1657 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1658 | if (IS_ERR(pcdev->clk)) | |
1659 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1660 | |
3bc43840 GL |
1661 | pcdev->res = res; |
1662 | ||
1663 | pcdev->pdata = pdev->dev.platform_data; | |
e9a1d94f RJ |
1664 | if (&pdev->dev.of_node && !pcdev->pdata) { |
1665 | err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); | |
1666 | } else { | |
1667 | pcdev->platform_flags = pcdev->pdata->flags; | |
1668 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
1669 | } | |
1670 | if (err < 0) | |
1671 | return err; | |
1672 | ||
ad5f2e85 GL |
1673 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1674 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1675 | /* |
1676 | * Platform hasn't set available data widths. This is bad. | |
1677 | * Warn and use a default. | |
1678 | */ | |
3bc43840 GL |
1679 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1680 | "data widths, using default 10 bit\n"); | |
1681 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1682 | } | |
679419aa GL |
1683 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1684 | pcdev->width_flags = 1 << 7; | |
1685 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1686 | pcdev->width_flags |= 1 << 8; | |
1687 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1688 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 | 1689 | if (!pcdev->mclk) { |
3bc43840 | 1690 | dev_warn(&pdev->dev, |
cf34cba7 | 1691 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1692 | "Using default 20MHz\n"); |
cf34cba7 | 1693 | pcdev->mclk = 20000000; |
3bc43840 GL |
1694 | } |
1695 | ||
40e2e092 | 1696 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1697 | |
3bc43840 GL |
1698 | INIT_LIST_HEAD(&pcdev->capture); |
1699 | spin_lock_init(&pcdev->lock); | |
1700 | ||
1701 | /* | |
1702 | * Request the regions. | |
1703 | */ | |
8efdb135 SK |
1704 | base = devm_ioremap_resource(&pdev->dev, res); |
1705 | if (IS_ERR(base)) | |
1706 | return PTR_ERR(base); | |
1707 | ||
3bc43840 GL |
1708 | pcdev->irq = irq; |
1709 | pcdev->base = base; | |
3bc43840 GL |
1710 | |
1711 | /* request dma */ | |
1e77d55a RJ |
1712 | dma_cap_zero(mask); |
1713 | dma_cap_set(DMA_SLAVE, mask); | |
1714 | dma_cap_set(DMA_PRIVATE, mask); | |
1715 | ||
1716 | params.prio = 0; | |
1717 | params.drcmr = 68; | |
1718 | pcdev->dma_chans[0] = | |
1719 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1720 | ¶ms, &pdev->dev, "CI_Y"); | |
1721 | if (!pcdev->dma_chans[0]) { | |
eff505fa | 1722 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
1e77d55a | 1723 | return -ENODEV; |
3bc43840 | 1724 | } |
a5462e5b | 1725 | |
1e77d55a RJ |
1726 | params.drcmr = 69; |
1727 | pcdev->dma_chans[1] = | |
1728 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1729 | ¶ms, &pdev->dev, "CI_U"); | |
1730 | if (!pcdev->dma_chans[1]) { | |
1731 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); | |
a5462e5b MR |
1732 | goto exit_free_dma_y; |
1733 | } | |
a5462e5b | 1734 | |
1e77d55a RJ |
1735 | params.drcmr = 70; |
1736 | pcdev->dma_chans[2] = | |
1737 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1738 | ¶ms, &pdev->dev, "CI_V"); | |
1739 | if (!pcdev->dma_chans[2]) { | |
eff505fa | 1740 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1741 | goto exit_free_dma_u; |
1742 | } | |
3bc43840 | 1743 | |
1e77d55a RJ |
1744 | for (i = 0; i < 3; i++) { |
1745 | config.src_addr = pcdev->res->start + CIBR0 + i * 8; | |
1746 | err = dmaengine_slave_config(pcdev->dma_chans[i], &config); | |
1747 | if (err < 0) { | |
1748 | dev_err(&pdev->dev, "dma slave config failed: %d\n", | |
1749 | err); | |
1750 | goto exit_free_dma; | |
1751 | } | |
1752 | } | |
3bc43840 GL |
1753 | |
1754 | /* request irq */ | |
47de201c JL |
1755 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1756 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1757 | if (err) { |
47de201c | 1758 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1759 | goto exit_free_dma; |
1760 | } | |
1761 | ||
eb6c8558 GL |
1762 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1763 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1764 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1765 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1766 | pcdev->soc_host.nr = pdev->id; |
e623ebe6 | 1767 | tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev); |
eff505fa | 1768 | |
eb6c8558 | 1769 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 | 1770 | if (err) |
47de201c | 1771 | goto exit_free_dma; |
3bc43840 GL |
1772 | |
1773 | return 0; | |
1774 | ||
3bc43840 | 1775 | exit_free_dma: |
1e77d55a | 1776 | dma_release_channel(pcdev->dma_chans[2]); |
a5462e5b | 1777 | exit_free_dma_u: |
1e77d55a | 1778 | dma_release_channel(pcdev->dma_chans[1]); |
a5462e5b | 1779 | exit_free_dma_y: |
1e77d55a | 1780 | dma_release_channel(pcdev->dma_chans[0]); |
3bc43840 GL |
1781 | return err; |
1782 | } | |
1783 | ||
4c62e976 | 1784 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 1785 | { |
eff505fa GL |
1786 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1787 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1788 | struct pxa_camera_dev, soc_host); | |
3bc43840 | 1789 | |
1e77d55a RJ |
1790 | dma_release_channel(pcdev->dma_chans[0]); |
1791 | dma_release_channel(pcdev->dma_chans[1]); | |
1792 | dma_release_channel(pcdev->dma_chans[2]); | |
3bc43840 | 1793 | |
eff505fa | 1794 | soc_camera_host_unregister(soc_host); |
3bc43840 | 1795 | |
7102b773 | 1796 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1797 | |
3bc43840 GL |
1798 | return 0; |
1799 | } | |
1800 | ||
56a49194 | 1801 | static const struct dev_pm_ops pxa_camera_pm = { |
7254026c GL |
1802 | .suspend = pxa_camera_suspend, |
1803 | .resume = pxa_camera_resume, | |
1804 | }; | |
1805 | ||
e9a1d94f RJ |
1806 | static const struct of_device_id pxa_camera_of_match[] = { |
1807 | { .compatible = "marvell,pxa270-qci", }, | |
1808 | {}, | |
1809 | }; | |
1810 | MODULE_DEVICE_TABLE(of, pxa_camera_of_match); | |
1811 | ||
3bc43840 | 1812 | static struct platform_driver pxa_camera_driver = { |
6003b2ad | 1813 | .driver = { |
3bc43840 | 1814 | .name = PXA_CAM_DRV_NAME, |
7254026c | 1815 | .pm = &pxa_camera_pm, |
e9a1d94f | 1816 | .of_match_table = of_match_ptr(pxa_camera_of_match), |
3bc43840 GL |
1817 | }, |
1818 | .probe = pxa_camera_probe, | |
4c62e976 | 1819 | .remove = pxa_camera_remove, |
3bc43840 GL |
1820 | }; |
1821 | ||
1d6629b1 | 1822 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
1823 | |
1824 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1825 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1826 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1827 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1828 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |