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9262e5a2 AT |
1 | /* |
2 | * Copyright (c) 2013 Texas Instruments Inc. | |
3 | * | |
4 | * David Griego, <dagriego@biglakesoftware.com> | |
5 | * Dale Farnsworth, <dale@farnsworth.org> | |
6 | * Archit Taneja, <archit@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef _TI_VPDMA_PRIV_H_ | |
14 | #define _TI_VPDMA_PRIV_H_ | |
15 | ||
16 | /* | |
17 | * VPDMA Register offsets | |
18 | */ | |
19 | ||
20 | /* Top level */ | |
21 | #define VPDMA_PID 0x00 | |
22 | #define VPDMA_LIST_ADDR 0x04 | |
23 | #define VPDMA_LIST_ATTR 0x08 | |
24 | #define VPDMA_LIST_STAT_SYNC 0x0c | |
25 | #define VPDMA_BG_RGB 0x18 | |
26 | #define VPDMA_BG_YUV 0x1c | |
27 | #define VPDMA_SETUP 0x30 | |
28 | #define VPDMA_MAX_SIZE1 0x34 | |
29 | #define VPDMA_MAX_SIZE2 0x38 | |
30 | #define VPDMA_MAX_SIZE3 0x3c | |
31 | ||
32 | /* Interrupts */ | |
33 | #define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8) | |
34 | #define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4) | |
35 | #define VPDMA_INT_CLIENT0_STAT 0x78 | |
36 | #define VPDMA_INT_CLIENT0_MASK 0x7c | |
37 | #define VPDMA_INT_CLIENT1_STAT 0x80 | |
38 | #define VPDMA_INT_CLIENT1_MASK 0x84 | |
39 | #define VPDMA_INT_LIST0_STAT 0x88 | |
40 | #define VPDMA_INT_LIST0_MASK 0x8c | |
41 | ||
42 | #define VPDMA_PERFMON(i) (0x200 + i * 4) | |
43 | ||
44 | /* VPE specific client registers */ | |
45 | #define VPDMA_DEI_CHROMA1_CSTAT 0x0300 | |
46 | #define VPDMA_DEI_LUMA1_CSTAT 0x0304 | |
47 | #define VPDMA_DEI_LUMA2_CSTAT 0x0308 | |
48 | #define VPDMA_DEI_CHROMA2_CSTAT 0x030c | |
49 | #define VPDMA_DEI_LUMA3_CSTAT 0x0310 | |
50 | #define VPDMA_DEI_CHROMA3_CSTAT 0x0314 | |
51 | #define VPDMA_DEI_MV_IN_CSTAT 0x0330 | |
52 | #define VPDMA_DEI_MV_OUT_CSTAT 0x033c | |
53 | #define VPDMA_VIP_UP_Y_CSTAT 0x0390 | |
54 | #define VPDMA_VIP_UP_UV_CSTAT 0x0394 | |
55 | #define VPDMA_VPI_CTL_CSTAT 0x03d0 | |
56 | ||
57 | /* Reg field info for VPDMA_CLIENT_CSTAT registers */ | |
58 | #define VPDMA_CSTAT_LINE_MODE_MASK 0x03 | |
59 | #define VPDMA_CSTAT_LINE_MODE_SHIFT 8 | |
60 | #define VPDMA_CSTAT_FRAME_START_MASK 0xf | |
61 | #define VPDMA_CSTAT_FRAME_START_SHIFT 10 | |
62 | ||
63 | #define VPDMA_LIST_NUM_MASK 0x07 | |
64 | #define VPDMA_LIST_NUM_SHFT 24 | |
65 | #define VPDMA_LIST_STOP_SHFT 20 | |
66 | #define VPDMA_LIST_RDY_MASK 0x01 | |
67 | #define VPDMA_LIST_RDY_SHFT 19 | |
68 | #define VPDMA_LIST_TYPE_MASK 0x03 | |
69 | #define VPDMA_LIST_TYPE_SHFT 16 | |
70 | #define VPDMA_LIST_SIZE_MASK 0xffff | |
71 | ||
72 | /* VPDMA data type values for data formats */ | |
73 | #define DATA_TYPE_Y444 0x0 | |
74 | #define DATA_TYPE_Y422 0x1 | |
75 | #define DATA_TYPE_Y420 0x2 | |
76 | #define DATA_TYPE_C444 0x4 | |
77 | #define DATA_TYPE_C422 0x5 | |
78 | #define DATA_TYPE_C420 0x6 | |
79 | #define DATA_TYPE_YC422 0x7 | |
80 | #define DATA_TYPE_YC444 0x8 | |
fe104a9b | 81 | #define DATA_TYPE_CY422 0x27 |
9262e5a2 AT |
82 | |
83 | #define DATA_TYPE_RGB16_565 0x0 | |
84 | #define DATA_TYPE_ARGB_1555 0x1 | |
85 | #define DATA_TYPE_ARGB_4444 0x2 | |
86 | #define DATA_TYPE_RGBA_5551 0x3 | |
87 | #define DATA_TYPE_RGBA_4444 0x4 | |
88 | #define DATA_TYPE_ARGB24_6666 0x5 | |
89 | #define DATA_TYPE_RGB24_888 0x6 | |
90 | #define DATA_TYPE_ARGB32_8888 0x7 | |
91 | #define DATA_TYPE_RGBA24_6666 0x8 | |
92 | #define DATA_TYPE_RGBA32_8888 0x9 | |
93 | #define DATA_TYPE_BGR16_565 0x10 | |
94 | #define DATA_TYPE_ABGR_1555 0x11 | |
95 | #define DATA_TYPE_ABGR_4444 0x12 | |
96 | #define DATA_TYPE_BGRA_5551 0x13 | |
97 | #define DATA_TYPE_BGRA_4444 0x14 | |
98 | #define DATA_TYPE_ABGR24_6666 0x15 | |
99 | #define DATA_TYPE_BGR24_888 0x16 | |
100 | #define DATA_TYPE_ABGR32_8888 0x17 | |
101 | #define DATA_TYPE_BGRA24_6666 0x18 | |
102 | #define DATA_TYPE_BGRA32_8888 0x19 | |
103 | ||
104 | #define DATA_TYPE_MV 0x3 | |
105 | ||
106 | /* VPDMA channel numbers(only VPE channels for now) */ | |
107 | #define VPE_CHAN_NUM_LUMA1_IN 0 | |
108 | #define VPE_CHAN_NUM_CHROMA1_IN 1 | |
109 | #define VPE_CHAN_NUM_LUMA2_IN 2 | |
110 | #define VPE_CHAN_NUM_CHROMA2_IN 3 | |
111 | #define VPE_CHAN_NUM_LUMA3_IN 4 | |
112 | #define VPE_CHAN_NUM_CHROMA3_IN 5 | |
113 | #define VPE_CHAN_NUM_MV_IN 12 | |
114 | #define VPE_CHAN_NUM_MV_OUT 15 | |
115 | #define VPE_CHAN_NUM_LUMA_OUT 102 | |
116 | #define VPE_CHAN_NUM_CHROMA_OUT 103 | |
117 | #define VPE_CHAN_NUM_RGB_OUT 106 | |
118 | ||
213b8ee4 AT |
119 | /* |
120 | * a VPDMA address data block payload for a configuration descriptor needs to | |
121 | * have each sub block length as a multiple of 16 bytes. Therefore, the overall | |
122 | * size of the payload also needs to be a multiple of 16 bytes. The sub block | |
123 | * lengths should be ensured to be aligned by the VPDMA user. | |
124 | */ | |
125 | #define VPDMA_ADB_SIZE_ALIGN 0x0f | |
126 | ||
127 | /* | |
128 | * data transfer descriptor | |
129 | */ | |
130 | struct vpdma_dtd { | |
131 | u32 type_ctl_stride; | |
132 | union { | |
133 | u32 xfer_length_height; | |
134 | u32 w1; | |
135 | }; | |
136 | dma_addr_t start_addr; | |
137 | u32 pkt_ctl; | |
138 | union { | |
139 | u32 frame_width_height; /* inbound */ | |
140 | dma_addr_t desc_write_addr; /* outbound */ | |
141 | }; | |
142 | union { | |
143 | u32 start_h_v; /* inbound */ | |
144 | u32 max_width_height; /* outbound */ | |
145 | }; | |
146 | u32 client_attr0; | |
147 | u32 client_attr1; | |
148 | }; | |
149 | ||
150 | /* Data Transfer Descriptor specifics */ | |
151 | #define DTD_NO_NOTIFY 0 | |
152 | #define DTD_NOTIFY 1 | |
153 | ||
154 | #define DTD_PKT_TYPE 0xa | |
155 | #define DTD_DIR_IN 0 | |
156 | #define DTD_DIR_OUT 1 | |
157 | ||
158 | /* type_ctl_stride */ | |
159 | #define DTD_DATA_TYPE_MASK 0x3f | |
160 | #define DTD_DATA_TYPE_SHFT 26 | |
161 | #define DTD_NOTIFY_MASK 0x01 | |
162 | #define DTD_NOTIFY_SHFT 25 | |
163 | #define DTD_FIELD_MASK 0x01 | |
164 | #define DTD_FIELD_SHFT 24 | |
165 | #define DTD_1D_MASK 0x01 | |
166 | #define DTD_1D_SHFT 23 | |
167 | #define DTD_EVEN_LINE_SKIP_MASK 0x01 | |
168 | #define DTD_EVEN_LINE_SKIP_SHFT 20 | |
169 | #define DTD_ODD_LINE_SKIP_MASK 0x01 | |
170 | #define DTD_ODD_LINE_SKIP_SHFT 16 | |
171 | #define DTD_LINE_STRIDE_MASK 0xffff | |
172 | #define DTD_LINE_STRIDE_SHFT 0 | |
173 | ||
174 | /* xfer_length_height */ | |
175 | #define DTD_LINE_LENGTH_MASK 0xffff | |
176 | #define DTD_LINE_LENGTH_SHFT 16 | |
177 | #define DTD_XFER_HEIGHT_MASK 0xffff | |
178 | #define DTD_XFER_HEIGHT_SHFT 0 | |
179 | ||
180 | /* pkt_ctl */ | |
181 | #define DTD_PKT_TYPE_MASK 0x1f | |
182 | #define DTD_PKT_TYPE_SHFT 27 | |
183 | #define DTD_MODE_MASK 0x01 | |
184 | #define DTD_MODE_SHFT 26 | |
185 | #define DTD_DIR_MASK 0x01 | |
186 | #define DTD_DIR_SHFT 25 | |
187 | #define DTD_CHAN_MASK 0x01ff | |
188 | #define DTD_CHAN_SHFT 16 | |
189 | #define DTD_PRI_MASK 0x0f | |
190 | #define DTD_PRI_SHFT 9 | |
191 | #define DTD_NEXT_CHAN_MASK 0x01ff | |
192 | #define DTD_NEXT_CHAN_SHFT 0 | |
193 | ||
194 | /* frame_width_height */ | |
195 | #define DTD_FRAME_WIDTH_MASK 0xffff | |
196 | #define DTD_FRAME_WIDTH_SHFT 16 | |
197 | #define DTD_FRAME_HEIGHT_MASK 0xffff | |
198 | #define DTD_FRAME_HEIGHT_SHFT 0 | |
199 | ||
200 | /* start_h_v */ | |
201 | #define DTD_H_START_MASK 0xffff | |
202 | #define DTD_H_START_SHFT 16 | |
203 | #define DTD_V_START_MASK 0xffff | |
204 | #define DTD_V_START_SHFT 0 | |
205 | ||
206 | #define DTD_DESC_START_SHIFT 5 | |
207 | #define DTD_WRITE_DESC_MASK 0x01 | |
208 | #define DTD_WRITE_DESC_SHIFT 2 | |
209 | #define DTD_DROP_DATA_MASK 0x01 | |
210 | #define DTD_DROP_DATA_SHIFT 1 | |
211 | #define DTD_USE_DESC_MASK 0x01 | |
212 | #define DTD_USE_DESC_SHIFT 0 | |
213 | ||
214 | /* max_width_height */ | |
215 | #define DTD_MAX_WIDTH_MASK 0x07 | |
216 | #define DTD_MAX_WIDTH_SHFT 4 | |
217 | #define DTD_MAX_HEIGHT_MASK 0x07 | |
218 | #define DTD_MAX_HEIGHT_SHFT 0 | |
219 | ||
220 | /* max width configurations */ | |
221 | /* unlimited width */ | |
222 | #define MAX_OUT_WIDTH_UNLIMITED 0 | |
223 | /* as specified in max_size1 reg */ | |
224 | #define MAX_OUT_WIDTH_REG1 1 | |
225 | /* as specified in max_size2 reg */ | |
226 | #define MAX_OUT_WIDTH_REG2 2 | |
227 | /* as specified in max_size3 reg */ | |
228 | #define MAX_OUT_WIDTH_REG3 3 | |
229 | /* maximum of 352 pixels as width */ | |
230 | #define MAX_OUT_WIDTH_352 4 | |
231 | /* maximum of 768 pixels as width */ | |
232 | #define MAX_OUT_WIDTH_768 5 | |
233 | /* maximum of 1280 pixels width */ | |
234 | #define MAX_OUT_WIDTH_1280 6 | |
235 | /* maximum of 1920 pixels as width */ | |
236 | #define MAX_OUT_WIDTH_1920 7 | |
237 | ||
238 | /* max height configurations */ | |
239 | /* unlimited height */ | |
240 | #define MAX_OUT_HEIGHT_UNLIMITED 0 | |
241 | /* as specified in max_size1 reg */ | |
242 | #define MAX_OUT_HEIGHT_REG1 1 | |
243 | /* as specified in max_size2 reg */ | |
244 | #define MAX_OUT_HEIGHT_REG2 2 | |
245 | /* as specified in max_size3 reg */ | |
246 | #define MAX_OUT_HEIGHT_REG3 3 | |
247 | /* maximum of 288 lines as height */ | |
248 | #define MAX_OUT_HEIGHT_288 4 | |
249 | /* maximum of 576 lines as height */ | |
250 | #define MAX_OUT_HEIGHT_576 5 | |
251 | /* maximum of 720 lines as height */ | |
252 | #define MAX_OUT_HEIGHT_720 6 | |
253 | /* maximum of 1080 lines as height */ | |
254 | #define MAX_OUT_HEIGHT_1080 7 | |
255 | ||
256 | static inline u32 dtd_type_ctl_stride(int type, bool notify, int field, | |
257 | bool one_d, bool even_line_skip, bool odd_line_skip, | |
258 | int line_stride) | |
259 | { | |
260 | return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) | | |
261 | (field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) | | |
262 | (even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) | | |
263 | (odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) | | |
264 | line_stride; | |
265 | } | |
266 | ||
267 | static inline u32 dtd_xfer_length_height(int line_length, int xfer_height) | |
268 | { | |
269 | return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height; | |
270 | } | |
271 | ||
272 | static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri, | |
273 | int next_chan) | |
274 | { | |
275 | return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) | | |
276 | (dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) | | |
277 | (pri << DTD_PRI_SHFT) | next_chan; | |
278 | } | |
279 | ||
280 | static inline u32 dtd_frame_width_height(int width, int height) | |
281 | { | |
282 | return (width << DTD_FRAME_WIDTH_SHFT) | height; | |
283 | } | |
284 | ||
285 | static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc, | |
286 | bool drop_data, bool use_desc) | |
287 | { | |
288 | return (addr << DTD_DESC_START_SHIFT) | | |
289 | (write_desc << DTD_WRITE_DESC_SHIFT) | | |
290 | (drop_data << DTD_DROP_DATA_SHIFT) | | |
291 | use_desc; | |
292 | } | |
293 | ||
294 | static inline u32 dtd_start_h_v(int h_start, int v_start) | |
295 | { | |
296 | return (h_start << DTD_H_START_SHFT) | v_start; | |
297 | } | |
298 | ||
299 | static inline u32 dtd_max_width_height(int max_width, int max_height) | |
300 | { | |
301 | return (max_width << DTD_MAX_WIDTH_SHFT) | max_height; | |
302 | } | |
303 | ||
304 | static inline int dtd_get_data_type(struct vpdma_dtd *dtd) | |
305 | { | |
306 | return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT; | |
307 | } | |
308 | ||
309 | static inline bool dtd_get_notify(struct vpdma_dtd *dtd) | |
310 | { | |
311 | return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK; | |
312 | } | |
313 | ||
314 | static inline int dtd_get_field(struct vpdma_dtd *dtd) | |
315 | { | |
316 | return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK; | |
317 | } | |
318 | ||
319 | static inline bool dtd_get_1d(struct vpdma_dtd *dtd) | |
320 | { | |
321 | return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK; | |
322 | } | |
323 | ||
324 | static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd) | |
325 | { | |
326 | return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT) | |
327 | & DTD_EVEN_LINE_SKIP_MASK; | |
328 | } | |
329 | ||
330 | static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd) | |
331 | { | |
332 | return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT) | |
333 | & DTD_ODD_LINE_SKIP_MASK; | |
334 | } | |
335 | ||
336 | static inline int dtd_get_line_stride(struct vpdma_dtd *dtd) | |
337 | { | |
338 | return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK; | |
339 | } | |
340 | ||
341 | static inline int dtd_get_line_length(struct vpdma_dtd *dtd) | |
342 | { | |
343 | return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT; | |
344 | } | |
345 | ||
346 | static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd) | |
347 | { | |
348 | return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK; | |
349 | } | |
350 | ||
351 | static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd) | |
352 | { | |
353 | return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT; | |
354 | } | |
355 | ||
356 | static inline bool dtd_get_mode(struct vpdma_dtd *dtd) | |
357 | { | |
358 | return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK; | |
359 | } | |
360 | ||
361 | static inline bool dtd_get_dir(struct vpdma_dtd *dtd) | |
362 | { | |
363 | return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK; | |
364 | } | |
365 | ||
366 | static inline int dtd_get_chan(struct vpdma_dtd *dtd) | |
367 | { | |
368 | return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK; | |
369 | } | |
370 | ||
371 | static inline int dtd_get_priority(struct vpdma_dtd *dtd) | |
372 | { | |
373 | return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK; | |
374 | } | |
375 | ||
376 | static inline int dtd_get_next_chan(struct vpdma_dtd *dtd) | |
377 | { | |
378 | return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK; | |
379 | } | |
380 | ||
381 | static inline int dtd_get_frame_width(struct vpdma_dtd *dtd) | |
382 | { | |
383 | return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT; | |
384 | } | |
385 | ||
386 | static inline int dtd_get_frame_height(struct vpdma_dtd *dtd) | |
387 | { | |
388 | return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK; | |
389 | } | |
390 | ||
391 | static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd) | |
392 | { | |
393 | return dtd->desc_write_addr >> DTD_DESC_START_SHIFT; | |
394 | } | |
395 | ||
396 | static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd) | |
397 | { | |
398 | return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) & | |
399 | DTD_WRITE_DESC_MASK; | |
400 | } | |
401 | ||
402 | static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd) | |
403 | { | |
404 | return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) & | |
405 | DTD_DROP_DATA_MASK; | |
406 | } | |
407 | ||
408 | static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd) | |
409 | { | |
410 | return dtd->desc_write_addr & DTD_USE_DESC_MASK; | |
411 | } | |
412 | ||
413 | static inline int dtd_get_h_start(struct vpdma_dtd *dtd) | |
414 | { | |
415 | return dtd->start_h_v >> DTD_H_START_SHFT; | |
416 | } | |
417 | ||
418 | static inline int dtd_get_v_start(struct vpdma_dtd *dtd) | |
419 | { | |
420 | return dtd->start_h_v & DTD_V_START_MASK; | |
421 | } | |
422 | ||
423 | static inline int dtd_get_max_width(struct vpdma_dtd *dtd) | |
424 | { | |
425 | return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) & | |
426 | DTD_MAX_WIDTH_MASK; | |
427 | } | |
428 | ||
429 | static inline int dtd_get_max_height(struct vpdma_dtd *dtd) | |
430 | { | |
431 | return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) & | |
432 | DTD_MAX_HEIGHT_MASK; | |
433 | } | |
434 | ||
435 | /* | |
436 | * configuration descriptor | |
437 | */ | |
438 | struct vpdma_cfd { | |
439 | union { | |
440 | u32 dest_addr_offset; | |
441 | u32 w0; | |
442 | }; | |
443 | union { | |
444 | u32 block_len; /* in words */ | |
445 | u32 w1; | |
446 | }; | |
447 | u32 payload_addr; | |
448 | u32 ctl_payload_len; /* in words */ | |
449 | }; | |
450 | ||
451 | /* Configuration descriptor specifics */ | |
452 | ||
453 | #define CFD_PKT_TYPE 0xb | |
454 | ||
455 | #define CFD_DIRECT 1 | |
456 | #define CFD_INDIRECT 0 | |
457 | #define CFD_CLS_ADB 0 | |
458 | #define CFD_CLS_BLOCK 1 | |
459 | ||
460 | /* block_len */ | |
461 | #define CFD__BLOCK_LEN_MASK 0xffff | |
462 | #define CFD__BLOCK_LEN_SHFT 0 | |
463 | ||
464 | /* ctl_payload_len */ | |
465 | #define CFD_PKT_TYPE_MASK 0x1f | |
466 | #define CFD_PKT_TYPE_SHFT 27 | |
467 | #define CFD_DIRECT_MASK 0x01 | |
468 | #define CFD_DIRECT_SHFT 26 | |
469 | #define CFD_CLASS_MASK 0x03 | |
470 | #define CFD_CLASS_SHFT 24 | |
471 | #define CFD_DEST_MASK 0xff | |
472 | #define CFD_DEST_SHFT 16 | |
473 | #define CFD_PAYLOAD_LEN_MASK 0xffff | |
474 | #define CFD_PAYLOAD_LEN_SHFT 0 | |
475 | ||
476 | static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest, | |
477 | int payload_len) | |
478 | { | |
479 | return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) | | |
480 | (direct << CFD_DIRECT_SHFT) | | |
481 | (cls << CFD_CLASS_SHFT) | | |
482 | (dest << CFD_DEST_SHFT) | | |
483 | payload_len; | |
484 | } | |
485 | ||
486 | static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd) | |
487 | { | |
488 | return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT; | |
489 | } | |
490 | ||
491 | static inline bool cfd_get_direct(struct vpdma_cfd *cfd) | |
492 | { | |
493 | return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK; | |
494 | } | |
495 | ||
496 | static inline bool cfd_get_class(struct vpdma_cfd *cfd) | |
497 | { | |
498 | return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK; | |
499 | } | |
500 | ||
501 | static inline int cfd_get_dest(struct vpdma_cfd *cfd) | |
502 | { | |
503 | return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK; | |
504 | } | |
505 | ||
506 | static inline int cfd_get_payload_len(struct vpdma_cfd *cfd) | |
507 | { | |
508 | return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK; | |
509 | } | |
510 | ||
511 | /* | |
512 | * control descriptor | |
513 | */ | |
514 | struct vpdma_ctd { | |
515 | union { | |
516 | u32 timer_value; | |
517 | u32 list_addr; | |
518 | u32 w0; | |
519 | }; | |
520 | union { | |
521 | u32 pixel_line_count; | |
522 | u32 list_size; | |
523 | u32 w1; | |
524 | }; | |
525 | union { | |
526 | u32 event; | |
527 | u32 fid_ctl; | |
528 | u32 w2; | |
529 | }; | |
530 | u32 type_source_ctl; | |
531 | }; | |
532 | ||
533 | /* control descriptor types */ | |
534 | #define CTD_TYPE_SYNC_ON_CLIENT 0 | |
535 | #define CTD_TYPE_SYNC_ON_LIST 1 | |
536 | #define CTD_TYPE_SYNC_ON_EXT 2 | |
537 | #define CTD_TYPE_SYNC_ON_LM_TIMER 3 | |
538 | #define CTD_TYPE_SYNC_ON_CHANNEL 4 | |
539 | #define CTD_TYPE_CHNG_CLIENT_IRQ 5 | |
540 | #define CTD_TYPE_SEND_IRQ 6 | |
541 | #define CTD_TYPE_RELOAD_LIST 7 | |
542 | #define CTD_TYPE_ABORT_CHANNEL 8 | |
543 | ||
544 | #define CTD_PKT_TYPE 0xc | |
545 | ||
546 | /* timer_value */ | |
547 | #define CTD_TIMER_VALUE_MASK 0xffff | |
548 | #define CTD_TIMER_VALUE_SHFT 0 | |
549 | ||
550 | /* pixel_line_count */ | |
551 | #define CTD_PIXEL_COUNT_MASK 0xffff | |
552 | #define CTD_PIXEL_COUNT_SHFT 16 | |
553 | #define CTD_LINE_COUNT_MASK 0xffff | |
554 | #define CTD_LINE_COUNT_SHFT 0 | |
555 | ||
556 | /* list_size */ | |
557 | #define CTD_LIST_SIZE_MASK 0xffff | |
558 | #define CTD_LIST_SIZE_SHFT 0 | |
559 | ||
560 | /* event */ | |
561 | #define CTD_EVENT_MASK 0x0f | |
562 | #define CTD_EVENT_SHFT 0 | |
563 | ||
564 | /* fid_ctl */ | |
565 | #define CTD_FID2_MASK 0x03 | |
566 | #define CTD_FID2_SHFT 4 | |
567 | #define CTD_FID1_MASK 0x03 | |
568 | #define CTD_FID1_SHFT 2 | |
569 | #define CTD_FID0_MASK 0x03 | |
570 | #define CTD_FID0_SHFT 0 | |
571 | ||
572 | /* type_source_ctl */ | |
573 | #define CTD_PKT_TYPE_MASK 0x1f | |
574 | #define CTD_PKT_TYPE_SHFT 27 | |
575 | #define CTD_SOURCE_MASK 0xff | |
576 | #define CTD_SOURCE_SHFT 16 | |
577 | #define CTD_CONTROL_MASK 0x0f | |
578 | #define CTD_CONTROL_SHFT 0 | |
579 | ||
580 | static inline u32 ctd_pixel_line_count(int pixel_count, int line_count) | |
581 | { | |
582 | return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count; | |
583 | } | |
584 | ||
585 | static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2) | |
586 | { | |
587 | return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0; | |
588 | } | |
589 | ||
590 | static inline u32 ctd_type_source_ctl(int source, int control) | |
591 | { | |
592 | return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) | | |
593 | (source << CTD_SOURCE_SHFT) | control; | |
594 | } | |
595 | ||
596 | static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd) | |
597 | { | |
598 | return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT; | |
599 | } | |
600 | ||
601 | static inline int ctd_get_line_count(struct vpdma_ctd *ctd) | |
602 | { | |
603 | return ctd->pixel_line_count & CTD_LINE_COUNT_MASK; | |
604 | } | |
605 | ||
606 | static inline int ctd_get_event(struct vpdma_ctd *ctd) | |
607 | { | |
608 | return ctd->event & CTD_EVENT_MASK; | |
609 | } | |
610 | ||
611 | static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd) | |
612 | { | |
613 | return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK; | |
614 | } | |
615 | ||
616 | static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd) | |
617 | { | |
618 | return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK; | |
619 | } | |
620 | ||
621 | static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd) | |
622 | { | |
623 | return ctd->fid_ctl & CTD_FID2_MASK; | |
624 | } | |
625 | ||
626 | static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd) | |
627 | { | |
628 | return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT; | |
629 | } | |
630 | ||
631 | static inline int ctd_get_source(struct vpdma_ctd *ctd) | |
632 | { | |
633 | return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK; | |
634 | } | |
635 | ||
636 | static inline int ctd_get_ctl(struct vpdma_ctd *ctd) | |
637 | { | |
638 | return ctd->type_source_ctl & CTD_CONTROL_MASK; | |
639 | } | |
640 | ||
9262e5a2 | 641 | #endif |