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45719127 AT |
1 | /* |
2 | * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver | |
3 | * | |
4 | * Copyright (c) 2013 Texas Instruments Inc. | |
5 | * David Griego, <dagriego@biglakesoftware.com> | |
6 | * Dale Farnsworth, <dale@farnsworth.org> | |
7 | * Archit Taneja, <archit@ti.com> | |
8 | * | |
9 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | |
10 | * Pawel Osciak, <pawel@osciak.com> | |
11 | * Marek Szyprowski, <m.szyprowski@samsung.com> | |
12 | * | |
13 | * Based on the virtual v4l2-mem2mem example device | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License version 2 as published by | |
17 | * the Free Software Foundation | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/ioctl.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/videodev2.h> | |
a51cd8f5 | 33 | #include <linux/log2.h> |
45719127 AT |
34 | |
35 | #include <media/v4l2-common.h> | |
36 | #include <media/v4l2-ctrls.h> | |
37 | #include <media/v4l2-device.h> | |
38 | #include <media/v4l2-event.h> | |
39 | #include <media/v4l2-ioctl.h> | |
40 | #include <media/v4l2-mem2mem.h> | |
41 | #include <media/videobuf2-core.h> | |
42 | #include <media/videobuf2-dma-contig.h> | |
43 | ||
44 | #include "vpdma.h" | |
45 | #include "vpe_regs.h" | |
44687b2e | 46 | #include "sc.h" |
6948082d | 47 | #include "csc.h" |
45719127 AT |
48 | |
49 | #define VPE_MODULE_NAME "vpe" | |
50 | ||
51 | /* minimum and maximum frame sizes */ | |
52 | #define MIN_W 128 | |
53 | #define MIN_H 128 | |
54 | #define MAX_W 1920 | |
55 | #define MAX_H 1080 | |
56 | ||
57 | /* required alignments */ | |
58 | #define S_ALIGN 0 /* multiple of 1 */ | |
59 | #define H_ALIGN 1 /* multiple of 2 */ | |
45719127 AT |
60 | |
61 | /* flags that indicate a format can be used for capture/output */ | |
62 | #define VPE_FMT_TYPE_CAPTURE (1 << 0) | |
63 | #define VPE_FMT_TYPE_OUTPUT (1 << 1) | |
64 | ||
65 | /* used as plane indices */ | |
66 | #define VPE_MAX_PLANES 2 | |
67 | #define VPE_LUMA 0 | |
68 | #define VPE_CHROMA 1 | |
69 | ||
70 | /* per m2m context info */ | |
585e6f01 AT |
71 | #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */ |
72 | ||
45719127 AT |
73 | #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */ |
74 | ||
75 | /* | |
76 | * each VPE context can need up to 3 config desciptors, 7 input descriptors, | |
77 | * 3 output descriptors, and 10 control descriptors | |
78 | */ | |
79 | #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \ | |
80 | 13 * VPDMA_CFD_CTD_DESC_SIZE) | |
81 | ||
82 | #define vpe_dbg(vpedev, fmt, arg...) \ | |
83 | dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg) | |
84 | #define vpe_err(vpedev, fmt, arg...) \ | |
85 | dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg) | |
86 | ||
87 | struct vpe_us_coeffs { | |
88 | unsigned short anchor_fid0_c0; | |
89 | unsigned short anchor_fid0_c1; | |
90 | unsigned short anchor_fid0_c2; | |
91 | unsigned short anchor_fid0_c3; | |
92 | unsigned short interp_fid0_c0; | |
93 | unsigned short interp_fid0_c1; | |
94 | unsigned short interp_fid0_c2; | |
95 | unsigned short interp_fid0_c3; | |
96 | unsigned short anchor_fid1_c0; | |
97 | unsigned short anchor_fid1_c1; | |
98 | unsigned short anchor_fid1_c2; | |
99 | unsigned short anchor_fid1_c3; | |
100 | unsigned short interp_fid1_c0; | |
101 | unsigned short interp_fid1_c1; | |
102 | unsigned short interp_fid1_c2; | |
103 | unsigned short interp_fid1_c3; | |
104 | }; | |
105 | ||
106 | /* | |
107 | * Default upsampler coefficients | |
108 | */ | |
109 | static const struct vpe_us_coeffs us_coeffs[] = { | |
110 | { | |
111 | /* Coefficients for progressive input */ | |
112 | 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8, | |
113 | 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8, | |
114 | }, | |
585e6f01 AT |
115 | { |
116 | /* Coefficients for Top Field Interlaced input */ | |
117 | 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3, | |
118 | /* Coefficients for Bottom Field Interlaced input */ | |
119 | 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9, | |
120 | }, | |
121 | }; | |
122 | ||
123 | /* | |
124 | * the following registers are for configuring some of the parameters of the | |
125 | * motion and edge detection blocks inside DEI, these generally remain the same, | |
126 | * these could be passed later via userspace if some one needs to tweak these. | |
127 | */ | |
128 | struct vpe_dei_regs { | |
129 | unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */ | |
130 | unsigned long edi_config_reg; /* VPE_DEI_REG3 */ | |
131 | unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */ | |
132 | unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */ | |
133 | unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */ | |
134 | unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */ | |
135 | }; | |
136 | ||
137 | /* | |
138 | * default expert DEI register values, unlikely to be modified. | |
139 | */ | |
140 | static const struct vpe_dei_regs dei_regs = { | |
141 | 0x020C0804u, | |
142 | 0x0118100Fu, | |
143 | 0x08040200u, | |
144 | 0x1010100Cu, | |
145 | 0x10101010u, | |
146 | 0x10101010u, | |
45719127 AT |
147 | }; |
148 | ||
149 | /* | |
150 | * The port_data structure contains per-port data. | |
151 | */ | |
152 | struct vpe_port_data { | |
153 | enum vpdma_channel channel; /* VPDMA channel */ | |
585e6f01 | 154 | u8 vb_index; /* input frame f, f-1, f-2 index */ |
45719127 AT |
155 | u8 vb_part; /* plane index for co-panar formats */ |
156 | }; | |
157 | ||
158 | /* | |
159 | * Define indices into the port_data tables | |
160 | */ | |
161 | #define VPE_PORT_LUMA1_IN 0 | |
162 | #define VPE_PORT_CHROMA1_IN 1 | |
585e6f01 AT |
163 | #define VPE_PORT_LUMA2_IN 2 |
164 | #define VPE_PORT_CHROMA2_IN 3 | |
165 | #define VPE_PORT_LUMA3_IN 4 | |
166 | #define VPE_PORT_CHROMA3_IN 5 | |
167 | #define VPE_PORT_MV_IN 6 | |
168 | #define VPE_PORT_MV_OUT 7 | |
45719127 AT |
169 | #define VPE_PORT_LUMA_OUT 8 |
170 | #define VPE_PORT_CHROMA_OUT 9 | |
171 | #define VPE_PORT_RGB_OUT 10 | |
172 | ||
173 | static const struct vpe_port_data port_data[11] = { | |
174 | [VPE_PORT_LUMA1_IN] = { | |
175 | .channel = VPE_CHAN_LUMA1_IN, | |
585e6f01 | 176 | .vb_index = 0, |
45719127 AT |
177 | .vb_part = VPE_LUMA, |
178 | }, | |
179 | [VPE_PORT_CHROMA1_IN] = { | |
180 | .channel = VPE_CHAN_CHROMA1_IN, | |
585e6f01 AT |
181 | .vb_index = 0, |
182 | .vb_part = VPE_CHROMA, | |
183 | }, | |
184 | [VPE_PORT_LUMA2_IN] = { | |
185 | .channel = VPE_CHAN_LUMA2_IN, | |
186 | .vb_index = 1, | |
187 | .vb_part = VPE_LUMA, | |
188 | }, | |
189 | [VPE_PORT_CHROMA2_IN] = { | |
190 | .channel = VPE_CHAN_CHROMA2_IN, | |
191 | .vb_index = 1, | |
192 | .vb_part = VPE_CHROMA, | |
193 | }, | |
194 | [VPE_PORT_LUMA3_IN] = { | |
195 | .channel = VPE_CHAN_LUMA3_IN, | |
196 | .vb_index = 2, | |
197 | .vb_part = VPE_LUMA, | |
198 | }, | |
199 | [VPE_PORT_CHROMA3_IN] = { | |
200 | .channel = VPE_CHAN_CHROMA3_IN, | |
201 | .vb_index = 2, | |
45719127 AT |
202 | .vb_part = VPE_CHROMA, |
203 | }, | |
585e6f01 AT |
204 | [VPE_PORT_MV_IN] = { |
205 | .channel = VPE_CHAN_MV_IN, | |
206 | }, | |
207 | [VPE_PORT_MV_OUT] = { | |
208 | .channel = VPE_CHAN_MV_OUT, | |
209 | }, | |
45719127 AT |
210 | [VPE_PORT_LUMA_OUT] = { |
211 | .channel = VPE_CHAN_LUMA_OUT, | |
212 | .vb_part = VPE_LUMA, | |
213 | }, | |
214 | [VPE_PORT_CHROMA_OUT] = { | |
215 | .channel = VPE_CHAN_CHROMA_OUT, | |
216 | .vb_part = VPE_CHROMA, | |
217 | }, | |
218 | [VPE_PORT_RGB_OUT] = { | |
219 | .channel = VPE_CHAN_RGB_OUT, | |
220 | .vb_part = VPE_LUMA, | |
221 | }, | |
222 | }; | |
223 | ||
224 | ||
225 | /* driver info for each of the supported video formats */ | |
226 | struct vpe_fmt { | |
227 | char *name; /* human-readable name */ | |
228 | u32 fourcc; /* standard format identifier */ | |
229 | u8 types; /* CAPTURE and/or OUTPUT */ | |
230 | u8 coplanar; /* set for unpacked Luma and Chroma */ | |
231 | /* vpdma format info for each plane */ | |
232 | struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES]; | |
233 | }; | |
234 | ||
235 | static struct vpe_fmt vpe_formats[] = { | |
236 | { | |
237 | .name = "YUV 422 co-planar", | |
238 | .fourcc = V4L2_PIX_FMT_NV16, | |
239 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
240 | .coplanar = 1, | |
241 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444], | |
242 | &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444], | |
243 | }, | |
244 | }, | |
245 | { | |
246 | .name = "YUV 420 co-planar", | |
247 | .fourcc = V4L2_PIX_FMT_NV12, | |
248 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
249 | .coplanar = 1, | |
250 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420], | |
251 | &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420], | |
252 | }, | |
253 | }, | |
254 | { | |
255 | .name = "YUYV 422 packed", | |
256 | .fourcc = V4L2_PIX_FMT_YUYV, | |
257 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
258 | .coplanar = 0, | |
259 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422], | |
260 | }, | |
261 | }, | |
262 | { | |
263 | .name = "UYVY 422 packed", | |
264 | .fourcc = V4L2_PIX_FMT_UYVY, | |
265 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
266 | .coplanar = 0, | |
267 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422], | |
268 | }, | |
269 | }, | |
30496799 AT |
270 | { |
271 | .name = "RGB888 packed", | |
272 | .fourcc = V4L2_PIX_FMT_RGB24, | |
273 | .types = VPE_FMT_TYPE_CAPTURE, | |
274 | .coplanar = 0, | |
275 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24], | |
276 | }, | |
277 | }, | |
278 | { | |
279 | .name = "ARGB32", | |
280 | .fourcc = V4L2_PIX_FMT_RGB32, | |
281 | .types = VPE_FMT_TYPE_CAPTURE, | |
282 | .coplanar = 0, | |
283 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32], | |
284 | }, | |
285 | }, | |
286 | { | |
287 | .name = "BGR888 packed", | |
288 | .fourcc = V4L2_PIX_FMT_BGR24, | |
289 | .types = VPE_FMT_TYPE_CAPTURE, | |
290 | .coplanar = 0, | |
291 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24], | |
292 | }, | |
293 | }, | |
294 | { | |
295 | .name = "ABGR32", | |
296 | .fourcc = V4L2_PIX_FMT_BGR32, | |
297 | .types = VPE_FMT_TYPE_CAPTURE, | |
298 | .coplanar = 0, | |
299 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32], | |
300 | }, | |
301 | }, | |
45719127 AT |
302 | }; |
303 | ||
304 | /* | |
305 | * per-queue, driver-specific private data. | |
306 | * there is one source queue and one destination queue for each m2m context. | |
307 | */ | |
308 | struct vpe_q_data { | |
309 | unsigned int width; /* frame width */ | |
310 | unsigned int height; /* frame height */ | |
311 | unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */ | |
312 | enum v4l2_colorspace colorspace; | |
585e6f01 | 313 | enum v4l2_field field; /* supported field value */ |
45719127 AT |
314 | unsigned int flags; |
315 | unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */ | |
316 | struct v4l2_rect c_rect; /* crop/compose rectangle */ | |
317 | struct vpe_fmt *fmt; /* format info */ | |
318 | }; | |
319 | ||
320 | /* vpe_q_data flag bits */ | |
321 | #define Q_DATA_FRAME_1D (1 << 0) | |
322 | #define Q_DATA_MODE_TILED (1 << 1) | |
585e6f01 | 323 | #define Q_DATA_INTERLACED (1 << 2) |
45719127 AT |
324 | |
325 | enum { | |
326 | Q_DATA_SRC = 0, | |
327 | Q_DATA_DST = 1, | |
328 | }; | |
329 | ||
330 | /* find our format description corresponding to the passed v4l2_format */ | |
331 | static struct vpe_fmt *find_format(struct v4l2_format *f) | |
332 | { | |
333 | struct vpe_fmt *fmt; | |
334 | unsigned int k; | |
335 | ||
336 | for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) { | |
337 | fmt = &vpe_formats[k]; | |
338 | if (fmt->fourcc == f->fmt.pix.pixelformat) | |
339 | return fmt; | |
340 | } | |
341 | ||
342 | return NULL; | |
343 | } | |
344 | ||
345 | /* | |
346 | * there is one vpe_dev structure in the driver, it is shared by | |
347 | * all instances. | |
348 | */ | |
349 | struct vpe_dev { | |
350 | struct v4l2_device v4l2_dev; | |
351 | struct video_device vfd; | |
352 | struct v4l2_m2m_dev *m2m_dev; | |
353 | ||
354 | atomic_t num_instances; /* count of driver instances */ | |
355 | dma_addr_t loaded_mmrs; /* shadow mmrs in device */ | |
356 | struct mutex dev_mutex; | |
357 | spinlock_t lock; | |
358 | ||
359 | int irq; | |
360 | void __iomem *base; | |
44687b2e | 361 | struct resource *res; |
45719127 AT |
362 | |
363 | struct vb2_alloc_ctx *alloc_ctx; | |
364 | struct vpdma_data *vpdma; /* vpdma data handle */ | |
44687b2e | 365 | struct sc_data *sc; /* scaler data handle */ |
6948082d | 366 | struct csc_data *csc; /* csc data handle */ |
45719127 AT |
367 | }; |
368 | ||
369 | /* | |
370 | * There is one vpe_ctx structure for each m2m context. | |
371 | */ | |
372 | struct vpe_ctx { | |
373 | struct v4l2_fh fh; | |
374 | struct vpe_dev *dev; | |
375 | struct v4l2_m2m_ctx *m2m_ctx; | |
376 | struct v4l2_ctrl_handler hdl; | |
377 | ||
585e6f01 | 378 | unsigned int field; /* current field */ |
45719127 AT |
379 | unsigned int sequence; /* current frame/field seq */ |
380 | unsigned int aborting; /* abort after next irq */ | |
381 | ||
382 | unsigned int bufs_per_job; /* input buffers per batch */ | |
383 | unsigned int bufs_completed; /* bufs done in this batch */ | |
384 | ||
385 | struct vpe_q_data q_data[2]; /* src & dst queue data */ | |
585e6f01 | 386 | struct vb2_buffer *src_vbs[VPE_MAX_SRC_BUFS]; |
45719127 AT |
387 | struct vb2_buffer *dst_vb; |
388 | ||
585e6f01 AT |
389 | dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */ |
390 | void *mv_buf[2]; /* virtual addrs of motion vector bufs */ | |
391 | size_t mv_buf_size; /* current motion vector buffer size */ | |
45719127 | 392 | struct vpdma_buf mmr_adb; /* shadow reg addr/data block */ |
773f0657 AT |
393 | struct vpdma_buf sc_coeff_h; /* h coeff buffer */ |
394 | struct vpdma_buf sc_coeff_v; /* v coeff buffer */ | |
45719127 AT |
395 | struct vpdma_desc_list desc_list; /* DMA descriptor list */ |
396 | ||
585e6f01 | 397 | bool deinterlacing; /* using de-interlacer */ |
45719127 | 398 | bool load_mmrs; /* have new shadow reg values */ |
585e6f01 AT |
399 | |
400 | unsigned int src_mv_buf_selector; | |
45719127 AT |
401 | }; |
402 | ||
403 | ||
404 | /* | |
405 | * M2M devices get 2 queues. | |
406 | * Return the queue given the type. | |
407 | */ | |
408 | static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx, | |
409 | enum v4l2_buf_type type) | |
410 | { | |
411 | switch (type) { | |
412 | case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: | |
413 | return &ctx->q_data[Q_DATA_SRC]; | |
414 | case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: | |
415 | return &ctx->q_data[Q_DATA_DST]; | |
416 | default: | |
417 | BUG(); | |
418 | } | |
419 | return NULL; | |
420 | } | |
421 | ||
422 | static u32 read_reg(struct vpe_dev *dev, int offset) | |
423 | { | |
424 | return ioread32(dev->base + offset); | |
425 | } | |
426 | ||
427 | static void write_reg(struct vpe_dev *dev, int offset, u32 value) | |
428 | { | |
429 | iowrite32(value, dev->base + offset); | |
430 | } | |
431 | ||
432 | /* register field read/write helpers */ | |
433 | static int get_field(u32 value, u32 mask, int shift) | |
434 | { | |
435 | return (value & (mask << shift)) >> shift; | |
436 | } | |
437 | ||
438 | static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift) | |
439 | { | |
440 | return get_field(read_reg(dev, offset), mask, shift); | |
441 | } | |
442 | ||
443 | static void write_field(u32 *valp, u32 field, u32 mask, int shift) | |
444 | { | |
445 | u32 val = *valp; | |
446 | ||
447 | val &= ~(mask << shift); | |
448 | val |= (field & mask) << shift; | |
449 | *valp = val; | |
450 | } | |
451 | ||
452 | static void write_field_reg(struct vpe_dev *dev, int offset, u32 field, | |
453 | u32 mask, int shift) | |
454 | { | |
455 | u32 val = read_reg(dev, offset); | |
456 | ||
457 | write_field(&val, field, mask, shift); | |
458 | ||
459 | write_reg(dev, offset, val); | |
460 | } | |
461 | ||
462 | /* | |
463 | * DMA address/data block for the shadow registers | |
464 | */ | |
465 | struct vpe_mmr_adb { | |
466 | struct vpdma_adb_hdr out_fmt_hdr; | |
467 | u32 out_fmt_reg[1]; | |
468 | u32 out_fmt_pad[3]; | |
469 | struct vpdma_adb_hdr us1_hdr; | |
470 | u32 us1_regs[8]; | |
471 | struct vpdma_adb_hdr us2_hdr; | |
472 | u32 us2_regs[8]; | |
473 | struct vpdma_adb_hdr us3_hdr; | |
474 | u32 us3_regs[8]; | |
475 | struct vpdma_adb_hdr dei_hdr; | |
585e6f01 | 476 | u32 dei_regs[8]; |
bbee8b39 AT |
477 | struct vpdma_adb_hdr sc_hdr0; |
478 | u32 sc_regs0[7]; | |
479 | u32 sc_pad0[1]; | |
480 | struct vpdma_adb_hdr sc_hdr8; | |
481 | u32 sc_regs8[6]; | |
482 | u32 sc_pad8[2]; | |
483 | struct vpdma_adb_hdr sc_hdr17; | |
484 | u32 sc_regs17[9]; | |
485 | u32 sc_pad17[3]; | |
45719127 AT |
486 | struct vpdma_adb_hdr csc_hdr; |
487 | u32 csc_regs[6]; | |
488 | u32 csc_pad[2]; | |
489 | }; | |
490 | ||
44687b2e AT |
491 | #define GET_OFFSET_TOP(ctx, obj, reg) \ |
492 | ((obj)->res->start - ctx->dev->res->start + reg) | |
493 | ||
45719127 AT |
494 | #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \ |
495 | VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a) | |
496 | /* | |
497 | * Set the headers for all of the address/data block structures. | |
498 | */ | |
499 | static void init_adb_hdrs(struct vpe_ctx *ctx) | |
500 | { | |
501 | VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT); | |
502 | VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0); | |
503 | VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0); | |
504 | VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0); | |
505 | VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE); | |
bbee8b39 | 506 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0, |
44687b2e | 507 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0)); |
bbee8b39 AT |
508 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8, |
509 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8)); | |
510 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17, | |
511 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17)); | |
6948082d AT |
512 | VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, |
513 | GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00)); | |
45719127 AT |
514 | }; |
515 | ||
585e6f01 AT |
516 | /* |
517 | * Allocate or re-allocate the motion vector DMA buffers | |
518 | * There are two buffers, one for input and one for output. | |
519 | * However, the roles are reversed after each field is processed. | |
520 | * In other words, after each field is processed, the previous | |
521 | * output (dst) MV buffer becomes the new input (src) MV buffer. | |
522 | */ | |
523 | static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size) | |
524 | { | |
525 | struct device *dev = ctx->dev->v4l2_dev.dev; | |
526 | ||
527 | if (ctx->mv_buf_size == size) | |
528 | return 0; | |
529 | ||
530 | if (ctx->mv_buf[0]) | |
531 | dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0], | |
532 | ctx->mv_buf_dma[0]); | |
533 | ||
534 | if (ctx->mv_buf[1]) | |
535 | dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1], | |
536 | ctx->mv_buf_dma[1]); | |
537 | ||
538 | if (size == 0) | |
539 | return 0; | |
540 | ||
541 | ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0], | |
542 | GFP_KERNEL); | |
543 | if (!ctx->mv_buf[0]) { | |
544 | vpe_err(ctx->dev, "failed to allocate motion vector buffer\n"); | |
545 | return -ENOMEM; | |
546 | } | |
547 | ||
548 | ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1], | |
549 | GFP_KERNEL); | |
550 | if (!ctx->mv_buf[1]) { | |
551 | vpe_err(ctx->dev, "failed to allocate motion vector buffer\n"); | |
552 | dma_free_coherent(dev, size, ctx->mv_buf[0], | |
553 | ctx->mv_buf_dma[0]); | |
554 | ||
555 | return -ENOMEM; | |
556 | } | |
557 | ||
558 | ctx->mv_buf_size = size; | |
559 | ctx->src_mv_buf_selector = 0; | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static void free_mv_buffers(struct vpe_ctx *ctx) | |
565 | { | |
566 | realloc_mv_buffers(ctx, 0); | |
567 | } | |
568 | ||
569 | /* | |
570 | * While de-interlacing, we keep the two most recent input buffers | |
571 | * around. This function frees those two buffers when we have | |
572 | * finished processing the current stream. | |
573 | */ | |
574 | static void free_vbs(struct vpe_ctx *ctx) | |
575 | { | |
576 | struct vpe_dev *dev = ctx->dev; | |
577 | unsigned long flags; | |
578 | ||
579 | if (ctx->src_vbs[2] == NULL) | |
580 | return; | |
581 | ||
582 | spin_lock_irqsave(&dev->lock, flags); | |
583 | if (ctx->src_vbs[2]) { | |
584 | v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE); | |
585 | v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE); | |
586 | } | |
587 | spin_unlock_irqrestore(&dev->lock, flags); | |
588 | } | |
589 | ||
45719127 AT |
590 | /* |
591 | * Enable or disable the VPE clocks | |
592 | */ | |
593 | static void vpe_set_clock_enable(struct vpe_dev *dev, bool on) | |
594 | { | |
595 | u32 val = 0; | |
596 | ||
597 | if (on) | |
598 | val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE; | |
599 | write_reg(dev, VPE_CLK_ENABLE, val); | |
600 | } | |
601 | ||
602 | static void vpe_top_reset(struct vpe_dev *dev) | |
603 | { | |
604 | ||
605 | write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK, | |
606 | VPE_DATA_PATH_CLK_RESET_SHIFT); | |
607 | ||
608 | usleep_range(100, 150); | |
609 | ||
610 | write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK, | |
611 | VPE_DATA_PATH_CLK_RESET_SHIFT); | |
612 | } | |
613 | ||
614 | static void vpe_top_vpdma_reset(struct vpe_dev *dev) | |
615 | { | |
616 | write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK, | |
617 | VPE_VPDMA_CLK_RESET_SHIFT); | |
618 | ||
619 | usleep_range(100, 150); | |
620 | ||
621 | write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK, | |
622 | VPE_VPDMA_CLK_RESET_SHIFT); | |
623 | } | |
624 | ||
625 | /* | |
626 | * Load the correct of upsampler coefficients into the shadow MMRs | |
627 | */ | |
628 | static void set_us_coefficients(struct vpe_ctx *ctx) | |
629 | { | |
630 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
585e6f01 | 631 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
45719127 AT |
632 | u32 *us1_reg = &mmr_adb->us1_regs[0]; |
633 | u32 *us2_reg = &mmr_adb->us2_regs[0]; | |
634 | u32 *us3_reg = &mmr_adb->us3_regs[0]; | |
635 | const unsigned short *cp, *end_cp; | |
636 | ||
637 | cp = &us_coeffs[0].anchor_fid0_c0; | |
638 | ||
585e6f01 AT |
639 | if (s_q_data->flags & Q_DATA_INTERLACED) /* interlaced */ |
640 | cp += sizeof(us_coeffs[0]) / sizeof(*cp); | |
641 | ||
45719127 AT |
642 | end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp); |
643 | ||
644 | while (cp < end_cp) { | |
645 | write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT); | |
646 | write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT); | |
647 | *us2_reg++ = *us1_reg; | |
648 | *us3_reg++ = *us1_reg++; | |
649 | } | |
650 | ctx->load_mmrs = true; | |
651 | } | |
652 | ||
653 | /* | |
654 | * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs. | |
655 | */ | |
656 | static void set_cfg_and_line_modes(struct vpe_ctx *ctx) | |
657 | { | |
658 | struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt; | |
659 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
660 | u32 *us1_reg0 = &mmr_adb->us1_regs[0]; | |
661 | u32 *us2_reg0 = &mmr_adb->us2_regs[0]; | |
662 | u32 *us3_reg0 = &mmr_adb->us3_regs[0]; | |
663 | int line_mode = 1; | |
664 | int cfg_mode = 1; | |
665 | ||
666 | /* | |
667 | * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing. | |
668 | * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing. | |
669 | */ | |
670 | ||
671 | if (fmt->fourcc == V4L2_PIX_FMT_NV12) { | |
672 | cfg_mode = 0; | |
673 | line_mode = 0; /* double lines to line buffer */ | |
674 | } | |
675 | ||
676 | write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
677 | write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
678 | write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
679 | ||
680 | /* regs for now */ | |
681 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN); | |
585e6f01 AT |
682 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN); |
683 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN); | |
45719127 AT |
684 | |
685 | /* frame start for input luma */ | |
686 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
687 | VPE_CHAN_LUMA1_IN); | |
585e6f01 AT |
688 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, |
689 | VPE_CHAN_LUMA2_IN); | |
690 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
691 | VPE_CHAN_LUMA3_IN); | |
45719127 AT |
692 | |
693 | /* frame start for input chroma */ | |
694 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
695 | VPE_CHAN_CHROMA1_IN); | |
585e6f01 AT |
696 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, |
697 | VPE_CHAN_CHROMA2_IN); | |
698 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
699 | VPE_CHAN_CHROMA3_IN); | |
700 | ||
701 | /* frame start for MV in client */ | |
702 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
703 | VPE_CHAN_MV_IN); | |
45719127 AT |
704 | |
705 | ctx->load_mmrs = true; | |
706 | } | |
707 | ||
708 | /* | |
709 | * Set the shadow registers that are modified when the source | |
710 | * format changes. | |
711 | */ | |
712 | static void set_src_registers(struct vpe_ctx *ctx) | |
713 | { | |
714 | set_us_coefficients(ctx); | |
715 | } | |
716 | ||
717 | /* | |
718 | * Set the shadow registers that are modified when the destination | |
719 | * format changes. | |
720 | */ | |
721 | static void set_dst_registers(struct vpe_ctx *ctx) | |
722 | { | |
723 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
30496799 | 724 | enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace; |
45719127 AT |
725 | struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt; |
726 | u32 val = 0; | |
727 | ||
30496799 AT |
728 | if (clrspc == V4L2_COLORSPACE_SRGB) |
729 | val |= VPE_RGB_OUT_SELECT; | |
45719127 AT |
730 | else if (fmt->fourcc == V4L2_PIX_FMT_NV16) |
731 | val |= VPE_COLOR_SEPARATE_422; | |
732 | ||
30496799 AT |
733 | /* |
734 | * the source of CHR_DS and CSC is always the scaler, irrespective of | |
735 | * whether it's used or not | |
736 | */ | |
737 | val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER; | |
45719127 AT |
738 | |
739 | if (fmt->fourcc != V4L2_PIX_FMT_NV12) | |
740 | val |= VPE_DS_BYPASS; | |
741 | ||
742 | mmr_adb->out_fmt_reg[0] = val; | |
743 | ||
744 | ctx->load_mmrs = true; | |
745 | } | |
746 | ||
747 | /* | |
748 | * Set the de-interlacer shadow register values | |
749 | */ | |
585e6f01 | 750 | static void set_dei_regs(struct vpe_ctx *ctx) |
45719127 AT |
751 | { |
752 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
753 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; | |
754 | unsigned int src_h = s_q_data->c_rect.height; | |
755 | unsigned int src_w = s_q_data->c_rect.width; | |
756 | u32 *dei_mmr0 = &mmr_adb->dei_regs[0]; | |
585e6f01 | 757 | bool deinterlace = true; |
45719127 AT |
758 | u32 val = 0; |
759 | ||
760 | /* | |
761 | * according to TRM, we should set DEI in progressive bypass mode when | |
762 | * the input content is progressive, however, DEI is bypassed correctly | |
763 | * for both progressive and interlace content in interlace bypass mode. | |
764 | * It has been recommended not to use progressive bypass mode. | |
765 | */ | |
585e6f01 AT |
766 | if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) || |
767 | !(s_q_data->flags & Q_DATA_INTERLACED)) { | |
768 | deinterlace = false; | |
769 | val = VPE_DEI_INTERLACE_BYPASS; | |
770 | } | |
771 | ||
772 | src_h = deinterlace ? src_h * 2 : src_h; | |
45719127 AT |
773 | |
774 | val |= (src_h << VPE_DEI_HEIGHT_SHIFT) | | |
775 | (src_w << VPE_DEI_WIDTH_SHIFT) | | |
776 | VPE_DEI_FIELD_FLUSH; | |
777 | ||
778 | *dei_mmr0 = val; | |
779 | ||
780 | ctx->load_mmrs = true; | |
781 | } | |
782 | ||
585e6f01 AT |
783 | static void set_dei_shadow_registers(struct vpe_ctx *ctx) |
784 | { | |
785 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
786 | u32 *dei_mmr = &mmr_adb->dei_regs[0]; | |
787 | const struct vpe_dei_regs *cur = &dei_regs; | |
788 | ||
789 | dei_mmr[2] = cur->mdt_spacial_freq_thr_reg; | |
790 | dei_mmr[3] = cur->edi_config_reg; | |
791 | dei_mmr[4] = cur->edi_lut_reg0; | |
792 | dei_mmr[5] = cur->edi_lut_reg1; | |
793 | dei_mmr[6] = cur->edi_lut_reg2; | |
794 | dei_mmr[7] = cur->edi_lut_reg3; | |
795 | ||
796 | ctx->load_mmrs = true; | |
797 | } | |
798 | ||
45719127 AT |
799 | /* |
800 | * Set the shadow registers whose values are modified when either the | |
801 | * source or destination format is changed. | |
802 | */ | |
803 | static int set_srcdst_params(struct vpe_ctx *ctx) | |
804 | { | |
585e6f01 AT |
805 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
806 | struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; | |
44687b2e | 807 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; |
773f0657 AT |
808 | unsigned int src_w = s_q_data->c_rect.width; |
809 | unsigned int src_h = s_q_data->c_rect.height; | |
810 | unsigned int dst_w = d_q_data->c_rect.width; | |
811 | unsigned int dst_h = d_q_data->c_rect.height; | |
585e6f01 AT |
812 | size_t mv_buf_size; |
813 | int ret; | |
814 | ||
45719127 | 815 | ctx->sequence = 0; |
585e6f01 AT |
816 | ctx->field = V4L2_FIELD_TOP; |
817 | ||
818 | if ((s_q_data->flags & Q_DATA_INTERLACED) && | |
819 | !(d_q_data->flags & Q_DATA_INTERLACED)) { | |
a51cd8f5 | 820 | int bytes_per_line; |
585e6f01 AT |
821 | const struct vpdma_data_format *mv = |
822 | &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
823 | ||
a51cd8f5 AT |
824 | /* |
825 | * we make sure that the source image has a 16 byte aligned | |
826 | * stride, we need to do the same for the motion vector buffer | |
827 | * by aligning it's stride to the next 16 byte boundry. this | |
828 | * extra space will not be used by the de-interlacer, but will | |
829 | * ensure that vpdma operates correctly | |
830 | */ | |
831 | bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3, | |
832 | VPDMA_STRIDE_ALIGN); | |
833 | mv_buf_size = bytes_per_line * s_q_data->height; | |
773f0657 AT |
834 | |
835 | ctx->deinterlacing = 1; | |
836 | src_h <<= 1; | |
585e6f01 AT |
837 | } else { |
838 | ctx->deinterlacing = 0; | |
839 | mv_buf_size = 0; | |
840 | } | |
841 | ||
842 | free_vbs(ctx); | |
843 | ||
844 | ret = realloc_mv_buffers(ctx, mv_buf_size); | |
845 | if (ret) | |
846 | return ret; | |
45719127 AT |
847 | |
848 | set_cfg_and_line_modes(ctx); | |
585e6f01 | 849 | set_dei_regs(ctx); |
6948082d | 850 | |
30496799 AT |
851 | csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0], |
852 | s_q_data->colorspace, d_q_data->colorspace); | |
bbee8b39 | 853 | |
773f0657 AT |
854 | sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w); |
855 | sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h); | |
bbee8b39 AT |
856 | |
857 | sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0], | |
858 | &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0], | |
859 | src_w, src_h, dst_w, dst_h); | |
45719127 AT |
860 | |
861 | return 0; | |
862 | } | |
863 | ||
864 | /* | |
865 | * Return the vpe_ctx structure for a given struct file | |
866 | */ | |
867 | static struct vpe_ctx *file2ctx(struct file *file) | |
868 | { | |
869 | return container_of(file->private_data, struct vpe_ctx, fh); | |
870 | } | |
871 | ||
872 | /* | |
873 | * mem2mem callbacks | |
874 | */ | |
875 | ||
876 | /** | |
877 | * job_ready() - check whether an instance is ready to be scheduled to run | |
878 | */ | |
879 | static int job_ready(void *priv) | |
880 | { | |
881 | struct vpe_ctx *ctx = priv; | |
882 | int needed = ctx->bufs_per_job; | |
883 | ||
585e6f01 AT |
884 | if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) |
885 | needed += 2; /* need additional two most recent fields */ | |
886 | ||
45719127 AT |
887 | if (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) < needed) |
888 | return 0; | |
889 | ||
890 | return 1; | |
891 | } | |
892 | ||
893 | static void job_abort(void *priv) | |
894 | { | |
895 | struct vpe_ctx *ctx = priv; | |
896 | ||
897 | /* Will cancel the transaction in the next interrupt handler */ | |
898 | ctx->aborting = 1; | |
899 | } | |
900 | ||
901 | /* | |
902 | * Lock access to the device | |
903 | */ | |
904 | static void vpe_lock(void *priv) | |
905 | { | |
906 | struct vpe_ctx *ctx = priv; | |
907 | struct vpe_dev *dev = ctx->dev; | |
908 | mutex_lock(&dev->dev_mutex); | |
909 | } | |
910 | ||
911 | static void vpe_unlock(void *priv) | |
912 | { | |
913 | struct vpe_ctx *ctx = priv; | |
914 | struct vpe_dev *dev = ctx->dev; | |
915 | mutex_unlock(&dev->dev_mutex); | |
916 | } | |
917 | ||
918 | static void vpe_dump_regs(struct vpe_dev *dev) | |
919 | { | |
920 | #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r)) | |
921 | ||
922 | vpe_dbg(dev, "VPE Registers:\n"); | |
923 | ||
924 | DUMPREG(PID); | |
925 | DUMPREG(SYSCONFIG); | |
926 | DUMPREG(INT0_STATUS0_RAW); | |
927 | DUMPREG(INT0_STATUS0); | |
928 | DUMPREG(INT0_ENABLE0); | |
929 | DUMPREG(INT0_STATUS1_RAW); | |
930 | DUMPREG(INT0_STATUS1); | |
931 | DUMPREG(INT0_ENABLE1); | |
932 | DUMPREG(CLK_ENABLE); | |
933 | DUMPREG(CLK_RESET); | |
934 | DUMPREG(CLK_FORMAT_SELECT); | |
935 | DUMPREG(CLK_RANGE_MAP); | |
936 | DUMPREG(US1_R0); | |
937 | DUMPREG(US1_R1); | |
938 | DUMPREG(US1_R2); | |
939 | DUMPREG(US1_R3); | |
940 | DUMPREG(US1_R4); | |
941 | DUMPREG(US1_R5); | |
942 | DUMPREG(US1_R6); | |
943 | DUMPREG(US1_R7); | |
944 | DUMPREG(US2_R0); | |
945 | DUMPREG(US2_R1); | |
946 | DUMPREG(US2_R2); | |
947 | DUMPREG(US2_R3); | |
948 | DUMPREG(US2_R4); | |
949 | DUMPREG(US2_R5); | |
950 | DUMPREG(US2_R6); | |
951 | DUMPREG(US2_R7); | |
952 | DUMPREG(US3_R0); | |
953 | DUMPREG(US3_R1); | |
954 | DUMPREG(US3_R2); | |
955 | DUMPREG(US3_R3); | |
956 | DUMPREG(US3_R4); | |
957 | DUMPREG(US3_R5); | |
958 | DUMPREG(US3_R6); | |
959 | DUMPREG(US3_R7); | |
960 | DUMPREG(DEI_FRAME_SIZE); | |
961 | DUMPREG(MDT_BYPASS); | |
962 | DUMPREG(MDT_SF_THRESHOLD); | |
963 | DUMPREG(EDI_CONFIG); | |
964 | DUMPREG(DEI_EDI_LUT_R0); | |
965 | DUMPREG(DEI_EDI_LUT_R1); | |
966 | DUMPREG(DEI_EDI_LUT_R2); | |
967 | DUMPREG(DEI_EDI_LUT_R3); | |
968 | DUMPREG(DEI_FMD_WINDOW_R0); | |
969 | DUMPREG(DEI_FMD_WINDOW_R1); | |
970 | DUMPREG(DEI_FMD_CONTROL_R0); | |
971 | DUMPREG(DEI_FMD_CONTROL_R1); | |
972 | DUMPREG(DEI_FMD_STATUS_R0); | |
973 | DUMPREG(DEI_FMD_STATUS_R1); | |
974 | DUMPREG(DEI_FMD_STATUS_R2); | |
45719127 | 975 | #undef DUMPREG |
44687b2e AT |
976 | |
977 | sc_dump_regs(dev->sc); | |
6948082d | 978 | csc_dump_regs(dev->csc); |
45719127 AT |
979 | } |
980 | ||
981 | static void add_out_dtd(struct vpe_ctx *ctx, int port) | |
982 | { | |
983 | struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST]; | |
984 | const struct vpe_port_data *p_data = &port_data[port]; | |
985 | struct vb2_buffer *vb = ctx->dst_vb; | |
986 | struct v4l2_rect *c_rect = &q_data->c_rect; | |
987 | struct vpe_fmt *fmt = q_data->fmt; | |
988 | const struct vpdma_data_format *vpdma_fmt; | |
585e6f01 | 989 | int mv_buf_selector = !ctx->src_mv_buf_selector; |
45719127 AT |
990 | dma_addr_t dma_addr; |
991 | u32 flags = 0; | |
992 | ||
585e6f01 AT |
993 | if (port == VPE_PORT_MV_OUT) { |
994 | vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
995 | dma_addr = ctx->mv_buf_dma[mv_buf_selector]; | |
996 | } else { | |
997 | /* to incorporate interleaved formats */ | |
998 | int plane = fmt->coplanar ? p_data->vb_part : 0; | |
999 | ||
1000 | vpdma_fmt = fmt->vpdma_fmt[plane]; | |
1001 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane); | |
1002 | if (!dma_addr) { | |
1003 | vpe_err(ctx->dev, | |
1004 | "acquiring output buffer(%d) dma_addr failed\n", | |
1005 | port); | |
1006 | return; | |
1007 | } | |
45719127 AT |
1008 | } |
1009 | ||
1010 | if (q_data->flags & Q_DATA_FRAME_1D) | |
1011 | flags |= VPDMA_DATA_FRAME_1D; | |
1012 | if (q_data->flags & Q_DATA_MODE_TILED) | |
1013 | flags |= VPDMA_DATA_MODE_TILED; | |
1014 | ||
1015 | vpdma_add_out_dtd(&ctx->desc_list, c_rect, vpdma_fmt, dma_addr, | |
1016 | p_data->channel, flags); | |
1017 | } | |
1018 | ||
1019 | static void add_in_dtd(struct vpe_ctx *ctx, int port) | |
1020 | { | |
1021 | struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC]; | |
1022 | const struct vpe_port_data *p_data = &port_data[port]; | |
585e6f01 | 1023 | struct vb2_buffer *vb = ctx->src_vbs[p_data->vb_index]; |
45719127 AT |
1024 | struct v4l2_rect *c_rect = &q_data->c_rect; |
1025 | struct vpe_fmt *fmt = q_data->fmt; | |
1026 | const struct vpdma_data_format *vpdma_fmt; | |
585e6f01 AT |
1027 | int mv_buf_selector = ctx->src_mv_buf_selector; |
1028 | int field = vb->v4l2_buf.field == V4L2_FIELD_BOTTOM; | |
45719127 AT |
1029 | dma_addr_t dma_addr; |
1030 | u32 flags = 0; | |
1031 | ||
585e6f01 AT |
1032 | if (port == VPE_PORT_MV_IN) { |
1033 | vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
1034 | dma_addr = ctx->mv_buf_dma[mv_buf_selector]; | |
1035 | } else { | |
1036 | /* to incorporate interleaved formats */ | |
1037 | int plane = fmt->coplanar ? p_data->vb_part : 0; | |
45719127 | 1038 | |
585e6f01 AT |
1039 | vpdma_fmt = fmt->vpdma_fmt[plane]; |
1040 | ||
1041 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane); | |
1042 | if (!dma_addr) { | |
1043 | vpe_err(ctx->dev, | |
1044 | "acquiring input buffer(%d) dma_addr failed\n", | |
1045 | port); | |
1046 | return; | |
1047 | } | |
45719127 AT |
1048 | } |
1049 | ||
1050 | if (q_data->flags & Q_DATA_FRAME_1D) | |
1051 | flags |= VPDMA_DATA_FRAME_1D; | |
1052 | if (q_data->flags & Q_DATA_MODE_TILED) | |
1053 | flags |= VPDMA_DATA_MODE_TILED; | |
1054 | ||
1055 | vpdma_add_in_dtd(&ctx->desc_list, q_data->width, q_data->height, | |
1056 | c_rect, vpdma_fmt, dma_addr, p_data->channel, field, flags); | |
1057 | } | |
1058 | ||
1059 | /* | |
1060 | * Enable the expected IRQ sources | |
1061 | */ | |
1062 | static void enable_irqs(struct vpe_ctx *ctx) | |
1063 | { | |
1064 | write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE); | |
585e6f01 AT |
1065 | write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT | |
1066 | VPE_DS1_UV_ERROR_INT); | |
45719127 AT |
1067 | |
1068 | vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true); | |
1069 | } | |
1070 | ||
1071 | static void disable_irqs(struct vpe_ctx *ctx) | |
1072 | { | |
1073 | write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff); | |
1074 | write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff); | |
1075 | ||
1076 | vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false); | |
1077 | } | |
1078 | ||
1079 | /* device_run() - prepares and starts the device | |
1080 | * | |
1081 | * This function is only called when both the source and destination | |
1082 | * buffers are in place. | |
1083 | */ | |
1084 | static void device_run(void *priv) | |
1085 | { | |
1086 | struct vpe_ctx *ctx = priv; | |
773f0657 | 1087 | struct sc_data *sc = ctx->dev->sc; |
45719127 AT |
1088 | struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; |
1089 | ||
585e6f01 AT |
1090 | if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) { |
1091 | ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx); | |
1092 | WARN_ON(ctx->src_vbs[2] == NULL); | |
1093 | ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx); | |
1094 | WARN_ON(ctx->src_vbs[1] == NULL); | |
1095 | } | |
1096 | ||
1097 | ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx); | |
1098 | WARN_ON(ctx->src_vbs[0] == NULL); | |
45719127 AT |
1099 | ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); |
1100 | WARN_ON(ctx->dst_vb == NULL); | |
1101 | ||
1102 | /* config descriptors */ | |
1103 | if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) { | |
1104 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb); | |
1105 | vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb); | |
1106 | ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr; | |
1107 | ctx->load_mmrs = false; | |
1108 | } | |
1109 | ||
773f0657 AT |
1110 | if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr || |
1111 | sc->load_coeff_h) { | |
1112 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h); | |
1113 | vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT, | |
1114 | &ctx->sc_coeff_h, 0); | |
1115 | ||
1116 | sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr; | |
1117 | sc->load_coeff_h = false; | |
1118 | } | |
1119 | ||
1120 | if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr || | |
1121 | sc->load_coeff_v) { | |
1122 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v); | |
1123 | vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT, | |
1124 | &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4); | |
1125 | ||
1126 | sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr; | |
1127 | sc->load_coeff_v = false; | |
1128 | } | |
1129 | ||
585e6f01 AT |
1130 | /* output data descriptors */ |
1131 | if (ctx->deinterlacing) | |
1132 | add_out_dtd(ctx, VPE_PORT_MV_OUT); | |
1133 | ||
30496799 AT |
1134 | if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) { |
1135 | add_out_dtd(ctx, VPE_PORT_RGB_OUT); | |
1136 | } else { | |
1137 | add_out_dtd(ctx, VPE_PORT_LUMA_OUT); | |
1138 | if (d_q_data->fmt->coplanar) | |
1139 | add_out_dtd(ctx, VPE_PORT_CHROMA_OUT); | |
1140 | } | |
45719127 | 1141 | |
585e6f01 AT |
1142 | /* input data descriptors */ |
1143 | if (ctx->deinterlacing) { | |
1144 | add_in_dtd(ctx, VPE_PORT_LUMA3_IN); | |
1145 | add_in_dtd(ctx, VPE_PORT_CHROMA3_IN); | |
1146 | ||
1147 | add_in_dtd(ctx, VPE_PORT_LUMA2_IN); | |
1148 | add_in_dtd(ctx, VPE_PORT_CHROMA2_IN); | |
1149 | } | |
1150 | ||
45719127 AT |
1151 | add_in_dtd(ctx, VPE_PORT_LUMA1_IN); |
1152 | add_in_dtd(ctx, VPE_PORT_CHROMA1_IN); | |
1153 | ||
585e6f01 AT |
1154 | if (ctx->deinterlacing) |
1155 | add_in_dtd(ctx, VPE_PORT_MV_IN); | |
1156 | ||
45719127 AT |
1157 | /* sync on channel control descriptors for input ports */ |
1158 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN); | |
1159 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN); | |
1160 | ||
585e6f01 AT |
1161 | if (ctx->deinterlacing) { |
1162 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1163 | VPE_CHAN_LUMA2_IN); | |
1164 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1165 | VPE_CHAN_CHROMA2_IN); | |
1166 | ||
1167 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1168 | VPE_CHAN_LUMA3_IN); | |
1169 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1170 | VPE_CHAN_CHROMA3_IN); | |
1171 | ||
1172 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN); | |
1173 | } | |
1174 | ||
45719127 | 1175 | /* sync on channel control descriptors for output ports */ |
30496799 AT |
1176 | if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) { |
1177 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1178 | VPE_CHAN_RGB_OUT); | |
1179 | } else { | |
1180 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1181 | VPE_CHAN_LUMA_OUT); | |
1182 | if (d_q_data->fmt->coplanar) | |
1183 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1184 | VPE_CHAN_CHROMA_OUT); | |
1185 | } | |
45719127 | 1186 | |
585e6f01 AT |
1187 | if (ctx->deinterlacing) |
1188 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT); | |
1189 | ||
45719127 AT |
1190 | enable_irqs(ctx); |
1191 | ||
1192 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf); | |
1193 | vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list); | |
1194 | } | |
1195 | ||
585e6f01 AT |
1196 | static void dei_error(struct vpe_ctx *ctx) |
1197 | { | |
1198 | dev_warn(ctx->dev->v4l2_dev.dev, | |
1199 | "received DEI error interrupt\n"); | |
1200 | } | |
1201 | ||
45719127 AT |
1202 | static void ds1_uv_error(struct vpe_ctx *ctx) |
1203 | { | |
1204 | dev_warn(ctx->dev->v4l2_dev.dev, | |
1205 | "received downsampler error interrupt\n"); | |
1206 | } | |
1207 | ||
1208 | static irqreturn_t vpe_irq(int irq_vpe, void *data) | |
1209 | { | |
1210 | struct vpe_dev *dev = (struct vpe_dev *)data; | |
1211 | struct vpe_ctx *ctx; | |
585e6f01 | 1212 | struct vpe_q_data *d_q_data; |
45719127 AT |
1213 | struct vb2_buffer *s_vb, *d_vb; |
1214 | struct v4l2_buffer *s_buf, *d_buf; | |
1215 | unsigned long flags; | |
1216 | u32 irqst0, irqst1; | |
1217 | ||
1218 | irqst0 = read_reg(dev, VPE_INT0_STATUS0); | |
1219 | if (irqst0) { | |
1220 | write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0); | |
1221 | vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0); | |
1222 | } | |
1223 | ||
1224 | irqst1 = read_reg(dev, VPE_INT0_STATUS1); | |
1225 | if (irqst1) { | |
1226 | write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1); | |
1227 | vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1); | |
1228 | } | |
1229 | ||
1230 | ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); | |
1231 | if (!ctx) { | |
1232 | vpe_err(dev, "instance released before end of transaction\n"); | |
1233 | goto handled; | |
1234 | } | |
1235 | ||
585e6f01 AT |
1236 | if (irqst1) { |
1237 | if (irqst1 & VPE_DEI_ERROR_INT) { | |
1238 | irqst1 &= ~VPE_DEI_ERROR_INT; | |
1239 | dei_error(ctx); | |
1240 | } | |
1241 | if (irqst1 & VPE_DS1_UV_ERROR_INT) { | |
1242 | irqst1 &= ~VPE_DS1_UV_ERROR_INT; | |
1243 | ds1_uv_error(ctx); | |
1244 | } | |
45719127 AT |
1245 | } |
1246 | ||
1247 | if (irqst0) { | |
1248 | if (irqst0 & VPE_INT0_LIST0_COMPLETE) | |
1249 | vpdma_clear_list_stat(ctx->dev->vpdma); | |
1250 | ||
1251 | irqst0 &= ~(VPE_INT0_LIST0_COMPLETE); | |
1252 | } | |
1253 | ||
1254 | if (irqst0 | irqst1) { | |
1255 | dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: " | |
1256 | "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n", | |
1257 | irqst0, irqst1); | |
1258 | } | |
1259 | ||
1260 | disable_irqs(ctx); | |
1261 | ||
1262 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf); | |
1263 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb); | |
773f0657 AT |
1264 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h); |
1265 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v); | |
45719127 AT |
1266 | |
1267 | vpdma_reset_desc_list(&ctx->desc_list); | |
1268 | ||
585e6f01 AT |
1269 | /* the previous dst mv buffer becomes the next src mv buffer */ |
1270 | ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector; | |
1271 | ||
45719127 AT |
1272 | if (ctx->aborting) |
1273 | goto finished; | |
1274 | ||
585e6f01 | 1275 | s_vb = ctx->src_vbs[0]; |
45719127 AT |
1276 | d_vb = ctx->dst_vb; |
1277 | s_buf = &s_vb->v4l2_buf; | |
1278 | d_buf = &d_vb->v4l2_buf; | |
1279 | ||
1280 | d_buf->timestamp = s_buf->timestamp; | |
1281 | if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) { | |
1282 | d_buf->flags |= V4L2_BUF_FLAG_TIMECODE; | |
1283 | d_buf->timecode = s_buf->timecode; | |
1284 | } | |
45719127 | 1285 | d_buf->sequence = ctx->sequence; |
585e6f01 AT |
1286 | d_buf->field = ctx->field; |
1287 | ||
1288 | d_q_data = &ctx->q_data[Q_DATA_DST]; | |
1289 | if (d_q_data->flags & Q_DATA_INTERLACED) { | |
1290 | if (ctx->field == V4L2_FIELD_BOTTOM) { | |
1291 | ctx->sequence++; | |
1292 | ctx->field = V4L2_FIELD_TOP; | |
1293 | } else { | |
1294 | WARN_ON(ctx->field != V4L2_FIELD_TOP); | |
1295 | ctx->field = V4L2_FIELD_BOTTOM; | |
1296 | } | |
1297 | } else { | |
1298 | ctx->sequence++; | |
1299 | } | |
45719127 | 1300 | |
585e6f01 AT |
1301 | if (ctx->deinterlacing) |
1302 | s_vb = ctx->src_vbs[2]; | |
45719127 AT |
1303 | |
1304 | spin_lock_irqsave(&dev->lock, flags); | |
1305 | v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE); | |
1306 | v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE); | |
1307 | spin_unlock_irqrestore(&dev->lock, flags); | |
1308 | ||
585e6f01 AT |
1309 | if (ctx->deinterlacing) { |
1310 | ctx->src_vbs[2] = ctx->src_vbs[1]; | |
1311 | ctx->src_vbs[1] = ctx->src_vbs[0]; | |
1312 | } | |
1313 | ||
45719127 AT |
1314 | ctx->bufs_completed++; |
1315 | if (ctx->bufs_completed < ctx->bufs_per_job) { | |
1316 | device_run(ctx); | |
1317 | goto handled; | |
1318 | } | |
1319 | ||
1320 | finished: | |
1321 | vpe_dbg(ctx->dev, "finishing transaction\n"); | |
1322 | ctx->bufs_completed = 0; | |
1323 | v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx); | |
1324 | handled: | |
1325 | return IRQ_HANDLED; | |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * video ioctls | |
1330 | */ | |
1331 | static int vpe_querycap(struct file *file, void *priv, | |
1332 | struct v4l2_capability *cap) | |
1333 | { | |
1334 | strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1); | |
1335 | strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1); | |
1336 | strlcpy(cap->bus_info, VPE_MODULE_NAME, sizeof(cap->bus_info)); | |
1337 | cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING; | |
1338 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type) | |
1343 | { | |
1344 | int i, index; | |
1345 | struct vpe_fmt *fmt = NULL; | |
1346 | ||
1347 | index = 0; | |
1348 | for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) { | |
1349 | if (vpe_formats[i].types & type) { | |
1350 | if (index == f->index) { | |
1351 | fmt = &vpe_formats[i]; | |
1352 | break; | |
1353 | } | |
1354 | index++; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | if (!fmt) | |
1359 | return -EINVAL; | |
1360 | ||
1361 | strncpy(f->description, fmt->name, sizeof(f->description) - 1); | |
1362 | f->pixelformat = fmt->fourcc; | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int vpe_enum_fmt(struct file *file, void *priv, | |
1367 | struct v4l2_fmtdesc *f) | |
1368 | { | |
1369 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1370 | return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT); | |
1371 | ||
1372 | return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE); | |
1373 | } | |
1374 | ||
1375 | static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1376 | { | |
1377 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1378 | struct vpe_ctx *ctx = file2ctx(file); | |
1379 | struct vb2_queue *vq; | |
1380 | struct vpe_q_data *q_data; | |
1381 | int i; | |
1382 | ||
1383 | vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type); | |
1384 | if (!vq) | |
1385 | return -EINVAL; | |
1386 | ||
1387 | q_data = get_q_data(ctx, f->type); | |
1388 | ||
1389 | pix->width = q_data->width; | |
1390 | pix->height = q_data->height; | |
1391 | pix->pixelformat = q_data->fmt->fourcc; | |
585e6f01 | 1392 | pix->field = q_data->field; |
45719127 AT |
1393 | |
1394 | if (V4L2_TYPE_IS_OUTPUT(f->type)) { | |
1395 | pix->colorspace = q_data->colorspace; | |
1396 | } else { | |
1397 | struct vpe_q_data *s_q_data; | |
1398 | ||
1399 | /* get colorspace from the source queue */ | |
1400 | s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); | |
1401 | ||
1402 | pix->colorspace = s_q_data->colorspace; | |
1403 | } | |
1404 | ||
1405 | pix->num_planes = q_data->fmt->coplanar ? 2 : 1; | |
1406 | ||
1407 | for (i = 0; i < pix->num_planes; i++) { | |
1408 | pix->plane_fmt[i].bytesperline = q_data->bytesperline[i]; | |
1409 | pix->plane_fmt[i].sizeimage = q_data->sizeimage[i]; | |
1410 | } | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f, | |
1416 | struct vpe_fmt *fmt, int type) | |
1417 | { | |
1418 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1419 | struct v4l2_plane_pix_format *plane_fmt; | |
a51cd8f5 AT |
1420 | unsigned int w_align; |
1421 | int i, depth, depth_bytes; | |
45719127 AT |
1422 | |
1423 | if (!fmt || !(fmt->types & type)) { | |
1424 | vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n", | |
1425 | pix->pixelformat); | |
1426 | return -EINVAL; | |
1427 | } | |
1428 | ||
585e6f01 AT |
1429 | if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE) |
1430 | pix->field = V4L2_FIELD_NONE; | |
45719127 | 1431 | |
a51cd8f5 AT |
1432 | depth = fmt->vpdma_fmt[VPE_LUMA]->depth; |
1433 | ||
1434 | /* | |
1435 | * the line stride should 16 byte aligned for VPDMA to work, based on | |
1436 | * the bytes per pixel, figure out how much the width should be aligned | |
1437 | * to make sure line stride is 16 byte aligned | |
1438 | */ | |
1439 | depth_bytes = depth >> 3; | |
1440 | ||
1441 | if (depth_bytes == 3) | |
1442 | /* | |
1443 | * if bpp is 3(as in some RGB formats), the pixel width doesn't | |
1444 | * really help in ensuring line stride is 16 byte aligned | |
1445 | */ | |
1446 | w_align = 4; | |
1447 | else | |
1448 | /* | |
1449 | * for the remainder bpp(4, 2 and 1), the pixel width alignment | |
1450 | * can ensure a line stride alignment of 16 bytes. For example, | |
1451 | * if bpp is 2, then the line stride can be 16 byte aligned if | |
1452 | * the width is 8 byte aligned | |
1453 | */ | |
1454 | w_align = order_base_2(VPDMA_DESC_ALIGN / depth_bytes); | |
1455 | ||
1456 | v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align, | |
45719127 AT |
1457 | &pix->height, MIN_H, MAX_H, H_ALIGN, |
1458 | S_ALIGN); | |
1459 | ||
1460 | pix->num_planes = fmt->coplanar ? 2 : 1; | |
1461 | pix->pixelformat = fmt->fourcc; | |
1462 | ||
30496799 AT |
1463 | if (!pix->colorspace) { |
1464 | if (fmt->fourcc == V4L2_PIX_FMT_RGB24 || | |
1465 | fmt->fourcc == V4L2_PIX_FMT_BGR24 || | |
1466 | fmt->fourcc == V4L2_PIX_FMT_RGB32 || | |
1467 | fmt->fourcc == V4L2_PIX_FMT_BGR32) { | |
1468 | pix->colorspace = V4L2_COLORSPACE_SRGB; | |
1469 | } else { | |
1470 | if (pix->height > 1280) /* HD */ | |
1471 | pix->colorspace = V4L2_COLORSPACE_REC709; | |
1472 | else /* SD */ | |
1473 | pix->colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1474 | } | |
45719127 AT |
1475 | } |
1476 | ||
1477 | for (i = 0; i < pix->num_planes; i++) { | |
45719127 AT |
1478 | plane_fmt = &pix->plane_fmt[i]; |
1479 | depth = fmt->vpdma_fmt[i]->depth; | |
1480 | ||
1481 | if (i == VPE_LUMA) | |
a51cd8f5 | 1482 | plane_fmt->bytesperline = (pix->width * depth) >> 3; |
45719127 AT |
1483 | else |
1484 | plane_fmt->bytesperline = pix->width; | |
1485 | ||
1486 | plane_fmt->sizeimage = | |
1487 | (pix->height * pix->width * depth) >> 3; | |
1488 | } | |
1489 | ||
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1494 | { | |
1495 | struct vpe_ctx *ctx = file2ctx(file); | |
1496 | struct vpe_fmt *fmt = find_format(f); | |
1497 | ||
1498 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1499 | return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT); | |
1500 | else | |
1501 | return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE); | |
1502 | } | |
1503 | ||
1504 | static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f) | |
1505 | { | |
1506 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1507 | struct v4l2_plane_pix_format *plane_fmt; | |
1508 | struct vpe_q_data *q_data; | |
1509 | struct vb2_queue *vq; | |
1510 | int i; | |
1511 | ||
1512 | vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type); | |
1513 | if (!vq) | |
1514 | return -EINVAL; | |
1515 | ||
1516 | if (vb2_is_busy(vq)) { | |
1517 | vpe_err(ctx->dev, "queue busy\n"); | |
1518 | return -EBUSY; | |
1519 | } | |
1520 | ||
1521 | q_data = get_q_data(ctx, f->type); | |
1522 | if (!q_data) | |
1523 | return -EINVAL; | |
1524 | ||
1525 | q_data->fmt = find_format(f); | |
1526 | q_data->width = pix->width; | |
1527 | q_data->height = pix->height; | |
1528 | q_data->colorspace = pix->colorspace; | |
585e6f01 | 1529 | q_data->field = pix->field; |
45719127 AT |
1530 | |
1531 | for (i = 0; i < pix->num_planes; i++) { | |
1532 | plane_fmt = &pix->plane_fmt[i]; | |
1533 | ||
1534 | q_data->bytesperline[i] = plane_fmt->bytesperline; | |
1535 | q_data->sizeimage[i] = plane_fmt->sizeimage; | |
1536 | } | |
1537 | ||
1538 | q_data->c_rect.left = 0; | |
1539 | q_data->c_rect.top = 0; | |
1540 | q_data->c_rect.width = q_data->width; | |
1541 | q_data->c_rect.height = q_data->height; | |
1542 | ||
585e6f01 AT |
1543 | if (q_data->field == V4L2_FIELD_ALTERNATE) |
1544 | q_data->flags |= Q_DATA_INTERLACED; | |
1545 | else | |
1546 | q_data->flags &= ~Q_DATA_INTERLACED; | |
1547 | ||
45719127 AT |
1548 | vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d", |
1549 | f->type, q_data->width, q_data->height, q_data->fmt->fourcc, | |
1550 | q_data->bytesperline[VPE_LUMA]); | |
1551 | if (q_data->fmt->coplanar) | |
1552 | vpe_dbg(ctx->dev, " bpl_uv %d\n", | |
1553 | q_data->bytesperline[VPE_CHROMA]); | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1559 | { | |
1560 | int ret; | |
1561 | struct vpe_ctx *ctx = file2ctx(file); | |
1562 | ||
1563 | ret = vpe_try_fmt(file, priv, f); | |
1564 | if (ret) | |
1565 | return ret; | |
1566 | ||
1567 | ret = __vpe_s_fmt(ctx, f); | |
1568 | if (ret) | |
1569 | return ret; | |
1570 | ||
1571 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1572 | set_src_registers(ctx); | |
1573 | else | |
1574 | set_dst_registers(ctx); | |
1575 | ||
1576 | return set_srcdst_params(ctx); | |
1577 | } | |
1578 | ||
1579 | static int vpe_reqbufs(struct file *file, void *priv, | |
1580 | struct v4l2_requestbuffers *reqbufs) | |
1581 | { | |
1582 | struct vpe_ctx *ctx = file2ctx(file); | |
1583 | ||
1584 | return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs); | |
1585 | } | |
1586 | ||
1587 | static int vpe_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf) | |
1588 | { | |
1589 | struct vpe_ctx *ctx = file2ctx(file); | |
1590 | ||
1591 | return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf); | |
1592 | } | |
1593 | ||
1594 | static int vpe_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) | |
1595 | { | |
1596 | struct vpe_ctx *ctx = file2ctx(file); | |
1597 | ||
1598 | return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf); | |
1599 | } | |
1600 | ||
1601 | static int vpe_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) | |
1602 | { | |
1603 | struct vpe_ctx *ctx = file2ctx(file); | |
1604 | ||
1605 | return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf); | |
1606 | } | |
1607 | ||
1608 | static int vpe_streamon(struct file *file, void *priv, enum v4l2_buf_type type) | |
1609 | { | |
1610 | struct vpe_ctx *ctx = file2ctx(file); | |
1611 | ||
1612 | return v4l2_m2m_streamon(file, ctx->m2m_ctx, type); | |
1613 | } | |
1614 | ||
1615 | static int vpe_streamoff(struct file *file, void *priv, enum v4l2_buf_type type) | |
1616 | { | |
1617 | struct vpe_ctx *ctx = file2ctx(file); | |
1618 | ||
1619 | vpe_dump_regs(ctx->dev); | |
1620 | vpdma_dump_regs(ctx->dev->vpdma); | |
1621 | ||
1622 | return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type); | |
1623 | } | |
1624 | ||
1625 | /* | |
1626 | * defines number of buffers/frames a context can process with VPE before | |
1627 | * switching to a different context. default value is 1 buffer per context | |
1628 | */ | |
1629 | #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0) | |
1630 | ||
1631 | static int vpe_s_ctrl(struct v4l2_ctrl *ctrl) | |
1632 | { | |
1633 | struct vpe_ctx *ctx = | |
1634 | container_of(ctrl->handler, struct vpe_ctx, hdl); | |
1635 | ||
1636 | switch (ctrl->id) { | |
1637 | case V4L2_CID_VPE_BUFS_PER_JOB: | |
1638 | ctx->bufs_per_job = ctrl->val; | |
1639 | break; | |
1640 | ||
1641 | default: | |
1642 | vpe_err(ctx->dev, "Invalid control\n"); | |
1643 | return -EINVAL; | |
1644 | } | |
1645 | ||
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | static const struct v4l2_ctrl_ops vpe_ctrl_ops = { | |
1650 | .s_ctrl = vpe_s_ctrl, | |
1651 | }; | |
1652 | ||
1653 | static const struct v4l2_ioctl_ops vpe_ioctl_ops = { | |
1654 | .vidioc_querycap = vpe_querycap, | |
1655 | ||
1656 | .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt, | |
1657 | .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt, | |
1658 | .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt, | |
1659 | .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt, | |
1660 | ||
1661 | .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt, | |
1662 | .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt, | |
1663 | .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt, | |
1664 | .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt, | |
1665 | ||
1666 | .vidioc_reqbufs = vpe_reqbufs, | |
1667 | .vidioc_querybuf = vpe_querybuf, | |
1668 | ||
1669 | .vidioc_qbuf = vpe_qbuf, | |
1670 | .vidioc_dqbuf = vpe_dqbuf, | |
1671 | ||
1672 | .vidioc_streamon = vpe_streamon, | |
1673 | .vidioc_streamoff = vpe_streamoff, | |
1674 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, | |
1675 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
1676 | }; | |
1677 | ||
1678 | /* | |
1679 | * Queue operations | |
1680 | */ | |
1681 | static int vpe_queue_setup(struct vb2_queue *vq, | |
1682 | const struct v4l2_format *fmt, | |
1683 | unsigned int *nbuffers, unsigned int *nplanes, | |
1684 | unsigned int sizes[], void *alloc_ctxs[]) | |
1685 | { | |
1686 | int i; | |
1687 | struct vpe_ctx *ctx = vb2_get_drv_priv(vq); | |
1688 | struct vpe_q_data *q_data; | |
1689 | ||
1690 | q_data = get_q_data(ctx, vq->type); | |
1691 | ||
1692 | *nplanes = q_data->fmt->coplanar ? 2 : 1; | |
1693 | ||
1694 | for (i = 0; i < *nplanes; i++) { | |
1695 | sizes[i] = q_data->sizeimage[i]; | |
1696 | alloc_ctxs[i] = ctx->dev->alloc_ctx; | |
1697 | } | |
1698 | ||
1699 | vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers, | |
1700 | sizes[VPE_LUMA]); | |
1701 | if (q_data->fmt->coplanar) | |
1702 | vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]); | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | static int vpe_buf_prepare(struct vb2_buffer *vb) | |
1708 | { | |
1709 | struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); | |
1710 | struct vpe_q_data *q_data; | |
1711 | int i, num_planes; | |
1712 | ||
1713 | vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type); | |
1714 | ||
1715 | q_data = get_q_data(ctx, vb->vb2_queue->type); | |
1716 | num_planes = q_data->fmt->coplanar ? 2 : 1; | |
1717 | ||
1718 | for (i = 0; i < num_planes; i++) { | |
1719 | if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) { | |
1720 | vpe_err(ctx->dev, | |
1721 | "data will not fit into plane (%lu < %lu)\n", | |
1722 | vb2_plane_size(vb, i), | |
1723 | (long) q_data->sizeimage[i]); | |
1724 | return -EINVAL; | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | for (i = 0; i < num_planes; i++) | |
1729 | vb2_set_plane_payload(vb, i, q_data->sizeimage[i]); | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | static void vpe_buf_queue(struct vb2_buffer *vb) | |
1735 | { | |
1736 | struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); | |
1737 | v4l2_m2m_buf_queue(ctx->m2m_ctx, vb); | |
1738 | } | |
1739 | ||
1740 | static void vpe_wait_prepare(struct vb2_queue *q) | |
1741 | { | |
1742 | struct vpe_ctx *ctx = vb2_get_drv_priv(q); | |
1743 | vpe_unlock(ctx); | |
1744 | } | |
1745 | ||
1746 | static void vpe_wait_finish(struct vb2_queue *q) | |
1747 | { | |
1748 | struct vpe_ctx *ctx = vb2_get_drv_priv(q); | |
1749 | vpe_lock(ctx); | |
1750 | } | |
1751 | ||
1752 | static struct vb2_ops vpe_qops = { | |
1753 | .queue_setup = vpe_queue_setup, | |
1754 | .buf_prepare = vpe_buf_prepare, | |
1755 | .buf_queue = vpe_buf_queue, | |
1756 | .wait_prepare = vpe_wait_prepare, | |
1757 | .wait_finish = vpe_wait_finish, | |
1758 | }; | |
1759 | ||
1760 | static int queue_init(void *priv, struct vb2_queue *src_vq, | |
1761 | struct vb2_queue *dst_vq) | |
1762 | { | |
1763 | struct vpe_ctx *ctx = priv; | |
1764 | int ret; | |
1765 | ||
1766 | memset(src_vq, 0, sizeof(*src_vq)); | |
1767 | src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
1768 | src_vq->io_modes = VB2_MMAP; | |
1769 | src_vq->drv_priv = ctx; | |
1770 | src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); | |
1771 | src_vq->ops = &vpe_qops; | |
1772 | src_vq->mem_ops = &vb2_dma_contig_memops; | |
ade48681 | 1773 | src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
45719127 AT |
1774 | |
1775 | ret = vb2_queue_init(src_vq); | |
1776 | if (ret) | |
1777 | return ret; | |
1778 | ||
1779 | memset(dst_vq, 0, sizeof(*dst_vq)); | |
1780 | dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
1781 | dst_vq->io_modes = VB2_MMAP; | |
1782 | dst_vq->drv_priv = ctx; | |
1783 | dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); | |
1784 | dst_vq->ops = &vpe_qops; | |
1785 | dst_vq->mem_ops = &vb2_dma_contig_memops; | |
ade48681 | 1786 | dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
45719127 AT |
1787 | |
1788 | return vb2_queue_init(dst_vq); | |
1789 | } | |
1790 | ||
1791 | static const struct v4l2_ctrl_config vpe_bufs_per_job = { | |
1792 | .ops = &vpe_ctrl_ops, | |
1793 | .id = V4L2_CID_VPE_BUFS_PER_JOB, | |
1794 | .name = "Buffers Per Transaction", | |
1795 | .type = V4L2_CTRL_TYPE_INTEGER, | |
1796 | .def = VPE_DEF_BUFS_PER_JOB, | |
1797 | .min = 1, | |
1798 | .max = VIDEO_MAX_FRAME, | |
1799 | .step = 1, | |
1800 | }; | |
1801 | ||
1802 | /* | |
1803 | * File operations | |
1804 | */ | |
1805 | static int vpe_open(struct file *file) | |
1806 | { | |
1807 | struct vpe_dev *dev = video_drvdata(file); | |
1808 | struct vpe_ctx *ctx = NULL; | |
1809 | struct vpe_q_data *s_q_data; | |
1810 | struct v4l2_ctrl_handler *hdl; | |
1811 | int ret; | |
1812 | ||
1813 | vpe_dbg(dev, "vpe_open\n"); | |
1814 | ||
1815 | if (!dev->vpdma->ready) { | |
1816 | vpe_err(dev, "vpdma firmware not loaded\n"); | |
1817 | return -ENODEV; | |
1818 | } | |
1819 | ||
1820 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
1821 | if (!ctx) | |
1822 | return -ENOMEM; | |
1823 | ||
1824 | ctx->dev = dev; | |
1825 | ||
1826 | if (mutex_lock_interruptible(&dev->dev_mutex)) { | |
1827 | ret = -ERESTARTSYS; | |
1828 | goto free_ctx; | |
1829 | } | |
1830 | ||
1831 | ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE, | |
1832 | VPDMA_LIST_TYPE_NORMAL); | |
1833 | if (ret != 0) | |
1834 | goto unlock; | |
1835 | ||
1836 | ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb)); | |
1837 | if (ret != 0) | |
1838 | goto free_desc_list; | |
1839 | ||
773f0657 AT |
1840 | ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE); |
1841 | if (ret != 0) | |
1842 | goto free_mmr_adb; | |
1843 | ||
1844 | ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE); | |
1845 | if (ret != 0) | |
1846 | goto free_sc_h; | |
1847 | ||
45719127 AT |
1848 | init_adb_hdrs(ctx); |
1849 | ||
1850 | v4l2_fh_init(&ctx->fh, video_devdata(file)); | |
1851 | file->private_data = &ctx->fh; | |
1852 | ||
1853 | hdl = &ctx->hdl; | |
1854 | v4l2_ctrl_handler_init(hdl, 1); | |
1855 | v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL); | |
1856 | if (hdl->error) { | |
1857 | ret = hdl->error; | |
1858 | goto exit_fh; | |
1859 | } | |
1860 | ctx->fh.ctrl_handler = hdl; | |
1861 | v4l2_ctrl_handler_setup(hdl); | |
1862 | ||
1863 | s_q_data = &ctx->q_data[Q_DATA_SRC]; | |
1864 | s_q_data->fmt = &vpe_formats[2]; | |
1865 | s_q_data->width = 1920; | |
1866 | s_q_data->height = 1080; | |
1867 | s_q_data->sizeimage[VPE_LUMA] = (s_q_data->width * s_q_data->height * | |
1868 | s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3; | |
30496799 | 1869 | s_q_data->colorspace = V4L2_COLORSPACE_SMPTE170M; |
585e6f01 | 1870 | s_q_data->field = V4L2_FIELD_NONE; |
45719127 AT |
1871 | s_q_data->c_rect.left = 0; |
1872 | s_q_data->c_rect.top = 0; | |
1873 | s_q_data->c_rect.width = s_q_data->width; | |
1874 | s_q_data->c_rect.height = s_q_data->height; | |
1875 | s_q_data->flags = 0; | |
1876 | ||
1877 | ctx->q_data[Q_DATA_DST] = *s_q_data; | |
1878 | ||
585e6f01 | 1879 | set_dei_shadow_registers(ctx); |
45719127 AT |
1880 | set_src_registers(ctx); |
1881 | set_dst_registers(ctx); | |
1882 | ret = set_srcdst_params(ctx); | |
1883 | if (ret) | |
1884 | goto exit_fh; | |
1885 | ||
1886 | ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init); | |
1887 | ||
1888 | if (IS_ERR(ctx->m2m_ctx)) { | |
1889 | ret = PTR_ERR(ctx->m2m_ctx); | |
1890 | goto exit_fh; | |
1891 | } | |
1892 | ||
1893 | v4l2_fh_add(&ctx->fh); | |
1894 | ||
1895 | /* | |
1896 | * for now, just report the creation of the first instance, we can later | |
1897 | * optimize the driver to enable or disable clocks when the first | |
1898 | * instance is created or the last instance released | |
1899 | */ | |
1900 | if (atomic_inc_return(&dev->num_instances) == 1) | |
1901 | vpe_dbg(dev, "first instance created\n"); | |
1902 | ||
1903 | ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB; | |
1904 | ||
1905 | ctx->load_mmrs = true; | |
1906 | ||
1907 | vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n", | |
1908 | ctx, ctx->m2m_ctx); | |
1909 | ||
1910 | mutex_unlock(&dev->dev_mutex); | |
1911 | ||
1912 | return 0; | |
1913 | exit_fh: | |
1914 | v4l2_ctrl_handler_free(hdl); | |
1915 | v4l2_fh_exit(&ctx->fh); | |
773f0657 AT |
1916 | vpdma_free_desc_buf(&ctx->sc_coeff_v); |
1917 | free_sc_h: | |
1918 | vpdma_free_desc_buf(&ctx->sc_coeff_h); | |
1919 | free_mmr_adb: | |
45719127 AT |
1920 | vpdma_free_desc_buf(&ctx->mmr_adb); |
1921 | free_desc_list: | |
1922 | vpdma_free_desc_list(&ctx->desc_list); | |
1923 | unlock: | |
1924 | mutex_unlock(&dev->dev_mutex); | |
1925 | free_ctx: | |
1926 | kfree(ctx); | |
1927 | return ret; | |
1928 | } | |
1929 | ||
1930 | static int vpe_release(struct file *file) | |
1931 | { | |
1932 | struct vpe_dev *dev = video_drvdata(file); | |
1933 | struct vpe_ctx *ctx = file2ctx(file); | |
1934 | ||
1935 | vpe_dbg(dev, "releasing instance %p\n", ctx); | |
1936 | ||
1937 | mutex_lock(&dev->dev_mutex); | |
585e6f01 AT |
1938 | free_vbs(ctx); |
1939 | free_mv_buffers(ctx); | |
45719127 AT |
1940 | vpdma_free_desc_list(&ctx->desc_list); |
1941 | vpdma_free_desc_buf(&ctx->mmr_adb); | |
1942 | ||
1943 | v4l2_fh_del(&ctx->fh); | |
1944 | v4l2_fh_exit(&ctx->fh); | |
1945 | v4l2_ctrl_handler_free(&ctx->hdl); | |
1946 | v4l2_m2m_ctx_release(ctx->m2m_ctx); | |
1947 | ||
1948 | kfree(ctx); | |
1949 | ||
1950 | /* | |
1951 | * for now, just report the release of the last instance, we can later | |
1952 | * optimize the driver to enable or disable clocks when the first | |
1953 | * instance is created or the last instance released | |
1954 | */ | |
1955 | if (atomic_dec_return(&dev->num_instances) == 0) | |
1956 | vpe_dbg(dev, "last instance released\n"); | |
1957 | ||
1958 | mutex_unlock(&dev->dev_mutex); | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
1963 | static unsigned int vpe_poll(struct file *file, | |
1964 | struct poll_table_struct *wait) | |
1965 | { | |
1966 | struct vpe_ctx *ctx = file2ctx(file); | |
1967 | struct vpe_dev *dev = ctx->dev; | |
1968 | int ret; | |
1969 | ||
1970 | mutex_lock(&dev->dev_mutex); | |
1971 | ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait); | |
1972 | mutex_unlock(&dev->dev_mutex); | |
1973 | return ret; | |
1974 | } | |
1975 | ||
1976 | static int vpe_mmap(struct file *file, struct vm_area_struct *vma) | |
1977 | { | |
1978 | struct vpe_ctx *ctx = file2ctx(file); | |
1979 | struct vpe_dev *dev = ctx->dev; | |
1980 | int ret; | |
1981 | ||
1982 | if (mutex_lock_interruptible(&dev->dev_mutex)) | |
1983 | return -ERESTARTSYS; | |
1984 | ret = v4l2_m2m_mmap(file, ctx->m2m_ctx, vma); | |
1985 | mutex_unlock(&dev->dev_mutex); | |
1986 | return ret; | |
1987 | } | |
1988 | ||
1989 | static const struct v4l2_file_operations vpe_fops = { | |
1990 | .owner = THIS_MODULE, | |
1991 | .open = vpe_open, | |
1992 | .release = vpe_release, | |
1993 | .poll = vpe_poll, | |
1994 | .unlocked_ioctl = video_ioctl2, | |
1995 | .mmap = vpe_mmap, | |
1996 | }; | |
1997 | ||
1998 | static struct video_device vpe_videodev = { | |
1999 | .name = VPE_MODULE_NAME, | |
2000 | .fops = &vpe_fops, | |
2001 | .ioctl_ops = &vpe_ioctl_ops, | |
2002 | .minor = -1, | |
2003 | .release = video_device_release, | |
2004 | .vfl_dir = VFL_DIR_M2M, | |
2005 | }; | |
2006 | ||
2007 | static struct v4l2_m2m_ops m2m_ops = { | |
2008 | .device_run = device_run, | |
2009 | .job_ready = job_ready, | |
2010 | .job_abort = job_abort, | |
2011 | .lock = vpe_lock, | |
2012 | .unlock = vpe_unlock, | |
2013 | }; | |
2014 | ||
2015 | static int vpe_runtime_get(struct platform_device *pdev) | |
2016 | { | |
2017 | int r; | |
2018 | ||
2019 | dev_dbg(&pdev->dev, "vpe_runtime_get\n"); | |
2020 | ||
2021 | r = pm_runtime_get_sync(&pdev->dev); | |
2022 | WARN_ON(r < 0); | |
2023 | return r < 0 ? r : 0; | |
2024 | } | |
2025 | ||
2026 | static void vpe_runtime_put(struct platform_device *pdev) | |
2027 | { | |
2028 | ||
2029 | int r; | |
2030 | ||
2031 | dev_dbg(&pdev->dev, "vpe_runtime_put\n"); | |
2032 | ||
2033 | r = pm_runtime_put_sync(&pdev->dev); | |
2034 | WARN_ON(r < 0 && r != -ENOSYS); | |
2035 | } | |
2036 | ||
2037 | static int vpe_probe(struct platform_device *pdev) | |
2038 | { | |
2039 | struct vpe_dev *dev; | |
2040 | struct video_device *vfd; | |
45719127 AT |
2041 | int ret, irq, func; |
2042 | ||
2043 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
b68231a1 WY |
2044 | if (!dev) |
2045 | return -ENOMEM; | |
45719127 AT |
2046 | |
2047 | spin_lock_init(&dev->lock); | |
2048 | ||
2049 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); | |
2050 | if (ret) | |
2051 | return ret; | |
2052 | ||
2053 | atomic_set(&dev->num_instances, 0); | |
2054 | mutex_init(&dev->dev_mutex); | |
2055 | ||
44687b2e AT |
2056 | dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2057 | "vpe_top"); | |
45719127 AT |
2058 | /* |
2059 | * HACK: we get resource info from device tree in the form of a list of | |
2060 | * VPE sub blocks, the driver currently uses only the base of vpe_top | |
2061 | * for register access, the driver should be changed later to access | |
2062 | * registers based on the sub block base addresses | |
2063 | */ | |
44687b2e | 2064 | dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K); |
b68231a1 WY |
2065 | if (!dev->base) { |
2066 | ret = -ENOMEM; | |
45719127 AT |
2067 | goto v4l2_dev_unreg; |
2068 | } | |
2069 | ||
2070 | irq = platform_get_irq(pdev, 0); | |
2071 | ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME, | |
2072 | dev); | |
2073 | if (ret) | |
2074 | goto v4l2_dev_unreg; | |
2075 | ||
2076 | platform_set_drvdata(pdev, dev); | |
2077 | ||
2078 | dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); | |
2079 | if (IS_ERR(dev->alloc_ctx)) { | |
2080 | vpe_err(dev, "Failed to alloc vb2 context\n"); | |
2081 | ret = PTR_ERR(dev->alloc_ctx); | |
2082 | goto v4l2_dev_unreg; | |
2083 | } | |
2084 | ||
2085 | dev->m2m_dev = v4l2_m2m_init(&m2m_ops); | |
2086 | if (IS_ERR(dev->m2m_dev)) { | |
2087 | vpe_err(dev, "Failed to init mem2mem device\n"); | |
2088 | ret = PTR_ERR(dev->m2m_dev); | |
2089 | goto rel_ctx; | |
2090 | } | |
2091 | ||
2092 | pm_runtime_enable(&pdev->dev); | |
2093 | ||
2094 | ret = vpe_runtime_get(pdev); | |
2095 | if (ret) | |
2096 | goto rel_m2m; | |
2097 | ||
2098 | /* Perform clk enable followed by reset */ | |
2099 | vpe_set_clock_enable(dev, 1); | |
2100 | ||
2101 | vpe_top_reset(dev); | |
2102 | ||
2103 | func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK, | |
2104 | VPE_PID_FUNC_SHIFT); | |
2105 | vpe_dbg(dev, "VPE PID function %x\n", func); | |
2106 | ||
2107 | vpe_top_vpdma_reset(dev); | |
2108 | ||
44687b2e AT |
2109 | dev->sc = sc_create(pdev); |
2110 | if (IS_ERR(dev->sc)) { | |
2111 | ret = PTR_ERR(dev->sc); | |
2112 | goto runtime_put; | |
2113 | } | |
2114 | ||
6948082d AT |
2115 | dev->csc = csc_create(pdev); |
2116 | if (IS_ERR(dev->csc)) { | |
2117 | ret = PTR_ERR(dev->csc); | |
2118 | goto runtime_put; | |
2119 | } | |
2120 | ||
45719127 | 2121 | dev->vpdma = vpdma_create(pdev); |
6676cafe WY |
2122 | if (IS_ERR(dev->vpdma)) { |
2123 | ret = PTR_ERR(dev->vpdma); | |
45719127 | 2124 | goto runtime_put; |
6676cafe | 2125 | } |
45719127 AT |
2126 | |
2127 | vfd = &dev->vfd; | |
2128 | *vfd = vpe_videodev; | |
2129 | vfd->lock = &dev->dev_mutex; | |
2130 | vfd->v4l2_dev = &dev->v4l2_dev; | |
2131 | ||
2132 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
2133 | if (ret) { | |
2134 | vpe_err(dev, "Failed to register video device\n"); | |
2135 | goto runtime_put; | |
2136 | } | |
2137 | ||
2138 | video_set_drvdata(vfd, dev); | |
2139 | snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name); | |
2140 | dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n", | |
2141 | vfd->num); | |
2142 | ||
2143 | return 0; | |
2144 | ||
2145 | runtime_put: | |
2146 | vpe_runtime_put(pdev); | |
2147 | rel_m2m: | |
2148 | pm_runtime_disable(&pdev->dev); | |
2149 | v4l2_m2m_release(dev->m2m_dev); | |
2150 | rel_ctx: | |
2151 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx); | |
2152 | v4l2_dev_unreg: | |
2153 | v4l2_device_unregister(&dev->v4l2_dev); | |
2154 | ||
2155 | return ret; | |
2156 | } | |
2157 | ||
2158 | static int vpe_remove(struct platform_device *pdev) | |
2159 | { | |
2160 | struct vpe_dev *dev = | |
2161 | (struct vpe_dev *) platform_get_drvdata(pdev); | |
2162 | ||
2163 | v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME); | |
2164 | ||
2165 | v4l2_m2m_release(dev->m2m_dev); | |
2166 | video_unregister_device(&dev->vfd); | |
2167 | v4l2_device_unregister(&dev->v4l2_dev); | |
2168 | vb2_dma_contig_cleanup_ctx(dev->alloc_ctx); | |
2169 | ||
2170 | vpe_set_clock_enable(dev, 0); | |
2171 | vpe_runtime_put(pdev); | |
2172 | pm_runtime_disable(&pdev->dev); | |
2173 | ||
2174 | return 0; | |
2175 | } | |
2176 | ||
2177 | #if defined(CONFIG_OF) | |
2178 | static const struct of_device_id vpe_of_match[] = { | |
2179 | { | |
2180 | .compatible = "ti,vpe", | |
2181 | }, | |
2182 | {}, | |
2183 | }; | |
2184 | #else | |
2185 | #define vpe_of_match NULL | |
2186 | #endif | |
2187 | ||
2188 | static struct platform_driver vpe_pdrv = { | |
2189 | .probe = vpe_probe, | |
2190 | .remove = vpe_remove, | |
2191 | .driver = { | |
2192 | .name = VPE_MODULE_NAME, | |
2193 | .owner = THIS_MODULE, | |
2194 | .of_match_table = vpe_of_match, | |
2195 | }, | |
2196 | }; | |
2197 | ||
903cbb83 | 2198 | module_platform_driver(vpe_pdrv); |
45719127 AT |
2199 | |
2200 | MODULE_DESCRIPTION("TI VPE driver"); | |
2201 | MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>"); | |
2202 | MODULE_LICENSE("GPL"); |