[deliverable/linux.git] / drivers / media / platform / vsp1 / vsp1_bru.c

/*
 * vsp1_bru.c  --  R-Car VSP1 Blend ROP Unit
 *
 * Copyright (C) 2013 Renesas Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/device.h>
#include <linux/gfp.h>

#include <media/v4l2-subdev.h>

#include "vsp1.h"
#include "vsp1_bru.h"
#include "vsp1_dl.h"
#include "vsp1_rwpf.h"
#include "vsp1_video.h"

#define BRU_MIN_SIZE				1U
#define BRU_MAX_SIZE				8190U

/* -----------------------------------------------------------------------------
 * Device Access
 */

static inline void vsp1_bru_write(struct vsp1_bru *bru, struct vsp1_dl_list *dl,
				  u32 reg, u32 data)
{
	vsp1_dl_list_write(dl, reg, data);
}

/* -----------------------------------------------------------------------------
 * Controls
 */

static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct vsp1_bru *bru =
		container_of(ctrl->handler, struct vsp1_bru, ctrls);

	switch (ctrl->id) {
	case V4L2_CID_BG_COLOR:
		bru->bgcolor = ctrl->val;
		break;
	}

	return 0;
}

static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	.s_ctrl = bru_s_ctrl,
};

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Operations
 */

/*
 * The BRU can't perform format conversion, all sink and source formats must be
 * identical. We pick the format on the first sink pad (pad 0) and propagate it
 * to all other pads.
 */

static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
			      struct v4l2_subdev_pad_config *cfg,
			      struct v4l2_subdev_mbus_code_enum *code)
{
	static const unsigned int codes[] = {
		MEDIA_BUS_FMT_ARGB8888_1X32,
		MEDIA_BUS_FMT_AYUV8_1X32,
	};
	struct vsp1_bru *bru = to_bru(subdev);

	if (code->pad == BRU_PAD_SINK(0)) {
		if (code->index >= ARRAY_SIZE(codes))
			return -EINVAL;

		code->code = codes[code->index];
	} else {
		struct v4l2_subdev_pad_config *config;
		struct v4l2_mbus_framefmt *format;

		if (code->index)
			return -EINVAL;

		config = vsp1_entity_get_pad_config(&bru->entity, cfg,
						    code->which);
		if (!config)
			return -EINVAL;

		format = vsp1_entity_get_pad_format(&bru->entity, config,
						    BRU_PAD_SINK(0));
		code->code = format->code;
	}

	return 0;
}

static int bru_enum_frame_size(struct v4l2_subdev *subdev,
			       struct v4l2_subdev_pad_config *cfg,
			       struct v4l2_subdev_frame_size_enum *fse)
{
	if (fse->index)
		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	    fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
		return -EINVAL;

	fse->min_width = BRU_MIN_SIZE;
	fse->max_width = BRU_MAX_SIZE;
	fse->min_height = BRU_MIN_SIZE;
	fse->max_height = BRU_MAX_SIZE;

	return 0;
}

static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
					 struct v4l2_subdev_pad_config *cfg,
					 unsigned int pad)
{
	return v4l2_subdev_get_try_compose(&bru->entity.subdev, cfg, pad);
}

static int bru_get_format(struct v4l2_subdev *subdev,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	if (!config)
		return -EINVAL;

	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, config,
						  fmt->pad);

	return 0;
}

static void bru_try_format(struct vsp1_bru *bru,
			   struct v4l2_subdev_pad_config *config,
			   unsigned int pad, struct v4l2_mbus_framefmt *fmt)
{
	struct v4l2_mbus_framefmt *format;

	switch (pad) {
	case BRU_PAD_SINK(0):
		/* Default to YUV if the requested format is not supported. */
		if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
		    fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
			fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
		break;

	default:
		/* The BRU can't perform format conversion. */
		format = vsp1_entity_get_pad_format(&bru->entity, config,
						    BRU_PAD_SINK(0));
		fmt->code = format->code;
		break;
	}

	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->field = V4L2_FIELD_NONE;
	fmt->colorspace = V4L2_COLORSPACE_SRGB;
}

static int bru_set_format(struct v4l2_subdev *subdev,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;
	struct v4l2_mbus_framefmt *format;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	if (!config)
		return -EINVAL;

	bru_try_format(bru, config, fmt->pad, &fmt->format);

	format = vsp1_entity_get_pad_format(&bru->entity, config, fmt->pad);
	*format = fmt->format;

	/* Reset the compose rectangle */
	if (fmt->pad != bru->entity.source_pad) {
		struct v4l2_rect *compose;

		compose = bru_get_compose(bru, config, fmt->pad);
		compose->left = 0;
		compose->top = 0;
		compose->width = format->width;
		compose->height = format->height;
	}

	/* Propagate the format code to all pads */
	if (fmt->pad == BRU_PAD_SINK(0)) {
		unsigned int i;

		for (i = 0; i <= bru->entity.source_pad; ++i) {
			format = vsp1_entity_get_pad_format(&bru->entity,
							    config, i);
			format->code = fmt->format.code;
		}
	}

	return 0;
}

static int bru_get_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	switch (sel->target) {
	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
		sel->r.left = 0;
		sel->r.top = 0;
		sel->r.width = BRU_MAX_SIZE;
		sel->r.height = BRU_MAX_SIZE;
		return 0;

	case V4L2_SEL_TGT_COMPOSE:
		config = vsp1_entity_get_pad_config(&bru->entity, cfg,
						    sel->which);
		if (!config)
			return -EINVAL;

		sel->r = *bru_get_compose(bru, config, sel->pad);
		return 0;

	default:
		return -EINVAL;
	}
}

static int bru_set_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;
	struct v4l2_mbus_framefmt *format;
	struct v4l2_rect *compose;

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	if (sel->target != V4L2_SEL_TGT_COMPOSE)
		return -EINVAL;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, sel->which);
	if (!config)
		return -EINVAL;

	/* The compose rectangle top left corner must be inside the output
	 * frame.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, config,
					    bru->entity.source_pad);
	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);

	/* Scaling isn't supported, the compose rectangle size must be identical
	 * to the sink format size.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad);
	sel->r.width = format->width;
	sel->r.height = format->height;

	compose = bru_get_compose(bru, config, sel->pad);
	*compose = sel->r;

	return 0;
}

static struct v4l2_subdev_pad_ops bru_pad_ops = {
	.init_cfg = vsp1_entity_init_cfg,
	.enum_mbus_code = bru_enum_mbus_code,
	.enum_frame_size = bru_enum_frame_size,
	.get_fmt = bru_get_format,
	.set_fmt = bru_set_format,
	.get_selection = bru_get_selection,
	.set_selection = bru_set_selection,
};

static struct v4l2_subdev_ops bru_ops = {
	.pad    = &bru_pad_ops,
};

/* -----------------------------------------------------------------------------
 * VSP1 Entity Operations
 */

static void bru_configure(struct vsp1_entity *entity,
			  struct vsp1_pipeline *pipe,
			  struct vsp1_dl_list *dl)
{
	struct vsp1_bru *bru = to_bru(&entity->subdev);
	struct v4l2_mbus_framefmt *format;
	unsigned int flags;
	unsigned int i;

	format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config,
					    bru->entity.source_pad);

	/* The hardware is extremely flexible but we have no userspace API to
	 * expose all the parameters, nor is it clear whether we would have use
	 * cases for all the supported modes. Let's just harcode the parameters
	 * to sane default values for now.
	 */

	/* Disable dithering and enable color data normalization unless the
	 * format at the pipeline output is premultiplied.
	 */
	flags = pipe->output ? pipe->output->format.flags : 0;
	vsp1_bru_write(bru, dl, VI6_BRU_INCTRL,
		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
		       0 : VI6_BRU_INCTRL_NRM);

	/* Set the background position to cover the whole output image and
	 * configure its color.
	 */
	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_SIZE,
		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_LOC, 0);

	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_COL, bru->bgcolor |
		       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));

	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	 * unit with a NOP operation to make BRU input 1 available as the
	 * Blend/ROP unit B SRC input.
	 */
	vsp1_bru_write(bru, dl, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) |
		       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
		       VI6_BRU_ROP_AROP(VI6_ROP_NOP));

	for (i = 0; i < bru->entity.source_pad; ++i) {
		bool premultiplied = false;
		u32 ctrl = 0;

		/* Configure all Blend/ROP units corresponding to an enabled BRU
		 * input for alpha blending. Blend/ROP units corresponding to
		 * disabled BRU inputs are used in ROP NOP mode to ignore the
		 * SRC input.
		 */
		if (bru->inputs[i].rpf) {
			ctrl |= VI6_BRU_CTRL_RBC;

			premultiplied = bru->inputs[i].rpf->format.flags
				      & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
		} else {
			ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
			     |  VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
		}

		/* Select the virtual RPF as the Blend/ROP unit A DST input to
		 * serve as a background color.
		 */
		if (i == 0)
			ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;

		/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
		 * D in that order. The Blend/ROP unit B SRC is hardwired to the
		 * ROP unit output, the corresponding register bits must be set
		 * to 0.
		 */
		if (i != 1)
			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);

		vsp1_bru_write(bru, dl, VI6_BRU_CTRL(i), ctrl);

		/* Harcode the blending formula to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * when the SRC input isn't premultiplied, and to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * otherwise.
		 */
		vsp1_bru_write(bru, dl, VI6_BRU_BLD(i),
			       VI6_BRU_BLD_CCMDX_255_SRC_A |
			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
						VI6_BRU_BLD_CCMDY_SRC_A) |
			       VI6_BRU_BLD_ACMDX_255_SRC_A |
			       VI6_BRU_BLD_ACMDY_COEFY |
			       (0xff << VI6_BRU_BLD_COEFY_SHIFT));
	}
}

static const struct vsp1_entity_operations bru_entity_ops = {
	.configure = bru_configure,
};

/* -----------------------------------------------------------------------------
 * Initialization and Cleanup
 */

struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1)
{
	struct vsp1_bru *bru;
	int ret;

	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	if (bru == NULL)
		return ERR_PTR(-ENOMEM);

	bru->entity.ops = &bru_entity_ops;
	bru->entity.type = VSP1_ENTITY_BRU;

	ret = vsp1_entity_init(vsp1, &bru->entity, "bru",
			       vsp1->info->num_bru_inputs + 1, &bru_ops);
	if (ret < 0)
		return ERR_PTR(ret);

	/* Initialize the control handler. */
	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
			  0, 0xffffff, 1, 0);

	bru->bgcolor = 0;

	bru->entity.subdev.ctrl_handler = &bru->ctrls;

	if (bru->ctrls.error) {
		dev_err(vsp1->dev, "bru: failed to initialize controls\n");
		ret = bru->ctrls.error;
		vsp1_entity_destroy(&bru->entity);
		return ERR_PTR(ret);
	}

	return bru;
}
Commit	Line	Data
629bb6d4 LP	1	/*
	2	* vsp1_bru.c -- R-Car VSP1 Blend ROP Unit
	3	*
	4	* Copyright (C) 2013 Renesas Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/gfp.h>
	16
	17	#include <media/v4l2-subdev.h>
	18
	19	#include "vsp1.h"
	20	#include "vsp1_bru.h"
5e8dbbf3	21	#include "vsp1_dl.h"
6418b4d6	22	#include "vsp1_rwpf.h"
9d40637a	23	#include "vsp1_video.h"
629bb6d4	24
8cb0b634	25	#define BRU_MIN_SIZE 1U
629bb6d4 LP	26	#define BRU_MAX_SIZE 8190U
	27
	28	/* -----------------------------------------------------------------------------
	29	* Device Access
	30	*/
	31
5e8dbbf3 LP	32	static inline void vsp1_bru_write(struct vsp1_bru bru, struct vsp1_dl_list dl,
5e8dbbf3 LP	33	u32 reg, u32 data)
629bb6d4	34	{
5e8dbbf3	35	vsp1_dl_list_write(dl, reg, data);
629bb6d4 LP	36	}
629bb6d4 LP	37
a16e2794 LP	38	/* -----------------------------------------------------------------------------
	39	* Controls
	40	*/
	41
	42	static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
	43	{
	44	struct vsp1_bru *bru =
	45	container_of(ctrl->handler, struct vsp1_bru, ctrls);
	46
a16e2794 LP	47	switch (ctrl->id) {
a16e2794 LP	48	case V4L2_CID_BG_COLOR:
f22af945	49	bru->bgcolor = ctrl->val;
a16e2794 LP	50	break;
	51	}
	52
	53	return 0;
	54	}
	55
	56	static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	57	.s_ctrl = bru_s_ctrl,
	58	};
	59
629bb6d4	60	/* -----------------------------------------------------------------------------
7b905f05	61	* V4L2 Subdevice Operations
629bb6d4 LP	62	*/
	63
	64	/*
	65	* The BRU can't perform format conversion, all sink and source formats must be
	66	* identical. We pick the format on the first sink pad (pad 0) and propagate it
	67	* to all other pads.
	68	*/
	69
	70	static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
f7234138	71	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	72	struct v4l2_subdev_mbus_code_enum *code)
	73	{
	74	static const unsigned int codes[] = {
27ffaeb0 BB	75	MEDIA_BUS_FMT_ARGB8888_1X32,
27ffaeb0 BB	76	MEDIA_BUS_FMT_AYUV8_1X32,
629bb6d4	77	};
3f1ccf16	78	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	79
	80	if (code->pad == BRU_PAD_SINK(0)) {
	81	if (code->index >= ARRAY_SIZE(codes))
	82	return -EINVAL;
	83
	84	code->code = codes[code->index];
	85	} else {
e790c3cb LP	86	struct v4l2_subdev_pad_config *config;
	87	struct v4l2_mbus_framefmt *format;
	88
629bb6d4 LP	89	if (code->index)
	90	return -EINVAL;
	91
e790c3cb	92	config = vsp1_entity_get_pad_config(&bru->entity, cfg,
1bd0a1bd	93	code->which);
e790c3cb LP	94	if (!config)
	95	return -EINVAL;
	96
	97	format = vsp1_entity_get_pad_format(&bru->entity, config,
	98	BRU_PAD_SINK(0));
629bb6d4 LP	99	code->code = format->code;
	100	}
	101
	102	return 0;
	103	}
	104
	105	static int bru_enum_frame_size(struct v4l2_subdev *subdev,
f7234138	106	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	107	struct v4l2_subdev_frame_size_enum *fse)
	108	{
	109	if (fse->index)
	110	return -EINVAL;
	111
27ffaeb0 BB	112	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
27ffaeb0 BB	113	fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
629bb6d4 LP	114	return -EINVAL;
	115
	116	fse->min_width = BRU_MIN_SIZE;
	117	fse->max_width = BRU_MAX_SIZE;
	118	fse->min_height = BRU_MIN_SIZE;
	119	fse->max_height = BRU_MAX_SIZE;
	120
	121	return 0;
	122	}
	123
	124	static struct v4l2_rect bru_get_compose(struct vsp1_bru bru,
f7234138	125	struct v4l2_subdev_pad_config *cfg,
b7e5107e	126	unsigned int pad)
629bb6d4	127	{
b7e5107e	128	return v4l2_subdev_get_try_compose(&bru->entity.subdev, cfg, pad);
629bb6d4 LP	129	}
629bb6d4 LP	130
1bd0a1bd LP	131	static int bru_get_format(struct v4l2_subdev *subdev,
1bd0a1bd LP	132	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	133	struct v4l2_subdev_format *fmt)
	134	{
	135	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb LP	136	struct v4l2_subdev_pad_config *config;
	137
	138	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	139	if (!config)
	140	return -EINVAL;
629bb6d4	141
e790c3cb LP	142	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	143	fmt->pad);
629bb6d4 LP	144
	145	return 0;
	146	}
	147
1bd0a1bd	148	static void bru_try_format(struct vsp1_bru *bru,
e790c3cb LP	149	struct v4l2_subdev_pad_config *config,
e790c3cb LP	150	unsigned int pad, struct v4l2_mbus_framefmt *fmt)
629bb6d4 LP	151	{
	152	struct v4l2_mbus_framefmt *format;
	153
	154	switch (pad) {
	155	case BRU_PAD_SINK(0):
	156	/* Default to YUV if the requested format is not supported. */
27ffaeb0 BB	157	if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	158	fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
	159	fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
629bb6d4 LP	160	break;
	161
	162	default:
	163	/* The BRU can't perform format conversion. */
e790c3cb LP	164	format = vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	165	BRU_PAD_SINK(0));
629bb6d4 LP	166	fmt->code = format->code;
	167	break;
	168	}
	169
	170	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	171	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	172	fmt->field = V4L2_FIELD_NONE;
	173	fmt->colorspace = V4L2_COLORSPACE_SRGB;
	174	}
	175
1bd0a1bd LP	176	static int bru_set_format(struct v4l2_subdev *subdev,
1bd0a1bd LP	177	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	178	struct v4l2_subdev_format *fmt)
	179	{
	180	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb	181	struct v4l2_subdev_pad_config *config;
629bb6d4 LP	182	struct v4l2_mbus_framefmt *format;
629bb6d4 LP	183
e790c3cb LP	184	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	185	if (!config)
	186	return -EINVAL;
	187
	188	bru_try_format(bru, config, fmt->pad, &fmt->format);
629bb6d4	189
e790c3cb	190	format = vsp1_entity_get_pad_format(&bru->entity, config, fmt->pad);
629bb6d4 LP	191	*format = fmt->format;
	192
	193	/* Reset the compose rectangle */
a96c5fa4	194	if (fmt->pad != bru->entity.source_pad) {
629bb6d4 LP	195	struct v4l2_rect *compose;
629bb6d4 LP	196
b7e5107e	197	compose = bru_get_compose(bru, config, fmt->pad);
629bb6d4 LP	198	compose->left = 0;
	199	compose->top = 0;
	200	compose->width = format->width;
	201	compose->height = format->height;
	202	}
	203
	204	/* Propagate the format code to all pads */
	205	if (fmt->pad == BRU_PAD_SINK(0)) {
	206	unsigned int i;
	207
a96c5fa4	208	for (i = 0; i <= bru->entity.source_pad; ++i) {
e790c3cb LP	209	format = vsp1_entity_get_pad_format(&bru->entity,
e790c3cb LP	210	config, i);
629bb6d4 LP	211	format->code = fmt->format.code;
	212	}
	213	}
	214
	215	return 0;
	216	}
	217
	218	static int bru_get_selection(struct v4l2_subdev *subdev,
f7234138	219	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	220	struct v4l2_subdev_selection *sel)
	221	{
	222	struct vsp1_bru *bru = to_bru(subdev);
b7e5107e	223	struct v4l2_subdev_pad_config *config;
629bb6d4	224
a96c5fa4	225	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	226	return -EINVAL;
	227
	228	switch (sel->target) {
	229	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	230	sel->r.left = 0;
	231	sel->r.top = 0;
	232	sel->r.width = BRU_MAX_SIZE;
	233	sel->r.height = BRU_MAX_SIZE;
	234	return 0;
	235
	236	case V4L2_SEL_TGT_COMPOSE:
b7e5107e LP	237	config = vsp1_entity_get_pad_config(&bru->entity, cfg,
	238	sel->which);
	239	if (!config)
	240	return -EINVAL;
	241
	242	sel->r = *bru_get_compose(bru, config, sel->pad);
629bb6d4 LP	243	return 0;
	244
	245	default:
	246	return -EINVAL;
	247	}
	248	}
	249
	250	static int bru_set_selection(struct v4l2_subdev *subdev,
f7234138	251	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	252	struct v4l2_subdev_selection *sel)
	253	{
	254	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb	255	struct v4l2_subdev_pad_config *config;
629bb6d4 LP	256	struct v4l2_mbus_framefmt *format;
	257	struct v4l2_rect *compose;
	258
a96c5fa4	259	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	260	return -EINVAL;
	261
	262	if (sel->target != V4L2_SEL_TGT_COMPOSE)
	263	return -EINVAL;
	264
e790c3cb LP	265	config = vsp1_entity_get_pad_config(&bru->entity, cfg, sel->which);
	266	if (!config)
	267	return -EINVAL;
	268
629bb6d4 LP	269	/* The compose rectangle top left corner must be inside the output
	270	* frame.
	271	*/
e790c3cb LP	272	format = vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	273	bru->entity.source_pad);
629bb6d4 LP	274	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	275	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
	276
	277	/* Scaling isn't supported, the compose rectangle size must be identical
	278	* to the sink format size.
	279	*/
e790c3cb	280	format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad);
629bb6d4 LP	281	sel->r.width = format->width;
	282	sel->r.height = format->height;
	283
b7e5107e	284	compose = bru_get_compose(bru, config, sel->pad);
629bb6d4 LP	285	*compose = sel->r;
	286
	287	return 0;
	288	}
	289
629bb6d4	290	static struct v4l2_subdev_pad_ops bru_pad_ops = {
0efdf0f5	291	.init_cfg = vsp1_entity_init_cfg,
629bb6d4 LP	292	.enum_mbus_code = bru_enum_mbus_code,
	293	.enum_frame_size = bru_enum_frame_size,
	294	.get_fmt = bru_get_format,
	295	.set_fmt = bru_set_format,
	296	.get_selection = bru_get_selection,
	297	.set_selection = bru_set_selection,
	298	};
	299
	300	static struct v4l2_subdev_ops bru_ops = {
629bb6d4 LP	301	.pad = &bru_pad_ops,
	302	};
	303
7b905f05 LP	304	/* -----------------------------------------------------------------------------
	305	* VSP1 Entity Operations
	306	*/
	307
83dd019d LP	308	static void bru_configure(struct vsp1_entity *entity,
	309	struct vsp1_pipeline *pipe,
	310	struct vsp1_dl_list *dl)
7b905f05	311	{
7b905f05 LP	312	struct vsp1_bru *bru = to_bru(&entity->subdev);
	313	struct v4l2_mbus_framefmt *format;
	314	unsigned int flags;
	315	unsigned int i;
	316
	317	format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config,
	318	bru->entity.source_pad);
	319
	320	/* The hardware is extremely flexible but we have no userspace API to
	321	* expose all the parameters, nor is it clear whether we would have use
	322	* cases for all the supported modes. Let's just harcode the parameters
	323	* to sane default values for now.
	324	*/
	325
	326	/* Disable dithering and enable color data normalization unless the
	327	* format at the pipeline output is premultiplied.
	328	*/
	329	flags = pipe->output ? pipe->output->format.flags : 0;
5e8dbbf3	330	vsp1_bru_write(bru, dl, VI6_BRU_INCTRL,
7b905f05 LP	331	flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
	332	0 : VI6_BRU_INCTRL_NRM);
	333
	334	/* Set the background position to cover the whole output image and
	335	* configure its color.
	336	*/
5e8dbbf3	337	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_SIZE,
7b905f05 LP	338	(format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) \|
7b905f05 LP	339	(format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
5e8dbbf3	340	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_LOC, 0);
7b905f05	341
5e8dbbf3	342	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_COL, bru->bgcolor \|
7b905f05 LP	343	(0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
	344
	345	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	346	* unit with a NOP operation to make BRU input 1 available as the
	347	* Blend/ROP unit B SRC input.
	348	*/
5e8dbbf3	349	vsp1_bru_write(bru, dl, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) \|
7b905f05 LP	350	VI6_BRU_ROP_CROP(VI6_ROP_NOP) \|
	351	VI6_BRU_ROP_AROP(VI6_ROP_NOP));
	352
	353	for (i = 0; i < bru->entity.source_pad; ++i) {
	354	bool premultiplied = false;
	355	u32 ctrl = 0;
	356
	357	/* Configure all Blend/ROP units corresponding to an enabled BRU
	358	* input for alpha blending. Blend/ROP units corresponding to
	359	* disabled BRU inputs are used in ROP NOP mode to ignore the
	360	* SRC input.
	361	*/
	362	if (bru->inputs[i].rpf) {
	363	ctrl \|= VI6_BRU_CTRL_RBC;
	364
	365	premultiplied = bru->inputs[i].rpf->format.flags
	366	& V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
	367	} else {
	368	ctrl \|= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
	369	\| VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
	370	}
	371
	372	/* Select the virtual RPF as the Blend/ROP unit A DST input to
	373	* serve as a background color.
	374	*/
	375	if (i == 0)
	376	ctrl \|= VI6_BRU_CTRL_DSTSEL_VRPF;
	377
	378	/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
	379	* D in that order. The Blend/ROP unit B SRC is hardwired to the
	380	* ROP unit output, the corresponding register bits must be set
	381	* to 0.
	382	*/
	383	if (i != 1)
	384	ctrl \|= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
	385
5e8dbbf3	386	vsp1_bru_write(bru, dl, VI6_BRU_CTRL(i), ctrl);
7b905f05 LP	387
	388	/* Harcode the blending formula to
	389	*
	390	* DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
	391	* DSTa = DSTa * (1 - SRCa) + SRCa
	392	*
	393	* when the SRC input isn't premultiplied, and to
	394	*
	395	* DSTc = DSTc * (1 - SRCa) + SRCc
	396	* DSTa = DSTa * (1 - SRCa) + SRCa
	397	*
	398	* otherwise.
	399	*/
5e8dbbf3	400	vsp1_bru_write(bru, dl, VI6_BRU_BLD(i),
7b905f05 LP	401	VI6_BRU_BLD_CCMDX_255_SRC_A \|
	402	(premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
	403	VI6_BRU_BLD_CCMDY_SRC_A) \|
	404	VI6_BRU_BLD_ACMDX_255_SRC_A \|
	405	VI6_BRU_BLD_ACMDY_COEFY \|
	406	(0xff << VI6_BRU_BLD_COEFY_SHIFT));
	407	}
	408	}
	409
	410	static const struct vsp1_entity_operations bru_entity_ops = {
	411	.configure = bru_configure,
	412	};
	413
629bb6d4 LP	414	/* -----------------------------------------------------------------------------
	415	* Initialization and Cleanup
	416	*/
	417
	418	struct vsp1_bru vsp1_bru_create(struct vsp1_device vsp1)
	419	{
629bb6d4 LP	420	struct vsp1_bru *bru;
	421	int ret;
	422
	423	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	424	if (bru == NULL)
	425	return ERR_PTR(-ENOMEM);
	426
7b905f05	427	bru->entity.ops = &bru_entity_ops;
629bb6d4 LP	428	bru->entity.type = VSP1_ENTITY_BRU;
629bb6d4 LP	429
823329df LP	430	ret = vsp1_entity_init(vsp1, &bru->entity, "bru",
823329df LP	431	vsp1->info->num_bru_inputs + 1, &bru_ops);
629bb6d4 LP	432	if (ret < 0)
	433	return ERR_PTR(ret);
	434
a16e2794 LP	435	/* Initialize the control handler. */
	436	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	437	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
	438	0, 0xffffff, 1, 0);
	439
f22af945 LP	440	bru->bgcolor = 0;
f22af945 LP	441
a16e2794 LP	442	bru->entity.subdev.ctrl_handler = &bru->ctrls;
	443
	444	if (bru->ctrls.error) {
	445	dev_err(vsp1->dev, "bru: failed to initialize controls\n");
	446	ret = bru->ctrls.error;
	447	vsp1_entity_destroy(&bru->entity);
	448	return ERR_PTR(ret);
	449	}
	450
629bb6d4 LP	451	return bru;
629bb6d4 LP	452	}