[deliverable/linux.git] / drivers / media / platform / vsp1 / vsp1_bru.c

/*
 * vsp1_bru.c  --  R-Car VSP1 Blend ROP Unit
 *
 * Copyright (C) 2013 Renesas Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/device.h>
#include <linux/gfp.h>

#include <media/v4l2-subdev.h>

#include "vsp1.h"
#include "vsp1_bru.h"
#include "vsp1_rwpf.h"
#include "vsp1_video.h"

#define BRU_MIN_SIZE				1U
#define BRU_MAX_SIZE				8190U

/* -----------------------------------------------------------------------------
 * Device Access
 */

static inline u32 vsp1_bru_read(struct vsp1_bru *bru, u32 reg)
{
	return vsp1_read(bru->entity.vsp1, reg);
}

static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
{
	vsp1_write(bru->entity.vsp1, reg, data);
}

/* -----------------------------------------------------------------------------
 * Controls
 */

static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct vsp1_bru *bru =
		container_of(ctrl->handler, struct vsp1_bru, ctrls);

	if (!vsp1_entity_is_streaming(&bru->entity))
		return 0;

	switch (ctrl->id) {
	case V4L2_CID_BG_COLOR:
		vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, ctrl->val |
			       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
		break;
	}

	return 0;
}

static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	.s_ctrl = bru_s_ctrl,
};

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Core Operations
 */

static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
{
	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;
	unsigned int flags;
	unsigned int i;
	int ret;

	ret = vsp1_entity_set_streaming(&bru->entity, enable);
	if (ret < 0)
		return ret;

	if (!enable)
		return 0;

	format = &bru->entity.formats[BRU_PAD_SOURCE];

	/* The hardware is extremely flexible but we have no userspace API to
	 * expose all the parameters, nor is it clear whether we would have use
	 * cases for all the supported modes. Let's just harcode the parameters
	 * to sane default values for now.
	 */

	/* Disable dithering and enable color data normalization unless the
	 * format at the pipeline output is premultiplied.
	 */
	flags = pipe->output ? pipe->output->format.flags : 0;
	vsp1_bru_write(bru, VI6_BRU_INCTRL,
		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
		       0 : VI6_BRU_INCTRL_NRM);

	/* Set the background position to cover the whole output image. */
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);

	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	 * unit with a NOP operation to make BRU input 1 available as the
	 * Blend/ROP unit B SRC input.
	 */
	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) |
		       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
		       VI6_BRU_ROP_AROP(VI6_ROP_NOP));

	for (i = 0; i < 4; ++i) {
		bool premultiplied = false;
		u32 ctrl = 0;

		/* Configure all Blend/ROP units corresponding to an enabled BRU
		 * input for alpha blending. Blend/ROP units corresponding to
		 * disabled BRU inputs are used in ROP NOP mode to ignore the
		 * SRC input.
		 */
		if (bru->inputs[i].rpf) {
			ctrl |= VI6_BRU_CTRL_RBC;

			premultiplied = bru->inputs[i].rpf->format.flags
				      & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
		} else {
			ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
			     |  VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
		}

		/* Select the virtual RPF as the Blend/ROP unit A DST input to
		 * serve as a background color.
		 */
		if (i == 0)
			ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;

		/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
		 * D in that order. The Blend/ROP unit B SRC is hardwired to the
		 * ROP unit output, the corresponding register bits must be set
		 * to 0.
		 */
		if (i != 1)
			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);

		vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);

		/* Harcode the blending formula to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * when the SRC input isn't premultiplied, and to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * otherwise.
		 */
		vsp1_bru_write(bru, VI6_BRU_BLD(i),
			       VI6_BRU_BLD_CCMDX_255_SRC_A |
			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
						VI6_BRU_BLD_CCMDY_SRC_A) |
			       VI6_BRU_BLD_ACMDX_255_SRC_A |
			       VI6_BRU_BLD_ACMDY_COEFY |
			       (0xff << VI6_BRU_BLD_COEFY_SHIFT));
	}

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Pad Operations
 */

/*
 * The BRU can't perform format conversion, all sink and source formats must be
 * identical. We pick the format on the first sink pad (pad 0) and propagate it
 * to all other pads.
 */

static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
			      struct v4l2_subdev_pad_config *cfg,
			      struct v4l2_subdev_mbus_code_enum *code)
{
	static const unsigned int codes[] = {
		MEDIA_BUS_FMT_ARGB8888_1X32,
		MEDIA_BUS_FMT_AYUV8_1X32,
	};
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;

	if (code->pad == BRU_PAD_SINK(0)) {
		if (code->index >= ARRAY_SIZE(codes))
			return -EINVAL;

		code->code = codes[code->index];
	} else {
		if (code->index)
			return -EINVAL;

		format = vsp1_entity_get_pad_format(&bru->entity, cfg,
						    BRU_PAD_SINK(0), code->which);
		code->code = format->code;
	}

	return 0;
}

static int bru_enum_frame_size(struct v4l2_subdev *subdev,
			       struct v4l2_subdev_pad_config *cfg,
			       struct v4l2_subdev_frame_size_enum *fse)
{
	if (fse->index)
		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	    fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
		return -EINVAL;

	fse->min_width = BRU_MIN_SIZE;
	fse->max_width = BRU_MAX_SIZE;
	fse->min_height = BRU_MIN_SIZE;
	fse->max_height = BRU_MAX_SIZE;

	return 0;
}

static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
					 struct v4l2_subdev_pad_config *cfg,
					 unsigned int pad, u32 which)
{
	switch (which) {
	case V4L2_SUBDEV_FORMAT_TRY:
		return v4l2_subdev_get_try_crop(&bru->entity.subdev, cfg, pad);
	case V4L2_SUBDEV_FORMAT_ACTIVE:
		return &bru->inputs[pad].compose;
	default:
		return NULL;
	}
}

static int bru_get_format(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);

	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
						  fmt->which);

	return 0;
}

static void bru_try_format(struct vsp1_bru *bru, struct v4l2_subdev_pad_config *cfg,
			   unsigned int pad, struct v4l2_mbus_framefmt *fmt,
			   enum v4l2_subdev_format_whence which)
{
	struct v4l2_mbus_framefmt *format;

	switch (pad) {
	case BRU_PAD_SINK(0):
		/* Default to YUV if the requested format is not supported. */
		if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
		    fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
			fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
		break;

	default:
		/* The BRU can't perform format conversion. */
		format = vsp1_entity_get_pad_format(&bru->entity, cfg,
						    BRU_PAD_SINK(0), which);
		fmt->code = format->code;
		break;
	}

	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->field = V4L2_FIELD_NONE;
	fmt->colorspace = V4L2_COLORSPACE_SRGB;
}

static int bru_set_format(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;

	bru_try_format(bru, cfg, fmt->pad, &fmt->format, fmt->which);

	format = vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
					    fmt->which);
	*format = fmt->format;

	/* Reset the compose rectangle */
	if (fmt->pad != BRU_PAD_SOURCE) {
		struct v4l2_rect *compose;

		compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
		compose->left = 0;
		compose->top = 0;
		compose->width = format->width;
		compose->height = format->height;
	}

	/* Propagate the format code to all pads */
	if (fmt->pad == BRU_PAD_SINK(0)) {
		unsigned int i;

		for (i = 0; i <= BRU_PAD_SOURCE; ++i) {
			format = vsp1_entity_get_pad_format(&bru->entity, cfg,
							    i, fmt->which);
			format->code = fmt->format.code;
		}
	}

	return 0;
}

static int bru_get_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);

	if (sel->pad == BRU_PAD_SOURCE)
		return -EINVAL;

	switch (sel->target) {
	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
		sel->r.left = 0;
		sel->r.top = 0;
		sel->r.width = BRU_MAX_SIZE;
		sel->r.height = BRU_MAX_SIZE;
		return 0;

	case V4L2_SEL_TGT_COMPOSE:
		sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
		return 0;

	default:
		return -EINVAL;
	}
}

static int bru_set_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;
	struct v4l2_rect *compose;

	if (sel->pad == BRU_PAD_SOURCE)
		return -EINVAL;

	if (sel->target != V4L2_SEL_TGT_COMPOSE)
		return -EINVAL;

	/* The compose rectangle top left corner must be inside the output
	 * frame.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, cfg, BRU_PAD_SOURCE,
					    sel->which);
	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);

	/* Scaling isn't supported, the compose rectangle size must be identical
	 * to the sink format size.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, cfg, sel->pad,
					    sel->which);
	sel->r.width = format->width;
	sel->r.height = format->height;

	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
	*compose = sel->r;

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Operations
 */

static struct v4l2_subdev_video_ops bru_video_ops = {
	.s_stream = bru_s_stream,
};

static struct v4l2_subdev_pad_ops bru_pad_ops = {
	.enum_mbus_code = bru_enum_mbus_code,
	.enum_frame_size = bru_enum_frame_size,
	.get_fmt = bru_get_format,
	.set_fmt = bru_set_format,
	.get_selection = bru_get_selection,
	.set_selection = bru_set_selection,
};

static struct v4l2_subdev_ops bru_ops = {
	.video	= &bru_video_ops,
	.pad    = &bru_pad_ops,
};

/* -----------------------------------------------------------------------------
 * Initialization and Cleanup
 */

struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1)
{
	struct v4l2_subdev *subdev;
	struct vsp1_bru *bru;
	int ret;

	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	if (bru == NULL)
		return ERR_PTR(-ENOMEM);

	bru->entity.type = VSP1_ENTITY_BRU;

	ret = vsp1_entity_init(vsp1, &bru->entity, 5);
	if (ret < 0)
		return ERR_PTR(ret);

	/* Initialize the V4L2 subdev. */
	subdev = &bru->entity.subdev;
	v4l2_subdev_init(subdev, &bru_ops);

	subdev->entity.ops = &vsp1_media_ops;
	subdev->internal_ops = &vsp1_subdev_internal_ops;
	snprintf(subdev->name, sizeof(subdev->name), "%s bru",
		 dev_name(vsp1->dev));
	v4l2_set_subdevdata(subdev, bru);
	subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;

	vsp1_entity_init_formats(subdev, NULL);

	/* Initialize the control handler. */
	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
			  0, 0xffffff, 1, 0);

	bru->entity.subdev.ctrl_handler = &bru->ctrls;

	if (bru->ctrls.error) {
		dev_err(vsp1->dev, "bru: failed to initialize controls\n");
		ret = bru->ctrls.error;
		vsp1_entity_destroy(&bru->entity);
		return ERR_PTR(ret);
	}

	return bru;
}
Commit	Line	Data
629bb6d4 LP	1	/*
	2	* vsp1_bru.c -- R-Car VSP1 Blend ROP Unit
	3	*
	4	* Copyright (C) 2013 Renesas Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/gfp.h>
	16
	17	#include <media/v4l2-subdev.h>
	18
	19	#include "vsp1.h"
	20	#include "vsp1_bru.h"
6418b4d6	21	#include "vsp1_rwpf.h"
9d40637a	22	#include "vsp1_video.h"
629bb6d4	23
8cb0b634	24	#define BRU_MIN_SIZE 1U
629bb6d4 LP	25	#define BRU_MAX_SIZE 8190U
	26
	27	/* -----------------------------------------------------------------------------
	28	* Device Access
	29	*/
	30
	31	static inline u32 vsp1_bru_read(struct vsp1_bru *bru, u32 reg)
	32	{
	33	return vsp1_read(bru->entity.vsp1, reg);
	34	}
	35
	36	static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
	37	{
	38	vsp1_write(bru->entity.vsp1, reg, data);
	39	}
	40
a16e2794 LP	41	/* -----------------------------------------------------------------------------
	42	* Controls
	43	*/
	44
	45	static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
	46	{
	47	struct vsp1_bru *bru =
	48	container_of(ctrl->handler, struct vsp1_bru, ctrls);
	49
	50	if (!vsp1_entity_is_streaming(&bru->entity))
	51	return 0;
	52
	53	switch (ctrl->id) {
	54	case V4L2_CID_BG_COLOR:
	55	vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, ctrl->val \|
	56	(0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
	57	break;
	58	}
	59
	60	return 0;
	61	}
	62
	63	static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	64	.s_ctrl = bru_s_ctrl,
	65	};
	66
629bb6d4 LP	67	/* -----------------------------------------------------------------------------
	68	* V4L2 Subdevice Core Operations
	69	*/
	70
629bb6d4 LP	71	static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
629bb6d4 LP	72	{
9aca813e	73	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
629bb6d4 LP	74	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	75	struct v4l2_mbus_framefmt *format;
9aca813e	76	unsigned int flags;
629bb6d4	77	unsigned int i;
a16e2794 LP	78	int ret;
	79
	80	ret = vsp1_entity_set_streaming(&bru->entity, enable);
	81	if (ret < 0)
	82	return ret;
629bb6d4 LP	83
	84	if (!enable)
	85	return 0;
	86
	87	format = &bru->entity.formats[BRU_PAD_SOURCE];
	88
	89	/* The hardware is extremely flexible but we have no userspace API to
	90	* expose all the parameters, nor is it clear whether we would have use
	91	* cases for all the supported modes. Let's just harcode the parameters
	92	* to sane default values for now.
	93	*/
	94
9aca813e LP	95	/* Disable dithering and enable color data normalization unless the
	96	* format at the pipeline output is premultiplied.
	97	*/
86960eec	98	flags = pipe->output ? pipe->output->format.flags : 0;
9aca813e LP	99	vsp1_bru_write(bru, VI6_BRU_INCTRL,
	100	flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
	101	0 : VI6_BRU_INCTRL_NRM);
629bb6d4	102
a16e2794	103	/* Set the background position to cover the whole output image. */
629bb6d4 LP	104	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
	105	(format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) \|
	106	(format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	107	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);
629bb6d4 LP	108
	109	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	110	* unit with a NOP operation to make BRU input 1 available as the
	111	* Blend/ROP unit B SRC input.
	112	*/
	113	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) \|
	114	VI6_BRU_ROP_CROP(VI6_ROP_NOP) \|
	115	VI6_BRU_ROP_AROP(VI6_ROP_NOP));
	116
	117	for (i = 0; i < 4; ++i) {
6418b4d6	118	bool premultiplied = false;
629bb6d4 LP	119	u32 ctrl = 0;
	120
	121	/* Configure all Blend/ROP units corresponding to an enabled BRU
	122	* input for alpha blending. Blend/ROP units corresponding to
	123	* disabled BRU inputs are used in ROP NOP mode to ignore the
	124	* SRC input.
	125	*/
6418b4d6	126	if (bru->inputs[i].rpf) {
629bb6d4	127	ctrl \|= VI6_BRU_CTRL_RBC;
6418b4d6	128
86960eec	129	premultiplied = bru->inputs[i].rpf->format.flags
6418b4d6 LP	130	& V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
6418b4d6 LP	131	} else {
629bb6d4 LP	132	ctrl \|= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
629bb6d4 LP	133	\| VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
6418b4d6	134	}
629bb6d4 LP	135
	136	/* Select the virtual RPF as the Blend/ROP unit A DST input to
	137	* serve as a background color.
	138	*/
	139	if (i == 0)
	140	ctrl \|= VI6_BRU_CTRL_DSTSEL_VRPF;
	141
	142	/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
	143	* D in that order. The Blend/ROP unit B SRC is hardwired to the
	144	* ROP unit output, the corresponding register bits must be set
	145	* to 0.
	146	*/
	147	if (i != 1)
	148	ctrl \|= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
	149
	150	vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);
	151
	152	/* Harcode the blending formula to
	153	*
	154	* DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
	155	* DSTa = DSTa * (1 - SRCa) + SRCa
6418b4d6 LP	156	*
	157	* when the SRC input isn't premultiplied, and to
	158	*
	159	* DSTc = DSTc * (1 - SRCa) + SRCc
	160	* DSTa = DSTa * (1 - SRCa) + SRCa
	161	*
	162	* otherwise.
629bb6d4 LP	163	*/
	164	vsp1_bru_write(bru, VI6_BRU_BLD(i),
	165	VI6_BRU_BLD_CCMDX_255_SRC_A \|
6418b4d6 LP	166	(premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
6418b4d6 LP	167	VI6_BRU_BLD_CCMDY_SRC_A) \|
629bb6d4 LP	168	VI6_BRU_BLD_ACMDX_255_SRC_A \|
	169	VI6_BRU_BLD_ACMDY_COEFY \|
	170	(0xff << VI6_BRU_BLD_COEFY_SHIFT));
	171	}
	172
	173	return 0;
	174	}
	175
	176	/* -----------------------------------------------------------------------------
	177	* V4L2 Subdevice Pad Operations
	178	*/
	179
	180	/*
	181	* The BRU can't perform format conversion, all sink and source formats must be
	182	* identical. We pick the format on the first sink pad (pad 0) and propagate it
	183	* to all other pads.
	184	*/
	185
	186	static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
f7234138	187	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	188	struct v4l2_subdev_mbus_code_enum *code)
	189	{
	190	static const unsigned int codes[] = {
27ffaeb0 BB	191	MEDIA_BUS_FMT_ARGB8888_1X32,
27ffaeb0 BB	192	MEDIA_BUS_FMT_AYUV8_1X32,
629bb6d4	193	};
3f1ccf16	194	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	195	struct v4l2_mbus_framefmt *format;
	196
	197	if (code->pad == BRU_PAD_SINK(0)) {
	198	if (code->index >= ARRAY_SIZE(codes))
	199	return -EINVAL;
	200
	201	code->code = codes[code->index];
	202	} else {
	203	if (code->index)
	204	return -EINVAL;
	205
3f1ccf16 HV	206	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
3f1ccf16 HV	207	BRU_PAD_SINK(0), code->which);
629bb6d4 LP	208	code->code = format->code;
	209	}
	210
	211	return 0;
	212	}
	213
	214	static int bru_enum_frame_size(struct v4l2_subdev *subdev,
f7234138	215	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	216	struct v4l2_subdev_frame_size_enum *fse)
	217	{
	218	if (fse->index)
	219	return -EINVAL;
	220
27ffaeb0 BB	221	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
27ffaeb0 BB	222	fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
629bb6d4 LP	223	return -EINVAL;
	224
	225	fse->min_width = BRU_MIN_SIZE;
	226	fse->max_width = BRU_MAX_SIZE;
	227	fse->min_height = BRU_MIN_SIZE;
	228	fse->max_height = BRU_MAX_SIZE;
	229
	230	return 0;
	231	}
	232
	233	static struct v4l2_rect bru_get_compose(struct vsp1_bru bru,
f7234138	234	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	235	unsigned int pad, u32 which)
	236	{
	237	switch (which) {
	238	case V4L2_SUBDEV_FORMAT_TRY:
f7234138	239	return v4l2_subdev_get_try_crop(&bru->entity.subdev, cfg, pad);
629bb6d4	240	case V4L2_SUBDEV_FORMAT_ACTIVE:
6418b4d6	241	return &bru->inputs[pad].compose;
629bb6d4 LP	242	default:
	243	return NULL;
	244	}
	245	}
	246
f7234138	247	static int bru_get_format(struct v4l2_subdev subdev, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	248	struct v4l2_subdev_format *fmt)
	249	{
	250	struct vsp1_bru *bru = to_bru(subdev);
	251
f7234138	252	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
629bb6d4 LP	253	fmt->which);
	254
	255	return 0;
	256	}
	257
f7234138	258	static void bru_try_format(struct vsp1_bru bru, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	259	unsigned int pad, struct v4l2_mbus_framefmt *fmt,
	260	enum v4l2_subdev_format_whence which)
	261	{
	262	struct v4l2_mbus_framefmt *format;
	263
	264	switch (pad) {
	265	case BRU_PAD_SINK(0):
	266	/* Default to YUV if the requested format is not supported. */
27ffaeb0 BB	267	if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	268	fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
	269	fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
629bb6d4 LP	270	break;
	271
	272	default:
	273	/* The BRU can't perform format conversion. */
f7234138	274	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
629bb6d4 LP	275	BRU_PAD_SINK(0), which);
	276	fmt->code = format->code;
	277	break;
	278	}
	279
	280	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	281	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	282	fmt->field = V4L2_FIELD_NONE;
	283	fmt->colorspace = V4L2_COLORSPACE_SRGB;
	284	}
	285
f7234138	286	static int bru_set_format(struct v4l2_subdev subdev, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	287	struct v4l2_subdev_format *fmt)
	288	{
	289	struct vsp1_bru *bru = to_bru(subdev);
	290	struct v4l2_mbus_framefmt *format;
	291
f7234138	292	bru_try_format(bru, cfg, fmt->pad, &fmt->format, fmt->which);
629bb6d4	293
f7234138	294	format = vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
629bb6d4 LP	295	fmt->which);
	296	*format = fmt->format;
	297
	298	/* Reset the compose rectangle */
	299	if (fmt->pad != BRU_PAD_SOURCE) {
	300	struct v4l2_rect *compose;
	301
f7234138	302	compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
629bb6d4 LP	303	compose->left = 0;
	304	compose->top = 0;
	305	compose->width = format->width;
	306	compose->height = format->height;
	307	}
	308
	309	/* Propagate the format code to all pads */
	310	if (fmt->pad == BRU_PAD_SINK(0)) {
	311	unsigned int i;
	312
	313	for (i = 0; i <= BRU_PAD_SOURCE; ++i) {
f7234138	314	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
629bb6d4 LP	315	i, fmt->which);
	316	format->code = fmt->format.code;
	317	}
	318	}
	319
	320	return 0;
	321	}
	322
	323	static int bru_get_selection(struct v4l2_subdev *subdev,
f7234138	324	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	325	struct v4l2_subdev_selection *sel)
	326	{
	327	struct vsp1_bru *bru = to_bru(subdev);
	328
	329	if (sel->pad == BRU_PAD_SOURCE)
	330	return -EINVAL;
	331
	332	switch (sel->target) {
	333	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	334	sel->r.left = 0;
	335	sel->r.top = 0;
	336	sel->r.width = BRU_MAX_SIZE;
	337	sel->r.height = BRU_MAX_SIZE;
	338	return 0;
	339
	340	case V4L2_SEL_TGT_COMPOSE:
f7234138	341	sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	342	return 0;
	343
	344	default:
	345	return -EINVAL;
	346	}
	347	}
	348
	349	static int bru_set_selection(struct v4l2_subdev *subdev,
f7234138	350	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	351	struct v4l2_subdev_selection *sel)
	352	{
	353	struct vsp1_bru *bru = to_bru(subdev);
	354	struct v4l2_mbus_framefmt *format;
	355	struct v4l2_rect *compose;
	356
	357	if (sel->pad == BRU_PAD_SOURCE)
	358	return -EINVAL;
	359
	360	if (sel->target != V4L2_SEL_TGT_COMPOSE)
	361	return -EINVAL;
	362
	363	/* The compose rectangle top left corner must be inside the output
	364	* frame.
	365	*/
f7234138	366	format = vsp1_entity_get_pad_format(&bru->entity, cfg, BRU_PAD_SOURCE,
629bb6d4 LP	367	sel->which);
	368	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	369	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
	370
	371	/* Scaling isn't supported, the compose rectangle size must be identical
	372	* to the sink format size.
	373	*/
f7234138	374	format = vsp1_entity_get_pad_format(&bru->entity, cfg, sel->pad,
629bb6d4 LP	375	sel->which);
	376	sel->r.width = format->width;
	377	sel->r.height = format->height;
	378
f7234138	379	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	380	*compose = sel->r;
	381
	382	return 0;
	383	}
	384
	385	/* -----------------------------------------------------------------------------
	386	* V4L2 Subdevice Operations
	387	*/
	388
	389	static struct v4l2_subdev_video_ops bru_video_ops = {
	390	.s_stream = bru_s_stream,
	391	};
	392
	393	static struct v4l2_subdev_pad_ops bru_pad_ops = {
	394	.enum_mbus_code = bru_enum_mbus_code,
	395	.enum_frame_size = bru_enum_frame_size,
	396	.get_fmt = bru_get_format,
	397	.set_fmt = bru_set_format,
	398	.get_selection = bru_get_selection,
	399	.set_selection = bru_set_selection,
	400	};
	401
	402	static struct v4l2_subdev_ops bru_ops = {
	403	.video = &bru_video_ops,
	404	.pad = &bru_pad_ops,
	405	};
	406
	407	/* -----------------------------------------------------------------------------
	408	* Initialization and Cleanup
	409	*/
	410
	411	struct vsp1_bru vsp1_bru_create(struct vsp1_device vsp1)
	412	{
	413	struct v4l2_subdev *subdev;
	414	struct vsp1_bru *bru;
	415	int ret;
	416
	417	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	418	if (bru == NULL)
	419	return ERR_PTR(-ENOMEM);
	420
	421	bru->entity.type = VSP1_ENTITY_BRU;
	422
	423	ret = vsp1_entity_init(vsp1, &bru->entity, 5);
	424	if (ret < 0)
	425	return ERR_PTR(ret);
	426
	427	/* Initialize the V4L2 subdev. */
	428	subdev = &bru->entity.subdev;
	429	v4l2_subdev_init(subdev, &bru_ops);
	430
	431	subdev->entity.ops = &vsp1_media_ops;
	432	subdev->internal_ops = &vsp1_subdev_internal_ops;
	433	snprintf(subdev->name, sizeof(subdev->name), "%s bru",
	434	dev_name(vsp1->dev));
	435	v4l2_set_subdevdata(subdev, bru);
	436	subdev->flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE;
	437
	438	vsp1_entity_init_formats(subdev, NULL);
	439
a16e2794 LP	440	/* Initialize the control handler. */
	441	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	442	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
	443	0, 0xffffff, 1, 0);
	444
	445	bru->entity.subdev.ctrl_handler = &bru->ctrls;
	446
	447	if (bru->ctrls.error) {
	448	dev_err(vsp1->dev, "bru: failed to initialize controls\n");
	449	ret = bru->ctrls.error;
	450	vsp1_entity_destroy(&bru->entity);
	451	return ERR_PTR(ret);
	452	}
	453
629bb6d4 LP	454	return bru;
629bb6d4 LP	455	}