[deliverable/linux.git] / drivers / media / platform / vsp1 / vsp1_bru.c

/*
 * vsp1_bru.c  --  R-Car VSP1 Blend ROP Unit
 *
 * Copyright (C) 2013 Renesas Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/device.h>
#include <linux/gfp.h>

#include <media/v4l2-subdev.h>

#include "vsp1.h"
#include "vsp1_bru.h"
#include "vsp1_rwpf.h"
#include "vsp1_video.h"

#define BRU_MIN_SIZE				1U
#define BRU_MAX_SIZE				8190U

/* -----------------------------------------------------------------------------
 * Device Access
 */

static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
{
	vsp1_mod_write(&bru->entity, reg, data);
}

/* -----------------------------------------------------------------------------
 * Controls
 */

static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct vsp1_bru *bru =
		container_of(ctrl->handler, struct vsp1_bru, ctrls);

	if (!vsp1_entity_is_streaming(&bru->entity))
		return 0;

	switch (ctrl->id) {
	case V4L2_CID_BG_COLOR:
		vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, ctrl->val |
			       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
		break;
	}

	return 0;
}

static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	.s_ctrl = bru_s_ctrl,
};

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Core Operations
 */

static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
{
	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;
	unsigned int flags;
	unsigned int i;
	int ret;

	ret = vsp1_entity_set_streaming(&bru->entity, enable);
	if (ret < 0)
		return ret;

	if (!enable)
		return 0;

	format = &bru->entity.formats[bru->entity.source_pad];

	/* The hardware is extremely flexible but we have no userspace API to
	 * expose all the parameters, nor is it clear whether we would have use
	 * cases for all the supported modes. Let's just harcode the parameters
	 * to sane default values for now.
	 */

	/* Disable dithering and enable color data normalization unless the
	 * format at the pipeline output is premultiplied.
	 */
	flags = pipe->output ? pipe->output->format.flags : 0;
	vsp1_bru_write(bru, VI6_BRU_INCTRL,
		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
		       0 : VI6_BRU_INCTRL_NRM);

	/* Set the background position to cover the whole output image. */
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);

	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	 * unit with a NOP operation to make BRU input 1 available as the
	 * Blend/ROP unit B SRC input.
	 */
	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) |
		       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
		       VI6_BRU_ROP_AROP(VI6_ROP_NOP));

	for (i = 0; i < bru->entity.source_pad; ++i) {
		bool premultiplied = false;
		u32 ctrl = 0;

		/* Configure all Blend/ROP units corresponding to an enabled BRU
		 * input for alpha blending. Blend/ROP units corresponding to
		 * disabled BRU inputs are used in ROP NOP mode to ignore the
		 * SRC input.
		 */
		if (bru->inputs[i].rpf) {
			ctrl |= VI6_BRU_CTRL_RBC;

			premultiplied = bru->inputs[i].rpf->format.flags
				      & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
		} else {
			ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
			     |  VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
		}

		/* Select the virtual RPF as the Blend/ROP unit A DST input to
		 * serve as a background color.
		 */
		if (i == 0)
			ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;

		/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
		 * D in that order. The Blend/ROP unit B SRC is hardwired to the
		 * ROP unit output, the corresponding register bits must be set
		 * to 0.
		 */
		if (i != 1)
			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);

		vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);

		/* Harcode the blending formula to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * when the SRC input isn't premultiplied, and to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * otherwise.
		 */
		vsp1_bru_write(bru, VI6_BRU_BLD(i),
			       VI6_BRU_BLD_CCMDX_255_SRC_A |
			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
						VI6_BRU_BLD_CCMDY_SRC_A) |
			       VI6_BRU_BLD_ACMDX_255_SRC_A |
			       VI6_BRU_BLD_ACMDY_COEFY |
			       (0xff << VI6_BRU_BLD_COEFY_SHIFT));
	}

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Pad Operations
 */

/*
 * The BRU can't perform format conversion, all sink and source formats must be
 * identical. We pick the format on the first sink pad (pad 0) and propagate it
 * to all other pads.
 */

static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
			      struct v4l2_subdev_pad_config *cfg,
			      struct v4l2_subdev_mbus_code_enum *code)
{
	static const unsigned int codes[] = {
		MEDIA_BUS_FMT_ARGB8888_1X32,
		MEDIA_BUS_FMT_AYUV8_1X32,
	};
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;

	if (code->pad == BRU_PAD_SINK(0)) {
		if (code->index >= ARRAY_SIZE(codes))
			return -EINVAL;

		code->code = codes[code->index];
	} else {
		if (code->index)
			return -EINVAL;

		format = vsp1_entity_get_pad_format(&bru->entity, cfg,
						    BRU_PAD_SINK(0), code->which);
		code->code = format->code;
	}

	return 0;
}

static int bru_enum_frame_size(struct v4l2_subdev *subdev,
			       struct v4l2_subdev_pad_config *cfg,
			       struct v4l2_subdev_frame_size_enum *fse)
{
	if (fse->index)
		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	    fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
		return -EINVAL;

	fse->min_width = BRU_MIN_SIZE;
	fse->max_width = BRU_MAX_SIZE;
	fse->min_height = BRU_MIN_SIZE;
	fse->max_height = BRU_MAX_SIZE;

	return 0;
}

static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
					 struct v4l2_subdev_pad_config *cfg,
					 unsigned int pad, u32 which)
{
	switch (which) {
	case V4L2_SUBDEV_FORMAT_TRY:
		return v4l2_subdev_get_try_crop(&bru->entity.subdev, cfg, pad);
	case V4L2_SUBDEV_FORMAT_ACTIVE:
		return &bru->inputs[pad].compose;
	default:
		return NULL;
	}
}

static int bru_get_format(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);

	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
						  fmt->which);

	return 0;
}

static void bru_try_format(struct vsp1_bru *bru, struct v4l2_subdev_pad_config *cfg,
			   unsigned int pad, struct v4l2_mbus_framefmt *fmt,
			   enum v4l2_subdev_format_whence which)
{
	struct v4l2_mbus_framefmt *format;

	switch (pad) {
	case BRU_PAD_SINK(0):
		/* Default to YUV if the requested format is not supported. */
		if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
		    fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
			fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
		break;

	default:
		/* The BRU can't perform format conversion. */
		format = vsp1_entity_get_pad_format(&bru->entity, cfg,
						    BRU_PAD_SINK(0), which);
		fmt->code = format->code;
		break;
	}

	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->field = V4L2_FIELD_NONE;
	fmt->colorspace = V4L2_COLORSPACE_SRGB;
}

static int bru_set_format(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;

	bru_try_format(bru, cfg, fmt->pad, &fmt->format, fmt->which);

	format = vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
					    fmt->which);
	*format = fmt->format;

	/* Reset the compose rectangle */
	if (fmt->pad != bru->entity.source_pad) {
		struct v4l2_rect *compose;

		compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
		compose->left = 0;
		compose->top = 0;
		compose->width = format->width;
		compose->height = format->height;
	}

	/* Propagate the format code to all pads */
	if (fmt->pad == BRU_PAD_SINK(0)) {
		unsigned int i;

		for (i = 0; i <= bru->entity.source_pad; ++i) {
			format = vsp1_entity_get_pad_format(&bru->entity, cfg,
							    i, fmt->which);
			format->code = fmt->format.code;
		}
	}

	return 0;
}

static int bru_get_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	switch (sel->target) {
	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
		sel->r.left = 0;
		sel->r.top = 0;
		sel->r.width = BRU_MAX_SIZE;
		sel->r.height = BRU_MAX_SIZE;
		return 0;

	case V4L2_SEL_TGT_COMPOSE:
		sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
		return 0;

	default:
		return -EINVAL;
	}
}

static int bru_set_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;
	struct v4l2_rect *compose;

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	if (sel->target != V4L2_SEL_TGT_COMPOSE)
		return -EINVAL;

	/* The compose rectangle top left corner must be inside the output
	 * frame.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
					    bru->entity.source_pad, sel->which);
	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);

	/* Scaling isn't supported, the compose rectangle size must be identical
	 * to the sink format size.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, cfg, sel->pad,
					    sel->which);
	sel->r.width = format->width;
	sel->r.height = format->height;

	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
	*compose = sel->r;

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Operations
 */

static struct v4l2_subdev_video_ops bru_video_ops = {
	.s_stream = bru_s_stream,
};

static struct v4l2_subdev_pad_ops bru_pad_ops = {
	.enum_mbus_code = bru_enum_mbus_code,
	.enum_frame_size = bru_enum_frame_size,
	.get_fmt = bru_get_format,
	.set_fmt = bru_set_format,
	.get_selection = bru_get_selection,
	.set_selection = bru_set_selection,
};

static struct v4l2_subdev_ops bru_ops = {
	.video	= &bru_video_ops,
	.pad    = &bru_pad_ops,
};

/* -----------------------------------------------------------------------------
 * Initialization and Cleanup
 */

struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1)
{
	struct v4l2_subdev *subdev;
	struct vsp1_bru *bru;
	int ret;

	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	if (bru == NULL)
		return ERR_PTR(-ENOMEM);

	bru->entity.type = VSP1_ENTITY_BRU;

	ret = vsp1_entity_init(vsp1, &bru->entity,
			       vsp1->info->num_bru_inputs + 1);
	if (ret < 0)
		return ERR_PTR(ret);

	/* Initialize the V4L2 subdev. */
	subdev = &bru->entity.subdev;
	v4l2_subdev_init(subdev, &bru_ops);

	subdev->entity.ops = &vsp1->media_ops;
	subdev->internal_ops = &vsp1_subdev_internal_ops;
	snprintf(subdev->name, sizeof(subdev->name), "%s bru",
		 dev_name(vsp1->dev));
	v4l2_set_subdevdata(subdev, bru);
	subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;

	vsp1_entity_init_formats(subdev, NULL);

	/* Initialize the control handler. */
	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
			  0, 0xffffff, 1, 0);

	bru->entity.subdev.ctrl_handler = &bru->ctrls;

	if (bru->ctrls.error) {
		dev_err(vsp1->dev, "bru: failed to initialize controls\n");
		ret = bru->ctrls.error;
		vsp1_entity_destroy(&bru->entity);
		return ERR_PTR(ret);
	}

	return bru;
}
Commit	Line	Data
629bb6d4 LP	1	/*
	2	* vsp1_bru.c -- R-Car VSP1 Blend ROP Unit
	3	*
	4	* Copyright (C) 2013 Renesas Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/gfp.h>
	16
	17	#include <media/v4l2-subdev.h>
	18
	19	#include "vsp1.h"
	20	#include "vsp1_bru.h"
6418b4d6	21	#include "vsp1_rwpf.h"
9d40637a	22	#include "vsp1_video.h"
629bb6d4	23
8cb0b634	24	#define BRU_MIN_SIZE 1U
629bb6d4 LP	25	#define BRU_MAX_SIZE 8190U
	26
	27	/* -----------------------------------------------------------------------------
	28	* Device Access
	29	*/
	30
629bb6d4 LP	31	static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
629bb6d4 LP	32	{
1517b039	33	vsp1_mod_write(&bru->entity, reg, data);
629bb6d4 LP	34	}
629bb6d4 LP	35
a16e2794 LP	36	/* -----------------------------------------------------------------------------
	37	* Controls
	38	*/
	39
	40	static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
	41	{
	42	struct vsp1_bru *bru =
	43	container_of(ctrl->handler, struct vsp1_bru, ctrls);
	44
	45	if (!vsp1_entity_is_streaming(&bru->entity))
	46	return 0;
	47
	48	switch (ctrl->id) {
	49	case V4L2_CID_BG_COLOR:
	50	vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, ctrl->val \|
	51	(0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
	52	break;
	53	}
	54
	55	return 0;
	56	}
	57
	58	static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	59	.s_ctrl = bru_s_ctrl,
	60	};
	61
629bb6d4 LP	62	/* -----------------------------------------------------------------------------
	63	* V4L2 Subdevice Core Operations
	64	*/
	65
629bb6d4 LP	66	static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
629bb6d4 LP	67	{
9aca813e	68	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
629bb6d4 LP	69	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	70	struct v4l2_mbus_framefmt *format;
9aca813e	71	unsigned int flags;
629bb6d4	72	unsigned int i;
a16e2794 LP	73	int ret;
	74
	75	ret = vsp1_entity_set_streaming(&bru->entity, enable);
	76	if (ret < 0)
	77	return ret;
629bb6d4 LP	78
	79	if (!enable)
	80	return 0;
	81
a96c5fa4	82	format = &bru->entity.formats[bru->entity.source_pad];
629bb6d4 LP	83
	84	/* The hardware is extremely flexible but we have no userspace API to
	85	* expose all the parameters, nor is it clear whether we would have use
	86	* cases for all the supported modes. Let's just harcode the parameters
	87	* to sane default values for now.
	88	*/
	89
9aca813e LP	90	/* Disable dithering and enable color data normalization unless the
	91	* format at the pipeline output is premultiplied.
	92	*/
86960eec	93	flags = pipe->output ? pipe->output->format.flags : 0;
9aca813e LP	94	vsp1_bru_write(bru, VI6_BRU_INCTRL,
	95	flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
	96	0 : VI6_BRU_INCTRL_NRM);
629bb6d4	97
a16e2794	98	/* Set the background position to cover the whole output image. */
629bb6d4 LP	99	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
	100	(format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) \|
	101	(format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	102	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);
629bb6d4 LP	103
	104	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	105	* unit with a NOP operation to make BRU input 1 available as the
	106	* Blend/ROP unit B SRC input.
	107	*/
	108	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) \|
	109	VI6_BRU_ROP_CROP(VI6_ROP_NOP) \|
	110	VI6_BRU_ROP_AROP(VI6_ROP_NOP));
	111
a96c5fa4	112	for (i = 0; i < bru->entity.source_pad; ++i) {
6418b4d6	113	bool premultiplied = false;
629bb6d4 LP	114	u32 ctrl = 0;
	115
	116	/* Configure all Blend/ROP units corresponding to an enabled BRU
	117	* input for alpha blending. Blend/ROP units corresponding to
	118	* disabled BRU inputs are used in ROP NOP mode to ignore the
	119	* SRC input.
	120	*/
6418b4d6	121	if (bru->inputs[i].rpf) {
629bb6d4	122	ctrl \|= VI6_BRU_CTRL_RBC;
6418b4d6	123
86960eec	124	premultiplied = bru->inputs[i].rpf->format.flags
6418b4d6 LP	125	& V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
6418b4d6 LP	126	} else {
629bb6d4 LP	127	ctrl \|= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
629bb6d4 LP	128	\| VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
6418b4d6	129	}
629bb6d4 LP	130
	131	/* Select the virtual RPF as the Blend/ROP unit A DST input to
	132	* serve as a background color.
	133	*/
	134	if (i == 0)
	135	ctrl \|= VI6_BRU_CTRL_DSTSEL_VRPF;
	136
	137	/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
	138	* D in that order. The Blend/ROP unit B SRC is hardwired to the
	139	* ROP unit output, the corresponding register bits must be set
	140	* to 0.
	141	*/
	142	if (i != 1)
	143	ctrl \|= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
	144
	145	vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);
	146
	147	/* Harcode the blending formula to
	148	*
	149	* DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
	150	* DSTa = DSTa * (1 - SRCa) + SRCa
6418b4d6 LP	151	*
	152	* when the SRC input isn't premultiplied, and to
	153	*
	154	* DSTc = DSTc * (1 - SRCa) + SRCc
	155	* DSTa = DSTa * (1 - SRCa) + SRCa
	156	*
	157	* otherwise.
629bb6d4 LP	158	*/
	159	vsp1_bru_write(bru, VI6_BRU_BLD(i),
	160	VI6_BRU_BLD_CCMDX_255_SRC_A \|
6418b4d6 LP	161	(premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
6418b4d6 LP	162	VI6_BRU_BLD_CCMDY_SRC_A) \|
629bb6d4 LP	163	VI6_BRU_BLD_ACMDX_255_SRC_A \|
	164	VI6_BRU_BLD_ACMDY_COEFY \|
	165	(0xff << VI6_BRU_BLD_COEFY_SHIFT));
	166	}
	167
	168	return 0;
	169	}
	170
	171	/* -----------------------------------------------------------------------------
	172	* V4L2 Subdevice Pad Operations
	173	*/
	174
	175	/*
	176	* The BRU can't perform format conversion, all sink and source formats must be
	177	* identical. We pick the format on the first sink pad (pad 0) and propagate it
	178	* to all other pads.
	179	*/
	180
	181	static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
f7234138	182	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	183	struct v4l2_subdev_mbus_code_enum *code)
	184	{
	185	static const unsigned int codes[] = {
27ffaeb0 BB	186	MEDIA_BUS_FMT_ARGB8888_1X32,
27ffaeb0 BB	187	MEDIA_BUS_FMT_AYUV8_1X32,
629bb6d4	188	};
3f1ccf16	189	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	190	struct v4l2_mbus_framefmt *format;
	191
	192	if (code->pad == BRU_PAD_SINK(0)) {
	193	if (code->index >= ARRAY_SIZE(codes))
	194	return -EINVAL;
	195
	196	code->code = codes[code->index];
	197	} else {
	198	if (code->index)
	199	return -EINVAL;
	200
3f1ccf16 HV	201	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
3f1ccf16 HV	202	BRU_PAD_SINK(0), code->which);
629bb6d4 LP	203	code->code = format->code;
	204	}
	205
	206	return 0;
	207	}
	208
	209	static int bru_enum_frame_size(struct v4l2_subdev *subdev,
f7234138	210	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	211	struct v4l2_subdev_frame_size_enum *fse)
	212	{
	213	if (fse->index)
	214	return -EINVAL;
	215
27ffaeb0 BB	216	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
27ffaeb0 BB	217	fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
629bb6d4 LP	218	return -EINVAL;
	219
	220	fse->min_width = BRU_MIN_SIZE;
	221	fse->max_width = BRU_MAX_SIZE;
	222	fse->min_height = BRU_MIN_SIZE;
	223	fse->max_height = BRU_MAX_SIZE;
	224
	225	return 0;
	226	}
	227
	228	static struct v4l2_rect bru_get_compose(struct vsp1_bru bru,
f7234138	229	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	230	unsigned int pad, u32 which)
	231	{
	232	switch (which) {
	233	case V4L2_SUBDEV_FORMAT_TRY:
f7234138	234	return v4l2_subdev_get_try_crop(&bru->entity.subdev, cfg, pad);
629bb6d4	235	case V4L2_SUBDEV_FORMAT_ACTIVE:
6418b4d6	236	return &bru->inputs[pad].compose;
629bb6d4 LP	237	default:
	238	return NULL;
	239	}
	240	}
	241
f7234138	242	static int bru_get_format(struct v4l2_subdev subdev, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	243	struct v4l2_subdev_format *fmt)
	244	{
	245	struct vsp1_bru *bru = to_bru(subdev);
	246
f7234138	247	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
629bb6d4 LP	248	fmt->which);
	249
	250	return 0;
	251	}
	252
f7234138	253	static void bru_try_format(struct vsp1_bru bru, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	254	unsigned int pad, struct v4l2_mbus_framefmt *fmt,
	255	enum v4l2_subdev_format_whence which)
	256	{
	257	struct v4l2_mbus_framefmt *format;
	258
	259	switch (pad) {
	260	case BRU_PAD_SINK(0):
	261	/* Default to YUV if the requested format is not supported. */
27ffaeb0 BB	262	if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	263	fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
	264	fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
629bb6d4 LP	265	break;
	266
	267	default:
	268	/* The BRU can't perform format conversion. */
f7234138	269	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
629bb6d4 LP	270	BRU_PAD_SINK(0), which);
	271	fmt->code = format->code;
	272	break;
	273	}
	274
	275	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	276	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	277	fmt->field = V4L2_FIELD_NONE;
	278	fmt->colorspace = V4L2_COLORSPACE_SRGB;
	279	}
	280
f7234138	281	static int bru_set_format(struct v4l2_subdev subdev, struct v4l2_subdev_pad_config cfg,
629bb6d4 LP	282	struct v4l2_subdev_format *fmt)
	283	{
	284	struct vsp1_bru *bru = to_bru(subdev);
	285	struct v4l2_mbus_framefmt *format;
	286
f7234138	287	bru_try_format(bru, cfg, fmt->pad, &fmt->format, fmt->which);
629bb6d4	288
f7234138	289	format = vsp1_entity_get_pad_format(&bru->entity, cfg, fmt->pad,
629bb6d4 LP	290	fmt->which);
	291	*format = fmt->format;
	292
	293	/* Reset the compose rectangle */
a96c5fa4	294	if (fmt->pad != bru->entity.source_pad) {
629bb6d4 LP	295	struct v4l2_rect *compose;
629bb6d4 LP	296
f7234138	297	compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
629bb6d4 LP	298	compose->left = 0;
	299	compose->top = 0;
	300	compose->width = format->width;
	301	compose->height = format->height;
	302	}
	303
	304	/* Propagate the format code to all pads */
	305	if (fmt->pad == BRU_PAD_SINK(0)) {
	306	unsigned int i;
	307
a96c5fa4	308	for (i = 0; i <= bru->entity.source_pad; ++i) {
f7234138	309	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
629bb6d4 LP	310	i, fmt->which);
	311	format->code = fmt->format.code;
	312	}
	313	}
	314
	315	return 0;
	316	}
	317
	318	static int bru_get_selection(struct v4l2_subdev *subdev,
f7234138	319	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	320	struct v4l2_subdev_selection *sel)
	321	{
	322	struct vsp1_bru *bru = to_bru(subdev);
	323
a96c5fa4	324	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	325	return -EINVAL;
	326
	327	switch (sel->target) {
	328	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	329	sel->r.left = 0;
	330	sel->r.top = 0;
	331	sel->r.width = BRU_MAX_SIZE;
	332	sel->r.height = BRU_MAX_SIZE;
	333	return 0;
	334
	335	case V4L2_SEL_TGT_COMPOSE:
f7234138	336	sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	337	return 0;
	338
	339	default:
	340	return -EINVAL;
	341	}
	342	}
	343
	344	static int bru_set_selection(struct v4l2_subdev *subdev,
f7234138	345	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	346	struct v4l2_subdev_selection *sel)
	347	{
	348	struct vsp1_bru *bru = to_bru(subdev);
	349	struct v4l2_mbus_framefmt *format;
	350	struct v4l2_rect *compose;
	351
a96c5fa4	352	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	353	return -EINVAL;
	354
	355	if (sel->target != V4L2_SEL_TGT_COMPOSE)
	356	return -EINVAL;
	357
	358	/* The compose rectangle top left corner must be inside the output
	359	* frame.
	360	*/
a96c5fa4 LP	361	format = vsp1_entity_get_pad_format(&bru->entity, cfg,
a96c5fa4 LP	362	bru->entity.source_pad, sel->which);
629bb6d4 LP	363	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	364	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
	365
	366	/* Scaling isn't supported, the compose rectangle size must be identical
	367	* to the sink format size.
	368	*/
f7234138	369	format = vsp1_entity_get_pad_format(&bru->entity, cfg, sel->pad,
629bb6d4 LP	370	sel->which);
	371	sel->r.width = format->width;
	372	sel->r.height = format->height;
	373
f7234138	374	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	375	*compose = sel->r;
	376
	377	return 0;
	378	}
	379
	380	/* -----------------------------------------------------------------------------
	381	* V4L2 Subdevice Operations
	382	*/
	383
	384	static struct v4l2_subdev_video_ops bru_video_ops = {
	385	.s_stream = bru_s_stream,
	386	};
	387
	388	static struct v4l2_subdev_pad_ops bru_pad_ops = {
	389	.enum_mbus_code = bru_enum_mbus_code,
	390	.enum_frame_size = bru_enum_frame_size,
	391	.get_fmt = bru_get_format,
	392	.set_fmt = bru_set_format,
	393	.get_selection = bru_get_selection,
	394	.set_selection = bru_set_selection,
	395	};
	396
	397	static struct v4l2_subdev_ops bru_ops = {
	398	.video = &bru_video_ops,
	399	.pad = &bru_pad_ops,
	400	};
	401
	402	/* -----------------------------------------------------------------------------
	403	* Initialization and Cleanup
	404	*/
	405
	406	struct vsp1_bru vsp1_bru_create(struct vsp1_device vsp1)
	407	{
	408	struct v4l2_subdev *subdev;
	409	struct vsp1_bru *bru;
	410	int ret;
	411
	412	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	413	if (bru == NULL)
	414	return ERR_PTR(-ENOMEM);
	415
	416	bru->entity.type = VSP1_ENTITY_BRU;
	417
a96c5fa4	418	ret = vsp1_entity_init(vsp1, &bru->entity,
5aa2eb3c	419	vsp1->info->num_bru_inputs + 1);
629bb6d4 LP	420	if (ret < 0)
	421	return ERR_PTR(ret);
	422
	423	/* Initialize the V4L2 subdev. */
	424	subdev = &bru->entity.subdev;
	425	v4l2_subdev_init(subdev, &bru_ops);
	426
babca007	427	subdev->entity.ops = &vsp1->media_ops;
629bb6d4 LP	428	subdev->internal_ops = &vsp1_subdev_internal_ops;
	429	snprintf(subdev->name, sizeof(subdev->name), "%s bru",
	430	dev_name(vsp1->dev));
	431	v4l2_set_subdevdata(subdev, bru);
	432	subdev->flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE;
	433
	434	vsp1_entity_init_formats(subdev, NULL);
	435
a16e2794 LP	436	/* Initialize the control handler. */
	437	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	438	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
	439	0, 0xffffff, 1, 0);
	440
	441	bru->entity.subdev.ctrl_handler = &bru->ctrls;
	442
	443	if (bru->ctrls.error) {
	444	dev_err(vsp1->dev, "bru: failed to initialize controls\n");
	445	ret = bru->ctrls.error;
	446	vsp1_entity_destroy(&bru->entity);
	447	return ERR_PTR(ret);
	448	}
	449
629bb6d4 LP	450	return bru;
629bb6d4 LP	451	}