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1517b039 TS |
1 | /* |
2 | * vsp1_dl.h -- R-Car VSP1 Display List | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Corporation | |
5 | * | |
6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/gfp.h> | |
17 | #include <linux/slab.h> | |
9489a8ff | 18 | #include <linux/workqueue.h> |
1517b039 TS |
19 | |
20 | #include "vsp1.h" | |
21 | #include "vsp1_dl.h" | |
1517b039 | 22 | |
f81e83c4 | 23 | #define VSP1_DL_NUM_ENTRIES 256 |
1517b039 TS |
24 | #define VSP1_DL_NUM_LISTS 3 |
25 | ||
12161989 LP |
26 | #define VSP1_DLH_INT_ENABLE (1 << 1) |
27 | #define VSP1_DLH_AUTO_START (1 << 0) | |
28 | ||
f81e83c4 LP |
29 | struct vsp1_dl_header_list { |
30 | u32 num_bytes; | |
31 | u32 addr; | |
32 | } __attribute__((__packed__)); | |
33 | ||
12161989 LP |
34 | struct vsp1_dl_header { |
35 | u32 num_lists; | |
f81e83c4 | 36 | struct vsp1_dl_header_list lists[8]; |
12161989 LP |
37 | u32 next_header; |
38 | u32 flags; | |
39 | } __attribute__((__packed__)); | |
40 | ||
1517b039 TS |
41 | struct vsp1_dl_entry { |
42 | u32 addr; | |
43 | u32 data; | |
44 | } __attribute__((__packed__)); | |
45 | ||
f81e83c4 LP |
46 | /** |
47 | * struct vsp1_dl_body - Display list body | |
48 | * @list: entry in the display list list of bodies | |
49 | * @vsp1: the VSP1 device | |
50 | * @entries: array of entries | |
51 | * @dma: DMA address of the entries | |
52 | * @size: size of the DMA memory in bytes | |
53 | * @num_entries: number of stored entries | |
54 | */ | |
55 | struct vsp1_dl_body { | |
c2dd2513 | 56 | struct list_head list; |
f81e83c4 LP |
57 | struct vsp1_device *vsp1; |
58 | ||
59 | struct vsp1_dl_entry *entries; | |
60 | dma_addr_t dma; | |
61 | size_t size; | |
62 | ||
63 | unsigned int num_entries; | |
64 | }; | |
1517b039 | 65 | |
f81e83c4 LP |
66 | /** |
67 | * struct vsp1_dl_list - Display list | |
68 | * @list: entry in the display list manager lists | |
69 | * @dlm: the display list manager | |
70 | * @header: display list header, NULL for headerless lists | |
71 | * @dma: DMA address for the header | |
72 | * @body0: first display list body | |
73 | * @fragments: list of extra display list bodies | |
74 | */ | |
75 | struct vsp1_dl_list { | |
76 | struct list_head list; | |
c2dd2513 | 77 | struct vsp1_dl_manager *dlm; |
1517b039 | 78 | |
12161989 | 79 | struct vsp1_dl_header *header; |
1517b039 | 80 | dma_addr_t dma; |
1517b039 | 81 | |
f81e83c4 LP |
82 | struct vsp1_dl_body body0; |
83 | struct list_head fragments; | |
1517b039 TS |
84 | }; |
85 | ||
12161989 LP |
86 | enum vsp1_dl_mode { |
87 | VSP1_DL_MODE_HEADER, | |
88 | VSP1_DL_MODE_HEADERLESS, | |
89 | }; | |
90 | ||
ef9621bc LP |
91 | /** |
92 | * struct vsp1_dl_manager - Display List manager | |
12161989 LP |
93 | * @index: index of the related WPF |
94 | * @mode: display list operation mode (header or headerless) | |
ef9621bc | 95 | * @vsp1: the VSP1 device |
9489a8ff | 96 | * @lock: protects the free, active, queued, pending and gc_fragments lists |
ef9621bc LP |
97 | * @free: array of all free display lists |
98 | * @active: list currently being processed (loaded) by hardware | |
99 | * @queued: list queued to the hardware (written to the DL registers) | |
100 | * @pending: list waiting to be queued to the hardware | |
9489a8ff LP |
101 | * @gc_work: fragments garbage collector work struct |
102 | * @gc_fragments: array of display list fragments waiting to be freed | |
ef9621bc LP |
103 | */ |
104 | struct vsp1_dl_manager { | |
12161989 LP |
105 | unsigned int index; |
106 | enum vsp1_dl_mode mode; | |
ef9621bc LP |
107 | struct vsp1_device *vsp1; |
108 | ||
109 | spinlock_t lock; | |
110 | struct list_head free; | |
111 | struct vsp1_dl_list *active; | |
112 | struct vsp1_dl_list *queued; | |
113 | struct vsp1_dl_list *pending; | |
9489a8ff LP |
114 | |
115 | struct work_struct gc_work; | |
116 | struct list_head gc_fragments; | |
ef9621bc LP |
117 | }; |
118 | ||
f81e83c4 LP |
119 | /* ----------------------------------------------------------------------------- |
120 | * Display List Body Management | |
121 | */ | |
122 | ||
123 | /* | |
124 | * Initialize a display list body object and allocate DMA memory for the body | |
125 | * data. The display list body object is expected to have been initialized to | |
126 | * 0 when allocated. | |
127 | */ | |
128 | static int vsp1_dl_body_init(struct vsp1_device *vsp1, | |
129 | struct vsp1_dl_body *dlb, unsigned int num_entries, | |
130 | size_t extra_size) | |
131 | { | |
132 | size_t size = num_entries * sizeof(*dlb->entries) + extra_size; | |
133 | ||
134 | dlb->vsp1 = vsp1; | |
135 | dlb->size = size; | |
136 | ||
137 | dlb->entries = dma_alloc_wc(vsp1->dev, dlb->size, &dlb->dma, | |
138 | GFP_KERNEL); | |
139 | if (!dlb->entries) | |
140 | return -ENOMEM; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | /* | |
146 | * Cleanup a display list body and free allocated DMA memory allocated. | |
147 | */ | |
148 | static void vsp1_dl_body_cleanup(struct vsp1_dl_body *dlb) | |
149 | { | |
150 | dma_free_wc(dlb->vsp1->dev, dlb->size, dlb->entries, dlb->dma); | |
151 | } | |
152 | ||
153 | /** | |
154 | * vsp1_dl_fragment_alloc - Allocate a display list fragment | |
155 | * @vsp1: The VSP1 device | |
156 | * @num_entries: The maximum number of entries that the fragment can contain | |
157 | * | |
158 | * Allocate a display list fragment with enough memory to contain the requested | |
159 | * number of entries. | |
160 | * | |
161 | * Return a pointer to a fragment on success or NULL if memory can't be | |
162 | * allocated. | |
163 | */ | |
164 | struct vsp1_dl_body *vsp1_dl_fragment_alloc(struct vsp1_device *vsp1, | |
165 | unsigned int num_entries) | |
166 | { | |
167 | struct vsp1_dl_body *dlb; | |
168 | int ret; | |
169 | ||
170 | dlb = kzalloc(sizeof(*dlb), GFP_KERNEL); | |
171 | if (!dlb) | |
172 | return NULL; | |
173 | ||
174 | ret = vsp1_dl_body_init(vsp1, dlb, num_entries, 0); | |
175 | if (ret < 0) { | |
176 | kfree(dlb); | |
177 | return NULL; | |
178 | } | |
179 | ||
180 | return dlb; | |
181 | } | |
182 | ||
183 | /** | |
184 | * vsp1_dl_fragment_free - Free a display list fragment | |
185 | * @dlb: The fragment | |
186 | * | |
187 | * Free the given display list fragment and the associated DMA memory. | |
188 | * | |
189 | * Fragments must only be freed explicitly if they are not added to a display | |
190 | * list, as the display list will take ownership of them and free them | |
191 | * otherwise. Manual free typically happens at cleanup time for fragments that | |
192 | * have been allocated but not used. | |
193 | * | |
194 | * Passing a NULL pointer to this function is safe, in that case no operation | |
195 | * will be performed. | |
196 | */ | |
197 | void vsp1_dl_fragment_free(struct vsp1_dl_body *dlb) | |
198 | { | |
199 | if (!dlb) | |
200 | return; | |
201 | ||
202 | vsp1_dl_body_cleanup(dlb); | |
203 | kfree(dlb); | |
204 | } | |
205 | ||
206 | /** | |
207 | * vsp1_dl_fragment_write - Write a register to a display list fragment | |
208 | * @dlb: The fragment | |
209 | * @reg: The register address | |
210 | * @data: The register value | |
211 | * | |
212 | * Write the given register and value to the display list fragment. The maximum | |
213 | * number of entries that can be written in a fragment is specified when the | |
214 | * fragment is allocated by vsp1_dl_fragment_alloc(). | |
215 | */ | |
216 | void vsp1_dl_fragment_write(struct vsp1_dl_body *dlb, u32 reg, u32 data) | |
217 | { | |
218 | dlb->entries[dlb->num_entries].addr = reg; | |
219 | dlb->entries[dlb->num_entries].data = data; | |
220 | dlb->num_entries++; | |
221 | } | |
222 | ||
1517b039 TS |
223 | /* ----------------------------------------------------------------------------- |
224 | * Display List Transaction Management | |
225 | */ | |
226 | ||
c2dd2513 | 227 | static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm) |
1517b039 | 228 | { |
c2dd2513 | 229 | struct vsp1_dl_list *dl; |
12161989 | 230 | size_t header_size; |
f81e83c4 | 231 | int ret; |
1517b039 | 232 | |
c2dd2513 LP |
233 | dl = kzalloc(sizeof(*dl), GFP_KERNEL); |
234 | if (!dl) | |
235 | return NULL; | |
1517b039 | 236 | |
f81e83c4 | 237 | INIT_LIST_HEAD(&dl->fragments); |
c2dd2513 | 238 | dl->dlm = dlm; |
c2dd2513 | 239 | |
f81e83c4 LP |
240 | /* Initialize the display list body and allocate DMA memory for the body |
241 | * and the optional header. Both are allocated together to avoid memory | |
242 | * fragmentation, with the header located right after the body in | |
243 | * memory. | |
244 | */ | |
245 | header_size = dlm->mode == VSP1_DL_MODE_HEADER | |
246 | ? ALIGN(sizeof(struct vsp1_dl_header), 8) | |
247 | : 0; | |
248 | ||
249 | ret = vsp1_dl_body_init(dlm->vsp1, &dl->body0, VSP1_DL_NUM_ENTRIES, | |
250 | header_size); | |
251 | if (ret < 0) { | |
c2dd2513 LP |
252 | kfree(dl); |
253 | return NULL; | |
254 | } | |
1517b039 | 255 | |
12161989 | 256 | if (dlm->mode == VSP1_DL_MODE_HEADER) { |
f81e83c4 LP |
257 | size_t header_offset = VSP1_DL_NUM_ENTRIES |
258 | * sizeof(*dl->body0.entries); | |
259 | ||
260 | dl->header = ((void *)dl->body0.entries) + header_offset; | |
261 | dl->dma = dl->body0.dma + header_offset; | |
262 | ||
12161989 | 263 | memset(dl->header, 0, sizeof(*dl->header)); |
f81e83c4 | 264 | dl->header->lists[0].addr = dl->body0.dma; |
12161989 LP |
265 | dl->header->flags = VSP1_DLH_INT_ENABLE; |
266 | } | |
267 | ||
c2dd2513 LP |
268 | return dl; |
269 | } | |
1517b039 | 270 | |
c2dd2513 LP |
271 | static void vsp1_dl_list_free(struct vsp1_dl_list *dl) |
272 | { | |
f81e83c4 | 273 | vsp1_dl_body_cleanup(&dl->body0); |
9489a8ff | 274 | list_splice_init(&dl->fragments, &dl->dlm->gc_fragments); |
c2dd2513 | 275 | kfree(dl); |
1517b039 TS |
276 | } |
277 | ||
c2dd2513 LP |
278 | /** |
279 | * vsp1_dl_list_get - Get a free display list | |
280 | * @dlm: The display list manager | |
281 | * | |
282 | * Get a display list from the pool of free lists and return it. | |
283 | * | |
284 | * This function must be called without the display list manager lock held. | |
285 | */ | |
286 | struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm) | |
1517b039 | 287 | { |
c2dd2513 | 288 | struct vsp1_dl_list *dl = NULL; |
1517b039 | 289 | unsigned long flags; |
1517b039 | 290 | |
c2dd2513 | 291 | spin_lock_irqsave(&dlm->lock, flags); |
1517b039 | 292 | |
c2dd2513 LP |
293 | if (!list_empty(&dlm->free)) { |
294 | dl = list_first_entry(&dlm->free, struct vsp1_dl_list, list); | |
295 | list_del(&dl->list); | |
1517b039 TS |
296 | } |
297 | ||
c2dd2513 LP |
298 | spin_unlock_irqrestore(&dlm->lock, flags); |
299 | ||
300 | return dl; | |
301 | } | |
1517b039 | 302 | |
d2c1b028 LP |
303 | /* This function must be called with the display list manager lock held.*/ |
304 | static void __vsp1_dl_list_put(struct vsp1_dl_list *dl) | |
305 | { | |
306 | if (!dl) | |
307 | return; | |
308 | ||
9489a8ff LP |
309 | /* We can't free fragments here as DMA memory can only be freed in |
310 | * interruptible context. Move all fragments to the display list | |
311 | * manager's list of fragments to be freed, they will be | |
312 | * garbage-collected by the work queue. | |
313 | */ | |
314 | if (!list_empty(&dl->fragments)) { | |
315 | list_splice_init(&dl->fragments, &dl->dlm->gc_fragments); | |
316 | schedule_work(&dl->dlm->gc_work); | |
317 | } | |
318 | ||
f81e83c4 | 319 | dl->body0.num_entries = 0; |
d2c1b028 LP |
320 | |
321 | list_add_tail(&dl->list, &dl->dlm->free); | |
322 | } | |
323 | ||
c2dd2513 LP |
324 | /** |
325 | * vsp1_dl_list_put - Release a display list | |
326 | * @dl: The display list | |
327 | * | |
328 | * Release the display list and return it to the pool of free lists. | |
329 | * | |
c2dd2513 LP |
330 | * Passing a NULL pointer to this function is safe, in that case no operation |
331 | * will be performed. | |
332 | */ | |
333 | void vsp1_dl_list_put(struct vsp1_dl_list *dl) | |
334 | { | |
d2c1b028 LP |
335 | unsigned long flags; |
336 | ||
c2dd2513 LP |
337 | if (!dl) |
338 | return; | |
1517b039 | 339 | |
d2c1b028 LP |
340 | spin_lock_irqsave(&dl->dlm->lock, flags); |
341 | __vsp1_dl_list_put(dl); | |
342 | spin_unlock_irqrestore(&dl->dlm->lock, flags); | |
1517b039 TS |
343 | } |
344 | ||
f81e83c4 LP |
345 | /** |
346 | * vsp1_dl_list_write - Write a register to the display list | |
347 | * @dl: The display list | |
348 | * @reg: The register address | |
349 | * @data: The register value | |
350 | * | |
351 | * Write the given register and value to the display list. Up to 256 registers | |
352 | * can be written per display list. | |
353 | */ | |
c2dd2513 | 354 | void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data) |
1517b039 | 355 | { |
f81e83c4 LP |
356 | vsp1_dl_fragment_write(&dl->body0, reg, data); |
357 | } | |
358 | ||
359 | /** | |
360 | * vsp1_dl_list_add_fragment - Add a fragment to the display list | |
361 | * @dl: The display list | |
362 | * @dlb: The fragment | |
363 | * | |
364 | * Add a display list body as a fragment to a display list. Registers contained | |
365 | * in fragments are processed after registers contained in the main display | |
366 | * list, in the order in which fragments are added. | |
367 | * | |
368 | * Adding a fragment to a display list passes ownership of the fragment to the | |
369 | * list. The caller must not touch the fragment after this call, and must not | |
370 | * free it explicitly with vsp1_dl_fragment_free(). | |
371 | * | |
372 | * Fragments are only usable for display lists in header mode. Attempt to | |
373 | * add a fragment to a header-less display list will return an error. | |
374 | */ | |
375 | int vsp1_dl_list_add_fragment(struct vsp1_dl_list *dl, | |
376 | struct vsp1_dl_body *dlb) | |
377 | { | |
378 | /* Multi-body lists are only available in header mode. */ | |
379 | if (dl->dlm->mode != VSP1_DL_MODE_HEADER) | |
380 | return -EINVAL; | |
381 | ||
382 | list_add_tail(&dlb->list, &dl->fragments); | |
383 | return 0; | |
1517b039 TS |
384 | } |
385 | ||
c2dd2513 | 386 | void vsp1_dl_list_commit(struct vsp1_dl_list *dl) |
1517b039 | 387 | { |
c2dd2513 LP |
388 | struct vsp1_dl_manager *dlm = dl->dlm; |
389 | struct vsp1_device *vsp1 = dlm->vsp1; | |
1517b039 TS |
390 | unsigned long flags; |
391 | bool update; | |
392 | ||
c2dd2513 | 393 | spin_lock_irqsave(&dlm->lock, flags); |
1517b039 | 394 | |
12161989 | 395 | if (dl->dlm->mode == VSP1_DL_MODE_HEADER) { |
f81e83c4 LP |
396 | struct vsp1_dl_header_list *hdr = dl->header->lists; |
397 | struct vsp1_dl_body *dlb; | |
398 | unsigned int num_lists = 0; | |
399 | ||
400 | /* Fill the header with the display list bodies addresses and | |
401 | * sizes. The address of the first body has already been filled | |
402 | * when the display list was allocated. | |
403 | * | |
404 | * In header mode the caller guarantees that the hardware is | |
405 | * idle at this point. | |
12161989 | 406 | */ |
f81e83c4 LP |
407 | hdr->num_bytes = dl->body0.num_entries |
408 | * sizeof(*dl->header->lists); | |
409 | ||
410 | list_for_each_entry(dlb, &dl->fragments, list) { | |
411 | num_lists++; | |
412 | hdr++; | |
413 | ||
414 | hdr->addr = dlb->dma; | |
415 | hdr->num_bytes = dlb->num_entries | |
416 | * sizeof(*dl->header->lists); | |
417 | } | |
418 | ||
419 | dl->header->num_lists = num_lists; | |
12161989 LP |
420 | vsp1_write(vsp1, VI6_DL_HDR_ADDR(dlm->index), dl->dma); |
421 | ||
422 | dlm->active = dl; | |
423 | goto done; | |
424 | } | |
425 | ||
1517b039 TS |
426 | /* Once the UPD bit has been set the hardware can start processing the |
427 | * display list at any time and we can't touch the address and size | |
428 | * registers. In that case mark the update as pending, it will be | |
429 | * queued up to the hardware by the frame end interrupt handler. | |
430 | */ | |
431 | update = !!(vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD); | |
432 | if (update) { | |
d2c1b028 | 433 | __vsp1_dl_list_put(dlm->pending); |
c2dd2513 | 434 | dlm->pending = dl; |
1517b039 TS |
435 | goto done; |
436 | } | |
437 | ||
438 | /* Program the hardware with the display list body address and size. | |
439 | * The UPD bit will be cleared by the device when the display list is | |
440 | * processed. | |
441 | */ | |
f81e83c4 | 442 | vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->body0.dma); |
1517b039 | 443 | vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD | |
f81e83c4 | 444 | (dl->body0.num_entries * sizeof(*dl->header->lists))); |
1517b039 | 445 | |
d2c1b028 | 446 | __vsp1_dl_list_put(dlm->queued); |
c2dd2513 | 447 | dlm->queued = dl; |
1517b039 TS |
448 | |
449 | done: | |
c2dd2513 | 450 | spin_unlock_irqrestore(&dlm->lock, flags); |
1517b039 TS |
451 | } |
452 | ||
453 | /* ----------------------------------------------------------------------------- | |
c2dd2513 | 454 | * Display List Manager |
1517b039 TS |
455 | */ |
456 | ||
c2dd2513 LP |
457 | /* Interrupt Handling */ |
458 | void vsp1_dlm_irq_display_start(struct vsp1_dl_manager *dlm) | |
1517b039 | 459 | { |
c2dd2513 | 460 | spin_lock(&dlm->lock); |
1517b039 TS |
461 | |
462 | /* The display start interrupt signals the end of the display list | |
463 | * processing by the device. The active display list, if any, won't be | |
464 | * accessed anymore and can be reused. | |
465 | */ | |
d2c1b028 | 466 | __vsp1_dl_list_put(dlm->active); |
c2dd2513 | 467 | dlm->active = NULL; |
1517b039 | 468 | |
c2dd2513 | 469 | spin_unlock(&dlm->lock); |
1517b039 TS |
470 | } |
471 | ||
c2dd2513 | 472 | void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm) |
1517b039 | 473 | { |
c2dd2513 | 474 | struct vsp1_device *vsp1 = dlm->vsp1; |
1517b039 | 475 | |
c2dd2513 LP |
476 | spin_lock(&dlm->lock); |
477 | ||
d2c1b028 | 478 | __vsp1_dl_list_put(dlm->active); |
c2dd2513 | 479 | dlm->active = NULL; |
1517b039 | 480 | |
12161989 LP |
481 | /* Header mode is used for mem-to-mem pipelines only. We don't need to |
482 | * perform any operation as there can't be any new display list queued | |
483 | * in that case. | |
484 | */ | |
485 | if (dlm->mode == VSP1_DL_MODE_HEADER) | |
486 | goto done; | |
487 | ||
1517b039 TS |
488 | /* The UPD bit set indicates that the commit operation raced with the |
489 | * interrupt and occurred after the frame end event and UPD clear but | |
490 | * before interrupt processing. The hardware hasn't taken the update | |
491 | * into account yet, we'll thus skip one frame and retry. | |
492 | */ | |
493 | if (vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD) | |
494 | goto done; | |
495 | ||
496 | /* The device starts processing the queued display list right after the | |
497 | * frame end interrupt. The display list thus becomes active. | |
498 | */ | |
c2dd2513 LP |
499 | if (dlm->queued) { |
500 | dlm->active = dlm->queued; | |
501 | dlm->queued = NULL; | |
1517b039 TS |
502 | } |
503 | ||
504 | /* Now that the UPD bit has been cleared we can queue the next display | |
505 | * list to the hardware if one has been prepared. | |
506 | */ | |
c2dd2513 LP |
507 | if (dlm->pending) { |
508 | struct vsp1_dl_list *dl = dlm->pending; | |
1517b039 | 509 | |
f81e83c4 | 510 | vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->body0.dma); |
1517b039 | 511 | vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD | |
f81e83c4 LP |
512 | (dl->body0.num_entries * |
513 | sizeof(*dl->header->lists))); | |
1517b039 | 514 | |
c2dd2513 LP |
515 | dlm->queued = dl; |
516 | dlm->pending = NULL; | |
1517b039 TS |
517 | } |
518 | ||
519 | done: | |
c2dd2513 | 520 | spin_unlock(&dlm->lock); |
1517b039 TS |
521 | } |
522 | ||
c2dd2513 LP |
523 | /* Hardware Setup */ |
524 | void vsp1_dlm_setup(struct vsp1_device *vsp1) | |
1517b039 | 525 | { |
351bbf99 LP |
526 | u32 ctrl = (256 << VI6_DL_CTRL_AR_WAIT_SHIFT) |
527 | | VI6_DL_CTRL_DC2 | VI6_DL_CTRL_DC1 | VI6_DL_CTRL_DC0 | |
528 | | VI6_DL_CTRL_DLE; | |
1517b039 | 529 | |
351bbf99 LP |
530 | /* The DRM pipeline operates with display lists in Continuous Frame |
531 | * Mode, all other pipelines use manual start. | |
1517b039 TS |
532 | */ |
533 | if (vsp1->drm) | |
351bbf99 | 534 | ctrl |= VI6_DL_CTRL_CFM0 | VI6_DL_CTRL_NH0; |
1517b039 TS |
535 | |
536 | vsp1_write(vsp1, VI6_DL_CTRL, ctrl); | |
537 | vsp1_write(vsp1, VI6_DL_SWAP, VI6_DL_SWAP_LWS); | |
538 | } | |
539 | ||
c2dd2513 LP |
540 | void vsp1_dlm_reset(struct vsp1_dl_manager *dlm) |
541 | { | |
d2c1b028 LP |
542 | unsigned long flags; |
543 | ||
544 | spin_lock_irqsave(&dlm->lock, flags); | |
545 | ||
546 | __vsp1_dl_list_put(dlm->active); | |
547 | __vsp1_dl_list_put(dlm->queued); | |
548 | __vsp1_dl_list_put(dlm->pending); | |
549 | ||
550 | spin_unlock_irqrestore(&dlm->lock, flags); | |
c2dd2513 LP |
551 | |
552 | dlm->active = NULL; | |
553 | dlm->queued = NULL; | |
554 | dlm->pending = NULL; | |
555 | } | |
1517b039 | 556 | |
9489a8ff LP |
557 | /* |
558 | * Free all fragments awaiting to be garbage-collected. | |
559 | * | |
560 | * This function must be called without the display list manager lock held. | |
561 | */ | |
562 | static void vsp1_dlm_fragments_free(struct vsp1_dl_manager *dlm) | |
563 | { | |
564 | unsigned long flags; | |
565 | ||
566 | spin_lock_irqsave(&dlm->lock, flags); | |
567 | ||
568 | while (!list_empty(&dlm->gc_fragments)) { | |
569 | struct vsp1_dl_body *dlb; | |
570 | ||
571 | dlb = list_first_entry(&dlm->gc_fragments, struct vsp1_dl_body, | |
572 | list); | |
573 | list_del(&dlb->list); | |
574 | ||
575 | spin_unlock_irqrestore(&dlm->lock, flags); | |
576 | vsp1_dl_fragment_free(dlb); | |
577 | spin_lock_irqsave(&dlm->lock, flags); | |
578 | } | |
579 | ||
580 | spin_unlock_irqrestore(&dlm->lock, flags); | |
581 | } | |
582 | ||
583 | static void vsp1_dlm_garbage_collect(struct work_struct *work) | |
584 | { | |
585 | struct vsp1_dl_manager *dlm = | |
586 | container_of(work, struct vsp1_dl_manager, gc_work); | |
587 | ||
588 | vsp1_dlm_fragments_free(dlm); | |
589 | } | |
590 | ||
ef9621bc | 591 | struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1, |
12161989 | 592 | unsigned int index, |
ef9621bc | 593 | unsigned int prealloc) |
1517b039 | 594 | { |
ef9621bc | 595 | struct vsp1_dl_manager *dlm; |
1517b039 TS |
596 | unsigned int i; |
597 | ||
ef9621bc LP |
598 | dlm = devm_kzalloc(vsp1->dev, sizeof(*dlm), GFP_KERNEL); |
599 | if (!dlm) | |
600 | return NULL; | |
601 | ||
12161989 LP |
602 | dlm->index = index; |
603 | dlm->mode = index == 0 && !vsp1->info->uapi | |
604 | ? VSP1_DL_MODE_HEADERLESS : VSP1_DL_MODE_HEADER; | |
c2dd2513 | 605 | dlm->vsp1 = vsp1; |
1517b039 | 606 | |
c2dd2513 LP |
607 | spin_lock_init(&dlm->lock); |
608 | INIT_LIST_HEAD(&dlm->free); | |
9489a8ff LP |
609 | INIT_LIST_HEAD(&dlm->gc_fragments); |
610 | INIT_WORK(&dlm->gc_work, vsp1_dlm_garbage_collect); | |
1517b039 | 611 | |
c2dd2513 LP |
612 | for (i = 0; i < prealloc; ++i) { |
613 | struct vsp1_dl_list *dl; | |
1517b039 | 614 | |
c2dd2513 LP |
615 | dl = vsp1_dl_list_alloc(dlm); |
616 | if (!dl) | |
ef9621bc | 617 | return NULL; |
1517b039 | 618 | |
c2dd2513 | 619 | list_add_tail(&dl->list, &dlm->free); |
1517b039 TS |
620 | } |
621 | ||
ef9621bc | 622 | return dlm; |
1517b039 TS |
623 | } |
624 | ||
ef9621bc | 625 | void vsp1_dlm_destroy(struct vsp1_dl_manager *dlm) |
1517b039 | 626 | { |
c2dd2513 LP |
627 | struct vsp1_dl_list *dl, *next; |
628 | ||
ef9621bc LP |
629 | if (!dlm) |
630 | return; | |
631 | ||
9489a8ff LP |
632 | cancel_work_sync(&dlm->gc_work); |
633 | ||
c2dd2513 LP |
634 | list_for_each_entry_safe(dl, next, &dlm->free, list) { |
635 | list_del(&dl->list); | |
636 | vsp1_dl_list_free(dl); | |
637 | } | |
9489a8ff LP |
638 | |
639 | vsp1_dlm_fragments_free(dlm); | |
1517b039 | 640 | } |