projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 26e0ca22 LP |
1 | /* |
| 2 | * vsp1_regs.h -- R-Car VSP1 Registers Definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
| 5 | * | |
| 6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 | |
| 10 | * as published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __VSP1_REGS_H__ | |
| 14 | #define __VSP1_REGS_H__ | |
| 15 | ||
| 16 | /* ----------------------------------------------------------------------------- | |
| 17 | * General Control Registers | |
| 18 | */ | |
| 19 | ||
| 20 | #define VI6_CMD(n) (0x0000 + (n) * 4) | |
| 21 | #define VI6_CMD_STRCMD (1 << 0) | |
| 22 | ||
| 23 | #define VI6_CLK_DCSWT 0x0018 | |
| 24 | #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8) | |
| 25 | #define VI6_CLK_DCSWT_CSTPW_SHIFT 8 | |
| 26 | #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0) | |
| 27 | #define VI6_CLK_DCSWT_CSTRW_SHIFT 0 | |
| 28 | ||
| 29 | #define VI6_SRESET 0x0028 | |
| 30 | #define VI6_SRESET_SRTS(n) (1 << (n)) | |
| 31 | ||
| 32 | #define VI6_STATUS 0x0038 | |
| 33 | #define VI6_STATUS_SYS_ACT(n) (1 << ((n) + 8)) | |
| 34 | ||
| 35 | #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) | |
| 36 | #define VI6_WFP_IRQ_ENB_DFEE (1 << 1) | |
| 37 | #define VI6_WFP_IRQ_ENB_FREE (1 << 0) | |
| 38 | ||
| 39 | #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) | |
| 40 | #define VI6_WFP_IRQ_STA_DFE (1 << 1) | |
| 41 | #define VI6_WFP_IRQ_STA_FRE (1 << 0) | |
| 42 | ||
| 43 | #define VI6_DISP_IRQ_ENB 0x0078 | |
| 44 | #define VI6_DISP_IRQ_ENB_DSTE (1 << 8) | |
| 45 | #define VI6_DISP_IRQ_ENB_MAEE (1 << 5) | |
| 59a7954c | 46 | #define VI6_DISP_IRQ_ENB_LNEE(n) (1 << (n)) |
| 26e0ca22 LP |
47 | |
| 48 | #define VI6_DISP_IRQ_STA 0x007c | |
| 5dc1e5fb | 49 | #define VI6_DISP_IRQ_STA_DST (1 << 8) |
| 26e0ca22 | 50 | #define VI6_DISP_IRQ_STA_MAE (1 << 5) |
| 533ab223 | 51 | #define VI6_DISP_IRQ_STA_LNE(n) (1 << (n)) |
| 26e0ca22 LP |
52 | |
| 53 | #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4) | |
| 54 | #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0) | |
| 55 | ||
| 56 | /* ----------------------------------------------------------------------------- | |
| 57 | * Display List Control Registers | |
| 58 | */ | |
| 59 | ||
| 60 | #define VI6_DL_CTRL 0x0100 | |
| 61 | #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16) | |
| 62 | #define VI6_DL_CTRL_AR_WAIT_SHIFT 16 | |
| 63 | #define VI6_DL_CTRL_DC2 (1 << 12) | |
| 64 | #define VI6_DL_CTRL_DC1 (1 << 8) | |
| 65 | #define VI6_DL_CTRL_DC0 (1 << 4) | |
| 66 | #define VI6_DL_CTRL_CFM0 (1 << 2) | |
| 67 | #define VI6_DL_CTRL_NH0 (1 << 1) | |
| 68 | #define VI6_DL_CTRL_DLE (1 << 0) | |
| 69 | ||
| 70 | #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4) | |
| 71 | ||
| 72 | #define VI6_DL_SWAP 0x0114 | |
| 73 | #define VI6_DL_SWAP_LWS (1 << 2) | |
| 74 | #define VI6_DL_SWAP_WDS (1 << 1) | |
| 75 | #define VI6_DL_SWAP_BTS (1 << 0) | |
| 76 | ||
| 77 | #define VI6_DL_EXT_CTRL 0x011c | |
| 78 | #define VI6_DL_EXT_CTRL_NWE (1 << 16) | |
| 79 | #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8) | |
| 80 | #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8 | |
| 81 | #define VI6_DL_EXT_CTRL_DLPRI (1 << 5) | |
| 82 | #define VI6_DL_EXT_CTRL_EXPRI (1 << 4) | |
| 83 | #define VI6_DL_EXT_CTRL_EXT (1 << 0) | |
| 84 | ||
| 85 | #define VI6_DL_BODY_SIZE 0x0120 | |
| 86 | #define VI6_DL_BODY_SIZE_UPD (1 << 24) | |
| 87 | #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0) | |
| 88 | #define VI6_DL_BODY_SIZE_BS_SHIFT 0 | |
| 89 | ||
| 90 | /* ----------------------------------------------------------------------------- | |
| 91 | * RPF Control Registers | |
| 92 | */ | |
| 93 | ||
| 94 | #define VI6_RPF_OFFSET 0x100 | |
| 95 | ||
| 96 | #define VI6_RPF_SRC_BSIZE 0x0300 | |
| 97 | #define VI6_RPF_SRC_BSIZE_BHSIZE_MASK (0x1fff << 16) | |
| 98 | #define VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT 16 | |
| 99 | #define VI6_RPF_SRC_BSIZE_BVSIZE_MASK (0x1fff << 0) | |
| 100 | #define VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT 0 | |
| 101 | ||
| 102 | #define VI6_RPF_SRC_ESIZE 0x0304 | |
| 103 | #define VI6_RPF_SRC_ESIZE_EHSIZE_MASK (0x1fff << 16) | |
| 104 | #define VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT 16 | |
| 105 | #define VI6_RPF_SRC_ESIZE_EVSIZE_MASK (0x1fff << 0) | |
| 106 | #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0 | |
| 107 | ||
| 108 | #define VI6_RPF_INFMT 0x0308 | |
| 109 | #define VI6_RPF_INFMT_VIR (1 << 28) | |
| 110 | #define VI6_RPF_INFMT_CIPM (1 << 16) | |
| 111 | #define VI6_RPF_INFMT_SPYCS (1 << 15) | |
| 112 | #define VI6_RPF_INFMT_SPUVS (1 << 14) | |
| 113 | #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12) | |
| 114 | #define VI6_RPF_INFMT_CEXT_EXT (1 << 12) | |
| 115 | #define VI6_RPF_INFMT_CEXT_ONE (2 << 12) | |
| 116 | #define VI6_RPF_INFMT_CEXT_MASK (3 << 12) | |
| 117 | #define VI6_RPF_INFMT_RDTM_BT601 (0 << 9) | |
| 118 | #define VI6_RPF_INFMT_RDTM_BT601_EXT (1 << 9) | |
| 119 | #define VI6_RPF_INFMT_RDTM_BT709 (2 << 9) | |
| 120 | #define VI6_RPF_INFMT_RDTM_BT709_EXT (3 << 9) | |
| 121 | #define VI6_RPF_INFMT_RDTM_MASK (7 << 9) | |
| 122 | #define VI6_RPF_INFMT_CSC (1 << 8) | |
| 123 | #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0) | |
| 124 | #define VI6_RPF_INFMT_RDFMT_SHIFT 0 | |
| 125 | ||
| 126 | #define VI6_RPF_DSWAP 0x030c | |
| 127 | #define VI6_RPF_DSWAP_A_LLS (1 << 11) | |
| 128 | #define VI6_RPF_DSWAP_A_LWS (1 << 10) | |
| 129 | #define VI6_RPF_DSWAP_A_WDS (1 << 9) | |
| 130 | #define VI6_RPF_DSWAP_A_BTS (1 << 8) | |
| 131 | #define VI6_RPF_DSWAP_P_LLS (1 << 3) | |
| 132 | #define VI6_RPF_DSWAP_P_LWS (1 << 2) | |
| 133 | #define VI6_RPF_DSWAP_P_WDS (1 << 1) | |
| 134 | #define VI6_RPF_DSWAP_P_BTS (1 << 0) | |
| 135 | ||
| 136 | #define VI6_RPF_LOC 0x0310 | |
| 137 | #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16) | |
| 138 | #define VI6_RPF_LOC_HCOORD_SHIFT 16 | |
| 139 | #define VI6_RPF_LOC_VCOORD_MASK (0x1fff << 0) | |
| 140 | #define VI6_RPF_LOC_VCOORD_SHIFT 0 | |
| 141 | ||
| 142 | #define VI6_RPF_ALPH_SEL 0x0314 | |
| 143 | #define VI6_RPF_ALPH_SEL_ASEL_PACKED (0 << 28) | |
| 144 | #define VI6_RPF_ALPH_SEL_ASEL_8B_PLANE (1 << 28) | |
| 145 | #define VI6_RPF_ALPH_SEL_ASEL_SELECT (2 << 28) | |
| 146 | #define VI6_RPF_ALPH_SEL_ASEL_1B_PLANE (3 << 28) | |
| 147 | #define VI6_RPF_ALPH_SEL_ASEL_FIXED (4 << 28) | |
| 148 | #define VI6_RPF_ALPH_SEL_ASEL_MASK (7 << 28) | |
| 149 | #define VI6_RPF_ALPH_SEL_ASEL_SHIFT 28 | |
| 150 | #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24) | |
| 151 | #define VI6_RPF_ALPH_SEL_IROP_SHIFT 24 | |
| 152 | #define VI6_RPF_ALPH_SEL_BSEL (1 << 23) | |
| 153 | #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18) | |
| 154 | #define VI6_RPF_ALPH_SEL_AEXT_EXT (1 << 18) | |
| 155 | #define VI6_RPF_ALPH_SEL_AEXT_ONE (2 << 18) | |
| 156 | #define VI6_RPF_ALPH_SEL_AEXT_MASK (3 << 18) | |
| 04d983fc LP |
157 | #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8) |
| 158 | #define VI6_RPF_ALPH_SEL_ALPHA1_SHIFT 8 | |
| 159 | #define VI6_RPF_ALPH_SEL_ALPHA0_MASK (0xff << 0) | |
| 160 | #define VI6_RPF_ALPH_SEL_ALPHA0_SHIFT 0 | |
| 26e0ca22 LP |
161 | |
| 162 | #define VI6_RPF_VRTCOL_SET 0x0318 | |
| 163 | #define VI6_RPF_VRTCOL_SET_LAYA_MASK (0xff << 24) | |
| 164 | #define VI6_RPF_VRTCOL_SET_LAYA_SHIFT 24 | |
| 165 | #define VI6_RPF_VRTCOL_SET_LAYR_MASK (0xff << 16) | |
| 166 | #define VI6_RPF_VRTCOL_SET_LAYR_SHIFT 16 | |
| 167 | #define VI6_RPF_VRTCOL_SET_LAYG_MASK (0xff << 8) | |
| 168 | #define VI6_RPF_VRTCOL_SET_LAYG_SHIFT 8 | |
| 169 | #define VI6_RPF_VRTCOL_SET_LAYB_MASK (0xff << 0) | |
| 170 | #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0 | |
| 171 | ||
| 172 | #define VI6_RPF_MSK_CTRL 0x031c | |
| 173 | #define VI6_RPF_MSK_CTRL_MSK_EN (1 << 24) | |
| 174 | #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16) | |
| 175 | #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16 | |
| 176 | #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8) | |
| 177 | #define VI6_RPF_MSK_CTRL_MGG_SHIFT 8 | |
| 178 | #define VI6_RPF_MSK_CTRL_MGB_MASK (0xff << 0) | |
| 179 | #define VI6_RPF_MSK_CTRL_MGB_SHIFT 0 | |
| 180 | ||
| 181 | #define VI6_RPF_MSK_SET0 0x0320 | |
| 182 | #define VI6_RPF_MSK_SET1 0x0324 | |
| 183 | #define VI6_RPF_MSK_SET_MSA_MASK (0xff << 24) | |
| 184 | #define VI6_RPF_MSK_SET_MSA_SHIFT 24 | |
| 185 | #define VI6_RPF_MSK_SET_MSR_MASK (0xff << 16) | |
| 186 | #define VI6_RPF_MSK_SET_MSR_SHIFT 16 | |
| 187 | #define VI6_RPF_MSK_SET_MSG_MASK (0xff << 8) | |
| 188 | #define VI6_RPF_MSK_SET_MSG_SHIFT 8 | |
| 189 | #define VI6_RPF_MSK_SET_MSB_MASK (0xff << 0) | |
| 190 | #define VI6_RPF_MSK_SET_MSB_SHIFT 0 | |
| 191 | ||
| 192 | #define VI6_RPF_CKEY_CTRL 0x0328 | |
| 193 | #define VI6_RPF_CKEY_CTRL_CV (1 << 4) | |
| 194 | #define VI6_RPF_CKEY_CTRL_SAPE1 (1 << 1) | |
| 195 | #define VI6_RPF_CKEY_CTRL_SAPE0 (1 << 0) | |
| 196 | ||
| 197 | #define VI6_RPF_CKEY_SET0 0x032c | |
| 198 | #define VI6_RPF_CKEY_SET1 0x0330 | |
| 199 | #define VI6_RPF_CKEY_SET_AP_MASK (0xff << 24) | |
| 200 | #define VI6_RPF_CKEY_SET_AP_SHIFT 24 | |
| 201 | #define VI6_RPF_CKEY_SET_R_MASK (0xff << 16) | |
| 202 | #define VI6_RPF_CKEY_SET_R_SHIFT 16 | |
| 203 | #define VI6_RPF_CKEY_SET_GY_MASK (0xff << 8) | |
| 204 | #define VI6_RPF_CKEY_SET_GY_SHIFT 8 | |
| 205 | #define VI6_RPF_CKEY_SET_B_MASK (0xff << 0) | |
| 206 | #define VI6_RPF_CKEY_SET_B_SHIFT 0 | |
| 207 | ||
| 208 | #define VI6_RPF_SRCM_PSTRIDE 0x0334 | |
| 209 | #define VI6_RPF_SRCM_PSTRIDE_Y_SHIFT 16 | |
| 210 | #define VI6_RPF_SRCM_PSTRIDE_C_SHIFT 0 | |
| 211 | ||
| 212 | #define VI6_RPF_SRCM_ASTRIDE 0x0338 | |
| 213 | #define VI6_RPF_SRCM_PSTRIDE_A_SHIFT 0 | |
| 214 | ||
| 215 | #define VI6_RPF_SRCM_ADDR_Y 0x033c | |
| 216 | #define VI6_RPF_SRCM_ADDR_C0 0x0340 | |
| 217 | #define VI6_RPF_SRCM_ADDR_C1 0x0344 | |
| 218 | #define VI6_RPF_SRCM_ADDR_AI 0x0348 | |
| 219 | ||
| 30276a73 LP |
220 | #define VI6_RPF_MULT_ALPHA 0x036c |
| 221 | #define VI6_RPF_MULT_ALPHA_A_MMD_NONE (0 << 12) | |
| 222 | #define VI6_RPF_MULT_ALPHA_A_MMD_RATIO (1 << 12) | |
| 223 | #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8) | |
| 224 | #define VI6_RPF_MULT_ALPHA_P_MMD_RATIO (1 << 8) | |
| 225 | #define VI6_RPF_MULT_ALPHA_P_MMD_IMAGE (2 << 8) | |
| 226 | #define VI6_RPF_MULT_ALPHA_P_MMD_BOTH (3 << 8) | |
| 227 | #define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff < 0) | |
| 228 | #define VI6_RPF_MULT_ALPHA_RATIO_SHIFT 0 | |
| 229 | ||
| 26e0ca22 LP |
230 | /* ----------------------------------------------------------------------------- |
| 231 | * WPF Control Registers | |
| 232 | */ | |
| 233 | ||
| 234 | #define VI6_WPF_OFFSET 0x100 | |
| 235 | ||
| 236 | #define VI6_WPF_SRCRPF 0x1000 | |
| 237 | #define VI6_WPF_SRCRPF_VIRACT_DIS (0 << 28) | |
| 238 | #define VI6_WPF_SRCRPF_VIRACT_SUB (1 << 28) | |
| 239 | #define VI6_WPF_SRCRPF_VIRACT_MST (2 << 28) | |
| 240 | #define VI6_WPF_SRCRPF_VIRACT_MASK (3 << 28) | |
| 241 | #define VI6_WPF_SRCRPF_RPF_ACT_DIS(n) (0 << ((n) * 2)) | |
| 242 | #define VI6_WPF_SRCRPF_RPF_ACT_SUB(n) (1 << ((n) * 2)) | |
| 243 | #define VI6_WPF_SRCRPF_RPF_ACT_MST(n) (2 << ((n) * 2)) | |
| 244 | #define VI6_WPF_SRCRPF_RPF_ACT_MASK(n) (3 << ((n) * 2)) | |
| 245 | ||
| 246 | #define VI6_WPF_HSZCLIP 0x1004 | |
| 247 | #define VI6_WPF_VSZCLIP 0x1008 | |
| 248 | #define VI6_WPF_SZCLIP_EN (1 << 28) | |
| 249 | #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16) | |
| 250 | #define VI6_WPF_SZCLIP_OFST_SHIFT 16 | |
| 03b36e4d | 251 | #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0) |
| 26e0ca22 LP |
252 | #define VI6_WPF_SZCLIP_SIZE_SHIFT 0 |
| 253 | ||
| 254 | #define VI6_WPF_OUTFMT 0x100c | |
| 255 | #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24) | |
| 256 | #define VI6_WPF_OUTFMT_PDV_SHIFT 24 | |
| 257 | #define VI6_WPF_OUTFMT_PXA (1 << 23) | |
| 894dde5c LP |
258 | #define VI6_WPF_OUTFMT_ROT (1 << 18) |
| 259 | #define VI6_WPF_OUTFMT_HFLP (1 << 17) | |
| 26e0ca22 LP |
260 | #define VI6_WPF_OUTFMT_FLP (1 << 16) |
| 261 | #define VI6_WPF_OUTFMT_SPYCS (1 << 15) | |
| 262 | #define VI6_WPF_OUTFMT_SPUVS (1 << 14) | |
| 263 | #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12) | |
| 264 | #define VI6_WPF_OUTFMT_DITH_EN (3 << 12) | |
| 265 | #define VI6_WPF_OUTFMT_DITH_MASK (3 << 12) | |
| 266 | #define VI6_WPF_OUTFMT_WRTM_BT601 (0 << 9) | |
| 267 | #define VI6_WPF_OUTFMT_WRTM_BT601_EXT (1 << 9) | |
| 268 | #define VI6_WPF_OUTFMT_WRTM_BT709 (2 << 9) | |
| 269 | #define VI6_WPF_OUTFMT_WRTM_BT709_EXT (3 << 9) | |
| 270 | #define VI6_WPF_OUTFMT_WRTM_MASK (7 << 9) | |
| 271 | #define VI6_WPF_OUTFMT_CSC (1 << 8) | |
| 272 | #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0) | |
| 273 | #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0 | |
| 274 | ||
| 275 | #define VI6_WPF_DSWAP 0x1010 | |
| 276 | #define VI6_WPF_DSWAP_P_LLS (1 << 3) | |
| 277 | #define VI6_WPF_DSWAP_P_LWS (1 << 2) | |
| 278 | #define VI6_WPF_DSWAP_P_WDS (1 << 1) | |
| 279 | #define VI6_WPF_DSWAP_P_BTS (1 << 0) | |
| 280 | ||
| 281 | #define VI6_WPF_RNDCTRL 0x1014 | |
| 282 | #define VI6_WPF_RNDCTRL_CBRM (1 << 28) | |
| 283 | #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24) | |
| 284 | #define VI6_WPF_RNDCTRL_ABRM_ROUND (1 << 24) | |
| 285 | #define VI6_WPF_RNDCTRL_ABRM_THRESH (2 << 24) | |
| 286 | #define VI6_WPF_RNDCTRL_ABRM_MASK (3 << 24) | |
| 287 | #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16) | |
| 288 | #define VI6_WPF_RNDCTRL_ATHRESH_SHIFT 16 | |
| 289 | #define VI6_WPF_RNDCTRL_CLMD_FULL (0 << 12) | |
| 290 | #define VI6_WPF_RNDCTRL_CLMD_CLIP (1 << 12) | |
| 291 | #define VI6_WPF_RNDCTRL_CLMD_EXT (2 << 12) | |
| 292 | #define VI6_WPF_RNDCTRL_CLMD_MASK (3 << 12) | |
| 293 | ||
| 894dde5c LP |
294 | #define VI6_WPF_ROT_CTRL 0x1018 |
| 295 | #define VI6_WPF_ROT_CTRL_LN16 (1 << 17) | |
| 296 | #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0) | |
| 297 | #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0 | |
| 298 | ||
| 26e0ca22 LP |
299 | #define VI6_WPF_DSTM_STRIDE_Y 0x101c |
| 300 | #define VI6_WPF_DSTM_STRIDE_C 0x1020 | |
| 301 | #define VI6_WPF_DSTM_ADDR_Y 0x1024 | |
| 302 | #define VI6_WPF_DSTM_ADDR_C0 0x1028 | |
| 303 | #define VI6_WPF_DSTM_ADDR_C1 0x102c | |
| 304 | ||
| 305 | #define VI6_WPF_WRBCK_CTRL 0x1034 | |
| 306 | #define VI6_WPF_WRBCK_CTRL_WBMD (1 << 0) | |
| 307 | ||
| 308 | /* ----------------------------------------------------------------------------- | |
| 309 | * DPR Control Registers | |
| 310 | */ | |
| 311 | ||
| 312 | #define VI6_DPR_RPF_ROUTE(n) (0x2000 + (n) * 4) | |
| 313 | ||
| 314 | #define VI6_DPR_WPF_FPORCH(n) (0x2014 + (n) * 4) | |
| 315 | #define VI6_DPR_WPF_FPORCH_FP_WPFN (5 << 8) | |
| 316 | ||
| 317 | #define VI6_DPR_SRU_ROUTE 0x2024 | |
| 318 | #define VI6_DPR_UDS_ROUTE(n) (0x2028 + (n) * 4) | |
| 319 | #define VI6_DPR_LUT_ROUTE 0x203c | |
| 320 | #define VI6_DPR_CLU_ROUTE 0x2040 | |
| 321 | #define VI6_DPR_HST_ROUTE 0x2044 | |
| 322 | #define VI6_DPR_HSI_ROUTE 0x2048 | |
| 323 | #define VI6_DPR_BRU_ROUTE 0x204c | |
| 45008ee9 | 324 | #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16) |
| 26e0ca22 | 325 | #define VI6_DPR_ROUTE_FXA_SHIFT 16 |
| 1aa78903 | 326 | #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) |
| 26e0ca22 LP |
327 | #define VI6_DPR_ROUTE_FP_SHIFT 8 |
| 328 | #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0) | |
| 329 | #define VI6_DPR_ROUTE_RT_SHIFT 0 | |
| 330 | ||
| 331 | #define VI6_DPR_HGO_SMPPT 0x2050 | |
| 332 | #define VI6_DPR_HGT_SMPPT 0x2054 | |
| 333 | #define VI6_DPR_SMPPT_TGW_MASK (7 << 8) | |
| 334 | #define VI6_DPR_SMPPT_TGW_SHIFT 8 | |
| 335 | #define VI6_DPR_SMPPT_PT_MASK (0x3f << 0) | |
| 336 | #define VI6_DPR_SMPPT_PT_SHIFT 0 | |
| 337 | ||
| 338 | #define VI6_DPR_NODE_RPF(n) (n) | |
| 339 | #define VI6_DPR_NODE_SRU 16 | |
| 340 | #define VI6_DPR_NODE_UDS(n) (17 + (n)) | |
| 341 | #define VI6_DPR_NODE_LUT 22 | |
| 7f2d50f8 | 342 | #define VI6_DPR_NODE_BRU_IN(n) (((n) <= 3) ? 23 + (n) : 49) |
| 26e0ca22 LP |
343 | #define VI6_DPR_NODE_BRU_OUT 27 |
| 344 | #define VI6_DPR_NODE_CLU 29 | |
| 345 | #define VI6_DPR_NODE_HST 30 | |
| 346 | #define VI6_DPR_NODE_HSI 31 | |
| 347 | #define VI6_DPR_NODE_LIF 55 | |
| 348 | #define VI6_DPR_NODE_WPF(n) (56 + (n)) | |
| 349 | #define VI6_DPR_NODE_UNUSED 63 | |
| 350 | ||
| 351 | /* ----------------------------------------------------------------------------- | |
| 352 | * SRU Control Registers | |
| 353 | */ | |
| 354 | ||
| 355 | #define VI6_SRU_CTRL0 0x2200 | |
| 58f896d8 | 356 | #define VI6_SRU_CTRL0_PARAM0_MASK (0x1ff << 16) |
| a626e64e | 357 | #define VI6_SRU_CTRL0_PARAM0_SHIFT 16 |
| 58f896d8 | 358 | #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8) |
| a626e64e LP |
359 | #define VI6_SRU_CTRL0_PARAM1_SHIFT 8 |
| 360 | #define VI6_SRU_CTRL0_MODE_UPSCALE (4 << 4) | |
| 361 | #define VI6_SRU_CTRL0_PARAM2 (1 << 3) | |
| 362 | #define VI6_SRU_CTRL0_PARAM3 (1 << 2) | |
| 363 | #define VI6_SRU_CTRL0_PARAM4 (1 << 1) | |
| 364 | #define VI6_SRU_CTRL0_EN (1 << 0) | |
| 365 | ||
| 26e0ca22 | 366 | #define VI6_SRU_CTRL1 0x2204 |
| a626e64e LP |
367 | #define VI6_SRU_CTRL1_PARAM5 0x7ff |
| 368 | ||
| 26e0ca22 | 369 | #define VI6_SRU_CTRL2 0x2208 |
| a626e64e LP |
370 | #define VI6_SRU_CTRL2_PARAM6_SHIFT 16 |
| 371 | #define VI6_SRU_CTRL2_PARAM7_SHIFT 8 | |
| 372 | #define VI6_SRU_CTRL2_PARAM8_SHIFT 0 | |
| 26e0ca22 LP |
373 | |
| 374 | /* ----------------------------------------------------------------------------- | |
| 375 | * UDS Control Registers | |
| 376 | */ | |
| 377 | ||
| 378 | #define VI6_UDS_OFFSET 0x100 | |
| 379 | ||
| 380 | #define VI6_UDS_CTRL 0x2300 | |
| 381 | #define VI6_UDS_CTRL_AMD (1 << 30) | |
| 382 | #define VI6_UDS_CTRL_FMD (1 << 29) | |
| 383 | #define VI6_UDS_CTRL_BLADV (1 << 28) | |
| 384 | #define VI6_UDS_CTRL_AON (1 << 25) | |
| 385 | #define VI6_UDS_CTRL_ATHON (1 << 24) | |
| 386 | #define VI6_UDS_CTRL_BC (1 << 20) | |
| 387 | #define VI6_UDS_CTRL_NE_A (1 << 19) | |
| 388 | #define VI6_UDS_CTRL_NE_RCR (1 << 18) | |
| 389 | #define VI6_UDS_CTRL_NE_GY (1 << 17) | |
| 390 | #define VI6_UDS_CTRL_NE_BCB (1 << 16) | |
| 391 | #define VI6_UDS_CTRL_TDIPC (1 << 1) | |
| 392 | ||
| 393 | #define VI6_UDS_SCALE 0x2304 | |
| 394 | #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28) | |
| 395 | #define VI6_UDS_SCALE_HMANT_SHIFT 28 | |
| 396 | #define VI6_UDS_SCALE_HFRAC_MASK (0xfff << 16) | |
| 397 | #define VI6_UDS_SCALE_HFRAC_SHIFT 16 | |
| 398 | #define VI6_UDS_SCALE_VMANT_MASK (0xf << 12) | |
| 399 | #define VI6_UDS_SCALE_VMANT_SHIFT 12 | |
| 400 | #define VI6_UDS_SCALE_VFRAC_MASK (0xfff << 0) | |
| 401 | #define VI6_UDS_SCALE_VFRAC_SHIFT 0 | |
| 402 | ||
| 403 | #define VI6_UDS_ALPTH 0x2308 | |
| 404 | #define VI6_UDS_ALPTH_TH1_MASK (0xff << 8) | |
| 405 | #define VI6_UDS_ALPTH_TH1_SHIFT 8 | |
| 406 | #define VI6_UDS_ALPTH_TH0_MASK (0xff << 0) | |
| 407 | #define VI6_UDS_ALPTH_TH0_SHIFT 0 | |
| 408 | ||
| 409 | #define VI6_UDS_ALPVAL 0x230c | |
| 410 | #define VI6_UDS_ALPVAL_VAL2_MASK (0xff << 16) | |
| 411 | #define VI6_UDS_ALPVAL_VAL2_SHIFT 16 | |
| 412 | #define VI6_UDS_ALPVAL_VAL1_MASK (0xff << 8) | |
| 413 | #define VI6_UDS_ALPVAL_VAL1_SHIFT 8 | |
| 414 | #define VI6_UDS_ALPVAL_VAL0_MASK (0xff << 0) | |
| 415 | #define VI6_UDS_ALPVAL_VAL0_SHIFT 0 | |
| 416 | ||
| 417 | #define VI6_UDS_PASS_BWIDTH 0x2310 | |
| 418 | #define VI6_UDS_PASS_BWIDTH_H_MASK (0x7f << 16) | |
| 419 | #define VI6_UDS_PASS_BWIDTH_H_SHIFT 16 | |
| 420 | #define VI6_UDS_PASS_BWIDTH_V_MASK (0x7f << 0) | |
| 421 | #define VI6_UDS_PASS_BWIDTH_V_SHIFT 0 | |
| 422 | ||
| 423 | #define VI6_UDS_IPC 0x2318 | |
| 424 | #define VI6_UDS_IPC_FIELD (1 << 27) | |
| 425 | #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0) | |
| 426 | #define VI6_UDS_IPC_VEDP_SHIFT 0 | |
| 427 | ||
| 428 | #define VI6_UDS_CLIP_SIZE 0x2324 | |
| 429 | #define VI6_UDS_CLIP_SIZE_HSIZE_MASK (0x1fff << 16) | |
| 430 | #define VI6_UDS_CLIP_SIZE_HSIZE_SHIFT 16 | |
| 431 | #define VI6_UDS_CLIP_SIZE_VSIZE_MASK (0x1fff << 0) | |
| 432 | #define VI6_UDS_CLIP_SIZE_VSIZE_SHIFT 0 | |
| 433 | ||
| 434 | #define VI6_UDS_FILL_COLOR 0x2328 | |
| 435 | #define VI6_UDS_FILL_COLOR_RFILC_MASK (0xff << 16) | |
| 436 | #define VI6_UDS_FILL_COLOR_RFILC_SHIFT 16 | |
| 437 | #define VI6_UDS_FILL_COLOR_GFILC_MASK (0xff << 8) | |
| 438 | #define VI6_UDS_FILL_COLOR_GFILC_SHIFT 8 | |
| 439 | #define VI6_UDS_FILL_COLOR_BFILC_MASK (0xff << 0) | |
| 440 | #define VI6_UDS_FILL_COLOR_BFILC_SHIFT 0 | |
| 441 | ||
| 442 | /* ----------------------------------------------------------------------------- | |
| 443 | * LUT Control Registers | |
| 444 | */ | |
| 445 | ||
| 446 | #define VI6_LUT_CTRL 0x2800 | |
| 989af883 | 447 | #define VI6_LUT_CTRL_EN (1 << 0) |
| 26e0ca22 LP |
448 | |
| 449 | /* ----------------------------------------------------------------------------- | |
| 450 | * CLU Control Registers | |
| 451 | */ | |
| 452 | ||
| 453 | #define VI6_CLU_CTRL 0x2900 | |
| 1fd87bf2 LP |
454 | #define VI6_CLU_CTRL_AAI (1 << 28) |
| 455 | #define VI6_CLU_CTRL_MVS (1 << 24) | |
| 456 | #define VI6_CLU_CTRL_AX1I_2D (3 << 14) | |
| 457 | #define VI6_CLU_CTRL_AX2I_2D (1 << 12) | |
| 458 | #define VI6_CLU_CTRL_OS0_2D (3 << 8) | |
| 459 | #define VI6_CLU_CTRL_OS1_2D (1 << 6) | |
| 460 | #define VI6_CLU_CTRL_OS2_2D (3 << 4) | |
| 461 | #define VI6_CLU_CTRL_M2D (1 << 1) | |
| 462 | #define VI6_CLU_CTRL_EN (1 << 0) | |
| 26e0ca22 LP |
463 | |
| 464 | /* ----------------------------------------------------------------------------- | |
| 465 | * HST Control Registers | |
| 466 | */ | |
| 467 | ||
| 468 | #define VI6_HST_CTRL 0x2a00 | |
| 5cdf5741 | 469 | #define VI6_HST_CTRL_EN (1 << 0) |
| 26e0ca22 LP |
470 | |
| 471 | /* ----------------------------------------------------------------------------- | |
| 472 | * HSI Control Registers | |
| 473 | */ | |
| 474 | ||
| 475 | #define VI6_HSI_CTRL 0x2b00 | |
| 5cdf5741 | 476 | #define VI6_HSI_CTRL_EN (1 << 0) |
| 26e0ca22 LP |
477 | |
| 478 | /* ----------------------------------------------------------------------------- | |
| 479 | * BRU Control Registers | |
| 480 | */ | |
| 481 | ||
| 629bb6d4 LP |
482 | #define VI6_ROP_NOP 0 |
| 483 | #define VI6_ROP_AND 1 | |
| 484 | #define VI6_ROP_AND_REV 2 | |
| 485 | #define VI6_ROP_COPY 3 | |
| 486 | #define VI6_ROP_AND_INV 4 | |
| 487 | #define VI6_ROP_CLEAR 5 | |
| 488 | #define VI6_ROP_XOR 6 | |
| 489 | #define VI6_ROP_OR 7 | |
| 490 | #define VI6_ROP_NOR 8 | |
| 491 | #define VI6_ROP_EQUIV 9 | |
| 492 | #define VI6_ROP_INVERT 10 | |
| 493 | #define VI6_ROP_OR_REV 11 | |
| 494 | #define VI6_ROP_COPY_INV 12 | |
| 495 | #define VI6_ROP_OR_INV 13 | |
| 496 | #define VI6_ROP_NAND 14 | |
| 497 | #define VI6_ROP_SET 15 | |
| 498 | ||
| 26e0ca22 | 499 | #define VI6_BRU_INCTRL 0x2c00 |
| 629bb6d4 LP |
500 | #define VI6_BRU_INCTRL_NRM (1 << 28) |
| 501 | #define VI6_BRU_INCTRL_DnON (1 << (16 + (n))) | |
| 502 | #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4)) | |
| 503 | #define VI6_BRU_INCTRL_DITHn_18BPP (1 << ((n) * 4)) | |
| 504 | #define VI6_BRU_INCTRL_DITHn_16BPP (2 << ((n) * 4)) | |
| 505 | #define VI6_BRU_INCTRL_DITHn_15BPP (3 << ((n) * 4)) | |
| 506 | #define VI6_BRU_INCTRL_DITHn_12BPP (4 << ((n) * 4)) | |
| 507 | #define VI6_BRU_INCTRL_DITHn_8BPP (5 << ((n) * 4)) | |
| 508 | #define VI6_BRU_INCTRL_DITHn_MASK (7 << ((n) * 4)) | |
| 509 | #define VI6_BRU_INCTRL_DITHn_SHIFT ((n) * 4) | |
| 510 | ||
| 26e0ca22 | 511 | #define VI6_BRU_VIRRPF_SIZE 0x2c04 |
| 629bb6d4 LP |
512 | #define VI6_BRU_VIRRPF_SIZE_HSIZE_MASK (0x1fff << 16) |
| 513 | #define VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT 16 | |
| 514 | #define VI6_BRU_VIRRPF_SIZE_VSIZE_MASK (0x1fff << 0) | |
| 515 | #define VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT 0 | |
| 516 | ||
| 26e0ca22 | 517 | #define VI6_BRU_VIRRPF_LOC 0x2c08 |
| 629bb6d4 LP |
518 | #define VI6_BRU_VIRRPF_LOC_HCOORD_MASK (0x1fff << 16) |
| 519 | #define VI6_BRU_VIRRPF_LOC_HCOORD_SHIFT 16 | |
| 520 | #define VI6_BRU_VIRRPF_LOC_VCOORD_MASK (0x1fff << 0) | |
| 521 | #define VI6_BRU_VIRRPF_LOC_VCOORD_SHIFT 0 | |
| 522 | ||
| 26e0ca22 | 523 | #define VI6_BRU_VIRRPF_COL 0x2c0c |
| 629bb6d4 LP |
524 | #define VI6_BRU_VIRRPF_COL_A_MASK (0xff << 24) |
| 525 | #define VI6_BRU_VIRRPF_COL_A_SHIFT 24 | |
| 526 | #define VI6_BRU_VIRRPF_COL_RCR_MASK (0xff << 16) | |
| 527 | #define VI6_BRU_VIRRPF_COL_RCR_SHIFT 16 | |
| 528 | #define VI6_BRU_VIRRPF_COL_GY_MASK (0xff << 8) | |
| 529 | #define VI6_BRU_VIRRPF_COL_GY_SHIFT 8 | |
| 530 | #define VI6_BRU_VIRRPF_COL_BCB_MASK (0xff << 0) | |
| 531 | #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0 | |
| 532 | ||
| 7f2d50f8 | 533 | #define VI6_BRU_CTRL(n) (0x2c10 + (n) * 8 + ((n) <= 3 ? 0 : 4)) |
| 629bb6d4 | 534 | #define VI6_BRU_CTRL_RBC (1 << 31) |
| 7f2d50f8 | 535 | #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) |
| 629bb6d4 LP |
536 | #define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20) |
| 537 | #define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20) | |
| 7f2d50f8 | 538 | #define VI6_BRU_CTRL_SRCSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 16) |
| 629bb6d4 LP |
539 | #define VI6_BRU_CTRL_SRCSEL_VRPF (4 << 16) |
| 540 | #define VI6_BRU_CTRL_SRCSEL_MASK (7 << 16) | |
| 541 | #define VI6_BRU_CTRL_CROP(rop) ((rop) << 4) | |
| 542 | #define VI6_BRU_CTRL_CROP_MASK (0xf << 4) | |
| 543 | #define VI6_BRU_CTRL_AROP(rop) ((rop) << 0) | |
| 544 | #define VI6_BRU_CTRL_AROP_MASK (0xf << 0) | |
| 545 | ||
| 7f2d50f8 | 546 | #define VI6_BRU_BLD(n) (0x2c14 + (n) * 8 + ((n) <= 3 ? 0 : 4)) |
| 629bb6d4 LP |
547 | #define VI6_BRU_BLD_CBES (1 << 31) |
| 548 | #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28) | |
| 549 | #define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28) | |
| 550 | #define VI6_BRU_BLD_CCMDX_SRC_A (2 << 28) | |
| 551 | #define VI6_BRU_BLD_CCMDX_255_SRC_A (3 << 28) | |
| 552 | #define VI6_BRU_BLD_CCMDX_COEFX (4 << 28) | |
| 553 | #define VI6_BRU_BLD_CCMDX_MASK (7 << 28) | |
| 554 | #define VI6_BRU_BLD_CCMDY_DST_A (0 << 24) | |
| 555 | #define VI6_BRU_BLD_CCMDY_255_DST_A (1 << 24) | |
| 556 | #define VI6_BRU_BLD_CCMDY_SRC_A (2 << 24) | |
| 557 | #define VI6_BRU_BLD_CCMDY_255_SRC_A (3 << 24) | |
| 558 | #define VI6_BRU_BLD_CCMDY_COEFY (4 << 24) | |
| 559 | #define VI6_BRU_BLD_CCMDY_MASK (7 << 24) | |
| 560 | #define VI6_BRU_BLD_CCMDY_SHIFT 24 | |
| 561 | #define VI6_BRU_BLD_ABES (1 << 23) | |
| 562 | #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20) | |
| 563 | #define VI6_BRU_BLD_ACMDX_255_DST_A (1 << 20) | |
| 564 | #define VI6_BRU_BLD_ACMDX_SRC_A (2 << 20) | |
| 565 | #define VI6_BRU_BLD_ACMDX_255_SRC_A (3 << 20) | |
| 566 | #define VI6_BRU_BLD_ACMDX_COEFX (4 << 20) | |
| 567 | #define VI6_BRU_BLD_ACMDX_MASK (7 << 20) | |
| 568 | #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16) | |
| 569 | #define VI6_BRU_BLD_ACMDY_255_DST_A (1 << 16) | |
| 570 | #define VI6_BRU_BLD_ACMDY_SRC_A (2 << 16) | |
| 571 | #define VI6_BRU_BLD_ACMDY_255_SRC_A (3 << 16) | |
| 572 | #define VI6_BRU_BLD_ACMDY_COEFY (4 << 16) | |
| 573 | #define VI6_BRU_BLD_ACMDY_MASK (7 << 16) | |
| 574 | #define VI6_BRU_BLD_COEFX_MASK (0xff << 8) | |
| 575 | #define VI6_BRU_BLD_COEFX_SHIFT 8 | |
| 576 | #define VI6_BRU_BLD_COEFY_MASK (0xff << 0) | |
| 577 | #define VI6_BRU_BLD_COEFY_SHIFT 0 | |
| 578 | ||
| 26e0ca22 | 579 | #define VI6_BRU_ROP 0x2c30 |
| 7f2d50f8 | 580 | #define VI6_BRU_ROP_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) |
| 629bb6d4 LP |
581 | #define VI6_BRU_ROP_DSTSEL_VRPF (4 << 20) |
| 582 | #define VI6_BRU_ROP_DSTSEL_MASK (7 << 20) | |
| 583 | #define VI6_BRU_ROP_CROP(rop) ((rop) << 4) | |
| 584 | #define VI6_BRU_ROP_CROP_MASK (0xf << 4) | |
| 585 | #define VI6_BRU_ROP_AROP(rop) ((rop) << 0) | |
| 586 | #define VI6_BRU_ROP_AROP_MASK (0xf << 0) | |
| 26e0ca22 LP |
587 | |
| 588 | /* ----------------------------------------------------------------------------- | |
| 589 | * HGO Control Registers | |
| 590 | */ | |
| 591 | ||
| 592 | #define VI6_HGO_OFFSET 0x3000 | |
| 593 | #define VI6_HGO_SIZE 0x3004 | |
| 594 | #define VI6_HGO_MODE 0x3008 | |
| 595 | #define VI6_HGO_LB_TH 0x300c | |
| 596 | #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8) | |
| 597 | #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8) | |
| 598 | #define VI6_HGO_R_HISTO 0x3030 | |
| 599 | #define VI6_HGO_R_MAXMIN 0x3130 | |
| 600 | #define VI6_HGO_R_SUM 0x3134 | |
| 601 | #define VI6_HGO_R_LB_DET 0x3138 | |
| 602 | #define VI6_HGO_G_HISTO 0x3140 | |
| 603 | #define VI6_HGO_G_MAXMIN 0x3240 | |
| 604 | #define VI6_HGO_G_SUM 0x3244 | |
| 605 | #define VI6_HGO_G_LB_DET 0x3248 | |
| 606 | #define VI6_HGO_B_HISTO 0x3250 | |
| 607 | #define VI6_HGO_B_MAXMIN 0x3350 | |
| 608 | #define VI6_HGO_B_SUM 0x3354 | |
| 609 | #define VI6_HGO_B_LB_DET 0x3358 | |
| 610 | #define VI6_HGO_REGRST 0x33fc | |
| 611 | ||
| 612 | /* ----------------------------------------------------------------------------- | |
| 613 | * HGT Control Registers | |
| 614 | */ | |
| 615 | ||
| 616 | #define VI6_HGT_OFFSET 0x3400 | |
| 617 | #define VI6_HGT_SIZE 0x3404 | |
| 618 | #define VI6_HGT_MODE 0x3408 | |
| 619 | #define VI6_HGT_HUE_AREA(n) (0x340c + (n) * 4) | |
| 620 | #define VI6_HGT_LB_TH 0x3424 | |
| 621 | #define VI6_HGT_LBn_H(n) (0x3438 + (n) * 8) | |
| 622 | #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8) | |
| 623 | #define VI6_HGT_HISTO(m, n) (0x3450 + (m) * 128 + (n) * 4) | |
| 624 | #define VI6_HGT_MAXMIN 0x3750 | |
| 625 | #define VI6_HGT_SUM 0x3754 | |
| 626 | #define VI6_HGT_LB_DET 0x3758 | |
| 627 | #define VI6_HGT_REGRST 0x37fc | |
| 628 | ||
| 629 | /* ----------------------------------------------------------------------------- | |
| 630 | * LIF Control Registers | |
| 631 | */ | |
| 632 | ||
| 633 | #define VI6_LIF_CTRL 0x3b00 | |
| 634 | #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16) | |
| 635 | #define VI6_LIF_CTRL_OBTH_SHIFT 16 | |
| 636 | #define VI6_LIF_CTRL_CFMT (1 << 4) | |
| 637 | #define VI6_LIF_CTRL_REQSEL (1 << 1) | |
| 638 | #define VI6_LIF_CTRL_LIF_EN (1 << 0) | |
| 639 | ||
| 640 | #define VI6_LIF_CSBTH 0x3b04 | |
| 641 | #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16) | |
| 642 | #define VI6_LIF_CSBTH_HBTH_SHIFT 16 | |
| 643 | #define VI6_LIF_CSBTH_LBTH_MASK (0x7ff << 0) | |
| 644 | #define VI6_LIF_CSBTH_LBTH_SHIFT 0 | |
| 645 | ||
| 646 | /* ----------------------------------------------------------------------------- | |
| 647 | * Security Control Registers | |
| 648 | */ | |
| 649 | ||
| 650 | #define VI6_SECURITY_CTRL0 0x3d00 | |
| 651 | #define VI6_SECURITY_CTRL1 0x3d04 | |
| 652 | ||
| 7f2d50f8 LP |
653 | /* ----------------------------------------------------------------------------- |
| 654 | * IP Version Registers | |
| 655 | */ | |
| 656 | ||
| 657 | #define VI6_IP_VERSION 0x3f00 | |
| 658 | #define VI6_IP_VERSION_MODEL_MASK (0xff << 8) | |
| 659 | #define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8) | |
| 660 | #define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8) | |
| 661 | #define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8) | |
| 662 | #define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8) | |
| 663 | #define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8) | |
| 664 | #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8) | |
| 665 | #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8) | |
| 666 | #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8) | |
| 667 | #define VI6_IP_VERSION_SOC_MASK (0xff << 0) | |
| 668 | #define VI6_IP_VERSION_SOC_H (0x01 << 0) | |
| 669 | #define VI6_IP_VERSION_SOC_M (0x02 << 0) | |
| 670 | ||
| 26e0ca22 LP |
671 | /* ----------------------------------------------------------------------------- |
| 672 | * RPF CLUT Registers | |
| 673 | */ | |
| 674 | ||
| 675 | #define VI6_CLUT_TABLE 0x4000 | |
| 676 | ||
| 677 | /* ----------------------------------------------------------------------------- | |
| 678 | * 1D LUT Registers | |
| 679 | */ | |
| 680 | ||
| 681 | #define VI6_LUT_TABLE 0x7000 | |
| 682 | ||
| 683 | /* ----------------------------------------------------------------------------- | |
| 684 | * 3D LUT Registers | |
| 685 | */ | |
| 686 | ||
| 687 | #define VI6_CLU_ADDR 0x7400 | |
| 688 | #define VI6_CLU_DATA 0x7404 | |
| 689 | ||
| 690 | /* ----------------------------------------------------------------------------- | |
| 691 | * Formats | |
| 692 | */ | |
| 693 | ||
| 694 | #define VI6_FMT_RGB_332 0x00 | |
| 695 | #define VI6_FMT_XRGB_4444 0x01 | |
| 696 | #define VI6_FMT_RGBX_4444 0x02 | |
| 697 | #define VI6_FMT_XRGB_1555 0x04 | |
| 698 | #define VI6_FMT_RGBX_5551 0x05 | |
| 699 | #define VI6_FMT_RGB_565 0x06 | |
| 700 | #define VI6_FMT_AXRGB_86666 0x07 | |
| 701 | #define VI6_FMT_RGBXA_66668 0x08 | |
| 702 | #define VI6_FMT_XRGBA_66668 0x09 | |
| 703 | #define VI6_FMT_ARGBX_86666 0x0a | |
| 704 | #define VI6_FMT_AXRXGXB_8262626 0x0b | |
| 705 | #define VI6_FMT_XRXGXBA_2626268 0x0c | |
| 706 | #define VI6_FMT_ARXGXBX_8626262 0x0d | |
| 707 | #define VI6_FMT_RXGXBXA_6262628 0x0e | |
| 708 | #define VI6_FMT_XRGB_6666 0x0f | |
| 709 | #define VI6_FMT_RGBX_6666 0x10 | |
| 710 | #define VI6_FMT_XRXGXB_262626 0x11 | |
| 711 | #define VI6_FMT_RXGXBX_626262 0x12 | |
| 712 | #define VI6_FMT_ARGB_8888 0x13 | |
| 713 | #define VI6_FMT_RGBA_8888 0x14 | |
| 714 | #define VI6_FMT_RGB_888 0x15 | |
| 715 | #define VI6_FMT_XRGXGB_763763 0x16 | |
| 716 | #define VI6_FMT_XXRGB_86666 0x17 | |
| 717 | #define VI6_FMT_BGR_888 0x18 | |
| 718 | #define VI6_FMT_ARGB_4444 0x19 | |
| 719 | #define VI6_FMT_RGBA_4444 0x1a | |
| 720 | #define VI6_FMT_ARGB_1555 0x1b | |
| 721 | #define VI6_FMT_RGBA_5551 0x1c | |
| 722 | #define VI6_FMT_ABGR_4444 0x1d | |
| 723 | #define VI6_FMT_BGRA_4444 0x1e | |
| 724 | #define VI6_FMT_ABGR_1555 0x1f | |
| 725 | #define VI6_FMT_BGRA_5551 0x20 | |
| 726 | #define VI6_FMT_XBXGXR_262626 0x21 | |
| 727 | #define VI6_FMT_ABGR_8888 0x22 | |
| 728 | #define VI6_FMT_XXRGB_88565 0x23 | |
| 729 | ||
| 730 | #define VI6_FMT_Y_UV_444 0x40 | |
| 731 | #define VI6_FMT_Y_UV_422 0x41 | |
| 732 | #define VI6_FMT_Y_UV_420 0x42 | |
| 733 | #define VI6_FMT_YUV_444 0x46 | |
| 734 | #define VI6_FMT_YUYV_422 0x47 | |
| 735 | #define VI6_FMT_YYUV_422 0x48 | |
| 736 | #define VI6_FMT_YUV_420 0x49 | |
| 737 | #define VI6_FMT_Y_U_V_444 0x4a | |
| 738 | #define VI6_FMT_Y_U_V_422 0x4b | |
| 739 | #define VI6_FMT_Y_U_V_420 0x4c | |
| 740 | ||
| 741 | #endif /* __VSP1_REGS_H__ */ |