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PNP: ide/ide-pnp: Use module_pnp_driver to register driver
[deliverable/linux.git] / drivers / media / rc / fintek-cir.c
CommitLineData
9bdc79ea
JW		 1/*
2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
3 *
4 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
5 *
6 * Special thanks to Fintek for providing hardware and spec sheets.
7 * This driver is based upon the nuvoton, ite and ene drivers for
8 * similar hardware.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 */
25
563cd5ce
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
9bdc79ea
JW		 28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pnp.h>
31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
35#include <media/rc-core.h>
36#include <linux/pci_ids.h>
37
38#include "fintek-cir.h"
39
40/* write val to config reg */
41static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
42{
43 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
44 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
45 outb(reg, fintek->cr_ip);
46 outb(val, fintek->cr_dp);
47}
48
49/* read val from config reg */
50static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
51{
52 u8 val;
53
54 outb(reg, fintek->cr_ip);
55 val = inb(fintek->cr_dp);
56
57 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
58 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
59 return val;
60}
61
62/* update config register bit without changing other bits */
63static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
64{
65 u8 tmp = fintek_cr_read(fintek, reg) | val;
66 fintek_cr_write(fintek, tmp, reg);
67}
68
69/* clear config register bit without changing other bits */
70static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
71{
72 u8 tmp = fintek_cr_read(fintek, reg) & ~val;
73 fintek_cr_write(fintek, tmp, reg);
74}
75
76/* enter config mode */
77static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
78{
79 /* Enabling Config Mode explicitly requires writing 2x */
80 outb(CONFIG_REG_ENABLE, fintek->cr_ip);
81 outb(CONFIG_REG_ENABLE, fintek->cr_ip);
82}
83
84/* exit config mode */
85static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
86{
87 outb(CONFIG_REG_DISABLE, fintek->cr_ip);
88}
89
90/*
91 * When you want to address a specific logical device, write its logical
92 * device number to GCR_LOGICAL_DEV_NO
93 */
94static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
95{
96 fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
97}
98
99/* write val to cir config register */
100static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
101{
102 outb(val, fintek->cir_addr + offset);
103}
104
105/* read val from cir config register */
106static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
107{
108 u8 val;
109
110 val = inb(fintek->cir_addr + offset);
111
112 return val;
113}
114
9bdc79ea
JW		 115/* dump current cir register contents */
116static void cir_dump_regs(struct fintek_dev *fintek)
117{
118 fintek_config_mode_enable(fintek);
83ec8225 119 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea 120
563cd5ce
JP		 121 pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
122 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
123 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
9bdc79ea 124 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
563cd5ce
JP		 125 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
126 fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
9bdc79ea
JW		 127
128 fintek_config_mode_disable(fintek);
129
563cd5ce
JP		 130 pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
131 pr_info(" * STATUS: 0x%x\n",
132 fintek_cir_reg_read(fintek, CIR_STATUS));
133 pr_info(" * CONTROL: 0x%x\n",
134 fintek_cir_reg_read(fintek, CIR_CONTROL));
135 pr_info(" * RX_DATA: 0x%x\n",
136 fintek_cir_reg_read(fintek, CIR_RX_DATA));
137 pr_info(" * TX_CONTROL: 0x%x\n",
138 fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
139 pr_info(" * TX_DATA: 0x%x\n",
140 fintek_cir_reg_read(fintek, CIR_TX_DATA));
9bdc79ea
JW		 141}
142
143/* detect hardware features */
144static int fintek_hw_detect(struct fintek_dev *fintek)
145{
146 unsigned long flags;
147 u8 chip_major, chip_minor;
148 u8 vendor_major, vendor_minor;
149 u8 portsel, ir_class;
83ec8225 150 u16 vendor, chip;
9bdc79ea
JW		 151
152 fintek_config_mode_enable(fintek);
153
154 /* Check if we're using config port 0x4e or 0x2e */
155 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
156 if (portsel == 0xff) {
157 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
158 fintek_config_mode_disable(fintek);
159 fintek->cr_ip = CR_INDEX_PORT2;
160 fintek->cr_dp = CR_DATA_PORT2;
161 fintek_config_mode_enable(fintek);
162 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
163 }
164 fit_dbg("portsel reg: 0x%02x", portsel);
165
166 ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
167 fit_dbg("ir_class reg: 0x%02x", ir_class);
168
169 switch (ir_class) {
170 case CLASS_RX_2TX:
171 case CLASS_RX_1TX:
172 fintek->hw_tx_capable = true;
173 break;
174 case CLASS_RX_ONLY:
175 default:
176 fintek->hw_tx_capable = false;
177 break;
178 }
179
180 chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
181 chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
83ec8225 182 chip = chip_major << 8 | chip_minor;
9bdc79ea
JW		 183
184 vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
185 vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
186 vendor = vendor_major << 8 | vendor_minor;
187
188 if (vendor != VENDOR_ID_FINTEK)
189 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
190 else
191 fit_dbg("Read Fintek vendor ID from chip");
192
193 fintek_config_mode_disable(fintek);
194
195 spin_lock_irqsave(&fintek->fintek_lock, flags);
196 fintek->chip_major = chip_major;
197 fintek->chip_minor = chip_minor;
198 fintek->chip_vendor = vendor;
83ec8225
MCC		 199
200 /*
201 * Newer reviews of this chipset uses port 8 instead of 5
202 */
3e1fd478 203 if ((chip != 0x0408) && (chip != 0x0804))
83ec8225
MCC		 204 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
205 else
206 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
207
9bdc79ea
JW		 208 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
209
9b08f417 210 return 0;
9bdc79ea
JW		 211}
212
213static void fintek_cir_ldev_init(struct fintek_dev *fintek)
214{
215 /* Select CIR logical device and enable */
83ec8225 216 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea
JW		 217 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
218
219 /* Write allocated CIR address and IRQ information to hardware */
220 fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
221 fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
222
223 fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
224
225 fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
226 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
227}
228
229/* enable CIR interrupts */
230static void fintek_enable_cir_irq(struct fintek_dev *fintek)
231{
232 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
233}
234
235static void fintek_cir_regs_init(struct fintek_dev *fintek)
236{
237 /* clear any and all stray interrupts */
238 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
239
240 /* and finally, enable interrupts */
241 fintek_enable_cir_irq(fintek);
242}
243
244static void fintek_enable_wake(struct fintek_dev *fintek)
245{
246 fintek_config_mode_enable(fintek);
247 fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
248
249 /* Allow CIR PME's to wake system */
250 fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
251 /* Enable CIR PME's */
252 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
253 /* Clear CIR PME status register */
254 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
255 /* Save state */
256 fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
257
258 fintek_config_mode_disable(fintek);
259}
260
261static int fintek_cmdsize(u8 cmd, u8 subcmd)
262{
263 int datasize = 0;
264
265 switch (cmd) {
266 case BUF_COMMAND_NULL:
267 if (subcmd == BUF_HW_CMD_HEADER)
268 datasize = 1;
269 break;
270 case BUF_HW_CMD_HEADER:
271 if (subcmd == BUF_CMD_G_REVISION)
272 datasize = 2;
273 break;
274 case BUF_COMMAND_HEADER:
275 switch (subcmd) {
276 case BUF_CMD_S_CARRIER:
277 case BUF_CMD_S_TIMEOUT:
278 case BUF_RSP_PULSE_COUNT:
279 datasize = 2;
280 break;
281 case BUF_CMD_SIG_END:
282 case BUF_CMD_S_TXMASK:
283 case BUF_CMD_S_RXSENSOR:
284 datasize = 1;
285 break;
286 }
287 }
288
289 return datasize;
290}
291
292/* process ir data stored in driver buffer */
293static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
294{
295 DEFINE_IR_RAW_EVENT(rawir);
296 u8 sample;
b83bfd1b 297 bool event = false;
9bdc79ea
JW		 298 int i;
299
300 for (i = 0; i < fintek->pkts; i++) {
301 sample = fintek->buf[i];
302 switch (fintek->parser_state) {
303 case CMD_HEADER:
304 fintek->cmd = sample;
305 if ((fintek->cmd == BUF_COMMAND_HEADER) ||
306 ((fintek->cmd & BUF_COMMAND_MASK) !=
307 BUF_PULSE_BIT)) {
308 fintek->parser_state = SUBCMD;
309 continue;
310 }
311 fintek->rem = (fintek->cmd & BUF_LEN_MASK);
312 fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
313 if (fintek->rem)
314 fintek->parser_state = PARSE_IRDATA;
315 else
316 ir_raw_event_reset(fintek->rdev);
317 break;
318 case SUBCMD:
319 fintek->rem = fintek_cmdsize(fintek->cmd, sample);
320 fintek->parser_state = CMD_DATA;
321 break;
322 case CMD_DATA:
323 fintek->rem--;
324 break;
325 case PARSE_IRDATA:
326 fintek->rem--;
327 init_ir_raw_event(&rawir);
328 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
329 rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
330 * CIR_SAMPLE_PERIOD);
331
332 fit_dbg("Storing %s with duration %d",
333 rawir.pulse ? "pulse" : "space",
334 rawir.duration);
b83bfd1b
SY		 335 if (ir_raw_event_store_with_filter(fintek->rdev,
336 &rawir))
337 event = true;
9bdc79ea
JW		 338 break;
339 }
340
341 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
342 fintek->parser_state = CMD_HEADER;
343 }
344
345 fintek->pkts = 0;
346
b83bfd1b
SY		 347 if (event) {
348 fit_dbg("Calling ir_raw_event_handle");
349 ir_raw_event_handle(fintek->rdev);
350 }
9bdc79ea
JW		 351}
352
353/* copy data from hardware rx register into driver buffer */
354static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
355{
356 unsigned long flags;
357 u8 sample, status;
358
359 spin_lock_irqsave(&fintek->fintek_lock, flags);
360
361 /*
362 * We must read data from CIR_RX_DATA until the hardware IR buffer
363 * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
364 * the CIR_STATUS register
365 */
366 do {
367 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
368 fit_dbg("%s: sample: 0x%02x", __func__, sample);
369
370 fintek->buf[fintek->pkts] = sample;
371 fintek->pkts++;
372
373 status = fintek_cir_reg_read(fintek, CIR_STATUS);
374 if (!(status & CIR_STATUS_IRQ_EN))
375 break;
376 } while (status & rx_irqs);
377
378 fintek_process_rx_ir_data(fintek);
379
380 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
381}
382
383static void fintek_cir_log_irqs(u8 status)
384{
385 fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
386 status & CIR_STATUS_IRQ_EN ? " IRQEN" : "",
387 status & CIR_STATUS_TX_FINISH ? " TXF" : "",
388 status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "",
389 status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "",
390 status & CIR_STATUS_RX_RECEIVE ? " RXOK" : "");
391}
392
393/* interrupt service routine for incoming and outgoing CIR data */
394static irqreturn_t fintek_cir_isr(int irq, void *data)
395{
396 struct fintek_dev *fintek = data;
397 u8 status, rx_irqs;
398
399 fit_dbg_verbose("%s firing", __func__);
400
401 fintek_config_mode_enable(fintek);
83ec8225 402 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea
JW		 403 fintek_config_mode_disable(fintek);
404
405 /*
406 * Get IR Status register contents. Write 1 to ack/clear
407 *
408 * bit: reg name - description
409 * 3: TX_FINISH - TX is finished
410 * 2: TX_UNDERRUN - TX underrun
411 * 1: RX_TIMEOUT - RX data timeout
412 * 0: RX_RECEIVE - RX data received
413 */
414 status = fintek_cir_reg_read(fintek, CIR_STATUS);
415 if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
416 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
417 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
418 return IRQ_RETVAL(IRQ_NONE);
419 }
420
421 if (debug)
422 fintek_cir_log_irqs(status);
423
424 rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
425 if (rx_irqs)
426 fintek_get_rx_ir_data(fintek, rx_irqs);
427
428 /* ack/clear all irq flags we've got */
429 fintek_cir_reg_write(fintek, status, CIR_STATUS);
430
431 fit_dbg_verbose("%s done", __func__);
432 return IRQ_RETVAL(IRQ_HANDLED);
433}
434
435static void fintek_enable_cir(struct fintek_dev *fintek)
436{
437 /* set IRQ enabled */
438 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
439
440 fintek_config_mode_enable(fintek);
441
442 /* enable the CIR logical device */
83ec8225 443 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea
JW		 444 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
445
446 fintek_config_mode_disable(fintek);
447
448 /* clear all pending interrupts */
449 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
450
451 /* enable interrupts */
452 fintek_enable_cir_irq(fintek);
453}
454
455static void fintek_disable_cir(struct fintek_dev *fintek)
456{
457 fintek_config_mode_enable(fintek);
458
459 /* disable the CIR logical device */
83ec8225 460 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea
JW		 461 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
462
463 fintek_config_mode_disable(fintek);
464}
465
466static int fintek_open(struct rc_dev *dev)
467{
468 struct fintek_dev *fintek = dev->priv;
469 unsigned long flags;
470
471 spin_lock_irqsave(&fintek->fintek_lock, flags);
472 fintek_enable_cir(fintek);
473 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
474
475 return 0;
476}
477
478static void fintek_close(struct rc_dev *dev)
479{
480 struct fintek_dev *fintek = dev->priv;
481 unsigned long flags;
482
483 spin_lock_irqsave(&fintek->fintek_lock, flags);
484 fintek_disable_cir(fintek);
485 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
486}
487
488/* Allocate memory, probe hardware, and initialize everything */
489static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
490{
491 struct fintek_dev *fintek;
492 struct rc_dev *rdev;
493 int ret = -ENOMEM;
494
495 fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
496 if (!fintek)
497 return ret;
498
499 /* input device for IR remote (and tx) */
500 rdev = rc_allocate_device();
501 if (!rdev)
70ef6991 502 goto exit_free_dev_rdev;
9bdc79ea
JW		 503
504 ret = -ENODEV;
505 /* validate pnp resources */
506 if (!pnp_port_valid(pdev, 0)) {
507 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 508 goto exit_free_dev_rdev;
9bdc79ea
JW		 509 }
510
511 if (!pnp_irq_valid(pdev, 0)) {
512 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
70ef6991 513 goto exit_free_dev_rdev;
9bdc79ea
JW		 514 }
515
516 fintek->cir_addr = pnp_port_start(pdev, 0);
517 fintek->cir_irq = pnp_irq(pdev, 0);
518 fintek->cir_port_len = pnp_port_len(pdev, 0);
519
520 fintek->cr_ip = CR_INDEX_PORT;
521 fintek->cr_dp = CR_DATA_PORT;
522
523 spin_lock_init(&fintek->fintek_lock);
524
9bdc79ea
JW		 525 pnp_set_drvdata(pdev, fintek);
526 fintek->pdev = pdev;
527
528 ret = fintek_hw_detect(fintek);
529 if (ret)
70ef6991 530 goto exit_free_dev_rdev;
9bdc79ea
JW		 531
532 /* Initialize CIR & CIR Wake Logical Devices */
533 fintek_config_mode_enable(fintek);
534 fintek_cir_ldev_init(fintek);
535 fintek_config_mode_disable(fintek);
536
537 /* Initialize CIR & CIR Wake Config Registers */
538 fintek_cir_regs_init(fintek);
539
540 /* Set up the rc device */
541 rdev->priv = fintek;
542 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 543 rdev->allowed_protocols = RC_BIT_ALL;
9bdc79ea
JW		 544 rdev->open = fintek_open;
545 rdev->close = fintek_close;
546 rdev->input_name = FINTEK_DESCRIPTION;
547 rdev->input_phys = "fintek/cir0";
548 rdev->input_id.bustype = BUS_HOST;
549 rdev->input_id.vendor = VENDOR_ID_FINTEK;
550 rdev->input_id.product = fintek->chip_major;
551 rdev->input_id.version = fintek->chip_minor;
552 rdev->dev.parent = &pdev->dev;
553 rdev->driver_name = FINTEK_DRIVER_NAME;
554 rdev->map_name = RC_MAP_RC6_MCE;
555 rdev->timeout = US_TO_NS(1000);
556 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
557 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
558
d62b6818
MK		 559 fintek->rdev = rdev;
560
9ef449c6
LH		 561 ret = -EBUSY;
562 /* now claim resources */
563 if (!request_region(fintek->cir_addr,
564 fintek->cir_port_len, FINTEK_DRIVER_NAME))
70ef6991 565 goto exit_free_dev_rdev;
9ef449c6
LH		 566
567 if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
568 FINTEK_DRIVER_NAME, (void *)fintek))
70ef6991 569 goto exit_free_cir_addr;
9ef449c6 570
9bdc79ea
JW		 571 ret = rc_register_device(rdev);
572 if (ret)
70ef6991 573 goto exit_free_irq;
9bdc79ea
JW		 574
575 device_init_wakeup(&pdev->dev, true);
d62b6818 576
9bdc79ea
JW		 577 fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
578 if (debug)
579 cir_dump_regs(fintek);
580
581 return 0;
582
70ef6991 583exit_free_irq:
f27b853e 584 free_irq(fintek->cir_irq, fintek);
70ef6991 585exit_free_cir_addr:
f27b853e 586 release_region(fintek->cir_addr, fintek->cir_port_len);
70ef6991 587exit_free_dev_rdev:
9bdc79ea
JW		 588 rc_free_device(rdev);
589 kfree(fintek);
590
591 return ret;
592}
593
4c62e976 594static void fintek_remove(struct pnp_dev *pdev)
9bdc79ea
JW		 595{
596 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
597 unsigned long flags;
598
599 spin_lock_irqsave(&fintek->fintek_lock, flags);
600 /* disable CIR */
601 fintek_disable_cir(fintek);
602 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
603 /* enable CIR Wake (for IR power-on) */
604 fintek_enable_wake(fintek);
605 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
606
607 /* free resources */
608 free_irq(fintek->cir_irq, fintek);
609 release_region(fintek->cir_addr, fintek->cir_port_len);
610
611 rc_unregister_device(fintek->rdev);
612
613 kfree(fintek);
614}
615
616static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
617{
618 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
0ae90252 619 unsigned long flags;
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JW		 620
621 fit_dbg("%s called", __func__);
622
0ae90252
JW		 623 spin_lock_irqsave(&fintek->fintek_lock, flags);
624
9bdc79ea
JW		 625 /* disable all CIR interrupts */
626 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
627
0ae90252
JW		 628 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
629
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JW		 630 fintek_config_mode_enable(fintek);
631
632 /* disable cir logical dev */
83ec8225 633 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
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JW		 634 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
635
636 fintek_config_mode_disable(fintek);
637
638 /* make sure wake is enabled */
639 fintek_enable_wake(fintek);
640
641 return 0;
642}
643
644static int fintek_resume(struct pnp_dev *pdev)
645{
9bdc79ea
JW		 646 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
647
648 fit_dbg("%s called", __func__);
649
650 /* open interrupt */
651 fintek_enable_cir_irq(fintek);
652
653 /* Enable CIR logical device */
654 fintek_config_mode_enable(fintek);
83ec8225 655 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
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JW		 656 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
657
658 fintek_config_mode_disable(fintek);
659
660 fintek_cir_regs_init(fintek);
661
9b08f417 662 return 0;
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JW		 663}
664
665static void fintek_shutdown(struct pnp_dev *pdev)
666{
667 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
668 fintek_enable_wake(fintek);
669}
670
671static const struct pnp_device_id fintek_ids[] = {
672 { "FIT0002", 0 }, /* CIR */
673 { "", 0 },
674};
675
676static struct pnp_driver fintek_driver = {
677 .name = FINTEK_DRIVER_NAME,
678 .id_table = fintek_ids,
679 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
680 .probe = fintek_probe,
4c62e976 681 .remove = fintek_remove,
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JW		 682 .suspend = fintek_suspend,
683 .resume = fintek_resume,
684 .shutdown = fintek_shutdown,
685};
686
d6740d86 687static int __init fintek_init(void)
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JW		 688{
689 return pnp_register_driver(&fintek_driver);
690}
691
d6740d86 692static void __exit fintek_exit(void)
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JW		 693{
694 pnp_unregister_driver(&fintek_driver);
695}
696
697module_param(debug, int, S_IRUGO | S_IWUSR);
698MODULE_PARM_DESC(debug, "Enable debugging output");
699
700MODULE_DEVICE_TABLE(pnp, fintek_ids);
701MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
702
703MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
704MODULE_LICENSE("GPL");
705
706module_init(fintek_init);
707module_exit(fintek_exit);
Linux kernel - Deliverables
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