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9bdc79ea JW |
1 | /* |
2 | * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR | |
3 | * | |
4 | * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com> | |
5 | * | |
6 | * Special thanks to Fintek for providing hardware and spec sheets. | |
7 | * This driver is based upon the nuvoton, ite and ene drivers for | |
8 | * similar hardware. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
23 | * USA | |
24 | */ | |
25 | ||
26 | #include <linux/spinlock.h> | |
27 | #include <linux/ioctl.h> | |
28 | ||
29 | /* platform driver name to register */ | |
30 | #define FINTEK_DRIVER_NAME "fintek-cir" | |
31 | #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver" | |
32 | #define VENDOR_ID_FINTEK 0x1934 | |
33 | ||
34 | ||
35 | /* debugging module parameter */ | |
36 | static int debug; | |
37 | ||
38 | #define fit_pr(level, text, ...) \ | |
39 | printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) | |
40 | ||
41 | #define fit_dbg(text, ...) \ | |
42 | if (debug) \ | |
43 | printk(KERN_DEBUG \ | |
44 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) | |
45 | ||
46 | #define fit_dbg_verbose(text, ...) \ | |
47 | if (debug > 1) \ | |
48 | printk(KERN_DEBUG \ | |
49 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) | |
50 | ||
51 | #define fit_dbg_wake(text, ...) \ | |
52 | if (debug > 2) \ | |
53 | printk(KERN_DEBUG \ | |
54 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) | |
55 | ||
56 | ||
57 | #define TX_BUF_LEN 256 | |
58 | #define RX_BUF_LEN 32 | |
59 | ||
60 | struct fintek_dev { | |
61 | struct pnp_dev *pdev; | |
62 | struct rc_dev *rdev; | |
63 | ||
64 | spinlock_t fintek_lock; | |
65 | ||
66 | /* for rx */ | |
67 | u8 buf[RX_BUF_LEN]; | |
68 | unsigned int pkts; | |
69 | ||
70 | struct { | |
71 | spinlock_t lock; | |
72 | u8 buf[TX_BUF_LEN]; | |
73 | unsigned int buf_count; | |
74 | unsigned int cur_buf_num; | |
75 | wait_queue_head_t queue; | |
76 | } tx; | |
77 | ||
78 | /* Config register index/data port pair */ | |
221cefa4 MCC |
79 | u32 cr_ip; |
80 | u32 cr_dp; | |
9bdc79ea JW |
81 | |
82 | /* hardware I/O settings */ | |
83 | unsigned long cir_addr; | |
84 | int cir_irq; | |
85 | int cir_port_len; | |
86 | ||
87 | /* hardware id */ | |
88 | u8 chip_major; | |
89 | u8 chip_minor; | |
90 | u16 chip_vendor; | |
83ec8225 | 91 | u8 logical_dev_cir; |
9bdc79ea JW |
92 | |
93 | /* hardware features */ | |
94 | bool hw_learning_capable; | |
95 | bool hw_tx_capable; | |
96 | ||
97 | /* rx settings */ | |
98 | bool learning_enabled; | |
99 | bool carrier_detect_enabled; | |
100 | ||
101 | enum { | |
102 | CMD_HEADER = 0, | |
103 | SUBCMD, | |
104 | CMD_DATA, | |
105 | PARSE_IRDATA, | |
106 | } parser_state; | |
107 | ||
108 | u8 cmd, rem; | |
109 | ||
110 | /* carrier period = 1 / frequency */ | |
111 | u32 carrier; | |
112 | }; | |
113 | ||
114 | /* buffer packet constants, largely identical to mceusb.c */ | |
115 | #define BUF_PULSE_BIT 0x80 | |
116 | #define BUF_LEN_MASK 0x1f | |
117 | #define BUF_SAMPLE_MASK 0x7f | |
118 | ||
119 | #define BUF_COMMAND_HEADER 0x9f | |
120 | #define BUF_COMMAND_MASK 0xe0 | |
121 | #define BUF_COMMAND_NULL 0x00 | |
122 | #define BUF_HW_CMD_HEADER 0xff | |
123 | #define BUF_CMD_G_REVISION 0x0b | |
124 | #define BUF_CMD_S_CARRIER 0x06 | |
125 | #define BUF_CMD_S_TIMEOUT 0x0c | |
126 | #define BUF_CMD_SIG_END 0x01 | |
127 | #define BUF_CMD_S_TXMASK 0x08 | |
128 | #define BUF_CMD_S_RXSENSOR 0x14 | |
129 | #define BUF_RSP_PULSE_COUNT 0x15 | |
130 | ||
131 | #define CIR_SAMPLE_PERIOD 50 | |
132 | ||
133 | /* | |
134 | * Configuration Register: | |
135 | * Index Port | |
136 | * Data Port | |
137 | */ | |
138 | #define CR_INDEX_PORT 0x2e | |
139 | #define CR_DATA_PORT 0x2f | |
140 | ||
141 | /* Possible alternate values, depends on how the chip is wired */ | |
142 | #define CR_INDEX_PORT2 0x4e | |
143 | #define CR_DATA_PORT2 0x4f | |
144 | ||
145 | /* | |
146 | * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is | |
147 | * active. 1 = 0x4e, 0 = 0x2e | |
148 | */ | |
149 | #define PORT_SEL_PORT_4E_EN 0x10 | |
150 | ||
151 | /* Extended Function Mode enable/disable magic values */ | |
152 | #define CONFIG_REG_ENABLE 0x87 | |
153 | #define CONFIG_REG_DISABLE 0xaa | |
154 | ||
155 | /* Chip IDs found in CR_CHIP_ID_{HI,LO} */ | |
156 | #define CHIP_ID_HIGH_F71809U 0x04 | |
157 | #define CHIP_ID_LOW_F71809U 0x08 | |
158 | ||
159 | /* | |
160 | * Global control regs we need to care about: | |
161 | * Global Control def. | |
162 | * Register name addr val. */ | |
163 | #define GCR_SOFTWARE_RESET 0x02 /* 0x00 */ | |
164 | #define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */ | |
165 | #define GCR_CHIP_ID_HI 0x20 /* 0x04 */ | |
166 | #define GCR_CHIP_ID_LO 0x21 /* 0x08 */ | |
167 | #define GCR_VENDOR_ID_HI 0x23 /* 0x19 */ | |
168 | #define GCR_VENDOR_ID_LO 0x24 /* 0x34 */ | |
169 | #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */ | |
170 | #define GCR_KBMOUSE_WAKEUP 0x27 | |
171 | ||
172 | #define LOGICAL_DEV_DISABLE 0x00 | |
173 | #define LOGICAL_DEV_ENABLE 0x01 | |
174 | ||
175 | /* Logical device number of the CIR function */ | |
83ec8225 MCC |
176 | #define LOGICAL_DEV_CIR_REV1 0x05 |
177 | #define LOGICAL_DEV_CIR_REV2 0x08 | |
9bdc79ea JW |
178 | |
179 | /* CIR Logical Device (LDN 0x08) config registers */ | |
180 | #define CIR_CR_COMMAND_INDEX 0x04 | |
181 | #define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host | |
182 | must set to 1. When host finshes write | |
183 | command to IR, host must clear to 0. */ | |
184 | #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write comand data */ | |
185 | #define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx, | |
186 | 0x33 = rx + 1 tx */ | |
187 | #define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */ | |
188 | #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */ | |
189 | #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */ | |
190 | #define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */ | |
191 | #define CIR_CR_PSOUT_STATUS 0xf1 | |
192 | #define CIR_CR_WAKE_KEY3_ADDR 0xf8 | |
193 | #define CIR_CR_WAKE_KEY3_CODE 0xf9 | |
194 | #define CIR_CR_WAKE_KEY3_DC 0xfa | |
195 | #define CIR_CR_WAKE_CONTROL 0xfb | |
196 | #define CIR_CR_WAKE_KEY12_ADDR 0xfc | |
197 | #define CIR_CR_WAKE_KEY4_ADDR 0xfd | |
198 | #define CIR_CR_WAKE_KEY5_ADDR 0xfe | |
199 | ||
200 | #define CLASS_RX_ONLY 0xff | |
201 | #define CLASS_RX_2TX 0x66 | |
202 | #define CLASS_RX_1TX 0x33 | |
203 | ||
204 | /* CIR device registers */ | |
205 | #define CIR_STATUS 0x00 | |
206 | #define CIR_RX_DATA 0x01 | |
207 | #define CIR_TX_CONTROL 0x02 | |
208 | #define CIR_TX_DATA 0x03 | |
209 | #define CIR_CONTROL 0x04 | |
210 | ||
211 | /* Bits to enable CIR wake */ | |
212 | #define LOGICAL_DEV_ACPI 0x01 | |
213 | #define LDEV_ACPI_WAKE_EN_REG 0xe8 | |
214 | #define ACPI_WAKE_EN_CIR_BIT 0x04 | |
215 | ||
216 | #define LDEV_ACPI_PME_EN_REG 0xf0 | |
217 | #define LDEV_ACPI_PME_CLR_REG 0xf1 | |
218 | #define ACPI_PME_CIR_BIT 0x02 | |
219 | ||
220 | #define LDEV_ACPI_STATE_REG 0xf4 | |
221 | #define ACPI_STATE_CIR_BIT 0x20 | |
222 | ||
223 | /* | |
224 | * CIR status register (0x00): | |
225 | * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable) | |
226 | * 3 - TX_FINISH (1 when TX finished, write 1 to clear) | |
227 | * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear) | |
228 | * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear) | |
229 | * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear) | |
230 | */ | |
231 | #define CIR_STATUS_IRQ_EN 0x80 | |
232 | #define CIR_STATUS_TX_FINISH 0x08 | |
233 | #define CIR_STATUS_TX_UNDERRUN 0x04 | |
234 | #define CIR_STATUS_RX_TIMEOUT 0x02 | |
235 | #define CIR_STATUS_RX_RECEIVE 0x01 | |
236 | #define CIR_STATUS_IRQ_MASK 0x0f | |
237 | ||
238 | /* | |
239 | * CIR TX control register (0x02): | |
240 | * 7 - TX_START (1 to indicate TX start, auto-cleared when done) | |
241 | * 6 - TX_END (1 to indicate TX data written to TX fifo) | |
242 | */ | |
243 | #define CIR_TX_CONTROL_TX_START 0x80 | |
244 | #define CIR_TX_CONTROL_TX_END 0x40 | |
245 |