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Merge 2.6.38-rc5 into staging-next
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pnp.h>
31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
6bda9644 35#include <media/rc-core.h>
6d2f5c27
JW		 36#include <linux/pci_ids.h>
37
38#include "nuvoton-cir.h"
39
40static char *chip_id = "w836x7hg";
41
42/* write val to config reg */
43static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
44{
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
47}
48
49/* read val from config reg */
50static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
51{
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
54}
55
56/* update config register bit without changing other bits */
57static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
58{
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
61}
62
63/* clear config register bit without changing other bits */
64static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
65{
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
68}
69
70/* enter extended function mode */
71static inline void nvt_efm_enable(struct nvt_dev *nvt)
72{
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76}
77
78/* exit extended function mode */
79static inline void nvt_efm_disable(struct nvt_dev *nvt)
80{
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
82}
83
84/*
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
88 */
89static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
90{
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
93}
94
95/* write val to cir config register */
96static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
97{
98 outb(val, nvt->cir_addr + offset);
99}
100
101/* read val from cir config register */
102static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
103{
104 u8 val;
105
106 val = inb(nvt->cir_addr + offset);
107
108 return val;
109}
110
111/* write val to cir wake register */
112static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
113 u8 val, u8 offset)
114{
115 outb(val, nvt->cir_wake_addr + offset);
116}
117
118/* read val from cir wake config register */
119static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
120{
121 u8 val;
122
123 val = inb(nvt->cir_wake_addr + offset);
124
125 return val;
126}
127
4e6e29ad
JW		 128#define pr_reg(text, ...) \
129 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
130
6d2f5c27
JW		 131/* dump current cir register contents */
132static void cir_dump_regs(struct nvt_dev *nvt)
133{
134 nvt_efm_enable(nvt);
135 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
136
4e6e29ad
JW		 137 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
138 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
6d2f5c27 139 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 140 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
6d2f5c27
JW		 141 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
142 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
4e6e29ad 143 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
6d2f5c27
JW		 144 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
145
146 nvt_efm_disable(nvt);
147
4e6e29ad
JW		 148 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
149 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
150 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
151 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
152 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
153 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
154 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
155 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
156 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
157 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
158 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
159 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
160 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
161 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
162 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
163 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
164 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 165}
166
167/* dump current cir wake register contents */
168static void cir_wake_dump_regs(struct nvt_dev *nvt)
169{
170 u8 i, fifo_len;
171
172 nvt_efm_enable(nvt);
173 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
174
4e6e29ad 175 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
6d2f5c27 176 NVT_DRIVER_NAME);
4e6e29ad 177 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
6d2f5c27 178 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 179 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
6d2f5c27 180 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad
JW		 181 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
182 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
6d2f5c27
JW		 183 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
184
185 nvt_efm_disable(nvt);
186
4e6e29ad
JW		 187 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
188 pr_reg(" * IRCON: 0x%x\n",
6d2f5c27 189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
4e6e29ad 190 pr_reg(" * IRSTS: 0x%x\n",
6d2f5c27 191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
4e6e29ad 192 pr_reg(" * IREN: 0x%x\n",
6d2f5c27 193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
4e6e29ad 194 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
6d2f5c27 195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
4e6e29ad 196 pr_reg(" * FIFO CMP TOL: 0x%x\n",
6d2f5c27 197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
4e6e29ad 198 pr_reg(" * FIFO COUNT: 0x%x\n",
6d2f5c27 199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
4e6e29ad 200 pr_reg(" * SLCH: 0x%x\n",
6d2f5c27 201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
4e6e29ad 202 pr_reg(" * SLCL: 0x%x\n",
6d2f5c27 203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
4e6e29ad 204 pr_reg(" * FIFOCON: 0x%x\n",
6d2f5c27 205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
4e6e29ad 206 pr_reg(" * SRXFSTS: 0x%x\n",
6d2f5c27 207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
4e6e29ad 208 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
6d2f5c27 209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
4e6e29ad 210 pr_reg(" * WR FIFO DATA: 0x%x\n",
6d2f5c27 211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
4e6e29ad 212 pr_reg(" * RD FIFO ONLY: 0x%x\n",
6d2f5c27 213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 214 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
6d2f5c27 215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
4e6e29ad 216 pr_reg(" * FIFO IGNORE: 0x%x\n",
6d2f5c27 217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
4e6e29ad 218 pr_reg(" * IRFSM: 0x%x\n",
6d2f5c27
JW		 219 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
220
221 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
4e6e29ad
JW		 222 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
223 pr_reg("* Contents = ");
6d2f5c27 224 for (i = 0; i < fifo_len; i++)
4e6e29ad 225 printk(KERN_CONT "%02x ",
6d2f5c27 226 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 227 printk(KERN_CONT "\n");
6d2f5c27
JW		 228}
229
230/* detect hardware features */
231static int nvt_hw_detect(struct nvt_dev *nvt)
232{
233 unsigned long flags;
234 u8 chip_major, chip_minor;
235 int ret = 0;
236
237 nvt_efm_enable(nvt);
238
239 /* Check if we're wired for the alternate EFER setup */
240 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
241 if (chip_major == 0xff) {
242 nvt->cr_efir = CR_EFIR2;
243 nvt->cr_efdr = CR_EFDR2;
244 nvt_efm_enable(nvt);
245 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
246 }
247
248 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
249 nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
250
5df465df
NK		 251 if (chip_major != CHIP_ID_HIGH ||
252 (chip_minor != CHIP_ID_LOW && chip_minor != CHIP_ID_LOW2)) {
253 nvt_pr(KERN_ERR, "%s: unsupported chip, id: 0x%02x 0x%02x",
254 chip_id, chip_major, chip_minor);
6d2f5c27 255 ret = -ENODEV;
5df465df 256 }
6d2f5c27
JW		 257
258 nvt_efm_disable(nvt);
259
260 spin_lock_irqsave(&nvt->nvt_lock, flags);
261 nvt->chip_major = chip_major;
262 nvt->chip_minor = chip_minor;
263 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
264
265 return ret;
266}
267
268static void nvt_cir_ldev_init(struct nvt_dev *nvt)
269{
270 u8 val;
271
272 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
273 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
274 val &= OUTPUT_PIN_SEL_MASK;
275 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
276 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
277
278 /* Select CIR logical device and enable */
279 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
280 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
281
282 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
283 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
284
285 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
286
287 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
288 nvt->cir_addr, nvt->cir_irq);
289}
290
291static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
292{
293 /* Select ACPI logical device, enable it and CIR Wake */
294 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
295 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
296
297 /* Enable CIR Wake via PSOUT# (Pin60) */
298 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
299
300 /* enable cir interrupt of mouse/keyboard IRQ event */
301 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
302
303 /* enable pme interrupt of cir wakeup event */
304 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
305
306 /* Select CIR Wake logical device and enable */
307 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
308 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
309
310 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
311 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
312
313 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
314
315 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
316 nvt->cir_wake_addr, nvt->cir_wake_irq);
317}
318
319/* clear out the hardware's cir rx fifo */
320static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
321{
322 u8 val;
323
324 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
325 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
326}
327
328/* clear out the hardware's cir wake rx fifo */
329static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
330{
331 u8 val;
332
333 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
334 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
335 CIR_WAKE_FIFOCON);
336}
337
338/* clear out the hardware's cir tx fifo */
339static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
340{
341 u8 val;
342
343 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
344 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
345}
346
fbdc781c
JW		 347/* enable RX Trigger Level Reach and Packet End interrupts */
348static void nvt_set_cir_iren(struct nvt_dev *nvt)
349{
350 u8 iren;
351
352 iren = CIR_IREN_RTR | CIR_IREN_PE;
353 nvt_cir_reg_write(nvt, iren, CIR_IREN);
354}
355
6d2f5c27
JW		 356static void nvt_cir_regs_init(struct nvt_dev *nvt)
357{
358 /* set sample limit count (PE interrupt raised when reached) */
359 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
360 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
361
362 /* set fifo irq trigger levels */
363 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
364 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
365
366 /*
367 * Enable TX and RX, specify carrier on = low, off = high, and set
368 * sample period (currently 50us)
369 */
4e6e29ad
JW		 370 nvt_cir_reg_write(nvt,
371 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
372 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
373 CIR_IRCON);
6d2f5c27
JW		 374
375 /* clear hardware rx and tx fifos */
376 nvt_clear_cir_fifo(nvt);
377 nvt_clear_tx_fifo(nvt);
378
379 /* clear any and all stray interrupts */
380 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
381
fbdc781c
JW		 382 /* and finally, enable interrupts */
383 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 384}
385
386static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
387{
388 /* set number of bytes needed for wake key comparison (default 67) */
389 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
390
391 /* set tolerance/variance allowed per byte during wake compare */
392 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
393 CIR_WAKE_FIFO_CMP_TOL);
394
395 /* set sample limit count (PE interrupt raised when reached) */
396 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
397 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
398
399 /* set cir wake fifo rx trigger level (currently 67) */
400 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
401 CIR_WAKE_FIFOCON);
402
403 /*
404 * Enable TX and RX, specific carrier on = low, off = high, and set
405 * sample period (currently 50us)
406 */
407 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
408 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
409 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
410 CIR_WAKE_IRCON);
411
412 /* clear cir wake rx fifo */
413 nvt_clear_cir_wake_fifo(nvt);
414
415 /* clear any and all stray interrupts */
416 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
417}
418
419static void nvt_enable_wake(struct nvt_dev *nvt)
420{
421 nvt_efm_enable(nvt);
422
423 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
424 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
425 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
426 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
427
428 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
429 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
430
431 nvt_efm_disable(nvt);
432
433 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
434 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 435 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
436 CIR_WAKE_IRCON);
6d2f5c27
JW		 437 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
438 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
439}
440
441/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
442static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
443{
444 u32 count, carrier, duration = 0;
445 int i;
446
447 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
448 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
449
450 for (i = 0; i < nvt->pkts; i++) {
451 if (nvt->buf[i] & BUF_PULSE_BIT)
452 duration += nvt->buf[i] & BUF_LEN_MASK;
453 }
454
455 duration *= SAMPLE_PERIOD;
456
457 if (!count || !duration) {
458 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
459 count, duration);
460 return 0;
461 }
462
b4608fae 463 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 464
465 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
466 nvt_dbg("WTF? Carrier frequency out of range!");
467
468 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
469 carrier, count, duration);
470
471 return carrier;
472}
473
474/*
475 * set carrier frequency
476 *
477 * set carrier on 2 registers: CP & CC
478 * always set CP as 0x81
479 * set CC by SPEC, CC = 3MHz/carrier - 1
480 */
d8b4b582 481static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 482{
d8b4b582 483 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 484 u16 val;
485
486 nvt_cir_reg_write(nvt, 1, CIR_CP);
487 val = 3000000 / (carrier) - 1;
488 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
489
490 nvt_dbg("cp: 0x%x cc: 0x%x\n",
491 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
492
493 return 0;
494}
495
496/*
497 * nvt_tx_ir
498 *
499 * 1) clean TX fifo first (handled by AP)
500 * 2) copy data from user space
501 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
502 * 4) send 9 packets to TX FIFO to open TTR
503 * in interrupt_handler:
504 * 5) send all data out
505 * go back to write():
506 * 6) disable TX interrupts, re-enable RX interupts
507 *
508 * The key problem of this function is user space data may larger than
509 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
510 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
511 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
512 * set TXFCONT as 0xff, until buf_count less than 0xff.
513 */
d8b4b582 514static int nvt_tx_ir(struct rc_dev *dev, int *txbuf, u32 n)
6d2f5c27 515{
d8b4b582 516 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 517 unsigned long flags;
518 size_t cur_count;
519 unsigned int i;
520 u8 iren;
521 int ret;
522
523 spin_lock_irqsave(&nvt->tx.lock, flags);
524
525 if (n >= TX_BUF_LEN) {
526 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
527 ret = TX_BUF_LEN;
528 } else {
529 nvt->tx.buf_count = cur_count = n;
530 ret = n;
531 }
532
533 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
534
535 nvt->tx.cur_buf_num = 0;
536
537 /* save currently enabled interrupts */
538 iren = nvt_cir_reg_read(nvt, CIR_IREN);
539
540 /* now disable all interrupts, save TFU & TTR */
541 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
542
543 nvt->tx.tx_state = ST_TX_REPLY;
544
545 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
546 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
547
548 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
549 for (i = 0; i < 9; i++)
550 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
551
552 spin_unlock_irqrestore(&nvt->tx.lock, flags);
553
554 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
555
556 spin_lock_irqsave(&nvt->tx.lock, flags);
557 nvt->tx.tx_state = ST_TX_NONE;
558 spin_unlock_irqrestore(&nvt->tx.lock, flags);
559
560 /* restore enabled interrupts to prior state */
561 nvt_cir_reg_write(nvt, iren, CIR_IREN);
562
563 return ret;
564}
565
566/* dump contents of the last rx buffer we got from the hw rx fifo */
567static void nvt_dump_rx_buf(struct nvt_dev *nvt)
568{
569 int i;
570
4e6e29ad 571 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 572 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 573 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
574 printk(KERN_CONT "\n");
6d2f5c27
JW		 575}
576
577/*
578 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
579 * trigger decode when appropriate.
580 *
581 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
582 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
583 * (default 50us) intervals for that pulse/space. A discrete signal is
584 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
585 * to signal more IR coming (repeats) or end of IR, respectively. We store
586 * sample data in the raw event kfifo until we see 0x7<something> (except f)
587 * or 0x80, at which time, we trigger a decode operation.
588 */
589static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
590{
4651918a 591 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 592 unsigned int count;
593 u32 carrier;
594 u8 sample;
595 int i;
596
597 nvt_dbg_verbose("%s firing", __func__);
598
599 if (debug)
600 nvt_dump_rx_buf(nvt);
601
602 if (nvt->carrier_detect_enabled)
603 carrier = nvt_rx_carrier_detect(nvt);
604
605 count = nvt->pkts;
606 nvt_dbg_verbose("Processing buffer of len %d", count);
607
b7582815
JW		 608 init_ir_raw_event(&rawir);
609
6d2f5c27
JW		 610 for (i = 0; i < count; i++) {
611 nvt->pkts--;
612 sample = nvt->buf[i];
613
614 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 615 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
616 * SAMPLE_PERIOD);
6d2f5c27
JW		 617
618 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
619 if (nvt->rawir.pulse == rawir.pulse)
620 nvt->rawir.duration += rawir.duration;
621 else {
622 nvt->rawir.duration = rawir.duration;
623 nvt->rawir.pulse = rawir.pulse;
624 }
625 continue;
626 }
627
628 rawir.duration += nvt->rawir.duration;
4651918a
ML		 629
630 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 631 nvt->rawir.duration = 0;
632 nvt->rawir.pulse = rawir.pulse;
633
634 if (sample == BUF_PULSE_BIT)
635 rawir.pulse = false;
636
637 if (rawir.duration) {
638 nvt_dbg("Storing %s with duration %d",
639 rawir.pulse ? "pulse" : "space",
640 rawir.duration);
641
642 ir_raw_event_store(nvt->rdev, &rawir);
643 }
644
645 /*
646 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
647 * indicates end of IR signal, but new data incoming. In both
648 * cases, it means we're ready to call ir_raw_event_handle
649 */
b7582815
JW		 650 if ((sample == BUF_PULSE_BIT) && nvt->pkts) {
651 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 652 ir_raw_event_handle(nvt->rdev);
b7582815 653 }
6d2f5c27
JW		 654 }
655
b7582815
JW		 656 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
657 ir_raw_event_handle(nvt->rdev);
658
6d2f5c27
JW		 659 if (nvt->pkts) {
660 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
661 nvt->pkts = 0;
662 }
663
664 nvt_dbg_verbose("%s done", __func__);
665}
666
fbdc781c
JW		 667static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
668{
669 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
670
671 nvt->pkts = 0;
672 nvt_clear_cir_fifo(nvt);
673 ir_raw_event_reset(nvt->rdev);
674}
675
6d2f5c27
JW		 676/* copy data from hardware rx fifo into driver buffer */
677static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
678{
679 unsigned long flags;
680 u8 fifocount, val;
681 unsigned int b_idx;
fbdc781c 682 bool overrun = false;
6d2f5c27
JW		 683 int i;
684
685 /* Get count of how many bytes to read from RX FIFO */
686 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
687 /* if we get 0xff, probably means the logical dev is disabled */
688 if (fifocount == 0xff)
689 return;
fbdc781c 690 /* watch out for a fifo overrun condition */
6d2f5c27 691 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 692 overrun = true;
693 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 694 }
695
696 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
697
698 spin_lock_irqsave(&nvt->nvt_lock, flags);
699
700 b_idx = nvt->pkts;
701
702 /* This should never happen, but lets check anyway... */
703 if (b_idx + fifocount > RX_BUF_LEN) {
704 nvt_process_rx_ir_data(nvt);
705 b_idx = 0;
706 }
707
708 /* Read fifocount bytes from CIR Sample RX FIFO register */
709 for (i = 0; i < fifocount; i++) {
710 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
711 nvt->buf[b_idx + i] = val;
712 }
713
714 nvt->pkts += fifocount;
715 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
716
717 nvt_process_rx_ir_data(nvt);
718
fbdc781c
JW		 719 if (overrun)
720 nvt_handle_rx_fifo_overrun(nvt);
721
6d2f5c27
JW		 722 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
723}
724
725static void nvt_cir_log_irqs(u8 status, u8 iren)
726{
727 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
728 status, iren,
729 status & CIR_IRSTS_RDR ? " RDR" : "",
730 status & CIR_IRSTS_RTR ? " RTR" : "",
731 status & CIR_IRSTS_PE ? " PE" : "",
732 status & CIR_IRSTS_RFO ? " RFO" : "",
733 status & CIR_IRSTS_TE ? " TE" : "",
734 status & CIR_IRSTS_TTR ? " TTR" : "",
735 status & CIR_IRSTS_TFU ? " TFU" : "",
736 status & CIR_IRSTS_GH ? " GH" : "",
737 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
738 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
739 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
740}
741
742static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
743{
744 unsigned long flags;
745 bool tx_inactive;
746 u8 tx_state;
747
748 spin_lock_irqsave(&nvt->tx.lock, flags);
749 tx_state = nvt->tx.tx_state;
750 spin_unlock_irqrestore(&nvt->tx.lock, flags);
751
752 tx_inactive = (tx_state == ST_TX_NONE);
753
754 return tx_inactive;
755}
756
757/* interrupt service routine for incoming and outgoing CIR data */
758static irqreturn_t nvt_cir_isr(int irq, void *data)
759{
760 struct nvt_dev *nvt = data;
761 u8 status, iren, cur_state;
762 unsigned long flags;
763
764 nvt_dbg_verbose("%s firing", __func__);
765
766 nvt_efm_enable(nvt);
767 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
768 nvt_efm_disable(nvt);
769
770 /*
771 * Get IR Status register contents. Write 1 to ack/clear
772 *
773 * bit: reg name - description
774 * 7: CIR_IRSTS_RDR - RX Data Ready
775 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
776 * 5: CIR_IRSTS_PE - Packet End
777 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
778 * 3: CIR_IRSTS_TE - TX FIFO Empty
779 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
780 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
781 * 0: CIR_IRSTS_GH - Min Length Detected
782 */
783 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
784 if (!status) {
785 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
786 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
787 return IRQ_RETVAL(IRQ_NONE);
788 }
789
790 /* ack/clear all irq flags we've got */
791 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
792 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
793
794 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
795 iren = nvt_cir_reg_read(nvt, CIR_IREN);
796 if (!iren) {
797 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
798 return IRQ_RETVAL(IRQ_NONE);
799 }
800
801 if (debug)
802 nvt_cir_log_irqs(status, iren);
803
804 if (status & CIR_IRSTS_RTR) {
805 /* FIXME: add code for study/learn mode */
806 /* We only do rx if not tx'ing */
807 if (nvt_cir_tx_inactive(nvt))
808 nvt_get_rx_ir_data(nvt);
809 }
810
811 if (status & CIR_IRSTS_PE) {
812 if (nvt_cir_tx_inactive(nvt))
813 nvt_get_rx_ir_data(nvt);
814
815 spin_lock_irqsave(&nvt->nvt_lock, flags);
816
817 cur_state = nvt->study_state;
818
819 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
820
821 if (cur_state == ST_STUDY_NONE)
822 nvt_clear_cir_fifo(nvt);
823 }
824
825 if (status & CIR_IRSTS_TE)
826 nvt_clear_tx_fifo(nvt);
827
828 if (status & CIR_IRSTS_TTR) {
829 unsigned int pos, count;
830 u8 tmp;
831
832 spin_lock_irqsave(&nvt->tx.lock, flags);
833
834 pos = nvt->tx.cur_buf_num;
835 count = nvt->tx.buf_count;
836
837 /* Write data into the hardware tx fifo while pos < count */
838 if (pos < count) {
839 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
840 nvt->tx.cur_buf_num++;
841 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
842 } else {
843 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
844 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
845 }
846
847 spin_unlock_irqrestore(&nvt->tx.lock, flags);
848
849 }
850
851 if (status & CIR_IRSTS_TFU) {
852 spin_lock_irqsave(&nvt->tx.lock, flags);
853 if (nvt->tx.tx_state == ST_TX_REPLY) {
854 nvt->tx.tx_state = ST_TX_REQUEST;
855 wake_up(&nvt->tx.queue);
856 }
857 spin_unlock_irqrestore(&nvt->tx.lock, flags);
858 }
859
860 nvt_dbg_verbose("%s done", __func__);
861 return IRQ_RETVAL(IRQ_HANDLED);
862}
863
864/* Interrupt service routine for CIR Wake */
865static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
866{
867 u8 status, iren, val;
868 struct nvt_dev *nvt = data;
869 unsigned long flags;
870
871 nvt_dbg_wake("%s firing", __func__);
872
873 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
874 if (!status)
875 return IRQ_RETVAL(IRQ_NONE);
876
877 if (status & CIR_WAKE_IRSTS_IR_PENDING)
878 nvt_clear_cir_wake_fifo(nvt);
879
880 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
881 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
882
883 /* Interrupt may be shared with CIR, bail if Wake not enabled */
884 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
885 if (!iren) {
886 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
887 return IRQ_RETVAL(IRQ_HANDLED);
888 }
889
890 if ((status & CIR_WAKE_IRSTS_PE) &&
891 (nvt->wake_state == ST_WAKE_START)) {
892 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
893 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
894 nvt_dbg("setting wake up key: 0x%x", val);
895 }
896
897 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
898 spin_lock_irqsave(&nvt->nvt_lock, flags);
899 nvt->wake_state = ST_WAKE_FINISH;
900 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
901 }
902
903 nvt_dbg_wake("%s done", __func__);
904 return IRQ_RETVAL(IRQ_HANDLED);
905}
906
907static void nvt_enable_cir(struct nvt_dev *nvt)
908{
909 /* set function enable flags */
910 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
911 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
912 CIR_IRCON);
913
914 nvt_efm_enable(nvt);
915
916 /* enable the CIR logical device */
917 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
918 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
919
920 nvt_efm_disable(nvt);
921
922 /* clear all pending interrupts */
923 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
924
925 /* enable interrupts */
fbdc781c 926 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 927}
928
929static void nvt_disable_cir(struct nvt_dev *nvt)
930{
931 /* disable CIR interrupts */
932 nvt_cir_reg_write(nvt, 0, CIR_IREN);
933
934 /* clear any and all pending interrupts */
935 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
936
937 /* clear all function enable flags */
938 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
939
940 /* clear hardware rx and tx fifos */
941 nvt_clear_cir_fifo(nvt);
942 nvt_clear_tx_fifo(nvt);
943
944 nvt_efm_enable(nvt);
945
946 /* disable the CIR logical device */
947 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
948 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
949
950 nvt_efm_disable(nvt);
951}
952
d8b4b582 953static int nvt_open(struct rc_dev *dev)
6d2f5c27 954{
d8b4b582 955 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 956 unsigned long flags;
957
958 spin_lock_irqsave(&nvt->nvt_lock, flags);
959 nvt->in_use = true;
960 nvt_enable_cir(nvt);
961 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
962
963 return 0;
964}
965
d8b4b582 966static void nvt_close(struct rc_dev *dev)
6d2f5c27 967{
d8b4b582 968 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 969 unsigned long flags;
970
971 spin_lock_irqsave(&nvt->nvt_lock, flags);
972 nvt->in_use = false;
973 nvt_disable_cir(nvt);
974 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
975}
976
977/* Allocate memory, probe hardware, and initialize everything */
978static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
979{
d8b4b582
DH		 980 struct nvt_dev *nvt;
981 struct rc_dev *rdev;
6d2f5c27
JW		 982 int ret = -ENOMEM;
983
984 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
985 if (!nvt)
986 return ret;
987
6d2f5c27 988 /* input device for IR remote (and tx) */
d8b4b582 989 rdev = rc_allocate_device();
6d2f5c27
JW		 990 if (!rdev)
991 goto failure;
992
993 ret = -ENODEV;
994 /* validate pnp resources */
995 if (!pnp_port_valid(pdev, 0) ||
996 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
997 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
998 goto failure;
999 }
1000
1001 if (!pnp_irq_valid(pdev, 0)) {
1002 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1003 goto failure;
1004 }
1005
1006 if (!pnp_port_valid(pdev, 1) ||
1007 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1008 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1009 goto failure;
1010 }
1011
1012 nvt->cir_addr = pnp_port_start(pdev, 0);
1013 nvt->cir_irq = pnp_irq(pdev, 0);
1014
1015 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1016 /* irq is always shared between cir and cir wake */
1017 nvt->cir_wake_irq = nvt->cir_irq;
1018
1019 nvt->cr_efir = CR_EFIR;
1020 nvt->cr_efdr = CR_EFDR;
1021
1022 spin_lock_init(&nvt->nvt_lock);
1023 spin_lock_init(&nvt->tx.lock);
4651918a 1024 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 1025
1026 ret = -EBUSY;
1027 /* now claim resources */
1028 if (!request_region(nvt->cir_addr,
1029 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1030 goto failure;
1031
1032 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1033 NVT_DRIVER_NAME, (void *)nvt))
1034 goto failure;
1035
1036 if (!request_region(nvt->cir_wake_addr,
1037 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1038 goto failure;
1039
1040 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1041 NVT_DRIVER_NAME, (void *)nvt))
1042 goto failure;
1043
1044 pnp_set_drvdata(pdev, nvt);
1045 nvt->pdev = pdev;
1046
1047 init_waitqueue_head(&nvt->tx.queue);
1048
1049 ret = nvt_hw_detect(nvt);
1050 if (ret)
1051 goto failure;
1052
1053 /* Initialize CIR & CIR Wake Logical Devices */
1054 nvt_efm_enable(nvt);
1055 nvt_cir_ldev_init(nvt);
1056 nvt_cir_wake_ldev_init(nvt);
1057 nvt_efm_disable(nvt);
1058
1059 /* Initialize CIR & CIR Wake Config Registers */
1060 nvt_cir_regs_init(nvt);
1061 nvt_cir_wake_regs_init(nvt);
1062
d8b4b582
DH		 1063 /* Set up the rc device */
1064 rdev->priv = nvt;
1065 rdev->driver_type = RC_DRIVER_IR_RAW;
52b66144 1066 rdev->allowed_protos = RC_TYPE_ALL;
d8b4b582
DH		 1067 rdev->open = nvt_open;
1068 rdev->close = nvt_close;
1069 rdev->tx_ir = nvt_tx_ir;
1070 rdev->s_tx_carrier = nvt_set_tx_carrier;
1071 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1072 rdev->input_id.bustype = BUS_HOST;
1073 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1074 rdev->input_id.product = nvt->chip_major;
1075 rdev->input_id.version = nvt->chip_minor;
1076 rdev->driver_name = NVT_DRIVER_NAME;
1077 rdev->map_name = RC_MAP_RC6_MCE;
6d2f5c27 1078#if 0
d8b4b582
DH		 1079 rdev->min_timeout = XYZ;
1080 rdev->max_timeout = XYZ;
1081 rdev->timeout = XYZ;
6d2f5c27 1082 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
d8b4b582 1083 rdev->rx_resolution = XYZ;
6d2f5c27 1084 /* tx bits */
d8b4b582 1085 rdev->tx_resolution = XYZ;
6d2f5c27 1086#endif
6d2f5c27 1087
d8b4b582 1088 ret = rc_register_device(rdev);
6d2f5c27
JW		 1089 if (ret)
1090 goto failure;
1091
d8b4b582
DH		 1092 device_set_wakeup_capable(&pdev->dev, 1);
1093 device_set_wakeup_enable(&pdev->dev, 1);
1094 nvt->rdev = rdev;
6d2f5c27
JW		 1095 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1096 if (debug) {
1097 cir_dump_regs(nvt);
1098 cir_wake_dump_regs(nvt);
1099 }
1100
1101 return 0;
1102
1103failure:
1104 if (nvt->cir_irq)
1105 free_irq(nvt->cir_irq, nvt);
1106 if (nvt->cir_addr)
1107 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1108
1109 if (nvt->cir_wake_irq)
1110 free_irq(nvt->cir_wake_irq, nvt);
1111 if (nvt->cir_wake_addr)
1112 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1113
d8b4b582 1114 rc_free_device(rdev);
6d2f5c27
JW		 1115 kfree(nvt);
1116
1117 return ret;
1118}
1119
1120static void __devexit nvt_remove(struct pnp_dev *pdev)
1121{
1122 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1123 unsigned long flags;
1124
1125 spin_lock_irqsave(&nvt->nvt_lock, flags);
1126 /* disable CIR */
1127 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1128 nvt_disable_cir(nvt);
1129 /* enable CIR Wake (for IR power-on) */
1130 nvt_enable_wake(nvt);
1131 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1132
1133 /* free resources */
1134 free_irq(nvt->cir_irq, nvt);
1135 free_irq(nvt->cir_wake_irq, nvt);
1136 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1137 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1138
d8b4b582 1139 rc_unregister_device(nvt->rdev);
6d2f5c27 1140
6d2f5c27
JW		 1141 kfree(nvt);
1142}
1143
1144static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1145{
1146 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1147 unsigned long flags;
1148
1149 nvt_dbg("%s called", __func__);
1150
1151 /* zero out misc state tracking */
1152 spin_lock_irqsave(&nvt->nvt_lock, flags);
1153 nvt->study_state = ST_STUDY_NONE;
1154 nvt->wake_state = ST_WAKE_NONE;
1155 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1156
1157 spin_lock_irqsave(&nvt->tx.lock, flags);
1158 nvt->tx.tx_state = ST_TX_NONE;
1159 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1160
1161 /* disable all CIR interrupts */
1162 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1163
1164 nvt_efm_enable(nvt);
1165
1166 /* disable cir logical dev */
1167 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1168 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1169
1170 nvt_efm_disable(nvt);
1171
1172 /* make sure wake is enabled */
1173 nvt_enable_wake(nvt);
1174
1175 return 0;
1176}
1177
1178static int nvt_resume(struct pnp_dev *pdev)
1179{
1180 int ret = 0;
1181 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1182
1183 nvt_dbg("%s called", __func__);
1184
1185 /* open interrupt */
fbdc781c 1186 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1187
1188 /* Enable CIR logical device */
1189 nvt_efm_enable(nvt);
1190 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1191 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1192
1193 nvt_efm_disable(nvt);
1194
1195 nvt_cir_regs_init(nvt);
1196 nvt_cir_wake_regs_init(nvt);
1197
1198 return ret;
1199}
1200
1201static void nvt_shutdown(struct pnp_dev *pdev)
1202{
1203 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1204 nvt_enable_wake(nvt);
1205}
1206
1207static const struct pnp_device_id nvt_ids[] = {
1208 { "WEC0530", 0 }, /* CIR */
1209 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1210 { "", 0 },
1211};
1212
1213static struct pnp_driver nvt_driver = {
1214 .name = NVT_DRIVER_NAME,
1215 .id_table = nvt_ids,
1216 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1217 .probe = nvt_probe,
1218 .remove = __devexit_p(nvt_remove),
1219 .suspend = nvt_suspend,
1220 .resume = nvt_resume,
1221 .shutdown = nvt_shutdown,
1222};
1223
1224int nvt_init(void)
1225{
1226 return pnp_register_driver(&nvt_driver);
1227}
1228
1229void nvt_exit(void)
1230{
1231 pnp_unregister_driver(&nvt_driver);
1232}
1233
1234module_param(debug, int, S_IRUGO | S_IWUSR);
1235MODULE_PARM_DESC(debug, "Enable debugging output");
1236
1237MODULE_DEVICE_TABLE(pnp, nvt_ids);
1238MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1239
1240MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1241MODULE_LICENSE("GPL");
1242
1243module_init(nvt_init);
1244module_exit(nvt_exit);
Linux kernel - Deliverables
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