[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.h

/*
 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
 *
 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
 * Copyright (C) 2009 Nuvoton PS Team
 *
 * Special thanks to Nuvoton for providing hardware, spec sheets and
 * sample code upon which portions of this driver are based. Indirect
 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
 * modeled after.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of the
 * License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
 */

#include <linux/spinlock.h>
#include <linux/ioctl.h>

/* platform driver name to register */
#define NVT_DRIVER_NAME "nuvoton-cir"

/* debugging module parameter */
static int debug;


#define nvt_pr(level, text, ...) \
	printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)

#define nvt_dbg(text, ...) \
	if (debug) \
		printk(KERN_DEBUG \
			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)

#define nvt_dbg_verbose(text, ...) \
	if (debug > 1) \
		printk(KERN_DEBUG \
			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)

#define nvt_dbg_wake(text, ...) \
	if (debug > 2) \
		printk(KERN_DEBUG \
			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)


/*
 * Original lirc driver said min value of 76, and recommended value of 256
 * for the buffer length, but then used 2048. Never mind that the size of the
 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
 * and I don't have TX-capable hardware to test/debug on...
 */
#define TX_BUF_LEN 256
#define RX_BUF_LEN 32
#define WAKE_FIFO_LEN 67

struct nvt_dev {
	struct pnp_dev *pdev;
	struct rc_dev *rdev;

	spinlock_t nvt_lock;

	/* for rx */
	u8 buf[RX_BUF_LEN];
	unsigned int pkts;

	struct {
		spinlock_t lock;
		u8 buf[TX_BUF_LEN];
		unsigned int buf_count;
		unsigned int cur_buf_num;
		wait_queue_head_t queue;
		u8 tx_state;
	} tx;

	/* EFER Config register index/data pair */
	u32 cr_efir;
	u32 cr_efdr;

	/* hardware I/O settings */
	unsigned long cir_addr;
	unsigned long cir_wake_addr;
	int cir_irq;
	int cir_wake_irq;

	/* hardware id */
	u8 chip_major;
	u8 chip_minor;

	/* hardware features */
	bool hw_learning_capable;
	bool hw_tx_capable;

	/* rx settings */
	bool learning_enabled;

	/* track cir wake state */
	u8 wake_state;
	/* for study */
	u8 study_state;
	/* carrier period = 1 / frequency */
	u32 carrier;
};

/* study states */
#define ST_STUDY_NONE      0x0
#define ST_STUDY_START     0x1
#define ST_STUDY_CARRIER   0x2
#define ST_STUDY_ALL_RECV  0x4

/* wake states */
#define ST_WAKE_NONE	0x0
#define ST_WAKE_START	0x1
#define ST_WAKE_FINISH	0x2

/* receive states */
#define ST_RX_WAIT_7F		0x1
#define ST_RX_WAIT_HEAD		0x2
#define ST_RX_WAIT_SILENT_END	0x4

/* send states */
#define ST_TX_NONE	0x0
#define ST_TX_REQUEST	0x2
#define ST_TX_REPLY	0x4

/* buffer packet constants */
#define BUF_PULSE_BIT	0x80
#define BUF_LEN_MASK	0x7f
#define BUF_REPEAT_BYTE	0x70
#define BUF_REPEAT_MASK	0xf0

/* CIR settings */

/* total length of CIR and CIR WAKE */
#define CIR_IOREG_LENGTH	0x0f

/* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */
#define CIR_RX_LIMIT_COUNT	0x7d0

/* CIR Regs */
#define CIR_IRCON	0x00
#define CIR_IRSTS	0x01
#define CIR_IREN	0x02
#define CIR_RXFCONT	0x03
#define CIR_CP		0x04
#define CIR_CC		0x05
#define CIR_SLCH	0x06
#define CIR_SLCL	0x07
#define CIR_FIFOCON	0x08
#define CIR_IRFIFOSTS	0x09
#define CIR_SRXFIFO	0x0a
#define CIR_TXFCONT	0x0b
#define CIR_STXFIFO	0x0c
#define CIR_FCCH	0x0d
#define CIR_FCCL	0x0e
#define CIR_IRFSM	0x0f

/* CIR IRCON settings */
#define CIR_IRCON_RECV	 0x80
#define CIR_IRCON_WIREN	 0x40
#define CIR_IRCON_TXEN	 0x20
#define CIR_IRCON_RXEN	 0x10
#define CIR_IRCON_WRXINV 0x08
#define CIR_IRCON_RXINV	 0x04

#define CIR_IRCON_SAMPLE_PERIOD_SEL_1	0x00
#define CIR_IRCON_SAMPLE_PERIOD_SEL_25	0x01
#define CIR_IRCON_SAMPLE_PERIOD_SEL_50	0x02
#define CIR_IRCON_SAMPLE_PERIOD_SEL_100	0x03

/* FIXME: make this a runtime option */
/* select sample period as 50us */
#define CIR_IRCON_SAMPLE_PERIOD_SEL	CIR_IRCON_SAMPLE_PERIOD_SEL_50

/* CIR IRSTS settings */
#define CIR_IRSTS_RDR	0x80
#define CIR_IRSTS_RTR	0x40
#define CIR_IRSTS_PE	0x20
#define CIR_IRSTS_RFO	0x10
#define CIR_IRSTS_TE	0x08
#define CIR_IRSTS_TTR	0x04
#define CIR_IRSTS_TFU	0x02
#define CIR_IRSTS_GH	0x01

/* CIR IREN settings */
#define CIR_IREN_RDR	0x80
#define CIR_IREN_RTR	0x40
#define CIR_IREN_PE	0x20
#define CIR_IREN_RFO	0x10
#define CIR_IREN_TE	0x08
#define CIR_IREN_TTR	0x04
#define CIR_IREN_TFU	0x02
#define CIR_IREN_GH	0x01

/* CIR FIFOCON settings */
#define CIR_FIFOCON_TXFIFOCLR		0x80

#define CIR_FIFOCON_TX_TRIGGER_LEV_31	0x00
#define CIR_FIFOCON_TX_TRIGGER_LEV_24	0x10
#define CIR_FIFOCON_TX_TRIGGER_LEV_16	0x20
#define CIR_FIFOCON_TX_TRIGGER_LEV_8	0x30

/* FIXME: make this a runtime option */
/* select TX trigger level as 16 */
#define CIR_FIFOCON_TX_TRIGGER_LEV	CIR_FIFOCON_TX_TRIGGER_LEV_16

#define CIR_FIFOCON_RXFIFOCLR		0x08

#define CIR_FIFOCON_RX_TRIGGER_LEV_1	0x00
#define CIR_FIFOCON_RX_TRIGGER_LEV_8	0x01
#define CIR_FIFOCON_RX_TRIGGER_LEV_16	0x02
#define CIR_FIFOCON_RX_TRIGGER_LEV_24	0x03

/* FIXME: make this a runtime option */
/* select RX trigger level as 24 */
#define CIR_FIFOCON_RX_TRIGGER_LEV	CIR_FIFOCON_RX_TRIGGER_LEV_24

/* CIR IRFIFOSTS settings */
#define CIR_IRFIFOSTS_IR_PENDING	0x80
#define CIR_IRFIFOSTS_RX_GS		0x40
#define CIR_IRFIFOSTS_RX_FTA		0x20
#define CIR_IRFIFOSTS_RX_EMPTY		0x10
#define CIR_IRFIFOSTS_RX_FULL		0x08
#define CIR_IRFIFOSTS_TX_FTA		0x04
#define CIR_IRFIFOSTS_TX_EMPTY		0x02
#define CIR_IRFIFOSTS_TX_FULL		0x01


/* CIR WAKE UP Regs */
#define CIR_WAKE_IRCON			0x00
#define CIR_WAKE_IRSTS			0x01
#define CIR_WAKE_IREN			0x02
#define CIR_WAKE_FIFO_CMP_DEEP		0x03
#define CIR_WAKE_FIFO_CMP_TOL		0x04
#define CIR_WAKE_FIFO_COUNT		0x05
#define CIR_WAKE_SLCH			0x06
#define CIR_WAKE_SLCL			0x07
#define CIR_WAKE_FIFOCON		0x08
#define CIR_WAKE_SRXFSTS		0x09
#define CIR_WAKE_SAMPLE_RX_FIFO		0x0a
#define CIR_WAKE_WR_FIFO_DATA		0x0b
#define CIR_WAKE_RD_FIFO_ONLY		0x0c
#define CIR_WAKE_RD_FIFO_ONLY_IDX	0x0d
#define CIR_WAKE_FIFO_IGNORE		0x0e
#define CIR_WAKE_IRFSM			0x0f

/* CIR WAKE UP IRCON settings */
#define CIR_WAKE_IRCON_DEC_RST		0x80
#define CIR_WAKE_IRCON_MODE1		0x40
#define CIR_WAKE_IRCON_MODE0		0x20
#define CIR_WAKE_IRCON_RXEN		0x10
#define CIR_WAKE_IRCON_R		0x08
#define CIR_WAKE_IRCON_RXINV		0x04

/* FIXME/jarod: make this a runtime option */
/* select a same sample period like cir register */
#define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL	CIR_IRCON_SAMPLE_PERIOD_SEL_50

/* CIR WAKE IRSTS Bits */
#define CIR_WAKE_IRSTS_RDR		0x80
#define CIR_WAKE_IRSTS_RTR		0x40
#define CIR_WAKE_IRSTS_PE		0x20
#define CIR_WAKE_IRSTS_RFO		0x10
#define CIR_WAKE_IRSTS_GH		0x08
#define CIR_WAKE_IRSTS_IR_PENDING	0x01

/* CIR WAKE UP IREN Bits */
#define CIR_WAKE_IREN_RDR		0x80
#define CIR_WAKE_IREN_RTR		0x40
#define CIR_WAKE_IREN_PE		0x20
#define CIR_WAKE_IREN_RFO		0x10
#define CIR_WAKE_IREN_TE		0x08
#define CIR_WAKE_IREN_TTR		0x04
#define CIR_WAKE_IREN_TFU		0x02
#define CIR_WAKE_IREN_GH		0x01

/* CIR WAKE FIFOCON settings */
#define CIR_WAKE_FIFOCON_RXFIFOCLR	0x08

#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67	0x00
#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66	0x01
#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65	0x02
#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64	0x03

/* FIXME: make this a runtime option */
/* select WAKE UP RX trigger level as 67 */
#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV	CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67

/* CIR WAKE SRXFSTS settings */
#define CIR_WAKE_IRFIFOSTS_RX_GS	0x80
#define CIR_WAKE_IRFIFOSTS_RX_FTA	0x40
#define CIR_WAKE_IRFIFOSTS_RX_EMPTY	0x20
#define CIR_WAKE_IRFIFOSTS_RX_FULL	0x10

/*
 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
 * the system comparing only 65 bytes (fails with this set to 67)
 */
#define CIR_WAKE_FIFO_CMP_BYTES		65
/* CIR Wake byte comparison tolerance */
#define CIR_WAKE_CMP_TOLERANCE		5

/*
 * Extended Function Enable Registers:
 *  Extended Function Index Register
 *  Extended Function Data Register
 */
#define CR_EFIR			0x2e
#define CR_EFDR			0x2f

/* Possible alternate EFER values, depends on how the chip is wired */
#define CR_EFIR2		0x4e
#define CR_EFDR2		0x4f

/* Extended Function Mode enable/disable magic values */
#define EFER_EFM_ENABLE		0x87
#define EFER_EFM_DISABLE	0xaa

/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
#define CHIP_ID_HIGH_667	0xa5
#define CHIP_ID_HIGH_677B	0xb4
#define CHIP_ID_HIGH_677C	0xc3
#define CHIP_ID_LOW_667		0x13
#define CHIP_ID_LOW_677B2	0x72
#define CHIP_ID_LOW_677B3	0x73
#define CHIP_ID_LOW_677C	0x33

/* Config regs we need to care about */
#define CR_SOFTWARE_RESET	0x02
#define CR_LOGICAL_DEV_SEL	0x07
#define CR_CHIP_ID_HI		0x20
#define CR_CHIP_ID_LO		0x21
#define CR_DEV_POWER_DOWN	0x22 /* bit 2 is CIR power, default power on */
#define CR_OUTPUT_PIN_SEL	0x27
#define CR_MULTIFUNC_PIN_SEL	0x2c
#define CR_LOGICAL_DEV_EN	0x30 /* valid for all logical devices */
/* next three regs valid for both the CIR and CIR_WAKE logical devices */
#define CR_CIR_BASE_ADDR_HI	0x60
#define CR_CIR_BASE_ADDR_LO	0x61
#define CR_CIR_IRQ_RSRC		0x70
/* next three regs valid only for ACPI logical dev */
#define CR_ACPI_CIR_WAKE	0xe0
#define CR_ACPI_IRQ_EVENTS	0xf6
#define CR_ACPI_IRQ_EVENTS2	0xf7

/* Logical devices that we need to care about */
#define LOGICAL_DEV_LPT		0x01
#define LOGICAL_DEV_CIR		0x06
#define LOGICAL_DEV_ACPI	0x0a
#define LOGICAL_DEV_CIR_WAKE	0x0e

#define LOGICAL_DEV_DISABLE	0x00
#define LOGICAL_DEV_ENABLE	0x01

#define CIR_WAKE_ENABLE_BIT	0x08
#define PME_INTR_CIR_PASS_BIT	0x08

/* w83677hg CIR pin config */
#define OUTPUT_PIN_SEL_MASK	0xbc
#define OUTPUT_ENABLE_CIR	0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
#define OUTPUT_ENABLE_CIRWB	0x40 /* enable wide-band sensor */

/* w83667hg CIR pin config */
#define MULTIFUNC_PIN_SEL_MASK	0x1f
#define MULTIFUNC_ENABLE_CIR	0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
#define MULTIFUNC_ENABLE_CIRWB	0x20 /* enable wide-band sensor */

/* MCE CIR signal length, related on sample period */

/* MCE CIR controller signal length: about 43ms
 * 43ms / 50us (sample period) * 0.85 (inaccuracy)
 */
#define CONTROLLER_BUF_LEN_MIN 830

/* MCE CIR keyboard signal length: about 26ms
 * 26ms / 50us (sample period) * 0.85 (inaccuracy)
 */
#define KEYBOARD_BUF_LEN_MAX 650
#define KEYBOARD_BUF_LEN_MIN 610

/* MCE CIR mouse signal length: about 24ms
 * 24ms / 50us (sample period) * 0.85 (inaccuracy)
 */
#define MOUSE_BUF_LEN_MIN 565

#define CIR_SAMPLE_PERIOD 50
#define CIR_SAMPLE_LOW_INACCURACY 0.85

/* MAX silence time that driver will sent to lirc */
#define MAX_SILENCE_TIME 60000

#if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
#define SAMPLE_PERIOD 100

#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
#define SAMPLE_PERIOD 50

#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
#define SAMPLE_PERIOD 25

#else
#define SAMPLE_PERIOD 1
#endif

/* as VISTA MCE definition, valid carrier value */
#define MAX_CARRIER 60000
#define MIN_CARRIER 30000
Commit	Line	Data
6d2f5c27 JW	1	/*
	2	* Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
	3	*
	4	* Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
	5	* Copyright (C) 2009 Nuvoton PS Team
	6	*
	7	* Special thanks to Nuvoton for providing hardware, spec sheets and
	8	* sample code upon which portions of this driver are based. Indirect
	9	* thanks also to Maxim Levitsky, whose ene_ir driver this driver is
	10	* modeled after.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of the
	15	* License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful, but
	18	* WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	20	* General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	25	* USA
	26	*/
	27
	28	#include <linux/spinlock.h>
4e6e29ad	29	#include <linux/ioctl.h>
6d2f5c27 JW	30
	31	/* platform driver name to register */
	32	#define NVT_DRIVER_NAME "nuvoton-cir"
	33
	34	/* debugging module parameter */
	35	static int debug;
	36
	37
	38	#define nvt_pr(level, text, ...) \
	39	printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
	40
	41	#define nvt_dbg(text, ...) \
	42	if (debug) \
	43	printk(KERN_DEBUG \
	44	KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
	45
	46	#define nvt_dbg_verbose(text, ...) \
	47	if (debug > 1) \
	48	printk(KERN_DEBUG \
	49	KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
	50
	51	#define nvt_dbg_wake(text, ...) \
	52	if (debug > 2) \
	53	printk(KERN_DEBUG \
	54	KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
	55
	56
	57	/*
	58	* Original lirc driver said min value of 76, and recommended value of 256
	59	* for the buffer length, but then used 2048. Never mind that the size of the
	60	* RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
	61	* not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
	62	* and I don't have TX-capable hardware to test/debug on...
	63	*/
	64	#define TX_BUF_LEN 256
	65	#define RX_BUF_LEN 32
da7ee60b	66	#define WAKE_FIFO_LEN 67
6d2f5c27 JW	67
	68	struct nvt_dev {
	69	struct pnp_dev *pdev;
d8b4b582	70	struct rc_dev *rdev;
6d2f5c27 JW	71
6d2f5c27 JW	72	spinlock_t nvt_lock;
6d2f5c27 JW	73
	74	/* for rx */
	75	u8 buf[RX_BUF_LEN];
	76	unsigned int pkts;
	77
	78	struct {
	79	spinlock_t lock;
	80	u8 buf[TX_BUF_LEN];
	81	unsigned int buf_count;
	82	unsigned int cur_buf_num;
	83	wait_queue_head_t queue;
	84	u8 tx_state;
	85	} tx;
	86
	87	/* EFER Config register index/data pair */
221cefa4 MCC	88	u32 cr_efir;
221cefa4 MCC	89	u32 cr_efdr;
6d2f5c27 JW	90
	91	/* hardware I/O settings */
	92	unsigned long cir_addr;
	93	unsigned long cir_wake_addr;
	94	int cir_irq;
	95	int cir_wake_irq;
	96
	97	/* hardware id */
	98	u8 chip_major;
	99	u8 chip_minor;
	100
	101	/* hardware features */
	102	bool hw_learning_capable;
	103	bool hw_tx_capable;
	104
	105	/* rx settings */
	106	bool learning_enabled;
6d2f5c27 JW	107
	108	/* track cir wake state */
	109	u8 wake_state;
	110	/* for study */
	111	u8 study_state;
	112	/* carrier period = 1 / frequency */
	113	u32 carrier;
	114	};
	115
	116	/* study states */
	117	#define ST_STUDY_NONE 0x0
	118	#define ST_STUDY_START 0x1
	119	#define ST_STUDY_CARRIER 0x2
	120	#define ST_STUDY_ALL_RECV 0x4
	121
	122	/* wake states */
	123	#define ST_WAKE_NONE 0x0
	124	#define ST_WAKE_START 0x1
	125	#define ST_WAKE_FINISH 0x2
	126
	127	/* receive states */
	128	#define ST_RX_WAIT_7F 0x1
	129	#define ST_RX_WAIT_HEAD 0x2
	130	#define ST_RX_WAIT_SILENT_END 0x4
	131
	132	/* send states */
	133	#define ST_TX_NONE 0x0
	134	#define ST_TX_REQUEST 0x2
	135	#define ST_TX_REPLY 0x4
	136
	137	/* buffer packet constants */
	138	#define BUF_PULSE_BIT 0x80
	139	#define BUF_LEN_MASK 0x7f
	140	#define BUF_REPEAT_BYTE 0x70
	141	#define BUF_REPEAT_MASK 0xf0
	142
	143	/* CIR settings */
	144
	145	/* total length of CIR and CIR WAKE */
	146	#define CIR_IOREG_LENGTH 0x0f
	147
	148	/* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */
	149	#define CIR_RX_LIMIT_COUNT 0x7d0
	150
	151	/* CIR Regs */
	152	#define CIR_IRCON 0x00
	153	#define CIR_IRSTS 0x01
	154	#define CIR_IREN 0x02
	155	#define CIR_RXFCONT 0x03
	156	#define CIR_CP 0x04
	157	#define CIR_CC 0x05
	158	#define CIR_SLCH 0x06
	159	#define CIR_SLCL 0x07
	160	#define CIR_FIFOCON 0x08
	161	#define CIR_IRFIFOSTS 0x09
	162	#define CIR_SRXFIFO 0x0a
	163	#define CIR_TXFCONT 0x0b
	164	#define CIR_STXFIFO 0x0c
	165	#define CIR_FCCH 0x0d
	166	#define CIR_FCCL 0x0e
	167	#define CIR_IRFSM 0x0f
	168
	169	/* CIR IRCON settings */
	170	#define CIR_IRCON_RECV 0x80
171	#define CIR_IRCON_WIREN 0x40
172	#define CIR_IRCON_TXEN 0x20
173	#define CIR_IRCON_RXEN 0x10
174	#define CIR_IRCON_WRXINV 0x08
175	#define CIR_IRCON_RXINV 0x04
176
177	#define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
178	#define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
179	#define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
180	#define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
181
182	/* FIXME: make this a runtime option */
183	/* select sample period as 50us */
184	#define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
185
186	/* CIR IRSTS settings */
187	#define CIR_IRSTS_RDR 0x80
188	#define CIR_IRSTS_RTR 0x40
189	#define CIR_IRSTS_PE 0x20
190	#define CIR_IRSTS_RFO 0x10
191	#define CIR_IRSTS_TE 0x08
192	#define CIR_IRSTS_TTR 0x04
193	#define CIR_IRSTS_TFU 0x02
194	#define CIR_IRSTS_GH 0x01
195
196	/* CIR IREN settings */
197	#define CIR_IREN_RDR 0x80
198	#define CIR_IREN_RTR 0x40
199	#define CIR_IREN_PE 0x20
200	#define CIR_IREN_RFO 0x10
201	#define CIR_IREN_TE 0x08
202	#define CIR_IREN_TTR 0x04
203	#define CIR_IREN_TFU 0x02
204	#define CIR_IREN_GH 0x01
205
206	/* CIR FIFOCON settings */
207	#define CIR_FIFOCON_TXFIFOCLR 0x80
208
209	#define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
210	#define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
211	#define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
212	#define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
213
214	/* FIXME: make this a runtime option */
215	/* select TX trigger level as 16 */
216	#define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
217
218	#define CIR_FIFOCON_RXFIFOCLR 0x08
219
220	#define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
221	#define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
222	#define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
223	#define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
224
225	/* FIXME: make this a runtime option */
226	/* select RX trigger level as 24 */
227	#define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
228
229	/* CIR IRFIFOSTS settings */
230	#define CIR_IRFIFOSTS_IR_PENDING 0x80
231	#define CIR_IRFIFOSTS_RX_GS 0x40
232	#define CIR_IRFIFOSTS_RX_FTA 0x20
233	#define CIR_IRFIFOSTS_RX_EMPTY 0x10
234	#define CIR_IRFIFOSTS_RX_FULL 0x08
235	#define CIR_IRFIFOSTS_TX_FTA 0x04
236	#define CIR_IRFIFOSTS_TX_EMPTY 0x02
237	#define CIR_IRFIFOSTS_TX_FULL 0x01
238
239
240	/* CIR WAKE UP Regs */
241	#define CIR_WAKE_IRCON 0x00
242	#define CIR_WAKE_IRSTS 0x01
243	#define CIR_WAKE_IREN 0x02
244	#define CIR_WAKE_FIFO_CMP_DEEP 0x03
245	#define CIR_WAKE_FIFO_CMP_TOL 0x04
246	#define CIR_WAKE_FIFO_COUNT 0x05
247	#define CIR_WAKE_SLCH 0x06
248	#define CIR_WAKE_SLCL 0x07
249	#define CIR_WAKE_FIFOCON 0x08
250	#define CIR_WAKE_SRXFSTS 0x09
251	#define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
252	#define CIR_WAKE_WR_FIFO_DATA 0x0b
253	#define CIR_WAKE_RD_FIFO_ONLY 0x0c
254	#define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
255	#define CIR_WAKE_FIFO_IGNORE 0x0e
256	#define CIR_WAKE_IRFSM 0x0f
257
258	/* CIR WAKE UP IRCON settings */
259	#define CIR_WAKE_IRCON_DEC_RST 0x80
260	#define CIR_WAKE_IRCON_MODE1 0x40
261	#define CIR_WAKE_IRCON_MODE0 0x20
262	#define CIR_WAKE_IRCON_RXEN 0x10
263	#define CIR_WAKE_IRCON_R 0x08
264	#define CIR_WAKE_IRCON_RXINV 0x04
265
266	/* FIXME/jarod: make this a runtime option */
267	/* select a same sample period like cir register */
268	#define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
269
270	/* CIR WAKE IRSTS Bits */
271	#define CIR_WAKE_IRSTS_RDR 0x80
272	#define CIR_WAKE_IRSTS_RTR 0x40
273	#define CIR_WAKE_IRSTS_PE 0x20
274	#define CIR_WAKE_IRSTS_RFO 0x10
275	#define CIR_WAKE_IRSTS_GH 0x08
276	#define CIR_WAKE_IRSTS_IR_PENDING 0x01
277
278	/* CIR WAKE UP IREN Bits */
279	#define CIR_WAKE_IREN_RDR 0x80
280	#define CIR_WAKE_IREN_RTR 0x40
281	#define CIR_WAKE_IREN_PE 0x20
282	#define CIR_WAKE_IREN_RFO 0x10
283	#define CIR_WAKE_IREN_TE 0x08
284	#define CIR_WAKE_IREN_TTR 0x04
285	#define CIR_WAKE_IREN_TFU 0x02
286	#define CIR_WAKE_IREN_GH 0x01
287
288	/* CIR WAKE FIFOCON settings */
289	#define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
290
291	#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
292	#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
293	#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
294	#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
295
296	/* FIXME: make this a runtime option */
297	/* select WAKE UP RX trigger level as 67 */
298	#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
299
300	/* CIR WAKE SRXFSTS settings */
301	#define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
302	#define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
303	#define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
304	#define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
305
3198ed16 JW	306	/*
	307	* The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
	308	* the system comparing only 65 bytes (fails with this set to 67)
	309	*/
	310	#define CIR_WAKE_FIFO_CMP_BYTES 65
6d2f5c27 JW	311	/* CIR Wake byte comparison tolerance */
	312	#define CIR_WAKE_CMP_TOLERANCE 5
	313
	314	/*
	315	* Extended Function Enable Registers:
	316	* Extended Function Index Register
	317	* Extended Function Data Register
	318	*/
	319	#define CR_EFIR 0x2e
	320	#define CR_EFDR 0x2f
	321
	322	/* Possible alternate EFER values, depends on how the chip is wired */
	323	#define CR_EFIR2 0x4e
	324	#define CR_EFDR2 0x4f
	325
	326	/* Extended Function Mode enable/disable magic values */
	327	#define EFER_EFM_ENABLE 0x87
	328	#define EFER_EFM_DISABLE 0xaa
	329
	330	/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
362d3a3a JW	331	#define CHIP_ID_HIGH_667 0xa5
	332	#define CHIP_ID_HIGH_677B 0xb4
	333	#define CHIP_ID_HIGH_677C 0xc3
	334	#define CHIP_ID_LOW_667 0x13
	335	#define CHIP_ID_LOW_677B2 0x72
	336	#define CHIP_ID_LOW_677B3 0x73
	337	#define CHIP_ID_LOW_677C 0x33
6d2f5c27 JW	338
	339	/* Config regs we need to care about */
	340	#define CR_SOFTWARE_RESET 0x02
	341	#define CR_LOGICAL_DEV_SEL 0x07
	342	#define CR_CHIP_ID_HI 0x20
	343	#define CR_CHIP_ID_LO 0x21
	344	#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
	345	#define CR_OUTPUT_PIN_SEL 0x27
39381d4f	346	#define CR_MULTIFUNC_PIN_SEL 0x2c
6d2f5c27 JW	347	#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
	348	/* next three regs valid for both the CIR and CIR_WAKE logical devices */
	349	#define CR_CIR_BASE_ADDR_HI 0x60
	350	#define CR_CIR_BASE_ADDR_LO 0x61
	351	#define CR_CIR_IRQ_RSRC 0x70
	352	/* next three regs valid only for ACPI logical dev */
	353	#define CR_ACPI_CIR_WAKE 0xe0
	354	#define CR_ACPI_IRQ_EVENTS 0xf6
	355	#define CR_ACPI_IRQ_EVENTS2 0xf7
	356
	357	/* Logical devices that we need to care about */
	358	#define LOGICAL_DEV_LPT 0x01
	359	#define LOGICAL_DEV_CIR 0x06
	360	#define LOGICAL_DEV_ACPI 0x0a
	361	#define LOGICAL_DEV_CIR_WAKE 0x0e
	362
	363	#define LOGICAL_DEV_DISABLE 0x00
	364	#define LOGICAL_DEV_ENABLE 0x01
	365
	366	#define CIR_WAKE_ENABLE_BIT 0x08
6d2f5c27 JW	367	#define PME_INTR_CIR_PASS_BIT 0x08
6d2f5c27 JW	368
39381d4f	369	/* w83677hg CIR pin config */
6d2f5c27 JW	370	#define OUTPUT_PIN_SEL_MASK 0xbc
	371	#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
	372	#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
	373
39381d4f JW	374	/* w83667hg CIR pin config */
	375	#define MULTIFUNC_PIN_SEL_MASK 0x1f
	376	#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
	377	#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
	378
6d2f5c27 JW	379	/* MCE CIR signal length, related on sample period */
	380
	381	/* MCE CIR controller signal length: about 43ms
	382	* 43ms / 50us (sample period) * 0.85 (inaccuracy)
	383	*/
	384	#define CONTROLLER_BUF_LEN_MIN 830
	385
	386	/* MCE CIR keyboard signal length: about 26ms
	387	* 26ms / 50us (sample period) * 0.85 (inaccuracy)
	388	*/
	389	#define KEYBOARD_BUF_LEN_MAX 650
	390	#define KEYBOARD_BUF_LEN_MIN 610
	391
	392	/* MCE CIR mouse signal length: about 24ms
	393	* 24ms / 50us (sample period) * 0.85 (inaccuracy)
	394	*/
	395	#define MOUSE_BUF_LEN_MIN 565
	396
	397	#define CIR_SAMPLE_PERIOD 50
	398	#define CIR_SAMPLE_LOW_INACCURACY 0.85
	399
	400	/* MAX silence time that driver will sent to lirc */
	401	#define MAX_SILENCE_TIME 60000
	402
	403	#if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
	404	#define SAMPLE_PERIOD 100
	405
	406	#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
	407	#define SAMPLE_PERIOD 50
	408
	409	#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
	410	#define SAMPLE_PERIOD 25
	411
	412	#else
	413	#define SAMPLE_PERIOD 1
	414	#endif
	415
	416	/* as VISTA MCE definition, valid carrier value */
	417	#define MAX_CARRIER 60000
	418	#define MIN_CARRIER 30000