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b4e3e59f AB |
1 | /* |
2 | * Driver for Allwinner sunXi IR controller | |
3 | * | |
4 | * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org> | |
5 | * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru> | |
6 | * | |
7 | * Based on sun5i-ir.c: | |
8 | * Copyright (C) 2007-2012 Daniel Wang | |
9 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | ||
22 | #include <linux/clk.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of_platform.h> | |
44f8af68 | 26 | #include <linux/reset.h> |
b4e3e59f AB |
27 | #include <media/rc-core.h> |
28 | ||
29 | #define SUNXI_IR_DEV "sunxi-ir" | |
30 | ||
31 | /* Registers */ | |
32 | /* IR Control */ | |
33 | #define SUNXI_IR_CTL_REG 0x00 | |
34 | /* Global Enable */ | |
35 | #define REG_CTL_GEN BIT(0) | |
36 | /* RX block enable */ | |
37 | #define REG_CTL_RXEN BIT(1) | |
38 | /* CIR mode */ | |
39 | #define REG_CTL_MD (BIT(4) | BIT(5)) | |
40 | ||
41 | /* Rx Config */ | |
42 | #define SUNXI_IR_RXCTL_REG 0x10 | |
43 | /* Pulse Polarity Invert flag */ | |
44 | #define REG_RXCTL_RPPI BIT(2) | |
45 | ||
46 | /* Rx Data */ | |
47 | #define SUNXI_IR_RXFIFO_REG 0x20 | |
48 | ||
49 | /* Rx Interrupt Enable */ | |
50 | #define SUNXI_IR_RXINT_REG 0x2C | |
51 | /* Rx FIFO Overflow */ | |
52 | #define REG_RXINT_ROI_EN BIT(0) | |
53 | /* Rx Packet End */ | |
54 | #define REG_RXINT_RPEI_EN BIT(1) | |
55 | /* Rx FIFO Data Available */ | |
56 | #define REG_RXINT_RAI_EN BIT(4) | |
57 | ||
58 | /* Rx FIFO available byte level */ | |
a4bca4c7 | 59 | #define REG_RXINT_RAL(val) ((val) << 8) |
b4e3e59f AB |
60 | |
61 | /* Rx Interrupt Status */ | |
62 | #define SUNXI_IR_RXSTA_REG 0x30 | |
63 | /* RX FIFO Get Available Counter */ | |
a4bca4c7 | 64 | #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) |
b4e3e59f AB |
65 | /* Clear all interrupt status value */ |
66 | #define REG_RXSTA_CLEARALL 0xff | |
67 | ||
68 | /* IR Sample Config */ | |
69 | #define SUNXI_IR_CIR_REG 0x34 | |
70 | /* CIR_REG register noise threshold */ | |
71 | #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2))) | |
72 | /* CIR_REG register idle threshold */ | |
73 | #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8))) | |
74 | ||
b4e3e59f AB |
75 | /* Required frequency for IR0 or IR1 clock in CIR mode */ |
76 | #define SUNXI_IR_BASE_CLK 8000000 | |
77 | /* Frequency after IR internal divider */ | |
78 | #define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64) | |
79 | /* Sample period in ns */ | |
80 | #define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK) | |
81 | /* Noise threshold in samples */ | |
82 | #define SUNXI_IR_RXNOISE 1 | |
83 | /* Idle Threshold in samples */ | |
84 | #define SUNXI_IR_RXIDLE 20 | |
85 | /* Time after which device stops sending data in ms */ | |
86 | #define SUNXI_IR_TIMEOUT 120 | |
87 | ||
88 | struct sunxi_ir { | |
89 | spinlock_t ir_lock; | |
90 | struct rc_dev *rc; | |
91 | void __iomem *base; | |
92 | int irq; | |
a4bca4c7 | 93 | int fifo_size; |
b4e3e59f AB |
94 | struct clk *clk; |
95 | struct clk *apb_clk; | |
44f8af68 | 96 | struct reset_control *rst; |
b4e3e59f AB |
97 | const char *map_name; |
98 | }; | |
99 | ||
100 | static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) | |
101 | { | |
102 | unsigned long status; | |
103 | unsigned char dt; | |
104 | unsigned int cnt, rc; | |
105 | struct sunxi_ir *ir = dev_id; | |
106 | DEFINE_IR_RAW_EVENT(rawir); | |
107 | ||
108 | spin_lock(&ir->ir_lock); | |
109 | ||
110 | status = readl(ir->base + SUNXI_IR_RXSTA_REG); | |
111 | ||
112 | /* clean all pending statuses */ | |
113 | writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); | |
114 | ||
a4bca4c7 | 115 | if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) { |
b4e3e59f AB |
116 | /* How many messages in fifo */ |
117 | rc = REG_RXSTA_GET_AC(status); | |
118 | /* Sanity check */ | |
a4bca4c7 | 119 | rc = rc > ir->fifo_size ? ir->fifo_size : rc; |
b4e3e59f AB |
120 | /* If we have data */ |
121 | for (cnt = 0; cnt < rc; cnt++) { | |
122 | /* for each bit in fifo */ | |
123 | dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); | |
124 | rawir.pulse = (dt & 0x80) != 0; | |
125 | rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE; | |
126 | ir_raw_event_store_with_filter(ir->rc, &rawir); | |
127 | } | |
128 | } | |
129 | ||
130 | if (status & REG_RXINT_ROI_EN) { | |
131 | ir_raw_event_reset(ir->rc); | |
132 | } else if (status & REG_RXINT_RPEI_EN) { | |
133 | ir_raw_event_set_idle(ir->rc, true); | |
134 | ir_raw_event_handle(ir->rc); | |
135 | } | |
136 | ||
137 | spin_unlock(&ir->ir_lock); | |
138 | ||
139 | return IRQ_HANDLED; | |
140 | } | |
141 | ||
142 | static int sunxi_ir_probe(struct platform_device *pdev) | |
143 | { | |
144 | int ret = 0; | |
145 | unsigned long tmp = 0; | |
146 | ||
147 | struct device *dev = &pdev->dev; | |
148 | struct device_node *dn = dev->of_node; | |
149 | struct resource *res; | |
150 | struct sunxi_ir *ir; | |
151 | ||
152 | ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL); | |
153 | if (!ir) | |
154 | return -ENOMEM; | |
155 | ||
a4bca4c7 HG |
156 | if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir")) |
157 | ir->fifo_size = 64; | |
158 | else | |
159 | ir->fifo_size = 16; | |
160 | ||
b4e3e59f AB |
161 | /* Clock */ |
162 | ir->apb_clk = devm_clk_get(dev, "apb"); | |
163 | if (IS_ERR(ir->apb_clk)) { | |
164 | dev_err(dev, "failed to get a apb clock.\n"); | |
165 | return PTR_ERR(ir->apb_clk); | |
166 | } | |
167 | ir->clk = devm_clk_get(dev, "ir"); | |
168 | if (IS_ERR(ir->clk)) { | |
169 | dev_err(dev, "failed to get a ir clock.\n"); | |
170 | return PTR_ERR(ir->clk); | |
171 | } | |
172 | ||
44f8af68 HG |
173 | /* Reset (optional) */ |
174 | ir->rst = devm_reset_control_get_optional(dev, NULL); | |
175 | if (IS_ERR(ir->rst)) { | |
176 | ret = PTR_ERR(ir->rst); | |
177 | if (ret == -EPROBE_DEFER) | |
178 | return ret; | |
179 | ir->rst = NULL; | |
180 | } else { | |
181 | ret = reset_control_deassert(ir->rst); | |
182 | if (ret) | |
183 | return ret; | |
184 | } | |
185 | ||
b4e3e59f AB |
186 | ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK); |
187 | if (ret) { | |
188 | dev_err(dev, "set ir base clock failed!\n"); | |
44f8af68 | 189 | goto exit_reset_assert; |
b4e3e59f AB |
190 | } |
191 | ||
192 | if (clk_prepare_enable(ir->apb_clk)) { | |
193 | dev_err(dev, "try to enable apb_ir_clk failed\n"); | |
44f8af68 HG |
194 | ret = -EINVAL; |
195 | goto exit_reset_assert; | |
b4e3e59f AB |
196 | } |
197 | ||
198 | if (clk_prepare_enable(ir->clk)) { | |
199 | dev_err(dev, "try to enable ir_clk failed\n"); | |
200 | ret = -EINVAL; | |
201 | goto exit_clkdisable_apb_clk; | |
202 | } | |
203 | ||
204 | /* IO */ | |
205 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
206 | ir->base = devm_ioremap_resource(dev, res); | |
207 | if (IS_ERR(ir->base)) { | |
208 | dev_err(dev, "failed to map registers\n"); | |
209 | ret = PTR_ERR(ir->base); | |
210 | goto exit_clkdisable_clk; | |
211 | } | |
212 | ||
213 | ir->rc = rc_allocate_device(); | |
214 | if (!ir->rc) { | |
215 | dev_err(dev, "failed to allocate device\n"); | |
216 | ret = -ENOMEM; | |
217 | goto exit_clkdisable_clk; | |
218 | } | |
219 | ||
220 | ir->rc->priv = ir; | |
221 | ir->rc->input_name = SUNXI_IR_DEV; | |
222 | ir->rc->input_phys = "sunxi-ir/input0"; | |
223 | ir->rc->input_id.bustype = BUS_HOST; | |
224 | ir->rc->input_id.vendor = 0x0001; | |
225 | ir->rc->input_id.product = 0x0001; | |
226 | ir->rc->input_id.version = 0x0100; | |
227 | ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL); | |
228 | ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY; | |
229 | ir->rc->dev.parent = dev; | |
230 | ir->rc->driver_type = RC_DRIVER_IR_RAW; | |
c5540fbb | 231 | ir->rc->allowed_protocols = RC_BIT_ALL; |
b4e3e59f AB |
232 | ir->rc->rx_resolution = SUNXI_IR_SAMPLE; |
233 | ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT); | |
234 | ir->rc->driver_name = SUNXI_IR_DEV; | |
235 | ||
236 | ret = rc_register_device(ir->rc); | |
237 | if (ret) { | |
238 | dev_err(dev, "failed to register rc device\n"); | |
239 | goto exit_free_dev; | |
240 | } | |
241 | ||
242 | platform_set_drvdata(pdev, ir); | |
243 | ||
244 | /* IRQ */ | |
245 | ir->irq = platform_get_irq(pdev, 0); | |
246 | if (ir->irq < 0) { | |
247 | dev_err(dev, "no irq resource\n"); | |
248 | ret = ir->irq; | |
249 | goto exit_free_dev; | |
250 | } | |
251 | ||
252 | ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir); | |
253 | if (ret) { | |
254 | dev_err(dev, "failed request irq\n"); | |
255 | goto exit_free_dev; | |
256 | } | |
257 | ||
258 | /* Enable CIR Mode */ | |
259 | writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); | |
260 | ||
261 | /* Set noise threshold and idle threshold */ | |
262 | writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), | |
263 | ir->base + SUNXI_IR_CIR_REG); | |
264 | ||
265 | /* Invert Input Signal */ | |
266 | writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); | |
267 | ||
268 | /* Clear All Rx Interrupt Status */ | |
269 | writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); | |
270 | ||
271 | /* | |
272 | * Enable IRQ on overflow, packet end, FIFO available with trigger | |
273 | * level | |
274 | */ | |
275 | writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | | |
a4bca4c7 | 276 | REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), |
b4e3e59f AB |
277 | ir->base + SUNXI_IR_RXINT_REG); |
278 | ||
279 | /* Enable IR Module */ | |
280 | tmp = readl(ir->base + SUNXI_IR_CTL_REG); | |
281 | writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); | |
282 | ||
283 | dev_info(dev, "initialized sunXi IR driver\n"); | |
284 | return 0; | |
285 | ||
286 | exit_free_dev: | |
287 | rc_free_device(ir->rc); | |
288 | exit_clkdisable_clk: | |
289 | clk_disable_unprepare(ir->clk); | |
290 | exit_clkdisable_apb_clk: | |
291 | clk_disable_unprepare(ir->apb_clk); | |
44f8af68 HG |
292 | exit_reset_assert: |
293 | if (ir->rst) | |
294 | reset_control_assert(ir->rst); | |
b4e3e59f AB |
295 | |
296 | return ret; | |
297 | } | |
298 | ||
299 | static int sunxi_ir_remove(struct platform_device *pdev) | |
300 | { | |
301 | unsigned long flags; | |
302 | struct sunxi_ir *ir = platform_get_drvdata(pdev); | |
303 | ||
304 | clk_disable_unprepare(ir->clk); | |
305 | clk_disable_unprepare(ir->apb_clk); | |
44f8af68 HG |
306 | if (ir->rst) |
307 | reset_control_assert(ir->rst); | |
b4e3e59f AB |
308 | |
309 | spin_lock_irqsave(&ir->ir_lock, flags); | |
310 | /* disable IR IRQ */ | |
311 | writel(0, ir->base + SUNXI_IR_RXINT_REG); | |
312 | /* clear All Rx Interrupt Status */ | |
313 | writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); | |
314 | /* disable IR */ | |
315 | writel(0, ir->base + SUNXI_IR_CTL_REG); | |
316 | spin_unlock_irqrestore(&ir->ir_lock, flags); | |
317 | ||
318 | rc_unregister_device(ir->rc); | |
319 | return 0; | |
320 | } | |
321 | ||
322 | static const struct of_device_id sunxi_ir_match[] = { | |
323 | { .compatible = "allwinner,sun4i-a10-ir", }, | |
a4bca4c7 | 324 | { .compatible = "allwinner,sun5i-a13-ir", }, |
b4e3e59f AB |
325 | {}, |
326 | }; | |
327 | ||
328 | static struct platform_driver sunxi_ir_driver = { | |
329 | .probe = sunxi_ir_probe, | |
330 | .remove = sunxi_ir_remove, | |
331 | .driver = { | |
332 | .name = SUNXI_IR_DEV, | |
b4e3e59f AB |
333 | .of_match_table = sunxi_ir_match, |
334 | }, | |
335 | }; | |
336 | ||
337 | module_platform_driver(sunxi_ir_driver); | |
338 | ||
339 | MODULE_DESCRIPTION("Allwinner sunXi IR controller driver"); | |
340 | MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>"); | |
341 | MODULE_LICENSE("GPL"); |