[deliverable/linux.git] / drivers / media / rc / sunxi-cir.c

/*
 * Driver for Allwinner sunXi IR controller
 *
 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
 *
 * Based on sun5i-ir.c:
 * Copyright (C) 2007-2012 Daniel Wang
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/reset.h>
#include <media/rc-core.h>

#define SUNXI_IR_DEV "sunxi-ir"

/* Registers */
/* IR Control */
#define SUNXI_IR_CTL_REG      0x00
/* Global Enable */
#define REG_CTL_GEN			BIT(0)
/* RX block enable */
#define REG_CTL_RXEN			BIT(1)
/* CIR mode */
#define REG_CTL_MD			(BIT(4) | BIT(5))

/* Rx Config */
#define SUNXI_IR_RXCTL_REG    0x10
/* Pulse Polarity Invert flag */
#define REG_RXCTL_RPPI			BIT(2)

/* Rx Data */
#define SUNXI_IR_RXFIFO_REG   0x20

/* Rx Interrupt Enable */
#define SUNXI_IR_RXINT_REG    0x2C
/* Rx FIFO Overflow */
#define REG_RXINT_ROI_EN		BIT(0)
/* Rx Packet End */
#define REG_RXINT_RPEI_EN		BIT(1)
/* Rx FIFO Data Available */
#define REG_RXINT_RAI_EN		BIT(4)

/* Rx FIFO available byte level */
#define REG_RXINT_RAL(val)    (((val) << 8) & (GENMASK(11, 8)))

/* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG    0x30
/* RX FIFO Get Available Counter */
#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (GENMASK(5, 0)))
/* Clear all interrupt status value */
#define REG_RXSTA_CLEARALL    0xff

/* IR Sample Config */
#define SUNXI_IR_CIR_REG      0x34
/* CIR_REG register noise threshold */
#define REG_CIR_NTHR(val)    (((val) << 2) & (GENMASK(7, 2)))
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))

/* Hardware supported fifo size */
#define SUNXI_IR_FIFO_SIZE    16
/* How many messages in FIFO trigger IRQ */
#define TRIGGER_LEVEL         8
/* Required frequency for IR0 or IR1 clock in CIR mode */
#define SUNXI_IR_BASE_CLK     8000000
/* Frequency after IR internal divider  */
#define SUNXI_IR_CLK          (SUNXI_IR_BASE_CLK / 64)
/* Sample period in ns */
#define SUNXI_IR_SAMPLE       (1000000000ul / SUNXI_IR_CLK)
/* Noise threshold in samples  */
#define SUNXI_IR_RXNOISE      1
/* Idle Threshold in samples */
#define SUNXI_IR_RXIDLE       20
/* Time after which device stops sending data in ms */
#define SUNXI_IR_TIMEOUT      120

struct sunxi_ir {
	spinlock_t      ir_lock;
	struct rc_dev   *rc;
	void __iomem    *base;
	int             irq;
	struct clk      *clk;
	struct clk      *apb_clk;
	struct reset_control *rst;
	const char      *map_name;
};

static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
{
	unsigned long status;
	unsigned char dt;
	unsigned int cnt, rc;
	struct sunxi_ir *ir = dev_id;
	DEFINE_IR_RAW_EVENT(rawir);

	spin_lock(&ir->ir_lock);

	status = readl(ir->base + SUNXI_IR_RXSTA_REG);

	/* clean all pending statuses */
	writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);

	if (status & REG_RXINT_RAI_EN) {
		/* How many messages in fifo */
		rc  = REG_RXSTA_GET_AC(status);
		/* Sanity check */
		rc = rc > SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
		/* If we have data */
		for (cnt = 0; cnt < rc; cnt++) {
			/* for each bit in fifo */
			dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
			rawir.pulse = (dt & 0x80) != 0;
			rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
			ir_raw_event_store_with_filter(ir->rc, &rawir);
		}
	}

	if (status & REG_RXINT_ROI_EN) {
		ir_raw_event_reset(ir->rc);
	} else if (status & REG_RXINT_RPEI_EN) {
		ir_raw_event_set_idle(ir->rc, true);
		ir_raw_event_handle(ir->rc);
	}

	spin_unlock(&ir->ir_lock);

	return IRQ_HANDLED;
}

static int sunxi_ir_probe(struct platform_device *pdev)
{
	int ret = 0;
	unsigned long tmp = 0;

	struct device *dev = &pdev->dev;
	struct device_node *dn = dev->of_node;
	struct resource *res;
	struct sunxi_ir *ir;

	ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
	if (!ir)
		return -ENOMEM;

	/* Clock */
	ir->apb_clk = devm_clk_get(dev, "apb");
	if (IS_ERR(ir->apb_clk)) {
		dev_err(dev, "failed to get a apb clock.\n");
		return PTR_ERR(ir->apb_clk);
	}
	ir->clk = devm_clk_get(dev, "ir");
	if (IS_ERR(ir->clk)) {
		dev_err(dev, "failed to get a ir clock.\n");
		return PTR_ERR(ir->clk);
	}

	/* Reset (optional) */
	ir->rst = devm_reset_control_get_optional(dev, NULL);
	if (IS_ERR(ir->rst)) {
		ret = PTR_ERR(ir->rst);
		if (ret == -EPROBE_DEFER)
			return ret;
		ir->rst = NULL;
	} else {
		ret = reset_control_deassert(ir->rst);
		if (ret)
			return ret;
	}

	ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
	if (ret) {
		dev_err(dev, "set ir base clock failed!\n");
		goto exit_reset_assert;
	}

	if (clk_prepare_enable(ir->apb_clk)) {
		dev_err(dev, "try to enable apb_ir_clk failed\n");
		ret = -EINVAL;
		goto exit_reset_assert;
	}

	if (clk_prepare_enable(ir->clk)) {
		dev_err(dev, "try to enable ir_clk failed\n");
		ret = -EINVAL;
		goto exit_clkdisable_apb_clk;
	}

	/* IO */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ir->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ir->base)) {
		dev_err(dev, "failed to map registers\n");
		ret = PTR_ERR(ir->base);
		goto exit_clkdisable_clk;
	}

	ir->rc = rc_allocate_device();
	if (!ir->rc) {
		dev_err(dev, "failed to allocate device\n");
		ret = -ENOMEM;
		goto exit_clkdisable_clk;
	}

	ir->rc->priv = ir;
	ir->rc->input_name = SUNXI_IR_DEV;
	ir->rc->input_phys = "sunxi-ir/input0";
	ir->rc->input_id.bustype = BUS_HOST;
	ir->rc->input_id.vendor = 0x0001;
	ir->rc->input_id.product = 0x0001;
	ir->rc->input_id.version = 0x0100;
	ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
	ir->rc->dev.parent = dev;
	ir->rc->driver_type = RC_DRIVER_IR_RAW;
	ir->rc->allowed_protocols = RC_BIT_ALL;
	ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
	ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
	ir->rc->driver_name = SUNXI_IR_DEV;

	ret = rc_register_device(ir->rc);
	if (ret) {
		dev_err(dev, "failed to register rc device\n");
		goto exit_free_dev;
	}

	platform_set_drvdata(pdev, ir);

	/* IRQ */
	ir->irq = platform_get_irq(pdev, 0);
	if (ir->irq < 0) {
		dev_err(dev, "no irq resource\n");
		ret = ir->irq;
		goto exit_free_dev;
	}

	ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
	if (ret) {
		dev_err(dev, "failed request irq\n");
		goto exit_free_dev;
	}

	/* Enable CIR Mode */
	writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);

	/* Set noise threshold and idle threshold */
	writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
	       ir->base + SUNXI_IR_CIR_REG);

	/* Invert Input Signal */
	writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);

	/* Clear All Rx Interrupt Status */
	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);

	/*
	 * Enable IRQ on overflow, packet end, FIFO available with trigger
	 * level
	 */
	writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
	       REG_RXINT_RAI_EN | REG_RXINT_RAL(TRIGGER_LEVEL - 1),
	       ir->base + SUNXI_IR_RXINT_REG);

	/* Enable IR Module */
	tmp = readl(ir->base + SUNXI_IR_CTL_REG);
	writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);

	dev_info(dev, "initialized sunXi IR driver\n");
	return 0;

exit_free_dev:
	rc_free_device(ir->rc);
exit_clkdisable_clk:
	clk_disable_unprepare(ir->clk);
exit_clkdisable_apb_clk:
	clk_disable_unprepare(ir->apb_clk);
exit_reset_assert:
	if (ir->rst)
		reset_control_assert(ir->rst);

	return ret;
}

static int sunxi_ir_remove(struct platform_device *pdev)
{
	unsigned long flags;
	struct sunxi_ir *ir = platform_get_drvdata(pdev);

	clk_disable_unprepare(ir->clk);
	clk_disable_unprepare(ir->apb_clk);
	if (ir->rst)
		reset_control_assert(ir->rst);

	spin_lock_irqsave(&ir->ir_lock, flags);
	/* disable IR IRQ */
	writel(0, ir->base + SUNXI_IR_RXINT_REG);
	/* clear All Rx Interrupt Status */
	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	/* disable IR */
	writel(0, ir->base + SUNXI_IR_CTL_REG);
	spin_unlock_irqrestore(&ir->ir_lock, flags);

	rc_unregister_device(ir->rc);
	return 0;
}

static const struct of_device_id sunxi_ir_match[] = {
	{ .compatible = "allwinner,sun4i-a10-ir", },
	{},
};

static struct platform_driver sunxi_ir_driver = {
	.probe          = sunxi_ir_probe,
	.remove         = sunxi_ir_remove,
	.driver = {
		.name = SUNXI_IR_DEV,
		.of_match_table = sunxi_ir_match,
	},
};

module_platform_driver(sunxi_ir_driver);

MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
b4e3e59f AB	1	/*
	2	* Driver for Allwinner sunXi IR controller
	3	*
	4	* Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
	5	* Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
	6	*
	7	* Based on sun5i-ir.c:
	8	* Copyright (C) 2007-2012 Daniel Wang
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*/
	21
	22	#include <linux/clk.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/module.h>
	25	#include <linux/of_platform.h>
44f8af68	26	#include <linux/reset.h>
b4e3e59f AB	27	#include <media/rc-core.h>
	28
	29	#define SUNXI_IR_DEV "sunxi-ir"
	30
	31	/* Registers */
	32	/* IR Control */
	33	#define SUNXI_IR_CTL_REG 0x00
	34	/* Global Enable */
	35	#define REG_CTL_GEN BIT(0)
	36	/* RX block enable */
	37	#define REG_CTL_RXEN BIT(1)
	38	/* CIR mode */
	39	#define REG_CTL_MD (BIT(4) \| BIT(5))
	40
	41	/* Rx Config */
	42	#define SUNXI_IR_RXCTL_REG 0x10
	43	/* Pulse Polarity Invert flag */
	44	#define REG_RXCTL_RPPI BIT(2)
	45
	46	/* Rx Data */
	47	#define SUNXI_IR_RXFIFO_REG 0x20
	48
	49	/* Rx Interrupt Enable */
	50	#define SUNXI_IR_RXINT_REG 0x2C
	51	/* Rx FIFO Overflow */
	52	#define REG_RXINT_ROI_EN BIT(0)
	53	/* Rx Packet End */
	54	#define REG_RXINT_RPEI_EN BIT(1)
	55	/* Rx FIFO Data Available */
	56	#define REG_RXINT_RAI_EN BIT(4)
	57
	58	/* Rx FIFO available byte level */
	59	#define REG_RXINT_RAL(val) (((val) << 8) & (GENMASK(11, 8)))
	60
	61	/* Rx Interrupt Status */
	62	#define SUNXI_IR_RXSTA_REG 0x30
	63	/* RX FIFO Get Available Counter */
	64	#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (GENMASK(5, 0)))
	65	/* Clear all interrupt status value */
	66	#define REG_RXSTA_CLEARALL 0xff
	67
	68	/* IR Sample Config */
	69	#define SUNXI_IR_CIR_REG 0x34
	70	/* CIR_REG register noise threshold */
	71	#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
	72	/* CIR_REG register idle threshold */
	73	#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
	74
	75	/* Hardware supported fifo size */
	76	#define SUNXI_IR_FIFO_SIZE 16
	77	/* How many messages in FIFO trigger IRQ */
	78	#define TRIGGER_LEVEL 8
	79	/* Required frequency for IR0 or IR1 clock in CIR mode */
	80	#define SUNXI_IR_BASE_CLK 8000000
	81	/* Frequency after IR internal divider */
	82	#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
	83	/* Sample period in ns */
	84	#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)
	85	/* Noise threshold in samples */
	86	#define SUNXI_IR_RXNOISE 1
	87	/* Idle Threshold in samples */
	88	#define SUNXI_IR_RXIDLE 20
	89	/* Time after which device stops sending data in ms */
	90	#define SUNXI_IR_TIMEOUT 120
91
92	struct sunxi_ir {
93	spinlock_t ir_lock;
94	struct rc_dev *rc;
95	void __iomem *base;
96	int irq;
97	struct clk *clk;
98	struct clk *apb_clk;
44f8af68	99	struct reset_control *rst;
b4e3e59f AB	100	const char *map_name;
	101	};
	102
	103	static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
	104	{
	105	unsigned long status;
	106	unsigned char dt;
	107	unsigned int cnt, rc;
	108	struct sunxi_ir *ir = dev_id;
	109	DEFINE_IR_RAW_EVENT(rawir);
	110
	111	spin_lock(&ir->ir_lock);
	112
	113	status = readl(ir->base + SUNXI_IR_RXSTA_REG);
	114
	115	/* clean all pending statuses */
	116	writel(status \| REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	117
	118	if (status & REG_RXINT_RAI_EN) {
	119	/* How many messages in fifo */
	120	rc = REG_RXSTA_GET_AC(status);
	121	/* Sanity check */
	122	rc = rc > SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
	123	/* If we have data */
	124	for (cnt = 0; cnt < rc; cnt++) {
	125	/* for each bit in fifo */
	126	dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
	127	rawir.pulse = (dt & 0x80) != 0;
	128	rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
	129	ir_raw_event_store_with_filter(ir->rc, &rawir);
	130	}
	131	}
	132
	133	if (status & REG_RXINT_ROI_EN) {
	134	ir_raw_event_reset(ir->rc);
	135	} else if (status & REG_RXINT_RPEI_EN) {
	136	ir_raw_event_set_idle(ir->rc, true);
	137	ir_raw_event_handle(ir->rc);
	138	}
	139
	140	spin_unlock(&ir->ir_lock);
	141
	142	return IRQ_HANDLED;
	143	}
	144
	145	static int sunxi_ir_probe(struct platform_device *pdev)
	146	{
	147	int ret = 0;
	148	unsigned long tmp = 0;
	149
	150	struct device *dev = &pdev->dev;
	151	struct device_node *dn = dev->of_node;
	152	struct resource *res;
	153	struct sunxi_ir *ir;
	154
	155	ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
	156	if (!ir)
	157	return -ENOMEM;
	158
	159	/* Clock */
	160	ir->apb_clk = devm_clk_get(dev, "apb");
	161	if (IS_ERR(ir->apb_clk)) {
	162	dev_err(dev, "failed to get a apb clock.\n");
	163	return PTR_ERR(ir->apb_clk);
164	}
165	ir->clk = devm_clk_get(dev, "ir");
166	if (IS_ERR(ir->clk)) {
167	dev_err(dev, "failed to get a ir clock.\n");
168	return PTR_ERR(ir->clk);
169	}
170
44f8af68 HG	171	/* Reset (optional) */
	172	ir->rst = devm_reset_control_get_optional(dev, NULL);
	173	if (IS_ERR(ir->rst)) {
	174	ret = PTR_ERR(ir->rst);
	175	if (ret == -EPROBE_DEFER)
	176	return ret;
	177	ir->rst = NULL;
	178	} else {
	179	ret = reset_control_deassert(ir->rst);
	180	if (ret)
	181	return ret;
	182	}
	183
b4e3e59f AB	184	ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
	185	if (ret) {
	186	dev_err(dev, "set ir base clock failed!\n");
44f8af68	187	goto exit_reset_assert;
b4e3e59f AB	188	}
	189
	190	if (clk_prepare_enable(ir->apb_clk)) {
	191	dev_err(dev, "try to enable apb_ir_clk failed\n");
44f8af68 HG	192	ret = -EINVAL;
44f8af68 HG	193	goto exit_reset_assert;
b4e3e59f AB	194	}
	195
	196	if (clk_prepare_enable(ir->clk)) {
	197	dev_err(dev, "try to enable ir_clk failed\n");
	198	ret = -EINVAL;
	199	goto exit_clkdisable_apb_clk;
	200	}
	201
	202	/* IO */
	203	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	204	ir->base = devm_ioremap_resource(dev, res);
	205	if (IS_ERR(ir->base)) {
	206	dev_err(dev, "failed to map registers\n");
	207	ret = PTR_ERR(ir->base);
	208	goto exit_clkdisable_clk;
	209	}
	210
	211	ir->rc = rc_allocate_device();
	212	if (!ir->rc) {
	213	dev_err(dev, "failed to allocate device\n");
	214	ret = -ENOMEM;
	215	goto exit_clkdisable_clk;
	216	}
	217
	218	ir->rc->priv = ir;
	219	ir->rc->input_name = SUNXI_IR_DEV;
	220	ir->rc->input_phys = "sunxi-ir/input0";
	221	ir->rc->input_id.bustype = BUS_HOST;
	222	ir->rc->input_id.vendor = 0x0001;
	223	ir->rc->input_id.product = 0x0001;
	224	ir->rc->input_id.version = 0x0100;
	225	ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	226	ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
	227	ir->rc->dev.parent = dev;
	228	ir->rc->driver_type = RC_DRIVER_IR_RAW;
c5540fbb	229	ir->rc->allowed_protocols = RC_BIT_ALL;
b4e3e59f AB	230	ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
	231	ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
	232	ir->rc->driver_name = SUNXI_IR_DEV;
	233
	234	ret = rc_register_device(ir->rc);
	235	if (ret) {
	236	dev_err(dev, "failed to register rc device\n");
	237	goto exit_free_dev;
	238	}
	239
	240	platform_set_drvdata(pdev, ir);
	241
	242	/* IRQ */
	243	ir->irq = platform_get_irq(pdev, 0);
	244	if (ir->irq < 0) {
	245	dev_err(dev, "no irq resource\n");
	246	ret = ir->irq;
	247	goto exit_free_dev;
	248	}
	249
	250	ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
	251	if (ret) {
	252	dev_err(dev, "failed request irq\n");
	253	goto exit_free_dev;
	254	}
	255
	256	/* Enable CIR Mode */
	257	writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
	258
	259	/* Set noise threshold and idle threshold */
	260	writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)\|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
	261	ir->base + SUNXI_IR_CIR_REG);
	262
	263	/* Invert Input Signal */
	264	writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
	265
	266	/* Clear All Rx Interrupt Status */
	267	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	268
	269	/*
	270	* Enable IRQ on overflow, packet end, FIFO available with trigger
	271	* level
	272	*/
	273	writel(REG_RXINT_ROI_EN \| REG_RXINT_RPEI_EN \|
	274	REG_RXINT_RAI_EN \| REG_RXINT_RAL(TRIGGER_LEVEL - 1),
	275	ir->base + SUNXI_IR_RXINT_REG);
	276
	277	/* Enable IR Module */
	278	tmp = readl(ir->base + SUNXI_IR_CTL_REG);
	279	writel(tmp \| REG_CTL_GEN \| REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
	280
	281	dev_info(dev, "initialized sunXi IR driver\n");
	282	return 0;
	283
	284	exit_free_dev:
	285	rc_free_device(ir->rc);
	286	exit_clkdisable_clk:
	287	clk_disable_unprepare(ir->clk);
	288	exit_clkdisable_apb_clk:
	289	clk_disable_unprepare(ir->apb_clk);
44f8af68 HG	290	exit_reset_assert:
	291	if (ir->rst)
	292	reset_control_assert(ir->rst);
b4e3e59f AB	293
	294	return ret;
	295	}
	296
	297	static int sunxi_ir_remove(struct platform_device *pdev)
	298	{
	299	unsigned long flags;
	300	struct sunxi_ir *ir = platform_get_drvdata(pdev);
	301
	302	clk_disable_unprepare(ir->clk);
	303	clk_disable_unprepare(ir->apb_clk);
44f8af68 HG	304	if (ir->rst)
44f8af68 HG	305	reset_control_assert(ir->rst);
b4e3e59f AB	306
	307	spin_lock_irqsave(&ir->ir_lock, flags);
	308	/* disable IR IRQ */
	309	writel(0, ir->base + SUNXI_IR_RXINT_REG);
	310	/* clear All Rx Interrupt Status */
	311	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	312	/* disable IR */
	313	writel(0, ir->base + SUNXI_IR_CTL_REG);
	314	spin_unlock_irqrestore(&ir->ir_lock, flags);
	315
	316	rc_unregister_device(ir->rc);
	317	return 0;
	318	}
	319
	320	static const struct of_device_id sunxi_ir_match[] = {
	321	{ .compatible = "allwinner,sun4i-a10-ir", },
	322	{},
	323	};
	324
	325	static struct platform_driver sunxi_ir_driver = {
	326	.probe = sunxi_ir_probe,
	327	.remove = sunxi_ir_remove,
	328	.driver = {
	329	.name = SUNXI_IR_DEV,
b4e3e59f AB	330	.of_match_table = sunxi_ir_match,
	331	},
	332	};
	333
	334	module_platform_driver(sunxi_ir_driver);
	335
	336	MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
	337	MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
	338	MODULE_LICENSE("GPL");