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e258b80e DH |
1 | /* |
2 | * winbond-cir.c - Driver for the Consumer IR functionality of Winbond | |
3 | * SuperI/O chips. | |
4 | * | |
5 | * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but | |
6 | * could probably support others (Winbond WEC102X, NatSemi, etc) | |
7 | * with minor modifications. | |
8 | * | |
b87f2edd DH |
9 | * Original Author: David Härdeman <david@hardeman.nu> |
10 | * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> | |
e258b80e | 11 | * |
5b2e303f DH |
12 | * Dedicated to my daughter Matilda, without whose loving attention this |
13 | * driver would have been finished in half the time and with a fraction | |
e258b80e DH |
14 | * of the bugs. |
15 | * | |
16 | * Written using: | |
17 | * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel | |
18 | * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) | |
19 | * o DSDT dumps | |
20 | * | |
21 | * Supported features: | |
c829f267 DH |
22 | * o IR Receive |
23 | * o IR Transmit | |
e258b80e DH |
24 | * o Wake-On-CIR functionality |
25 | * | |
26 | * To do: | |
5b2e303f | 27 | * o Learning |
e258b80e DH |
28 | * |
29 | * This program is free software; you can redistribute it and/or modify | |
30 | * it under the terms of the GNU General Public License as published by | |
31 | * the Free Software Foundation; either version 2 of the License, or | |
32 | * (at your option) any later version. | |
33 | * | |
34 | * This program is distributed in the hope that it will be useful, | |
35 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
36 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
37 | * GNU General Public License for more details. | |
38 | * | |
39 | * You should have received a copy of the GNU General Public License | |
40 | * along with this program; if not, write to the Free Software | |
41 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
42 | */ | |
43 | ||
d8a10ac9 JP |
44 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
45 | ||
e258b80e DH |
46 | #include <linux/module.h> |
47 | #include <linux/pnp.h> | |
48 | #include <linux/interrupt.h> | |
49 | #include <linux/timer.h> | |
e258b80e | 50 | #include <linux/leds.h> |
e258b80e DH |
51 | #include <linux/spinlock.h> |
52 | #include <linux/pci_ids.h> | |
53 | #include <linux/io.h> | |
54 | #include <linux/bitrev.h> | |
5a0e3ad6 | 55 | #include <linux/slab.h> |
c829f267 DH |
56 | #include <linux/wait.h> |
57 | #include <linux/sched.h> | |
6bda9644 | 58 | #include <media/rc-core.h> |
e258b80e DH |
59 | |
60 | #define DRVNAME "winbond-cir" | |
61 | ||
62 | /* CEIR Wake-Up Registers, relative to data->wbase */ | |
63 | #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ | |
64 | #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ | |
65 | #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ | |
66 | #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ | |
67 | #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ | |
68 | #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ | |
69 | #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ | |
70 | #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ | |
71 | #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ | |
72 | #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ | |
73 | ||
74 | /* CEIR Enhanced Functionality Registers, relative to data->ebase */ | |
75 | #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ | |
76 | #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ | |
77 | #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ | |
78 | #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ | |
79 | #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ | |
80 | ||
81 | /* SP3 Banked Registers, relative to data->sbase */ | |
82 | #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ | |
83 | /* Bank 0 */ | |
84 | #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ | |
85 | #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ | |
86 | #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ | |
87 | #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ | |
88 | #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ | |
89 | #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ | |
90 | #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ | |
91 | #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ | |
92 | #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ | |
93 | /* Bank 2 */ | |
94 | #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ | |
95 | #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ | |
96 | #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ | |
97 | #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ | |
98 | #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ | |
99 | #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ | |
100 | /* Bank 3 */ | |
101 | #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ | |
102 | #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ | |
103 | #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ | |
104 | /* Bank 4 */ | |
105 | #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ | |
106 | /* Bank 5 */ | |
107 | #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ | |
108 | /* Bank 6 */ | |
109 | #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ | |
5b2e303f | 110 | #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ |
e258b80e DH |
111 | /* Bank 7 */ |
112 | #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ | |
113 | #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ | |
114 | #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ | |
115 | #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ | |
116 | #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ | |
117 | ||
118 | /* | |
119 | * Magic values follow | |
120 | */ | |
121 | ||
122 | /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
123 | #define WBCIR_IRQ_NONE 0x00 | |
124 | /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
125 | #define WBCIR_IRQ_RX 0x01 | |
c829f267 DH |
126 | /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
127 | #define WBCIR_IRQ_TX_LOW 0x02 | |
e258b80e DH |
128 | /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
129 | #define WBCIR_IRQ_ERR 0x04 | |
c829f267 DH |
130 | /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
131 | #define WBCIR_IRQ_TX_EMPTY 0x20 | |
e258b80e DH |
132 | /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ |
133 | #define WBCIR_LED_ENABLE 0x80 | |
134 | /* RX data available bit for WBCIR_REG_SP3_LSR */ | |
135 | #define WBCIR_RX_AVAIL 0x01 | |
c829f267 DH |
136 | /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ |
137 | #define WBCIR_RX_OVERRUN 0x02 | |
138 | /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ | |
139 | #define WBCIR_TX_EOT 0x04 | |
e258b80e DH |
140 | /* RX disable bit for WBCIR_REG_SP3_ASCR */ |
141 | #define WBCIR_RX_DISABLE 0x20 | |
c829f267 DH |
142 | /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ |
143 | #define WBCIR_TX_UNDERRUN 0x40 | |
e258b80e DH |
144 | /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ |
145 | #define WBCIR_EXT_ENABLE 0x01 | |
146 | /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
147 | #define WBCIR_REGSEL_COMPARE 0x10 | |
148 | /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
149 | #define WBCIR_REGSEL_MASK 0x20 | |
150 | /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ | |
151 | #define WBCIR_REG_ADDR0 0x00 | |
152 | ||
153 | /* Valid banks for the SP3 UART */ | |
154 | enum wbcir_bank { | |
155 | WBCIR_BANK_0 = 0x00, | |
156 | WBCIR_BANK_1 = 0x80, | |
157 | WBCIR_BANK_2 = 0xE0, | |
158 | WBCIR_BANK_3 = 0xE4, | |
159 | WBCIR_BANK_4 = 0xE8, | |
160 | WBCIR_BANK_5 = 0xEC, | |
161 | WBCIR_BANK_6 = 0xF0, | |
162 | WBCIR_BANK_7 = 0xF4, | |
163 | }; | |
164 | ||
5b2e303f | 165 | /* Supported power-on IR Protocols */ |
e258b80e DH |
166 | enum wbcir_protocol { |
167 | IR_PROTOCOL_RC5 = 0x0, | |
168 | IR_PROTOCOL_NEC = 0x1, | |
169 | IR_PROTOCOL_RC6 = 0x2, | |
170 | }; | |
171 | ||
c829f267 DH |
172 | /* Possible states for IR reception */ |
173 | enum wbcir_rxstate { | |
174 | WBCIR_RXSTATE_INACTIVE = 0, | |
175 | WBCIR_RXSTATE_ACTIVE, | |
176 | WBCIR_RXSTATE_ERROR | |
177 | }; | |
178 | ||
179 | /* Possible states for IR transmission */ | |
180 | enum wbcir_txstate { | |
181 | WBCIR_TXSTATE_INACTIVE = 0, | |
182 | WBCIR_TXSTATE_ACTIVE, | |
c829f267 DH |
183 | WBCIR_TXSTATE_ERROR |
184 | }; | |
185 | ||
e258b80e | 186 | /* Misc */ |
54fd321e | 187 | #define WBCIR_NAME "winbond-cir" |
e258b80e DH |
188 | #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ |
189 | #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ | |
e258b80e DH |
190 | #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */ |
191 | #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ | |
192 | #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ | |
193 | #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ | |
e258b80e | 194 | |
5b2e303f | 195 | /* Per-device data */ |
e258b80e | 196 | struct wbcir_data { |
5b2e303f | 197 | spinlock_t spinlock; |
c829f267 DH |
198 | struct rc_dev *dev; |
199 | struct led_classdev led; | |
5b2e303f | 200 | |
e258b80e DH |
201 | unsigned long wbase; /* Wake-Up Baseaddr */ |
202 | unsigned long ebase; /* Enhanced Func. Baseaddr */ | |
203 | unsigned long sbase; /* Serial Port Baseaddr */ | |
204 | unsigned int irq; /* Serial Port IRQ */ | |
c829f267 | 205 | u8 irqmask; |
e258b80e | 206 | |
c829f267 DH |
207 | /* RX state */ |
208 | enum wbcir_rxstate rxstate; | |
e258b80e | 209 | struct led_trigger *rxtrigger; |
c829f267 | 210 | struct ir_raw_event rxev; |
e258b80e | 211 | |
c829f267 DH |
212 | /* TX state */ |
213 | enum wbcir_txstate txstate; | |
214 | struct led_trigger *txtrigger; | |
215 | u32 txlen; | |
216 | u32 txoff; | |
217 | u32 *txbuf; | |
c829f267 DH |
218 | u8 txmask; |
219 | u32 txcarrier; | |
e258b80e DH |
220 | }; |
221 | ||
222 | static enum wbcir_protocol protocol = IR_PROTOCOL_RC6; | |
223 | module_param(protocol, uint, 0444); | |
5b2e303f | 224 | MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command " |
e258b80e DH |
225 | "(0 = RC5, 1 = NEC, 2 = RC6A, default)"); |
226 | ||
90ab5ee9 | 227 | static bool invert; /* default = 0 */ |
e258b80e DH |
228 | module_param(invert, bool, 0444); |
229 | MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); | |
230 | ||
90ab5ee9 | 231 | static bool txandrx; /* default = 0 */ |
c829f267 | 232 | module_param(txandrx, bool, 0444); |
57f4422f | 233 | MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); |
c829f267 | 234 | |
e258b80e DH |
235 | static unsigned int wake_sc = 0x800F040C; |
236 | module_param(wake_sc, uint, 0644); | |
237 | MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command"); | |
238 | ||
239 | static unsigned int wake_rc6mode = 6; | |
240 | module_param(wake_rc6mode, uint, 0644); | |
241 | MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command " | |
242 | "(0 = 0, 6 = 6A, default)"); | |
243 | ||
244 | ||
245 | ||
246 | /***************************************************************************** | |
247 | * | |
248 | * UTILITY FUNCTIONS | |
249 | * | |
250 | *****************************************************************************/ | |
251 | ||
252 | /* Caller needs to hold wbcir_lock */ | |
253 | static void | |
254 | wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) | |
255 | { | |
256 | u8 val; | |
257 | ||
258 | val = inb(addr); | |
259 | val = ((val & ~mask) | (bits & mask)); | |
260 | outb(val, addr); | |
261 | } | |
262 | ||
263 | /* Selects the register bank for the serial port */ | |
264 | static inline void | |
265 | wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) | |
266 | { | |
267 | outb(bank, data->sbase + WBCIR_REG_SP3_BSR); | |
268 | } | |
269 | ||
c829f267 DH |
270 | static inline void |
271 | wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) | |
272 | { | |
273 | if (data->irqmask == irqmask) | |
274 | return; | |
275 | ||
276 | wbcir_select_bank(data, WBCIR_BANK_0); | |
277 | outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); | |
278 | data->irqmask = irqmask; | |
279 | } | |
280 | ||
e258b80e DH |
281 | static enum led_brightness |
282 | wbcir_led_brightness_get(struct led_classdev *led_cdev) | |
283 | { | |
284 | struct wbcir_data *data = container_of(led_cdev, | |
285 | struct wbcir_data, | |
286 | led); | |
287 | ||
288 | if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) | |
289 | return LED_FULL; | |
290 | else | |
291 | return LED_OFF; | |
292 | } | |
293 | ||
294 | static void | |
295 | wbcir_led_brightness_set(struct led_classdev *led_cdev, | |
5b2e303f | 296 | enum led_brightness brightness) |
e258b80e DH |
297 | { |
298 | struct wbcir_data *data = container_of(led_cdev, | |
299 | struct wbcir_data, | |
300 | led); | |
301 | ||
302 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, | |
303 | brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, | |
304 | WBCIR_LED_ENABLE); | |
305 | } | |
306 | ||
5b2e303f | 307 | /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ |
e258b80e DH |
308 | static u8 |
309 | wbcir_to_rc6cells(u8 val) | |
310 | { | |
311 | u8 coded = 0x00; | |
312 | int i; | |
313 | ||
314 | val &= 0x0F; | |
315 | for (i = 0; i < 4; i++) { | |
316 | if (val & 0x01) | |
317 | coded |= 0x02 << (i * 2); | |
318 | else | |
319 | coded |= 0x01 << (i * 2); | |
320 | val >>= 1; | |
321 | } | |
322 | ||
323 | return coded; | |
324 | } | |
325 | ||
e258b80e DH |
326 | /***************************************************************************** |
327 | * | |
328 | * INTERRUPT FUNCTIONS | |
329 | * | |
330 | *****************************************************************************/ | |
331 | ||
c829f267 | 332 | static void |
488ebc48 | 333 | wbcir_idle_rx(struct rc_dev *dev, bool idle) |
e258b80e | 334 | { |
488ebc48 | 335 | struct wbcir_data *data = dev->priv; |
e258b80e | 336 | |
488ebc48 | 337 | if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) { |
c829f267 | 338 | data->rxstate = WBCIR_RXSTATE_ACTIVE; |
5b2e303f DH |
339 | led_trigger_event(data->rxtrigger, LED_FULL); |
340 | } | |
341 | ||
488ebc48 DH |
342 | if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) |
343 | /* Tell hardware to go idle by setting RXINACTIVE */ | |
344 | outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); | |
345 | } | |
e258b80e | 346 | |
488ebc48 DH |
347 | static void |
348 | wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) | |
349 | { | |
350 | u8 irdata; | |
351 | DEFINE_IR_RAW_EVENT(rawir); | |
5b2e303f | 352 | |
488ebc48 DH |
353 | /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ |
354 | while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { | |
355 | irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); | |
c829f267 | 356 | if (data->rxstate == WBCIR_RXSTATE_ERROR) |
5b2e303f | 357 | continue; |
488ebc48 | 358 | rawir.pulse = irdata & 0x80 ? false : true; |
30cedcf3 | 359 | rawir.duration = US_TO_NS(((irdata & 0x7F) + 1) * 10); |
488ebc48 | 360 | ir_raw_event_store_with_filter(data->dev, &rawir); |
e258b80e DH |
361 | } |
362 | ||
488ebc48 DH |
363 | /* Check if we should go idle */ |
364 | if (data->dev->idle) { | |
5b2e303f | 365 | led_trigger_event(data->rxtrigger, LED_OFF); |
c829f267 | 366 | data->rxstate = WBCIR_RXSTATE_INACTIVE; |
e258b80e DH |
367 | } |
368 | ||
5b2e303f | 369 | ir_raw_event_handle(data->dev); |
c829f267 DH |
370 | } |
371 | ||
372 | static void | |
373 | wbcir_irq_tx(struct wbcir_data *data) | |
374 | { | |
375 | unsigned int space; | |
376 | unsigned int used; | |
377 | u8 bytes[16]; | |
378 | u8 byte; | |
379 | ||
380 | if (!data->txbuf) | |
381 | return; | |
382 | ||
383 | switch (data->txstate) { | |
384 | case WBCIR_TXSTATE_INACTIVE: | |
385 | /* TX FIFO empty */ | |
386 | space = 16; | |
387 | led_trigger_event(data->txtrigger, LED_FULL); | |
388 | break; | |
389 | case WBCIR_TXSTATE_ACTIVE: | |
390 | /* TX FIFO low (3 bytes or less) */ | |
391 | space = 13; | |
392 | break; | |
393 | case WBCIR_TXSTATE_ERROR: | |
394 | space = 0; | |
395 | break; | |
396 | default: | |
397 | return; | |
398 | } | |
399 | ||
400 | /* | |
401 | * TX data is run-length coded in bytes: YXXXXXXX | |
402 | * Y = space (1) or pulse (0) | |
403 | * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) | |
404 | */ | |
405 | for (used = 0; used < space && data->txoff != data->txlen; used++) { | |
406 | if (data->txbuf[data->txoff] == 0) { | |
407 | data->txoff++; | |
408 | continue; | |
409 | } | |
410 | byte = min((u32)0x80, data->txbuf[data->txoff]); | |
411 | data->txbuf[data->txoff] -= byte; | |
412 | byte--; | |
413 | byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ | |
414 | bytes[used] = byte; | |
415 | } | |
416 | ||
417 | while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen) | |
418 | data->txoff++; | |
419 | ||
420 | if (used == 0) { | |
421 | /* Finished */ | |
422 | if (data->txstate == WBCIR_TXSTATE_ERROR) | |
423 | /* Clear TX underrun bit */ | |
424 | outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); | |
c829f267 DH |
425 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
426 | led_trigger_event(data->txtrigger, LED_OFF); | |
7bfb5dc1 DH |
427 | kfree(data->txbuf); |
428 | data->txbuf = NULL; | |
429 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
430 | } else if (data->txoff == data->txlen) { |
431 | /* At the end of transmission, tell the hw before last byte */ | |
432 | outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); | |
433 | outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); | |
434 | outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); | |
435 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
436 | WBCIR_IRQ_TX_EMPTY); | |
437 | } else { | |
438 | /* More data to follow... */ | |
439 | outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); | |
440 | if (data->txstate == WBCIR_TXSTATE_INACTIVE) { | |
441 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
442 | WBCIR_IRQ_TX_LOW); | |
443 | data->txstate = WBCIR_TXSTATE_ACTIVE; | |
444 | } | |
445 | } | |
446 | } | |
447 | ||
448 | static irqreturn_t | |
449 | wbcir_irq_handler(int irqno, void *cookie) | |
450 | { | |
451 | struct pnp_dev *device = cookie; | |
452 | struct wbcir_data *data = pnp_get_drvdata(device); | |
453 | unsigned long flags; | |
454 | u8 status; | |
455 | ||
456 | spin_lock_irqsave(&data->spinlock, flags); | |
457 | wbcir_select_bank(data, WBCIR_BANK_0); | |
458 | status = inb(data->sbase + WBCIR_REG_SP3_EIR); | |
459 | status &= data->irqmask; | |
460 | ||
461 | if (!status) { | |
462 | spin_unlock_irqrestore(&data->spinlock, flags); | |
463 | return IRQ_NONE; | |
464 | } | |
465 | ||
466 | if (status & WBCIR_IRQ_ERR) { | |
467 | /* RX overflow? (read clears bit) */ | |
468 | if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { | |
469 | data->rxstate = WBCIR_RXSTATE_ERROR; | |
470 | ir_raw_event_reset(data->dev); | |
471 | } | |
472 | ||
473 | /* TX underflow? */ | |
474 | if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) | |
475 | data->txstate = WBCIR_TXSTATE_ERROR; | |
476 | } | |
477 | ||
478 | if (status & WBCIR_IRQ_RX) | |
479 | wbcir_irq_rx(data, device); | |
480 | ||
481 | if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) | |
482 | wbcir_irq_tx(data); | |
5b2e303f | 483 | |
5b2e303f | 484 | spin_unlock_irqrestore(&data->spinlock, flags); |
e258b80e DH |
485 | return IRQ_HANDLED; |
486 | } | |
487 | ||
c829f267 DH |
488 | /***************************************************************************** |
489 | * | |
490 | * RC-CORE INTERFACE FUNCTIONS | |
491 | * | |
492 | *****************************************************************************/ | |
493 | ||
494 | static int | |
495 | wbcir_txcarrier(struct rc_dev *dev, u32 carrier) | |
496 | { | |
497 | struct wbcir_data *data = dev->priv; | |
498 | unsigned long flags; | |
499 | u8 val; | |
500 | u32 freq; | |
501 | ||
502 | freq = DIV_ROUND_CLOSEST(carrier, 1000); | |
503 | if (freq < 30 || freq > 60) | |
504 | return -EINVAL; | |
505 | ||
506 | switch (freq) { | |
507 | case 58: | |
508 | case 59: | |
509 | case 60: | |
510 | val = freq - 58; | |
511 | freq *= 1000; | |
512 | break; | |
513 | case 57: | |
514 | val = freq - 27; | |
515 | freq = 56900; | |
516 | break; | |
517 | default: | |
518 | val = freq - 27; | |
519 | freq *= 1000; | |
520 | break; | |
521 | } | |
522 | ||
523 | spin_lock_irqsave(&data->spinlock, flags); | |
524 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
525 | spin_unlock_irqrestore(&data->spinlock, flags); | |
526 | return -EBUSY; | |
527 | } | |
528 | ||
529 | if (data->txcarrier != freq) { | |
530 | wbcir_select_bank(data, WBCIR_BANK_7); | |
531 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); | |
532 | data->txcarrier = freq; | |
533 | } | |
534 | ||
535 | spin_unlock_irqrestore(&data->spinlock, flags); | |
536 | return 0; | |
537 | } | |
538 | ||
539 | static int | |
540 | wbcir_txmask(struct rc_dev *dev, u32 mask) | |
541 | { | |
542 | struct wbcir_data *data = dev->priv; | |
543 | unsigned long flags; | |
544 | u8 val; | |
545 | ||
546 | /* Four outputs, only one output can be enabled at a time */ | |
547 | switch (mask) { | |
548 | case 0x1: | |
549 | val = 0x0; | |
550 | break; | |
551 | case 0x2: | |
552 | val = 0x1; | |
553 | break; | |
554 | case 0x4: | |
555 | val = 0x2; | |
556 | break; | |
557 | case 0x8: | |
558 | val = 0x3; | |
559 | break; | |
560 | default: | |
561 | return -EINVAL; | |
562 | } | |
563 | ||
564 | spin_lock_irqsave(&data->spinlock, flags); | |
565 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
566 | spin_unlock_irqrestore(&data->spinlock, flags); | |
567 | return -EBUSY; | |
568 | } | |
569 | ||
570 | if (data->txmask != mask) { | |
571 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); | |
572 | data->txmask = mask; | |
573 | } | |
574 | ||
575 | spin_unlock_irqrestore(&data->spinlock, flags); | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static int | |
7bfb5dc1 | 580 | wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) |
c829f267 DH |
581 | { |
582 | struct wbcir_data *data = dev->priv; | |
7bfb5dc1 | 583 | unsigned *buf; |
c829f267 DH |
584 | unsigned i; |
585 | unsigned long flags; | |
586 | ||
7bfb5dc1 DH |
587 | buf = kmalloc(count * sizeof(*b), GFP_KERNEL); |
588 | if (!buf) | |
589 | return -ENOMEM; | |
590 | ||
591 | /* Convert values to multiples of 10us */ | |
592 | for (i = 0; i < count; i++) | |
593 | buf[i] = DIV_ROUND_CLOSEST(b[i], 10); | |
594 | ||
c829f267 DH |
595 | /* Not sure if this is possible, but better safe than sorry */ |
596 | spin_lock_irqsave(&data->spinlock, flags); | |
597 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
598 | spin_unlock_irqrestore(&data->spinlock, flags); | |
7bfb5dc1 | 599 | kfree(buf); |
c829f267 DH |
600 | return -EBUSY; |
601 | } | |
602 | ||
c829f267 DH |
603 | /* Fill the TX fifo once, the irq handler will do the rest */ |
604 | data->txbuf = buf; | |
605 | data->txlen = count; | |
606 | data->txoff = 0; | |
607 | wbcir_irq_tx(data); | |
608 | ||
c829f267 | 609 | /* We're done */ |
c829f267 | 610 | spin_unlock_irqrestore(&data->spinlock, flags); |
c829f267 DH |
611 | return count; |
612 | } | |
e258b80e DH |
613 | |
614 | /***************************************************************************** | |
615 | * | |
197d4db7 | 616 | * SETUP/INIT/SUSPEND/RESUME FUNCTIONS |
e258b80e DH |
617 | * |
618 | *****************************************************************************/ | |
619 | ||
620 | static void | |
621 | wbcir_shutdown(struct pnp_dev *device) | |
622 | { | |
623 | struct device *dev = &device->dev; | |
624 | struct wbcir_data *data = pnp_get_drvdata(device); | |
67cdd42e | 625 | bool do_wake = true; |
e258b80e DH |
626 | u8 match[11]; |
627 | u8 mask[11]; | |
628 | u8 rc6_csl = 0; | |
629 | int i; | |
630 | ||
631 | memset(match, 0, sizeof(match)); | |
632 | memset(mask, 0, sizeof(mask)); | |
633 | ||
634 | if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) { | |
67cdd42e | 635 | do_wake = false; |
e258b80e DH |
636 | goto finish; |
637 | } | |
638 | ||
639 | switch (protocol) { | |
640 | case IR_PROTOCOL_RC5: | |
641 | if (wake_sc > 0xFFF) { | |
67cdd42e | 642 | do_wake = false; |
e258b80e DH |
643 | dev_err(dev, "RC5 - Invalid wake scancode\n"); |
644 | break; | |
645 | } | |
646 | ||
647 | /* Mask = 13 bits, ex toggle */ | |
648 | mask[0] = 0xFF; | |
649 | mask[1] = 0x17; | |
650 | ||
651 | match[0] = (wake_sc & 0x003F); /* 6 command bits */ | |
652 | match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */ | |
653 | match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */ | |
654 | if (!(wake_sc & 0x0040)) /* 2nd start bit */ | |
655 | match[1] |= 0x10; | |
656 | ||
657 | break; | |
658 | ||
659 | case IR_PROTOCOL_NEC: | |
660 | if (wake_sc > 0xFFFFFF) { | |
67cdd42e | 661 | do_wake = false; |
e258b80e DH |
662 | dev_err(dev, "NEC - Invalid wake scancode\n"); |
663 | break; | |
664 | } | |
665 | ||
666 | mask[0] = mask[1] = mask[2] = mask[3] = 0xFF; | |
667 | ||
668 | match[1] = bitrev8((wake_sc & 0xFF)); | |
669 | match[0] = ~match[1]; | |
670 | ||
671 | match[3] = bitrev8((wake_sc & 0xFF00) >> 8); | |
672 | if (wake_sc > 0xFFFF) | |
673 | match[2] = bitrev8((wake_sc & 0xFF0000) >> 16); | |
674 | else | |
675 | match[2] = ~match[3]; | |
676 | ||
677 | break; | |
678 | ||
679 | case IR_PROTOCOL_RC6: | |
680 | ||
681 | if (wake_rc6mode == 0) { | |
682 | if (wake_sc > 0xFFFF) { | |
67cdd42e | 683 | do_wake = false; |
e258b80e DH |
684 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
685 | break; | |
686 | } | |
687 | ||
688 | /* Command */ | |
689 | match[0] = wbcir_to_rc6cells(wake_sc >> 0); | |
690 | mask[0] = 0xFF; | |
691 | match[1] = wbcir_to_rc6cells(wake_sc >> 4); | |
692 | mask[1] = 0xFF; | |
693 | ||
694 | /* Address */ | |
695 | match[2] = wbcir_to_rc6cells(wake_sc >> 8); | |
696 | mask[2] = 0xFF; | |
697 | match[3] = wbcir_to_rc6cells(wake_sc >> 12); | |
698 | mask[3] = 0xFF; | |
699 | ||
700 | /* Header */ | |
701 | match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ | |
702 | mask[4] = 0xF0; | |
703 | match[5] = 0x09; /* start bit = 1, mode2 = 0 */ | |
704 | mask[5] = 0x0F; | |
705 | ||
706 | rc6_csl = 44; | |
707 | ||
708 | } else if (wake_rc6mode == 6) { | |
709 | i = 0; | |
710 | ||
711 | /* Command */ | |
712 | match[i] = wbcir_to_rc6cells(wake_sc >> 0); | |
713 | mask[i++] = 0xFF; | |
714 | match[i] = wbcir_to_rc6cells(wake_sc >> 4); | |
715 | mask[i++] = 0xFF; | |
716 | ||
717 | /* Address + Toggle */ | |
718 | match[i] = wbcir_to_rc6cells(wake_sc >> 8); | |
719 | mask[i++] = 0xFF; | |
720 | match[i] = wbcir_to_rc6cells(wake_sc >> 12); | |
721 | mask[i++] = 0x3F; | |
722 | ||
723 | /* Customer bits 7 - 0 */ | |
724 | match[i] = wbcir_to_rc6cells(wake_sc >> 16); | |
725 | mask[i++] = 0xFF; | |
726 | match[i] = wbcir_to_rc6cells(wake_sc >> 20); | |
727 | mask[i++] = 0xFF; | |
728 | ||
729 | if (wake_sc & 0x80000000) { | |
730 | /* Customer range bit and bits 15 - 8 */ | |
731 | match[i] = wbcir_to_rc6cells(wake_sc >> 24); | |
732 | mask[i++] = 0xFF; | |
733 | match[i] = wbcir_to_rc6cells(wake_sc >> 28); | |
734 | mask[i++] = 0xFF; | |
735 | rc6_csl = 76; | |
736 | } else if (wake_sc <= 0x007FFFFF) { | |
737 | rc6_csl = 60; | |
738 | } else { | |
67cdd42e | 739 | do_wake = false; |
e258b80e DH |
740 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
741 | break; | |
742 | } | |
743 | ||
744 | /* Header */ | |
745 | match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ | |
746 | mask[i++] = 0xFF; | |
747 | match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ | |
748 | mask[i++] = 0x0F; | |
749 | ||
750 | } else { | |
67cdd42e | 751 | do_wake = false; |
e258b80e DH |
752 | dev_err(dev, "RC6 - Invalid wake mode\n"); |
753 | } | |
754 | ||
755 | break; | |
756 | ||
757 | default: | |
67cdd42e | 758 | do_wake = false; |
e258b80e DH |
759 | break; |
760 | } | |
761 | ||
762 | finish: | |
763 | if (do_wake) { | |
764 | /* Set compare and compare mask */ | |
765 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
766 | WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, | |
767 | 0x3F); | |
768 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); | |
769 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
770 | WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, | |
771 | 0x3F); | |
772 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); | |
773 | ||
774 | /* RC6 Compare String Len */ | |
775 | outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); | |
776 | ||
777 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
778 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
779 | ||
780 | /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ | |
781 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); | |
782 | ||
783 | /* Set CEIR_EN */ | |
784 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01); | |
785 | ||
786 | } else { | |
787 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
788 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
789 | ||
790 | /* Clear CEIR_EN */ | |
791 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
792 | } | |
793 | ||
197d4db7 DH |
794 | /* |
795 | * ACPI will set the HW disable bit for SP3 which means that the | |
796 | * output signals are left in an undefined state which may cause | |
797 | * spurious interrupts which we need to ignore until the hardware | |
798 | * is reinitialized. | |
799 | */ | |
c829f267 | 800 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 801 | disable_irq(data->irq); |
c829f267 DH |
802 | |
803 | /* Disable LED */ | |
804 | led_trigger_event(data->rxtrigger, LED_OFF); | |
805 | led_trigger_event(data->txtrigger, LED_OFF); | |
e258b80e DH |
806 | } |
807 | ||
808 | static int | |
809 | wbcir_suspend(struct pnp_dev *device, pm_message_t state) | |
810 | { | |
811 | wbcir_shutdown(device); | |
812 | return 0; | |
813 | } | |
814 | ||
e258b80e | 815 | static void |
197d4db7 | 816 | wbcir_init_hw(struct wbcir_data *data) |
e258b80e DH |
817 | { |
818 | u8 tmp; | |
819 | ||
197d4db7 | 820 | /* Disable interrupts */ |
c829f267 | 821 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 822 | |
e258b80e DH |
823 | /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */ |
824 | tmp = protocol << 4; | |
825 | if (invert) | |
826 | tmp |= 0x08; | |
827 | outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL); | |
828 | ||
829 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
830 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
831 | ||
832 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
833 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
834 | ||
835 | /* Set RC5 cell time to correspond to 36 kHz */ | |
836 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); | |
837 | ||
838 | /* Set IRTX_INV */ | |
839 | if (invert) | |
840 | outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL); | |
841 | else | |
842 | outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); | |
843 | ||
844 | /* | |
c829f267 | 845 | * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, |
e258b80e DH |
846 | * set SP3_IRRX_SW to binary 01, helpfully not documented |
847 | */ | |
848 | outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); | |
c829f267 | 849 | data->txmask = 0x1; |
197d4db7 DH |
850 | |
851 | /* Enable extended mode */ | |
852 | wbcir_select_bank(data, WBCIR_BANK_2); | |
853 | outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); | |
854 | ||
855 | /* | |
856 | * Configure baud generator, IR data will be sampled at | |
857 | * a bitrate of: (24Mhz * prescaler) / (divisor * 16). | |
858 | * | |
859 | * The ECIR registers include a flag to change the | |
860 | * 24Mhz clock freq to 48Mhz. | |
861 | * | |
862 | * It's not documented in the specs, but fifo levels | |
863 | * other than 16 seems to be unsupported. | |
864 | */ | |
865 | ||
866 | /* prescaler 1.0, tx/rx fifo lvl 16 */ | |
867 | outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); | |
868 | ||
b87f2edd DH |
869 | /* Set baud divisor to sample every 10 us */ |
870 | outb(0x0F, data->sbase + WBCIR_REG_SP3_BGDL); | |
197d4db7 DH |
871 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
872 | ||
873 | /* Set CEIR mode */ | |
874 | wbcir_select_bank(data, WBCIR_BANK_0); | |
875 | outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); | |
876 | inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ | |
877 | inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ | |
878 | ||
b87f2edd | 879 | /* Disable RX demod, enable run-length enc/dec, set freq span */ |
197d4db7 | 880 | wbcir_select_bank(data, WBCIR_BANK_7); |
b87f2edd | 881 | outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); |
197d4db7 DH |
882 | |
883 | /* Disable timer */ | |
884 | wbcir_select_bank(data, WBCIR_BANK_4); | |
885 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); | |
886 | ||
c829f267 | 887 | /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ |
197d4db7 | 888 | wbcir_select_bank(data, WBCIR_BANK_5); |
c829f267 | 889 | outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); |
197d4db7 DH |
890 | |
891 | /* Disable CRC */ | |
892 | wbcir_select_bank(data, WBCIR_BANK_6); | |
893 | outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); | |
894 | ||
c829f267 | 895 | /* Set RX demodulation freq, not really used */ |
197d4db7 DH |
896 | wbcir_select_bank(data, WBCIR_BANK_7); |
897 | outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); | |
c829f267 DH |
898 | |
899 | /* Set TX modulation, 36kHz, 7us pulse width */ | |
197d4db7 | 900 | outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); |
c829f267 | 901 | data->txcarrier = 36000; |
197d4db7 DH |
902 | |
903 | /* Set invert and pin direction */ | |
904 | if (invert) | |
905 | outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
906 | else | |
907 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
908 | ||
909 | /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ | |
910 | wbcir_select_bank(data, WBCIR_BANK_0); | |
911 | outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); | |
912 | ||
913 | /* Clear AUX status bits */ | |
914 | outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); | |
915 | ||
c829f267 DH |
916 | /* Clear RX state */ |
917 | data->rxstate = WBCIR_RXSTATE_INACTIVE; | |
918 | data->rxev.duration = 0; | |
5b2e303f DH |
919 | ir_raw_event_reset(data->dev); |
920 | ir_raw_event_handle(data->dev); | |
921 | ||
7bfb5dc1 | 922 | /* Clear TX state */ |
c829f267 | 923 | if (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
7bfb5dc1 DH |
924 | kfree(data->txbuf); |
925 | data->txbuf = NULL; | |
926 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
927 | } |
928 | ||
197d4db7 | 929 | /* Enable interrupts */ |
c829f267 | 930 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
197d4db7 DH |
931 | } |
932 | ||
933 | static int | |
934 | wbcir_resume(struct pnp_dev *device) | |
935 | { | |
936 | struct wbcir_data *data = pnp_get_drvdata(device); | |
937 | ||
938 | wbcir_init_hw(data); | |
939 | enable_irq(data->irq); | |
940 | ||
941 | return 0; | |
e258b80e DH |
942 | } |
943 | ||
944 | static int __devinit | |
945 | wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) | |
946 | { | |
947 | struct device *dev = &device->dev; | |
948 | struct wbcir_data *data; | |
949 | int err; | |
950 | ||
951 | if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && | |
952 | pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && | |
953 | pnp_port_len(device, 2) == SP_IOMEM_LEN)) { | |
954 | dev_err(dev, "Invalid resources\n"); | |
955 | return -ENODEV; | |
956 | } | |
957 | ||
958 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
959 | if (!data) { | |
960 | err = -ENOMEM; | |
961 | goto exit; | |
962 | } | |
963 | ||
964 | pnp_set_drvdata(device, data); | |
965 | ||
5b2e303f | 966 | spin_lock_init(&data->spinlock); |
e258b80e DH |
967 | data->ebase = pnp_port_start(device, 0); |
968 | data->wbase = pnp_port_start(device, 1); | |
969 | data->sbase = pnp_port_start(device, 2); | |
970 | data->irq = pnp_irq(device, 0); | |
971 | ||
972 | if (data->wbase == 0 || data->ebase == 0 || | |
973 | data->sbase == 0 || data->irq == 0) { | |
974 | err = -ENODEV; | |
975 | dev_err(dev, "Invalid resources\n"); | |
976 | goto exit_free_data; | |
977 | } | |
978 | ||
979 | dev_dbg(&device->dev, "Found device " | |
980 | "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", | |
981 | data->wbase, data->ebase, data->sbase, data->irq); | |
982 | ||
e258b80e DH |
983 | led_trigger_register_simple("cir-tx", &data->txtrigger); |
984 | if (!data->txtrigger) { | |
985 | err = -ENOMEM; | |
9ef449c6 | 986 | goto exit_free_data; |
e258b80e DH |
987 | } |
988 | ||
989 | led_trigger_register_simple("cir-rx", &data->rxtrigger); | |
990 | if (!data->rxtrigger) { | |
991 | err = -ENOMEM; | |
992 | goto exit_unregister_txtrigger; | |
993 | } | |
994 | ||
995 | data->led.name = "cir::activity"; | |
996 | data->led.default_trigger = "cir-rx"; | |
997 | data->led.brightness_set = wbcir_led_brightness_set; | |
998 | data->led.brightness_get = wbcir_led_brightness_get; | |
999 | err = led_classdev_register(&device->dev, &data->led); | |
1000 | if (err) | |
1001 | goto exit_unregister_rxtrigger; | |
1002 | ||
5b2e303f DH |
1003 | data->dev = rc_allocate_device(); |
1004 | if (!data->dev) { | |
e258b80e DH |
1005 | err = -ENOMEM; |
1006 | goto exit_unregister_led; | |
1007 | } | |
1008 | ||
d9b78695 | 1009 | data->dev->driver_type = RC_DRIVER_IR_RAW; |
5b2e303f DH |
1010 | data->dev->driver_name = WBCIR_NAME; |
1011 | data->dev->input_name = WBCIR_NAME; | |
1012 | data->dev->input_phys = "wbcir/cir0"; | |
1013 | data->dev->input_id.bustype = BUS_HOST; | |
1014 | data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; | |
1015 | data->dev->input_id.product = WBCIR_ID_FAMILY; | |
1016 | data->dev->input_id.version = WBCIR_ID_CHIP; | |
c829f267 | 1017 | data->dev->map_name = RC_MAP_RC6_MCE; |
488ebc48 | 1018 | data->dev->s_idle = wbcir_idle_rx; |
c829f267 DH |
1019 | data->dev->s_tx_mask = wbcir_txmask; |
1020 | data->dev->s_tx_carrier = wbcir_txcarrier; | |
1021 | data->dev->tx_ir = wbcir_tx; | |
5b2e303f DH |
1022 | data->dev->priv = data; |
1023 | data->dev->dev.parent = &device->dev; | |
8299d628 AB |
1024 | data->dev->timeout = MS_TO_NS(100); |
1025 | data->dev->allowed_protos = RC_TYPE_ALL; | |
5b2e303f | 1026 | |
9ef449c6 LH |
1027 | if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { |
1028 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1029 | data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); | |
1030 | err = -EBUSY; | |
1031 | goto exit_free_rc; | |
1032 | } | |
1033 | ||
1034 | if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { | |
1035 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1036 | data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); | |
1037 | err = -EBUSY; | |
1038 | goto exit_release_wbase; | |
1039 | } | |
1040 | ||
1041 | if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { | |
1042 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1043 | data->sbase, data->sbase + SP_IOMEM_LEN - 1); | |
1044 | err = -EBUSY; | |
1045 | goto exit_release_ebase; | |
1046 | } | |
1047 | ||
1048 | err = request_irq(data->irq, wbcir_irq_handler, | |
1049 | IRQF_DISABLED, DRVNAME, device); | |
1050 | if (err) { | |
1051 | dev_err(dev, "Failed to claim IRQ %u\n", data->irq); | |
1052 | err = -EBUSY; | |
1053 | goto exit_release_sbase; | |
1054 | } | |
1055 | ||
5b2e303f | 1056 | err = rc_register_device(data->dev); |
e258b80e | 1057 | if (err) |
9ef449c6 | 1058 | goto exit_free_irq; |
e258b80e DH |
1059 | |
1060 | device_init_wakeup(&device->dev, 1); | |
1061 | ||
197d4db7 | 1062 | wbcir_init_hw(data); |
e258b80e DH |
1063 | |
1064 | return 0; | |
1065 | ||
e258b80e DH |
1066 | exit_free_irq: |
1067 | free_irq(data->irq, device); | |
1068 | exit_release_sbase: | |
1069 | release_region(data->sbase, SP_IOMEM_LEN); | |
1070 | exit_release_ebase: | |
1071 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1072 | exit_release_wbase: | |
1073 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
9ef449c6 LH |
1074 | exit_free_rc: |
1075 | rc_free_device(data->dev); | |
1076 | exit_unregister_led: | |
1077 | led_classdev_unregister(&data->led); | |
1078 | exit_unregister_rxtrigger: | |
1079 | led_trigger_unregister_simple(data->rxtrigger); | |
1080 | exit_unregister_txtrigger: | |
1081 | led_trigger_unregister_simple(data->txtrigger); | |
e258b80e DH |
1082 | exit_free_data: |
1083 | kfree(data); | |
1084 | pnp_set_drvdata(device, NULL); | |
1085 | exit: | |
1086 | return err; | |
1087 | } | |
1088 | ||
1089 | static void __devexit | |
1090 | wbcir_remove(struct pnp_dev *device) | |
1091 | { | |
1092 | struct wbcir_data *data = pnp_get_drvdata(device); | |
e258b80e DH |
1093 | |
1094 | /* Disable interrupts */ | |
c829f267 | 1095 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
e258b80e DH |
1096 | free_irq(data->irq, device); |
1097 | ||
1098 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
1099 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
1100 | ||
1101 | /* Clear CEIR_EN */ | |
1102 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
1103 | ||
1104 | /* Clear BUFF_EN, END_EN, MATCH_EN */ | |
1105 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
1106 | ||
5b2e303f | 1107 | rc_unregister_device(data->dev); |
e258b80e DH |
1108 | |
1109 | led_trigger_unregister_simple(data->rxtrigger); | |
1110 | led_trigger_unregister_simple(data->txtrigger); | |
1111 | led_classdev_unregister(&data->led); | |
1112 | ||
1113 | /* This is ok since &data->led isn't actually used */ | |
1114 | wbcir_led_brightness_set(&data->led, LED_OFF); | |
1115 | ||
1116 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
1117 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1118 | release_region(data->sbase, SP_IOMEM_LEN); | |
1119 | ||
e258b80e DH |
1120 | kfree(data); |
1121 | ||
1122 | pnp_set_drvdata(device, NULL); | |
1123 | } | |
1124 | ||
1125 | static const struct pnp_device_id wbcir_ids[] = { | |
1126 | { "WEC1022", 0 }, | |
1127 | { "", 0 } | |
1128 | }; | |
1129 | MODULE_DEVICE_TABLE(pnp, wbcir_ids); | |
1130 | ||
1131 | static struct pnp_driver wbcir_driver = { | |
1132 | .name = WBCIR_NAME, | |
1133 | .id_table = wbcir_ids, | |
1134 | .probe = wbcir_probe, | |
1135 | .remove = __devexit_p(wbcir_remove), | |
1136 | .suspend = wbcir_suspend, | |
1137 | .resume = wbcir_resume, | |
1138 | .shutdown = wbcir_shutdown | |
1139 | }; | |
1140 | ||
1141 | static int __init | |
1142 | wbcir_init(void) | |
1143 | { | |
1144 | int ret; | |
1145 | ||
1146 | switch (protocol) { | |
1147 | case IR_PROTOCOL_RC5: | |
1148 | case IR_PROTOCOL_NEC: | |
1149 | case IR_PROTOCOL_RC6: | |
1150 | break; | |
1151 | default: | |
d8a10ac9 | 1152 | pr_err("Invalid power-on protocol\n"); |
e258b80e DH |
1153 | } |
1154 | ||
1155 | ret = pnp_register_driver(&wbcir_driver); | |
1156 | if (ret) | |
d8a10ac9 | 1157 | pr_err("Unable to register driver\n"); |
e258b80e DH |
1158 | |
1159 | return ret; | |
1160 | } | |
1161 | ||
1162 | static void __exit | |
1163 | wbcir_exit(void) | |
1164 | { | |
1165 | pnp_unregister_driver(&wbcir_driver); | |
1166 | } | |
1167 | ||
e258b80e DH |
1168 | module_init(wbcir_init); |
1169 | module_exit(wbcir_exit); | |
1170 | ||
d36b6910 | 1171 | MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); |
5b2e303f DH |
1172 | MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); |
1173 | MODULE_LICENSE("GPL"); |