projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] ene_ir: Use current logging styles
[deliverable/linux.git] / drivers / media / rc / winbond-cir.c
CommitLineData
e258b80e
DH		 1/*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
b87f2edd
DH		 9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
e258b80e 11 *
5b2e303f
DH		 12 * Dedicated to my daughter Matilda, without whose loving attention this
13 * driver would have been finished in half the time and with a fraction
e258b80e
DH		 14 * of the bugs.
15 *
16 * Written using:
17 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
18 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
19 * o DSDT dumps
20 *
21 * Supported features:
c829f267
DH		 22 * o IR Receive
23 * o IR Transmit
e258b80e
DH		 24 * o Wake-On-CIR functionality
25 *
26 * To do:
5b2e303f 27 * o Learning
e258b80e
DH		 28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
42 */
43
44#include <linux/module.h>
45#include <linux/pnp.h>
46#include <linux/interrupt.h>
47#include <linux/timer.h>
e258b80e 48#include <linux/leds.h>
e258b80e
DH		 49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/io.h>
52#include <linux/bitrev.h>
5a0e3ad6 53#include <linux/slab.h>
c829f267
DH		 54#include <linux/wait.h>
55#include <linux/sched.h>
6bda9644 56#include <media/rc-core.h>
e258b80e
DH		 57
58#define DRVNAME "winbond-cir"
59
60/* CEIR Wake-Up Registers, relative to data->wbase */
61#define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
62#define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
63#define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
64#define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
65#define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
66#define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
67#define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
68#define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
69#define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
70#define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
71
72/* CEIR Enhanced Functionality Registers, relative to data->ebase */
73#define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
74#define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
75#define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
76#define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
77#define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
78
79/* SP3 Banked Registers, relative to data->sbase */
80#define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
81 /* Bank 0 */
82#define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
83#define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
84#define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
85#define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
86#define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
87#define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
88#define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
89#define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
90#define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
91 /* Bank 2 */
92#define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
93#define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
94#define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
95#define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
96#define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
97#define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
98 /* Bank 3 */
99#define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
100#define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
101#define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
102 /* Bank 4 */
103#define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
104 /* Bank 5 */
105#define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
106 /* Bank 6 */
107#define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
5b2e303f 108#define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
e258b80e
DH		 109 /* Bank 7 */
110#define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
111#define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
112#define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
113#define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
114#define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
115
116/*
117 * Magic values follow
118 */
119
120/* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
121#define WBCIR_IRQ_NONE 0x00
122/* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
123#define WBCIR_IRQ_RX 0x01
c829f267
DH		 124/* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
125#define WBCIR_IRQ_TX_LOW 0x02
e258b80e
DH		 126/* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
127#define WBCIR_IRQ_ERR 0x04
c829f267
DH		 128/* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
129#define WBCIR_IRQ_TX_EMPTY 0x20
e258b80e
DH		 130/* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
131#define WBCIR_LED_ENABLE 0x80
132/* RX data available bit for WBCIR_REG_SP3_LSR */
133#define WBCIR_RX_AVAIL 0x01
c829f267
DH		 134/* RX data overrun error bit for WBCIR_REG_SP3_LSR */
135#define WBCIR_RX_OVERRUN 0x02
136/* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
137#define WBCIR_TX_EOT 0x04
e258b80e
DH		 138/* RX disable bit for WBCIR_REG_SP3_ASCR */
139#define WBCIR_RX_DISABLE 0x20
c829f267
DH		 140/* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
141#define WBCIR_TX_UNDERRUN 0x40
e258b80e
DH		 142/* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
143#define WBCIR_EXT_ENABLE 0x01
144/* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
145#define WBCIR_REGSEL_COMPARE 0x10
146/* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
147#define WBCIR_REGSEL_MASK 0x20
148/* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
149#define WBCIR_REG_ADDR0 0x00
150
151/* Valid banks for the SP3 UART */
152enum wbcir_bank {
153 WBCIR_BANK_0 = 0x00,
154 WBCIR_BANK_1 = 0x80,
155 WBCIR_BANK_2 = 0xE0,
156 WBCIR_BANK_3 = 0xE4,
157 WBCIR_BANK_4 = 0xE8,
158 WBCIR_BANK_5 = 0xEC,
159 WBCIR_BANK_6 = 0xF0,
160 WBCIR_BANK_7 = 0xF4,
161};
162
5b2e303f 163/* Supported power-on IR Protocols */
e258b80e
DH		 164enum wbcir_protocol {
165 IR_PROTOCOL_RC5 = 0x0,
166 IR_PROTOCOL_NEC = 0x1,
167 IR_PROTOCOL_RC6 = 0x2,
168};
169
c829f267
DH		 170/* Possible states for IR reception */
171enum wbcir_rxstate {
172 WBCIR_RXSTATE_INACTIVE = 0,
173 WBCIR_RXSTATE_ACTIVE,
174 WBCIR_RXSTATE_ERROR
175};
176
177/* Possible states for IR transmission */
178enum wbcir_txstate {
179 WBCIR_TXSTATE_INACTIVE = 0,
180 WBCIR_TXSTATE_ACTIVE,
181 WBCIR_TXSTATE_DONE,
182 WBCIR_TXSTATE_ERROR
183};
184
e258b80e
DH		 185/* Misc */
186#define WBCIR_NAME "Winbond CIR"
187#define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
188#define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
e258b80e
DH		 189#define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
190#define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
191#define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
192#define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
e258b80e 193
5b2e303f 194/* Per-device data */
e258b80e 195struct wbcir_data {
5b2e303f 196 spinlock_t spinlock;
c829f267
DH		 197 struct rc_dev *dev;
198 struct led_classdev led;
5b2e303f 199
e258b80e
DH		 200 unsigned long wbase; /* Wake-Up Baseaddr */
201 unsigned long ebase; /* Enhanced Func. Baseaddr */
202 unsigned long sbase; /* Serial Port Baseaddr */
203 unsigned int irq; /* Serial Port IRQ */
c829f267 204 u8 irqmask;
e258b80e 205
c829f267
DH		 206 /* RX state */
207 enum wbcir_rxstate rxstate;
e258b80e 208 struct led_trigger *rxtrigger;
c829f267 209 struct ir_raw_event rxev;
e258b80e 210
c829f267
DH		 211 /* TX state */
212 enum wbcir_txstate txstate;
213 struct led_trigger *txtrigger;
214 u32 txlen;
215 u32 txoff;
216 u32 *txbuf;
217 wait_queue_head_t txwaitq;
218 u8 txmask;
219 u32 txcarrier;
e258b80e
DH		 220};
221
222static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
223module_param(protocol, uint, 0444);
5b2e303f 224MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
e258b80e
DH		 225 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
226
227static int invert; /* default = 0 */
228module_param(invert, bool, 0444);
229MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
230
c829f267
DH		 231static int txandrx; /* default = 0 */
232module_param(txandrx, bool, 0444);
233MODULE_PARM_DESC(invert, "Allow simultaneous TX and RX");
234
e258b80e
DH		 235static unsigned int wake_sc = 0x800F040C;
236module_param(wake_sc, uint, 0644);
237MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
238
239static unsigned int wake_rc6mode = 6;
240module_param(wake_rc6mode, uint, 0644);
241MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
242 "(0 = 0, 6 = 6A, default)");
243
244
245
246/*****************************************************************************
247 *
248 * UTILITY FUNCTIONS
249 *
250 *****************************************************************************/
251
252/* Caller needs to hold wbcir_lock */
253static void
254wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
255{
256 u8 val;
257
258 val = inb(addr);
259 val = ((val & ~mask) | (bits & mask));
260 outb(val, addr);
261}
262
263/* Selects the register bank for the serial port */
264static inline void
265wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
266{
267 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
268}
269
c829f267
DH		 270static inline void
271wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
272{
273 if (data->irqmask == irqmask)
274 return;
275
276 wbcir_select_bank(data, WBCIR_BANK_0);
277 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
278 data->irqmask = irqmask;
279}
280
e258b80e
DH		 281static enum led_brightness
282wbcir_led_brightness_get(struct led_classdev *led_cdev)
283{
284 struct wbcir_data *data = container_of(led_cdev,
285 struct wbcir_data,
286 led);
287
288 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
289 return LED_FULL;
290 else
291 return LED_OFF;
292}
293
294static void
295wbcir_led_brightness_set(struct led_classdev *led_cdev,
5b2e303f 296 enum led_brightness brightness)
e258b80e
DH		 297{
298 struct wbcir_data *data = container_of(led_cdev,
299 struct wbcir_data,
300 led);
301
302 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
303 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
304 WBCIR_LED_ENABLE);
305}
306
5b2e303f 307/* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
e258b80e
DH		 308static u8
309wbcir_to_rc6cells(u8 val)
310{
311 u8 coded = 0x00;
312 int i;
313
314 val &= 0x0F;
315 for (i = 0; i < 4; i++) {
316 if (val & 0x01)
317 coded |= 0x02 << (i * 2);
318 else
319 coded |= 0x01 << (i * 2);
320 val >>= 1;
321 }
322
323 return coded;
324}
325
e258b80e
DH		 326/*****************************************************************************
327 *
328 * INTERRUPT FUNCTIONS
329 *
330 *****************************************************************************/
331
c829f267 332static void
488ebc48 333wbcir_idle_rx(struct rc_dev *dev, bool idle)
e258b80e 334{
488ebc48 335 struct wbcir_data *data = dev->priv;
e258b80e 336
488ebc48 337 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
c829f267 338 data->rxstate = WBCIR_RXSTATE_ACTIVE;
5b2e303f
DH		 339 led_trigger_event(data->rxtrigger, LED_FULL);
340 }
341
488ebc48
DH		 342 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE)
343 /* Tell hardware to go idle by setting RXINACTIVE */
344 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
345}
e258b80e 346
488ebc48
DH		 347static void
348wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
349{
350 u8 irdata;
351 DEFINE_IR_RAW_EVENT(rawir);
5b2e303f 352
488ebc48
DH		 353 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
354 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
355 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
c829f267 356 if (data->rxstate == WBCIR_RXSTATE_ERROR)
5b2e303f 357 continue;
488ebc48
DH		 358 rawir.pulse = irdata & 0x80 ? false : true;
359 rawir.duration = US_TO_NS((irdata & 0x7F) * 10);
360 ir_raw_event_store_with_filter(data->dev, &rawir);
e258b80e
DH		 361 }
362
488ebc48
DH		 363 /* Check if we should go idle */
364 if (data->dev->idle) {
5b2e303f 365 led_trigger_event(data->rxtrigger, LED_OFF);
c829f267 366 data->rxstate = WBCIR_RXSTATE_INACTIVE;
e258b80e
DH		 367 }
368
5b2e303f 369 ir_raw_event_handle(data->dev);
c829f267
DH		 370}
371
372static void
373wbcir_irq_tx(struct wbcir_data *data)
374{
375 unsigned int space;
376 unsigned int used;
377 u8 bytes[16];
378 u8 byte;
379
380 if (!data->txbuf)
381 return;
382
383 switch (data->txstate) {
384 case WBCIR_TXSTATE_INACTIVE:
385 /* TX FIFO empty */
386 space = 16;
387 led_trigger_event(data->txtrigger, LED_FULL);
388 break;
389 case WBCIR_TXSTATE_ACTIVE:
390 /* TX FIFO low (3 bytes or less) */
391 space = 13;
392 break;
393 case WBCIR_TXSTATE_ERROR:
394 space = 0;
395 break;
396 default:
397 return;
398 }
399
400 /*
401 * TX data is run-length coded in bytes: YXXXXXXX
402 * Y = space (1) or pulse (0)
403 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
404 */
405 for (used = 0; used < space && data->txoff != data->txlen; used++) {
406 if (data->txbuf[data->txoff] == 0) {
407 data->txoff++;
408 continue;
409 }
410 byte = min((u32)0x80, data->txbuf[data->txoff]);
411 data->txbuf[data->txoff] -= byte;
412 byte--;
413 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
414 bytes[used] = byte;
415 }
416
417 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
418 data->txoff++;
419
420 if (used == 0) {
421 /* Finished */
422 if (data->txstate == WBCIR_TXSTATE_ERROR)
423 /* Clear TX underrun bit */
424 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
425 else
426 data->txstate = WBCIR_TXSTATE_DONE;
427 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
428 led_trigger_event(data->txtrigger, LED_OFF);
429 wake_up(&data->txwaitq);
430 } else if (data->txoff == data->txlen) {
431 /* At the end of transmission, tell the hw before last byte */
432 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
433 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
434 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
435 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
436 WBCIR_IRQ_TX_EMPTY);
437 } else {
438 /* More data to follow... */
439 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
440 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
441 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
442 WBCIR_IRQ_TX_LOW);
443 data->txstate = WBCIR_TXSTATE_ACTIVE;
444 }
445 }
446}
447
448static irqreturn_t
449wbcir_irq_handler(int irqno, void *cookie)
450{
451 struct pnp_dev *device = cookie;
452 struct wbcir_data *data = pnp_get_drvdata(device);
453 unsigned long flags;
454 u8 status;
455
456 spin_lock_irqsave(&data->spinlock, flags);
457 wbcir_select_bank(data, WBCIR_BANK_0);
458 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
459 status &= data->irqmask;
460
461 if (!status) {
462 spin_unlock_irqrestore(&data->spinlock, flags);
463 return IRQ_NONE;
464 }
465
466 if (status & WBCIR_IRQ_ERR) {
467 /* RX overflow? (read clears bit) */
468 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
469 data->rxstate = WBCIR_RXSTATE_ERROR;
470 ir_raw_event_reset(data->dev);
471 }
472
473 /* TX underflow? */
474 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
475 data->txstate = WBCIR_TXSTATE_ERROR;
476 }
477
478 if (status & WBCIR_IRQ_RX)
479 wbcir_irq_rx(data, device);
480
481 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
482 wbcir_irq_tx(data);
5b2e303f 483
5b2e303f 484 spin_unlock_irqrestore(&data->spinlock, flags);
e258b80e
DH		 485 return IRQ_HANDLED;
486}
487
c829f267
DH		 488/*****************************************************************************
489 *
490 * RC-CORE INTERFACE FUNCTIONS
491 *
492 *****************************************************************************/
493
494static int
495wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
496{
497 struct wbcir_data *data = dev->priv;
498 unsigned long flags;
499 u8 val;
500 u32 freq;
501
502 freq = DIV_ROUND_CLOSEST(carrier, 1000);
503 if (freq < 30 || freq > 60)
504 return -EINVAL;
505
506 switch (freq) {
507 case 58:
508 case 59:
509 case 60:
510 val = freq - 58;
511 freq *= 1000;
512 break;
513 case 57:
514 val = freq - 27;
515 freq = 56900;
516 break;
517 default:
518 val = freq - 27;
519 freq *= 1000;
520 break;
521 }
522
523 spin_lock_irqsave(&data->spinlock, flags);
524 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
525 spin_unlock_irqrestore(&data->spinlock, flags);
526 return -EBUSY;
527 }
528
529 if (data->txcarrier != freq) {
530 wbcir_select_bank(data, WBCIR_BANK_7);
531 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
532 data->txcarrier = freq;
533 }
534
535 spin_unlock_irqrestore(&data->spinlock, flags);
536 return 0;
537}
538
539static int
540wbcir_txmask(struct rc_dev *dev, u32 mask)
541{
542 struct wbcir_data *data = dev->priv;
543 unsigned long flags;
544 u8 val;
545
546 /* Four outputs, only one output can be enabled at a time */
547 switch (mask) {
548 case 0x1:
549 val = 0x0;
550 break;
551 case 0x2:
552 val = 0x1;
553 break;
554 case 0x4:
555 val = 0x2;
556 break;
557 case 0x8:
558 val = 0x3;
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 spin_lock_irqsave(&data->spinlock, flags);
565 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
566 spin_unlock_irqrestore(&data->spinlock, flags);
567 return -EBUSY;
568 }
569
570 if (data->txmask != mask) {
571 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
572 data->txmask = mask;
573 }
574
575 spin_unlock_irqrestore(&data->spinlock, flags);
576 return 0;
577}
578
579static int
5588dc2b 580wbcir_tx(struct rc_dev *dev, unsigned *buf, unsigned count)
c829f267
DH		 581{
582 struct wbcir_data *data = dev->priv;
c829f267
DH		 583 unsigned i;
584 unsigned long flags;
585
c829f267
DH		 586 /* Not sure if this is possible, but better safe than sorry */
587 spin_lock_irqsave(&data->spinlock, flags);
588 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
589 spin_unlock_irqrestore(&data->spinlock, flags);
590 return -EBUSY;
591 }
592
593 /* Convert values to multiples of 10us */
594 for (i = 0; i < count; i++)
595 buf[i] = DIV_ROUND_CLOSEST(buf[i], 10);
596
597 /* Fill the TX fifo once, the irq handler will do the rest */
598 data->txbuf = buf;
599 data->txlen = count;
600 data->txoff = 0;
601 wbcir_irq_tx(data);
602
603 /* Wait for the TX to complete */
604 while (data->txstate == WBCIR_TXSTATE_ACTIVE) {
605 spin_unlock_irqrestore(&data->spinlock, flags);
606 wait_event(data->txwaitq, data->txstate != WBCIR_TXSTATE_ACTIVE);
607 spin_lock_irqsave(&data->spinlock, flags);
608 }
609
610 /* We're done */
611 if (data->txstate == WBCIR_TXSTATE_ERROR)
612 count = -EAGAIN;
613 data->txstate = WBCIR_TXSTATE_INACTIVE;
614 data->txbuf = NULL;
615 spin_unlock_irqrestore(&data->spinlock, flags);
e258b80e 616
c829f267
DH		 617 return count;
618}
e258b80e
DH		 619
620/*****************************************************************************
621 *
197d4db7 622 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
e258b80e
DH		 623 *
624 *****************************************************************************/
625
626static void
627wbcir_shutdown(struct pnp_dev *device)
628{
629 struct device *dev = &device->dev;
630 struct wbcir_data *data = pnp_get_drvdata(device);
67cdd42e 631 bool do_wake = true;
e258b80e
DH		 632 u8 match[11];
633 u8 mask[11];
634 u8 rc6_csl = 0;
635 int i;
636
637 memset(match, 0, sizeof(match));
638 memset(mask, 0, sizeof(mask));
639
640 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
67cdd42e 641 do_wake = false;
e258b80e
DH		 642 goto finish;
643 }
644
645 switch (protocol) {
646 case IR_PROTOCOL_RC5:
647 if (wake_sc > 0xFFF) {
67cdd42e 648 do_wake = false;
e258b80e
DH		 649 dev_err(dev, "RC5 - Invalid wake scancode\n");
650 break;
651 }
652
653 /* Mask = 13 bits, ex toggle */
654 mask[0] = 0xFF;
655 mask[1] = 0x17;
656
657 match[0] = (wake_sc & 0x003F); /* 6 command bits */
658 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
659 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
660 if (!(wake_sc & 0x0040)) /* 2nd start bit */
661 match[1] |= 0x10;
662
663 break;
664
665 case IR_PROTOCOL_NEC:
666 if (wake_sc > 0xFFFFFF) {
67cdd42e 667 do_wake = false;
e258b80e
DH		 668 dev_err(dev, "NEC - Invalid wake scancode\n");
669 break;
670 }
671
672 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
673
674 match[1] = bitrev8((wake_sc & 0xFF));
675 match[0] = ~match[1];
676
677 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
678 if (wake_sc > 0xFFFF)
679 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
680 else
681 match[2] = ~match[3];
682
683 break;
684
685 case IR_PROTOCOL_RC6:
686
687 if (wake_rc6mode == 0) {
688 if (wake_sc > 0xFFFF) {
67cdd42e 689 do_wake = false;
e258b80e
DH		 690 dev_err(dev, "RC6 - Invalid wake scancode\n");
691 break;
692 }
693
694 /* Command */
695 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
696 mask[0] = 0xFF;
697 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
698 mask[1] = 0xFF;
699
700 /* Address */
701 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
702 mask[2] = 0xFF;
703 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
704 mask[3] = 0xFF;
705
706 /* Header */
707 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
708 mask[4] = 0xF0;
709 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
710 mask[5] = 0x0F;
711
712 rc6_csl = 44;
713
714 } else if (wake_rc6mode == 6) {
715 i = 0;
716
717 /* Command */
718 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
719 mask[i++] = 0xFF;
720 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
721 mask[i++] = 0xFF;
722
723 /* Address + Toggle */
724 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
725 mask[i++] = 0xFF;
726 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
727 mask[i++] = 0x3F;
728
729 /* Customer bits 7 - 0 */
730 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
731 mask[i++] = 0xFF;
732 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
733 mask[i++] = 0xFF;
734
735 if (wake_sc & 0x80000000) {
736 /* Customer range bit and bits 15 - 8 */
737 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
738 mask[i++] = 0xFF;
739 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
740 mask[i++] = 0xFF;
741 rc6_csl = 76;
742 } else if (wake_sc <= 0x007FFFFF) {
743 rc6_csl = 60;
744 } else {
67cdd42e 745 do_wake = false;
e258b80e
DH		 746 dev_err(dev, "RC6 - Invalid wake scancode\n");
747 break;
748 }
749
750 /* Header */
751 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
752 mask[i++] = 0xFF;
753 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
754 mask[i++] = 0x0F;
755
756 } else {
67cdd42e 757 do_wake = false;
e258b80e
DH		 758 dev_err(dev, "RC6 - Invalid wake mode\n");
759 }
760
761 break;
762
763 default:
67cdd42e 764 do_wake = false;
e258b80e
DH		 765 break;
766 }
767
768finish:
769 if (do_wake) {
770 /* Set compare and compare mask */
771 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
772 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
773 0x3F);
774 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
775 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
776 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
777 0x3F);
778 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
779
780 /* RC6 Compare String Len */
781 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
782
783 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
784 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
785
786 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
787 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
788
789 /* Set CEIR_EN */
790 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
791
792 } else {
793 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
794 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
795
796 /* Clear CEIR_EN */
797 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
798 }
799
197d4db7
DH		 800 /*
801 * ACPI will set the HW disable bit for SP3 which means that the
802 * output signals are left in an undefined state which may cause
803 * spurious interrupts which we need to ignore until the hardware
804 * is reinitialized.
805 */
c829f267 806 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
197d4db7 807 disable_irq(data->irq);
c829f267
DH		 808
809 /* Disable LED */
810 led_trigger_event(data->rxtrigger, LED_OFF);
811 led_trigger_event(data->txtrigger, LED_OFF);
e258b80e
DH		 812}
813
814static int
815wbcir_suspend(struct pnp_dev *device, pm_message_t state)
816{
817 wbcir_shutdown(device);
818 return 0;
819}
820
e258b80e 821static void
197d4db7 822wbcir_init_hw(struct wbcir_data *data)
e258b80e
DH		 823{
824 u8 tmp;
825
197d4db7 826 /* Disable interrupts */
c829f267 827 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
197d4db7 828
e258b80e
DH		 829 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
830 tmp = protocol << 4;
831 if (invert)
832 tmp |= 0x08;
833 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
834
835 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
836 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
837
838 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
839 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
840
841 /* Set RC5 cell time to correspond to 36 kHz */
842 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
843
844 /* Set IRTX_INV */
845 if (invert)
846 outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL);
847 else
848 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
849
850 /*
c829f267 851 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
e258b80e
DH		 852 * set SP3_IRRX_SW to binary 01, helpfully not documented
853 */
854 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
c829f267 855 data->txmask = 0x1;
197d4db7
DH		 856
857 /* Enable extended mode */
858 wbcir_select_bank(data, WBCIR_BANK_2);
859 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
860
861 /*
862 * Configure baud generator, IR data will be sampled at
863 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
864 *
865 * The ECIR registers include a flag to change the
866 * 24Mhz clock freq to 48Mhz.
867 *
868 * It's not documented in the specs, but fifo levels
869 * other than 16 seems to be unsupported.
870 */
871
872 /* prescaler 1.0, tx/rx fifo lvl 16 */
873 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
874
b87f2edd
DH		 875 /* Set baud divisor to sample every 10 us */
876 outb(0x0F, data->sbase + WBCIR_REG_SP3_BGDL);
197d4db7
DH		 877 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
878
879 /* Set CEIR mode */
880 wbcir_select_bank(data, WBCIR_BANK_0);
881 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
882 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
883 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
884
b87f2edd 885 /* Disable RX demod, enable run-length enc/dec, set freq span */
197d4db7 886 wbcir_select_bank(data, WBCIR_BANK_7);
b87f2edd 887 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
197d4db7
DH		 888
889 /* Disable timer */
890 wbcir_select_bank(data, WBCIR_BANK_4);
891 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
892
c829f267 893 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
197d4db7 894 wbcir_select_bank(data, WBCIR_BANK_5);
c829f267 895 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
197d4db7
DH		 896
897 /* Disable CRC */
898 wbcir_select_bank(data, WBCIR_BANK_6);
899 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
900
c829f267 901 /* Set RX demodulation freq, not really used */
197d4db7
DH		 902 wbcir_select_bank(data, WBCIR_BANK_7);
903 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
c829f267
DH		 904
905 /* Set TX modulation, 36kHz, 7us pulse width */
197d4db7 906 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
c829f267 907 data->txcarrier = 36000;
197d4db7
DH		 908
909 /* Set invert and pin direction */
910 if (invert)
911 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
912 else
913 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
914
915 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
916 wbcir_select_bank(data, WBCIR_BANK_0);
917 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
918
919 /* Clear AUX status bits */
920 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
921
c829f267
DH		 922 /* Clear RX state */
923 data->rxstate = WBCIR_RXSTATE_INACTIVE;
924 data->rxev.duration = 0;
5b2e303f
DH		 925 ir_raw_event_reset(data->dev);
926 ir_raw_event_handle(data->dev);
927
c829f267
DH		 928 /*
929 * Check TX state, if we did a suspend/resume cycle while TX was
930 * active, we will have a process waiting in txwaitq.
931 */
932 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
933 data->txstate = WBCIR_TXSTATE_ERROR;
934 wake_up(&data->txwaitq);
935 }
936
197d4db7 937 /* Enable interrupts */
c829f267 938 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
197d4db7
DH		 939}
940
941static int
942wbcir_resume(struct pnp_dev *device)
943{
944 struct wbcir_data *data = pnp_get_drvdata(device);
945
946 wbcir_init_hw(data);
947 enable_irq(data->irq);
948
949 return 0;
e258b80e
DH		 950}
951
952static int __devinit
953wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
954{
955 struct device *dev = &device->dev;
956 struct wbcir_data *data;
957 int err;
958
959 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
960 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
961 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
962 dev_err(dev, "Invalid resources\n");
963 return -ENODEV;
964 }
965
966 data = kzalloc(sizeof(*data), GFP_KERNEL);
967 if (!data) {
968 err = -ENOMEM;
969 goto exit;
970 }
971
972 pnp_set_drvdata(device, data);
973
5b2e303f 974 spin_lock_init(&data->spinlock);
c829f267 975 init_waitqueue_head(&data->txwaitq);
e258b80e
DH		 976 data->ebase = pnp_port_start(device, 0);
977 data->wbase = pnp_port_start(device, 1);
978 data->sbase = pnp_port_start(device, 2);
979 data->irq = pnp_irq(device, 0);
980
981 if (data->wbase == 0 || data->ebase == 0 ||
982 data->sbase == 0 || data->irq == 0) {
983 err = -ENODEV;
984 dev_err(dev, "Invalid resources\n");
985 goto exit_free_data;
986 }
987
988 dev_dbg(&device->dev, "Found device "
989 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
990 data->wbase, data->ebase, data->sbase, data->irq);
991
992 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
993 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
994 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
995 err = -EBUSY;
996 goto exit_free_data;
997 }
998
999 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1000 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1001 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1002 err = -EBUSY;
1003 goto exit_release_wbase;
1004 }
1005
1006 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1007 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1008 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1009 err = -EBUSY;
1010 goto exit_release_ebase;
1011 }
1012
1013 err = request_irq(data->irq, wbcir_irq_handler,
1014 IRQF_DISABLED, DRVNAME, device);
1015 if (err) {
1016 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1017 err = -EBUSY;
1018 goto exit_release_sbase;
1019 }
1020
1021 led_trigger_register_simple("cir-tx", &data->txtrigger);
1022 if (!data->txtrigger) {
1023 err = -ENOMEM;
1024 goto exit_free_irq;
1025 }
1026
1027 led_trigger_register_simple("cir-rx", &data->rxtrigger);
1028 if (!data->rxtrigger) {
1029 err = -ENOMEM;
1030 goto exit_unregister_txtrigger;
1031 }
1032
1033 data->led.name = "cir::activity";
1034 data->led.default_trigger = "cir-rx";
1035 data->led.brightness_set = wbcir_led_brightness_set;
1036 data->led.brightness_get = wbcir_led_brightness_get;
1037 err = led_classdev_register(&device->dev, &data->led);
1038 if (err)
1039 goto exit_unregister_rxtrigger;
1040
5b2e303f
DH		 1041 data->dev = rc_allocate_device();
1042 if (!data->dev) {
e258b80e
DH		 1043 err = -ENOMEM;
1044 goto exit_unregister_led;
1045 }
1046
5b2e303f
DH		 1047 data->dev->driver_name = WBCIR_NAME;
1048 data->dev->input_name = WBCIR_NAME;
1049 data->dev->input_phys = "wbcir/cir0";
1050 data->dev->input_id.bustype = BUS_HOST;
1051 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1052 data->dev->input_id.product = WBCIR_ID_FAMILY;
1053 data->dev->input_id.version = WBCIR_ID_CHIP;
c829f267 1054 data->dev->map_name = RC_MAP_RC6_MCE;
488ebc48 1055 data->dev->s_idle = wbcir_idle_rx;
c829f267
DH		 1056 data->dev->s_tx_mask = wbcir_txmask;
1057 data->dev->s_tx_carrier = wbcir_txcarrier;
1058 data->dev->tx_ir = wbcir_tx;
5b2e303f
DH		 1059 data->dev->priv = data;
1060 data->dev->dev.parent = &device->dev;
1061
1062 err = rc_register_device(data->dev);
e258b80e 1063 if (err)
5b2e303f 1064 goto exit_free_rc;
e258b80e
DH		 1065
1066 device_init_wakeup(&device->dev, 1);
1067
197d4db7 1068 wbcir_init_hw(data);
e258b80e
DH		 1069
1070 return 0;
1071
5b2e303f
DH		 1072exit_free_rc:
1073 rc_free_device(data->dev);
e258b80e
DH		 1074exit_unregister_led:
1075 led_classdev_unregister(&data->led);
1076exit_unregister_rxtrigger:
1077 led_trigger_unregister_simple(data->rxtrigger);
1078exit_unregister_txtrigger:
1079 led_trigger_unregister_simple(data->txtrigger);
1080exit_free_irq:
1081 free_irq(data->irq, device);
1082exit_release_sbase:
1083 release_region(data->sbase, SP_IOMEM_LEN);
1084exit_release_ebase:
1085 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1086exit_release_wbase:
1087 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1088exit_free_data:
1089 kfree(data);
1090 pnp_set_drvdata(device, NULL);
1091exit:
1092 return err;
1093}
1094
1095static void __devexit
1096wbcir_remove(struct pnp_dev *device)
1097{
1098 struct wbcir_data *data = pnp_get_drvdata(device);
e258b80e
DH		 1099
1100 /* Disable interrupts */
c829f267 1101 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
e258b80e
DH		 1102 free_irq(data->irq, device);
1103
1104 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1105 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1106
1107 /* Clear CEIR_EN */
1108 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1109
1110 /* Clear BUFF_EN, END_EN, MATCH_EN */
1111 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1112
5b2e303f 1113 rc_unregister_device(data->dev);
e258b80e
DH		 1114
1115 led_trigger_unregister_simple(data->rxtrigger);
1116 led_trigger_unregister_simple(data->txtrigger);
1117 led_classdev_unregister(&data->led);
1118
1119 /* This is ok since &data->led isn't actually used */
1120 wbcir_led_brightness_set(&data->led, LED_OFF);
1121
1122 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1123 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1124 release_region(data->sbase, SP_IOMEM_LEN);
1125
e258b80e
DH		 1126 kfree(data);
1127
1128 pnp_set_drvdata(device, NULL);
1129}
1130
1131static const struct pnp_device_id wbcir_ids[] = {
1132 { "WEC1022", 0 },
1133 { "", 0 }
1134};
1135MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1136
1137static struct pnp_driver wbcir_driver = {
1138 .name = WBCIR_NAME,
1139 .id_table = wbcir_ids,
1140 .probe = wbcir_probe,
1141 .remove = __devexit_p(wbcir_remove),
1142 .suspend = wbcir_suspend,
1143 .resume = wbcir_resume,
1144 .shutdown = wbcir_shutdown
1145};
1146
1147static int __init
1148wbcir_init(void)
1149{
1150 int ret;
1151
1152 switch (protocol) {
1153 case IR_PROTOCOL_RC5:
1154 case IR_PROTOCOL_NEC:
1155 case IR_PROTOCOL_RC6:
1156 break;
1157 default:
5b2e303f 1158 printk(KERN_ERR DRVNAME ": Invalid power-on protocol\n");
e258b80e
DH		 1159 }
1160
1161 ret = pnp_register_driver(&wbcir_driver);
1162 if (ret)
1163 printk(KERN_ERR DRVNAME ": Unable to register driver\n");
1164
1165 return ret;
1166}
1167
1168static void __exit
1169wbcir_exit(void)
1170{
1171 pnp_unregister_driver(&wbcir_driver);
1172}
1173
e258b80e
DH		 1174module_init(wbcir_init);
1175module_exit(wbcir_exit);
1176