projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] winbond-cir: increase IR receiver resolution
[deliverable/linux.git] / drivers / media / rc / winbond-cir.c
CommitLineData
e258b80e
DH		 1/*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
b87f2edd
DH		 9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
e258b80e 11 *
5b2e303f
DH		 12 * Dedicated to my daughter Matilda, without whose loving attention this
13 * driver would have been finished in half the time and with a fraction
e258b80e
DH		 14 * of the bugs.
15 *
16 * Written using:
17 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
18 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
19 * o DSDT dumps
20 *
21 * Supported features:
c829f267
DH		 22 * o IR Receive
23 * o IR Transmit
e258b80e
DH		 24 * o Wake-On-CIR functionality
25 *
26 * To do:
5b2e303f 27 * o Learning
e258b80e
DH		 28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
42 */
43
d8a10ac9
JP		 44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
e258b80e
DH		 46#include <linux/module.h>
47#include <linux/pnp.h>
48#include <linux/interrupt.h>
49#include <linux/timer.h>
e258b80e 50#include <linux/leds.h>
e258b80e
DH		 51#include <linux/spinlock.h>
52#include <linux/pci_ids.h>
53#include <linux/io.h>
54#include <linux/bitrev.h>
5a0e3ad6 55#include <linux/slab.h>
c829f267
DH		 56#include <linux/wait.h>
57#include <linux/sched.h>
6bda9644 58#include <media/rc-core.h>
e258b80e
DH		 59
60#define DRVNAME "winbond-cir"
61
62/* CEIR Wake-Up Registers, relative to data->wbase */
63#define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
64#define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
65#define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
66#define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
67#define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
68#define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
69#define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
70#define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
71#define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
72#define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
73
74/* CEIR Enhanced Functionality Registers, relative to data->ebase */
75#define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
76#define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
77#define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
78#define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
79#define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
80
81/* SP3 Banked Registers, relative to data->sbase */
82#define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
83 /* Bank 0 */
84#define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
85#define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
86#define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
87#define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
88#define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
89#define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
90#define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
91#define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
92#define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
93 /* Bank 2 */
94#define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
95#define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
96#define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
97#define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
98#define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
99#define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
100 /* Bank 3 */
101#define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
102#define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
103#define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
104 /* Bank 4 */
105#define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
106 /* Bank 5 */
107#define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
108 /* Bank 6 */
109#define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
5b2e303f 110#define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
e258b80e
DH		 111 /* Bank 7 */
112#define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
113#define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
114#define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
115#define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
116#define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
117
118/*
119 * Magic values follow
120 */
121
122/* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
123#define WBCIR_IRQ_NONE 0x00
124/* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
125#define WBCIR_IRQ_RX 0x01
c829f267
DH		 126/* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
127#define WBCIR_IRQ_TX_LOW 0x02
e258b80e
DH		 128/* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
129#define WBCIR_IRQ_ERR 0x04
c829f267
DH		 130/* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
131#define WBCIR_IRQ_TX_EMPTY 0x20
e258b80e
DH		 132/* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
133#define WBCIR_LED_ENABLE 0x80
134/* RX data available bit for WBCIR_REG_SP3_LSR */
135#define WBCIR_RX_AVAIL 0x01
c829f267
DH		 136/* RX data overrun error bit for WBCIR_REG_SP3_LSR */
137#define WBCIR_RX_OVERRUN 0x02
138/* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
139#define WBCIR_TX_EOT 0x04
e258b80e
DH		 140/* RX disable bit for WBCIR_REG_SP3_ASCR */
141#define WBCIR_RX_DISABLE 0x20
c829f267
DH		 142/* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
143#define WBCIR_TX_UNDERRUN 0x40
e258b80e
DH		 144/* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
145#define WBCIR_EXT_ENABLE 0x01
146/* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
147#define WBCIR_REGSEL_COMPARE 0x10
148/* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
149#define WBCIR_REGSEL_MASK 0x20
150/* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
151#define WBCIR_REG_ADDR0 0x00
152
153/* Valid banks for the SP3 UART */
154enum wbcir_bank {
155 WBCIR_BANK_0 = 0x00,
156 WBCIR_BANK_1 = 0x80,
157 WBCIR_BANK_2 = 0xE0,
158 WBCIR_BANK_3 = 0xE4,
159 WBCIR_BANK_4 = 0xE8,
160 WBCIR_BANK_5 = 0xEC,
161 WBCIR_BANK_6 = 0xF0,
162 WBCIR_BANK_7 = 0xF4,
163};
164
5b2e303f 165/* Supported power-on IR Protocols */
e258b80e
DH		 166enum wbcir_protocol {
167 IR_PROTOCOL_RC5 = 0x0,
168 IR_PROTOCOL_NEC = 0x1,
169 IR_PROTOCOL_RC6 = 0x2,
170};
171
c829f267
DH		 172/* Possible states for IR reception */
173enum wbcir_rxstate {
174 WBCIR_RXSTATE_INACTIVE = 0,
175 WBCIR_RXSTATE_ACTIVE,
176 WBCIR_RXSTATE_ERROR
177};
178
179/* Possible states for IR transmission */
180enum wbcir_txstate {
181 WBCIR_TXSTATE_INACTIVE = 0,
182 WBCIR_TXSTATE_ACTIVE,
c829f267
DH		 183 WBCIR_TXSTATE_ERROR
184};
185
e258b80e 186/* Misc */
a66cd0b6 187#define WBCIR_NAME "Winbond CIR"
e258b80e
DH		 188#define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
189#define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
e258b80e
DH		 190#define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
191#define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
192#define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
193#define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
e258b80e 194
5b2e303f 195/* Per-device data */
e258b80e 196struct wbcir_data {
5b2e303f 197 spinlock_t spinlock;
c829f267
DH		 198 struct rc_dev *dev;
199 struct led_classdev led;
5b2e303f 200
e258b80e
DH		 201 unsigned long wbase; /* Wake-Up Baseaddr */
202 unsigned long ebase; /* Enhanced Func. Baseaddr */
203 unsigned long sbase; /* Serial Port Baseaddr */
204 unsigned int irq; /* Serial Port IRQ */
c829f267 205 u8 irqmask;
e258b80e 206
c829f267
DH		 207 /* RX state */
208 enum wbcir_rxstate rxstate;
e258b80e 209 struct led_trigger *rxtrigger;
e258b80e 210
c829f267
DH		 211 /* TX state */
212 enum wbcir_txstate txstate;
213 struct led_trigger *txtrigger;
214 u32 txlen;
215 u32 txoff;
216 u32 *txbuf;
c829f267
DH		 217 u8 txmask;
218 u32 txcarrier;
e258b80e
DH		 219};
220
221static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
222module_param(protocol, uint, 0444);
5b2e303f 223MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
e258b80e
DH		 224 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
225
90ab5ee9 226static bool invert; /* default = 0 */
e258b80e
DH		 227module_param(invert, bool, 0444);
228MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
229
90ab5ee9 230static bool txandrx; /* default = 0 */
c829f267 231module_param(txandrx, bool, 0444);
57f4422f 232MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
c829f267 233
e258b80e
DH		 234static unsigned int wake_sc = 0x800F040C;
235module_param(wake_sc, uint, 0644);
236MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
237
238static unsigned int wake_rc6mode = 6;
239module_param(wake_rc6mode, uint, 0644);
240MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
241 "(0 = 0, 6 = 6A, default)");
242
243
244
245/*****************************************************************************
246 *
247 * UTILITY FUNCTIONS
248 *
249 *****************************************************************************/
250
251/* Caller needs to hold wbcir_lock */
252static void
253wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
254{
255 u8 val;
256
257 val = inb(addr);
258 val = ((val & ~mask) | (bits & mask));
259 outb(val, addr);
260}
261
262/* Selects the register bank for the serial port */
263static inline void
264wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
265{
266 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
267}
268
c829f267
DH		 269static inline void
270wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
271{
272 if (data->irqmask == irqmask)
273 return;
274
275 wbcir_select_bank(data, WBCIR_BANK_0);
276 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
277 data->irqmask = irqmask;
278}
279
e258b80e
DH		 280static enum led_brightness
281wbcir_led_brightness_get(struct led_classdev *led_cdev)
282{
283 struct wbcir_data *data = container_of(led_cdev,
284 struct wbcir_data,
285 led);
286
287 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
288 return LED_FULL;
289 else
290 return LED_OFF;
291}
292
293static void
294wbcir_led_brightness_set(struct led_classdev *led_cdev,
5b2e303f 295 enum led_brightness brightness)
e258b80e
DH		 296{
297 struct wbcir_data *data = container_of(led_cdev,
298 struct wbcir_data,
299 led);
300
301 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
302 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
303 WBCIR_LED_ENABLE);
304}
305
5b2e303f 306/* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
e258b80e
DH		 307static u8
308wbcir_to_rc6cells(u8 val)
309{
310 u8 coded = 0x00;
311 int i;
312
313 val &= 0x0F;
314 for (i = 0; i < 4; i++) {
315 if (val & 0x01)
316 coded |= 0x02 << (i * 2);
317 else
318 coded |= 0x01 << (i * 2);
319 val >>= 1;
320 }
321
322 return coded;
323}
324
e258b80e
DH		 325/*****************************************************************************
326 *
327 * INTERRUPT FUNCTIONS
328 *
329 *****************************************************************************/
330
c829f267 331static void
488ebc48 332wbcir_idle_rx(struct rc_dev *dev, bool idle)
e258b80e 333{
488ebc48 334 struct wbcir_data *data = dev->priv;
e258b80e 335
488ebc48 336 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
c829f267 337 data->rxstate = WBCIR_RXSTATE_ACTIVE;
5b2e303f
DH		 338 led_trigger_event(data->rxtrigger, LED_FULL);
339 }
340
e5eda7fa
SY		 341 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
342 data->rxstate = WBCIR_RXSTATE_INACTIVE;
343 led_trigger_event(data->rxtrigger, LED_OFF);
488ebc48
DH		 344 /* Tell hardware to go idle by setting RXINACTIVE */
345 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
e5eda7fa 346 }
488ebc48 347}
e258b80e 348
488ebc48
DH		 349static void
350wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
351{
352 u8 irdata;
353 DEFINE_IR_RAW_EVENT(rawir);
5b2e303f 354
488ebc48
DH		 355 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
356 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
357 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
c829f267 358 if (data->rxstate == WBCIR_RXSTATE_ERROR)
5b2e303f 359 continue;
488ebc48 360 rawir.pulse = irdata & 0x80 ? false : true;
c496e716 361 rawir.duration = US_TO_NS(((irdata & 0x7F) + 1) * 2);
488ebc48 362 ir_raw_event_store_with_filter(data->dev, &rawir);
e258b80e
DH		 363 }
364
5b2e303f 365 ir_raw_event_handle(data->dev);
c829f267
DH		 366}
367
368static void
369wbcir_irq_tx(struct wbcir_data *data)
370{
371 unsigned int space;
372 unsigned int used;
373 u8 bytes[16];
374 u8 byte;
375
376 if (!data->txbuf)
377 return;
378
379 switch (data->txstate) {
380 case WBCIR_TXSTATE_INACTIVE:
381 /* TX FIFO empty */
382 space = 16;
383 led_trigger_event(data->txtrigger, LED_FULL);
384 break;
385 case WBCIR_TXSTATE_ACTIVE:
386 /* TX FIFO low (3 bytes or less) */
387 space = 13;
388 break;
389 case WBCIR_TXSTATE_ERROR:
390 space = 0;
391 break;
392 default:
393 return;
394 }
395
396 /*
397 * TX data is run-length coded in bytes: YXXXXXXX
398 * Y = space (1) or pulse (0)
399 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
400 */
401 for (used = 0; used < space && data->txoff != data->txlen; used++) {
402 if (data->txbuf[data->txoff] == 0) {
403 data->txoff++;
404 continue;
405 }
406 byte = min((u32)0x80, data->txbuf[data->txoff]);
407 data->txbuf[data->txoff] -= byte;
408 byte--;
409 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
410 bytes[used] = byte;
411 }
412
413 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
414 data->txoff++;
415
416 if (used == 0) {
417 /* Finished */
418 if (data->txstate == WBCIR_TXSTATE_ERROR)
419 /* Clear TX underrun bit */
420 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
c829f267
DH		 421 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
422 led_trigger_event(data->txtrigger, LED_OFF);
7bfb5dc1
DH		 423 kfree(data->txbuf);
424 data->txbuf = NULL;
425 data->txstate = WBCIR_TXSTATE_INACTIVE;
c829f267
DH		 426 } else if (data->txoff == data->txlen) {
427 /* At the end of transmission, tell the hw before last byte */
428 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
429 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
430 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
431 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
432 WBCIR_IRQ_TX_EMPTY);
433 } else {
434 /* More data to follow... */
435 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
436 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
437 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
438 WBCIR_IRQ_TX_LOW);
439 data->txstate = WBCIR_TXSTATE_ACTIVE;
440 }
441 }
442}
443
444static irqreturn_t
445wbcir_irq_handler(int irqno, void *cookie)
446{
447 struct pnp_dev *device = cookie;
448 struct wbcir_data *data = pnp_get_drvdata(device);
449 unsigned long flags;
450 u8 status;
451
452 spin_lock_irqsave(&data->spinlock, flags);
453 wbcir_select_bank(data, WBCIR_BANK_0);
454 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
455 status &= data->irqmask;
456
457 if (!status) {
458 spin_unlock_irqrestore(&data->spinlock, flags);
459 return IRQ_NONE;
460 }
461
462 if (status & WBCIR_IRQ_ERR) {
463 /* RX overflow? (read clears bit) */
464 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
465 data->rxstate = WBCIR_RXSTATE_ERROR;
466 ir_raw_event_reset(data->dev);
467 }
468
469 /* TX underflow? */
470 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
471 data->txstate = WBCIR_TXSTATE_ERROR;
472 }
473
474 if (status & WBCIR_IRQ_RX)
475 wbcir_irq_rx(data, device);
476
477 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
478 wbcir_irq_tx(data);
5b2e303f 479
5b2e303f 480 spin_unlock_irqrestore(&data->spinlock, flags);
e258b80e
DH		 481 return IRQ_HANDLED;
482}
483
c829f267
DH		 484/*****************************************************************************
485 *
486 * RC-CORE INTERFACE FUNCTIONS
487 *
488 *****************************************************************************/
489
490static int
491wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
492{
493 struct wbcir_data *data = dev->priv;
494 unsigned long flags;
495 u8 val;
496 u32 freq;
497
498 freq = DIV_ROUND_CLOSEST(carrier, 1000);
499 if (freq < 30 || freq > 60)
500 return -EINVAL;
501
502 switch (freq) {
503 case 58:
504 case 59:
505 case 60:
506 val = freq - 58;
507 freq *= 1000;
508 break;
509 case 57:
510 val = freq - 27;
511 freq = 56900;
512 break;
513 default:
514 val = freq - 27;
515 freq *= 1000;
516 break;
517 }
518
519 spin_lock_irqsave(&data->spinlock, flags);
520 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
521 spin_unlock_irqrestore(&data->spinlock, flags);
522 return -EBUSY;
523 }
524
525 if (data->txcarrier != freq) {
526 wbcir_select_bank(data, WBCIR_BANK_7);
527 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
528 data->txcarrier = freq;
529 }
530
531 spin_unlock_irqrestore(&data->spinlock, flags);
532 return 0;
533}
534
535static int
536wbcir_txmask(struct rc_dev *dev, u32 mask)
537{
538 struct wbcir_data *data = dev->priv;
539 unsigned long flags;
540 u8 val;
541
542 /* Four outputs, only one output can be enabled at a time */
543 switch (mask) {
544 case 0x1:
545 val = 0x0;
546 break;
547 case 0x2:
548 val = 0x1;
549 break;
550 case 0x4:
551 val = 0x2;
552 break;
553 case 0x8:
554 val = 0x3;
555 break;
556 default:
557 return -EINVAL;
558 }
559
560 spin_lock_irqsave(&data->spinlock, flags);
561 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
562 spin_unlock_irqrestore(&data->spinlock, flags);
563 return -EBUSY;
564 }
565
566 if (data->txmask != mask) {
567 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
568 data->txmask = mask;
569 }
570
571 spin_unlock_irqrestore(&data->spinlock, flags);
572 return 0;
573}
574
575static int
7bfb5dc1 576wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
c829f267
DH		 577{
578 struct wbcir_data *data = dev->priv;
7bfb5dc1 579 unsigned *buf;
c829f267
DH		 580 unsigned i;
581 unsigned long flags;
582
7bfb5dc1
DH		 583 buf = kmalloc(count * sizeof(*b), GFP_KERNEL);
584 if (!buf)
585 return -ENOMEM;
586
587 /* Convert values to multiples of 10us */
588 for (i = 0; i < count; i++)
589 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
590
c829f267
DH		 591 /* Not sure if this is possible, but better safe than sorry */
592 spin_lock_irqsave(&data->spinlock, flags);
593 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
594 spin_unlock_irqrestore(&data->spinlock, flags);
7bfb5dc1 595 kfree(buf);
c829f267
DH		 596 return -EBUSY;
597 }
598
c829f267
DH		 599 /* Fill the TX fifo once, the irq handler will do the rest */
600 data->txbuf = buf;
601 data->txlen = count;
602 data->txoff = 0;
603 wbcir_irq_tx(data);
604
c829f267 605 /* We're done */
c829f267 606 spin_unlock_irqrestore(&data->spinlock, flags);
c829f267
DH		 607 return count;
608}
e258b80e
DH		 609
610/*****************************************************************************
611 *
197d4db7 612 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
e258b80e
DH		 613 *
614 *****************************************************************************/
615
616static void
617wbcir_shutdown(struct pnp_dev *device)
618{
619 struct device *dev = &device->dev;
620 struct wbcir_data *data = pnp_get_drvdata(device);
67cdd42e 621 bool do_wake = true;
e258b80e
DH		 622 u8 match[11];
623 u8 mask[11];
624 u8 rc6_csl = 0;
625 int i;
626
627 memset(match, 0, sizeof(match));
628 memset(mask, 0, sizeof(mask));
629
630 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
67cdd42e 631 do_wake = false;
e258b80e
DH		 632 goto finish;
633 }
634
635 switch (protocol) {
636 case IR_PROTOCOL_RC5:
637 if (wake_sc > 0xFFF) {
67cdd42e 638 do_wake = false;
e258b80e
DH		 639 dev_err(dev, "RC5 - Invalid wake scancode\n");
640 break;
641 }
642
643 /* Mask = 13 bits, ex toggle */
644 mask[0] = 0xFF;
645 mask[1] = 0x17;
646
647 match[0] = (wake_sc & 0x003F); /* 6 command bits */
648 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
649 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
650 if (!(wake_sc & 0x0040)) /* 2nd start bit */
651 match[1] |= 0x10;
652
653 break;
654
655 case IR_PROTOCOL_NEC:
656 if (wake_sc > 0xFFFFFF) {
67cdd42e 657 do_wake = false;
e258b80e
DH		 658 dev_err(dev, "NEC - Invalid wake scancode\n");
659 break;
660 }
661
662 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
663
664 match[1] = bitrev8((wake_sc & 0xFF));
665 match[0] = ~match[1];
666
667 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
668 if (wake_sc > 0xFFFF)
669 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
670 else
671 match[2] = ~match[3];
672
673 break;
674
675 case IR_PROTOCOL_RC6:
676
677 if (wake_rc6mode == 0) {
678 if (wake_sc > 0xFFFF) {
67cdd42e 679 do_wake = false;
e258b80e
DH		 680 dev_err(dev, "RC6 - Invalid wake scancode\n");
681 break;
682 }
683
684 /* Command */
685 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
686 mask[0] = 0xFF;
687 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
688 mask[1] = 0xFF;
689
690 /* Address */
691 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
692 mask[2] = 0xFF;
693 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
694 mask[3] = 0xFF;
695
696 /* Header */
697 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
698 mask[4] = 0xF0;
699 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
700 mask[5] = 0x0F;
701
702 rc6_csl = 44;
703
704 } else if (wake_rc6mode == 6) {
705 i = 0;
706
707 /* Command */
708 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
709 mask[i++] = 0xFF;
710 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
711 mask[i++] = 0xFF;
712
713 /* Address + Toggle */
714 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
715 mask[i++] = 0xFF;
716 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
717 mask[i++] = 0x3F;
718
719 /* Customer bits 7 - 0 */
720 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
721 mask[i++] = 0xFF;
722 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
723 mask[i++] = 0xFF;
724
725 if (wake_sc & 0x80000000) {
726 /* Customer range bit and bits 15 - 8 */
727 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
728 mask[i++] = 0xFF;
729 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
730 mask[i++] = 0xFF;
731 rc6_csl = 76;
732 } else if (wake_sc <= 0x007FFFFF) {
733 rc6_csl = 60;
734 } else {
67cdd42e 735 do_wake = false;
e258b80e
DH		 736 dev_err(dev, "RC6 - Invalid wake scancode\n");
737 break;
738 }
739
740 /* Header */
741 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
742 mask[i++] = 0xFF;
743 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
744 mask[i++] = 0x0F;
745
746 } else {
67cdd42e 747 do_wake = false;
e258b80e
DH		 748 dev_err(dev, "RC6 - Invalid wake mode\n");
749 }
750
751 break;
752
753 default:
67cdd42e 754 do_wake = false;
e258b80e
DH		 755 break;
756 }
757
758finish:
759 if (do_wake) {
760 /* Set compare and compare mask */
761 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
762 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
763 0x3F);
764 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
765 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
766 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
767 0x3F);
768 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
769
770 /* RC6 Compare String Len */
771 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
772
773 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
774 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
775
776 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
777 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
778
779 /* Set CEIR_EN */
780 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
781
782 } else {
783 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
784 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
785
786 /* Clear CEIR_EN */
787 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
788 }
789
197d4db7
DH		 790 /*
791 * ACPI will set the HW disable bit for SP3 which means that the
792 * output signals are left in an undefined state which may cause
793 * spurious interrupts which we need to ignore until the hardware
794 * is reinitialized.
795 */
c829f267 796 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
197d4db7 797 disable_irq(data->irq);
c829f267
DH		 798
799 /* Disable LED */
800 led_trigger_event(data->rxtrigger, LED_OFF);
801 led_trigger_event(data->txtrigger, LED_OFF);
e258b80e
DH		 802}
803
804static int
805wbcir_suspend(struct pnp_dev *device, pm_message_t state)
806{
807 wbcir_shutdown(device);
808 return 0;
809}
810
e258b80e 811static void
197d4db7 812wbcir_init_hw(struct wbcir_data *data)
e258b80e
DH		 813{
814 u8 tmp;
815
197d4db7 816 /* Disable interrupts */
c829f267 817 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
197d4db7 818
e258b80e
DH		 819 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
820 tmp = protocol << 4;
821 if (invert)
822 tmp |= 0x08;
823 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
824
825 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
826 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
827
828 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
829 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
830
831 /* Set RC5 cell time to correspond to 36 kHz */
832 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
833
834 /* Set IRTX_INV */
835 if (invert)
836 outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL);
837 else
838 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
839
840 /*
c829f267 841 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
e258b80e
DH		 842 * set SP3_IRRX_SW to binary 01, helpfully not documented
843 */
844 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
c829f267 845 data->txmask = 0x1;
197d4db7
DH		 846
847 /* Enable extended mode */
848 wbcir_select_bank(data, WBCIR_BANK_2);
849 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
850
851 /*
852 * Configure baud generator, IR data will be sampled at
853 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
854 *
855 * The ECIR registers include a flag to change the
856 * 24Mhz clock freq to 48Mhz.
857 *
858 * It's not documented in the specs, but fifo levels
859 * other than 16 seems to be unsupported.
860 */
861
862 /* prescaler 1.0, tx/rx fifo lvl 16 */
863 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
864
c496e716
SY		 865 /* Set baud divisor to sample every 2 ns */
866 outb(0x03, data->sbase + WBCIR_REG_SP3_BGDL);
197d4db7
DH		 867 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
868
869 /* Set CEIR mode */
870 wbcir_select_bank(data, WBCIR_BANK_0);
871 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
872 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
873 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
874
c496e716
SY		 875 /*
876 * Disable RX demod, enable run-length enc/dec, set freq span and
877 * enable over-sampling
878 */
197d4db7 879 wbcir_select_bank(data, WBCIR_BANK_7);
c496e716 880 outb(0xd0, data->sbase + WBCIR_REG_SP3_RCCFG);
197d4db7
DH		 881
882 /* Disable timer */
883 wbcir_select_bank(data, WBCIR_BANK_4);
884 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
885
c829f267 886 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
197d4db7 887 wbcir_select_bank(data, WBCIR_BANK_5);
c829f267 888 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
197d4db7
DH		 889
890 /* Disable CRC */
891 wbcir_select_bank(data, WBCIR_BANK_6);
892 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
893
c829f267 894 /* Set RX demodulation freq, not really used */
197d4db7
DH		 895 wbcir_select_bank(data, WBCIR_BANK_7);
896 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
c829f267
DH		 897
898 /* Set TX modulation, 36kHz, 7us pulse width */
197d4db7 899 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
c829f267 900 data->txcarrier = 36000;
197d4db7
DH		 901
902 /* Set invert and pin direction */
903 if (invert)
904 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
905 else
906 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
907
908 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
909 wbcir_select_bank(data, WBCIR_BANK_0);
910 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
911
912 /* Clear AUX status bits */
913 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
914
c829f267
DH		 915 /* Clear RX state */
916 data->rxstate = WBCIR_RXSTATE_INACTIVE;
5b2e303f 917 ir_raw_event_reset(data->dev);
e5eda7fa 918 ir_raw_event_set_idle(data->dev, true);
5b2e303f 919
7bfb5dc1 920 /* Clear TX state */
c829f267 921 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
7bfb5dc1
DH		 922 kfree(data->txbuf);
923 data->txbuf = NULL;
924 data->txstate = WBCIR_TXSTATE_INACTIVE;
c829f267
DH		 925 }
926
197d4db7 927 /* Enable interrupts */
c829f267 928 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
197d4db7
DH		 929}
930
931static int
932wbcir_resume(struct pnp_dev *device)
933{
934 struct wbcir_data *data = pnp_get_drvdata(device);
935
936 wbcir_init_hw(data);
937 enable_irq(data->irq);
938
939 return 0;
e258b80e
DH		 940}
941
942static int __devinit
943wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
944{
945 struct device *dev = &device->dev;
946 struct wbcir_data *data;
947 int err;
948
949 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
950 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
951 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
952 dev_err(dev, "Invalid resources\n");
953 return -ENODEV;
954 }
955
956 data = kzalloc(sizeof(*data), GFP_KERNEL);
957 if (!data) {
958 err = -ENOMEM;
959 goto exit;
960 }
961
962 pnp_set_drvdata(device, data);
963
5b2e303f 964 spin_lock_init(&data->spinlock);
e258b80e
DH		 965 data->ebase = pnp_port_start(device, 0);
966 data->wbase = pnp_port_start(device, 1);
967 data->sbase = pnp_port_start(device, 2);
968 data->irq = pnp_irq(device, 0);
969
970 if (data->wbase == 0 || data->ebase == 0 ||
971 data->sbase == 0 || data->irq == 0) {
972 err = -ENODEV;
973 dev_err(dev, "Invalid resources\n");
974 goto exit_free_data;
975 }
976
977 dev_dbg(&device->dev, "Found device "
978 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
979 data->wbase, data->ebase, data->sbase, data->irq);
980
e258b80e
DH		 981 led_trigger_register_simple("cir-tx", &data->txtrigger);
982 if (!data->txtrigger) {
983 err = -ENOMEM;
9ef449c6 984 goto exit_free_data;
e258b80e
DH		 985 }
986
987 led_trigger_register_simple("cir-rx", &data->rxtrigger);
988 if (!data->rxtrigger) {
989 err = -ENOMEM;
990 goto exit_unregister_txtrigger;
991 }
992
993 data->led.name = "cir::activity";
994 data->led.default_trigger = "cir-rx";
995 data->led.brightness_set = wbcir_led_brightness_set;
996 data->led.brightness_get = wbcir_led_brightness_get;
997 err = led_classdev_register(&device->dev, &data->led);
998 if (err)
999 goto exit_unregister_rxtrigger;
1000
5b2e303f
DH		 1001 data->dev = rc_allocate_device();
1002 if (!data->dev) {
e258b80e
DH		 1003 err = -ENOMEM;
1004 goto exit_unregister_led;
1005 }
1006
d9b78695 1007 data->dev->driver_type = RC_DRIVER_IR_RAW;
a66cd0b6 1008 data->dev->driver_name = DRVNAME;
5b2e303f
DH		 1009 data->dev->input_name = WBCIR_NAME;
1010 data->dev->input_phys = "wbcir/cir0";
1011 data->dev->input_id.bustype = BUS_HOST;
1012 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1013 data->dev->input_id.product = WBCIR_ID_FAMILY;
1014 data->dev->input_id.version = WBCIR_ID_CHIP;
c829f267 1015 data->dev->map_name = RC_MAP_RC6_MCE;
488ebc48 1016 data->dev->s_idle = wbcir_idle_rx;
c829f267
DH		 1017 data->dev->s_tx_mask = wbcir_txmask;
1018 data->dev->s_tx_carrier = wbcir_txcarrier;
1019 data->dev->tx_ir = wbcir_tx;
5b2e303f
DH		 1020 data->dev->priv = data;
1021 data->dev->dev.parent = &device->dev;
8299d628 1022 data->dev->timeout = MS_TO_NS(100);
c496e716 1023 data->dev->rx_resolution = US_TO_NS(2);
c003ab1b 1024 data->dev->allowed_protos = RC_BIT_ALL;
5b2e303f 1025
9ef449c6
LH		 1026 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1027 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1028 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1029 err = -EBUSY;
1030 goto exit_free_rc;
1031 }
1032
1033 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1034 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1035 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1036 err = -EBUSY;
1037 goto exit_release_wbase;
1038 }
1039
1040 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1041 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1042 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1043 err = -EBUSY;
1044 goto exit_release_ebase;
1045 }
1046
1047 err = request_irq(data->irq, wbcir_irq_handler,
1048 IRQF_DISABLED, DRVNAME, device);
1049 if (err) {
1050 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1051 err = -EBUSY;
1052 goto exit_release_sbase;
1053 }
1054
5b2e303f 1055 err = rc_register_device(data->dev);
e258b80e 1056 if (err)
9ef449c6 1057 goto exit_free_irq;
e258b80e
DH		 1058
1059 device_init_wakeup(&device->dev, 1);
1060
197d4db7 1061 wbcir_init_hw(data);
e258b80e
DH		 1062
1063 return 0;
1064
e258b80e
DH		 1065exit_free_irq:
1066 free_irq(data->irq, device);
1067exit_release_sbase:
1068 release_region(data->sbase, SP_IOMEM_LEN);
1069exit_release_ebase:
1070 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1071exit_release_wbase:
1072 release_region(data->wbase, WAKEUP_IOMEM_LEN);
9ef449c6
LH		 1073exit_free_rc:
1074 rc_free_device(data->dev);
1075exit_unregister_led:
1076 led_classdev_unregister(&data->led);
1077exit_unregister_rxtrigger:
1078 led_trigger_unregister_simple(data->rxtrigger);
1079exit_unregister_txtrigger:
1080 led_trigger_unregister_simple(data->txtrigger);
e258b80e
DH		 1081exit_free_data:
1082 kfree(data);
1083 pnp_set_drvdata(device, NULL);
1084exit:
1085 return err;
1086}
1087
1088static void __devexit
1089wbcir_remove(struct pnp_dev *device)
1090{
1091 struct wbcir_data *data = pnp_get_drvdata(device);
e258b80e
DH		 1092
1093 /* Disable interrupts */
c829f267 1094 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
e258b80e
DH		 1095 free_irq(data->irq, device);
1096
1097 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1098 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1099
1100 /* Clear CEIR_EN */
1101 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1102
1103 /* Clear BUFF_EN, END_EN, MATCH_EN */
1104 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1105
5b2e303f 1106 rc_unregister_device(data->dev);
e258b80e
DH		 1107
1108 led_trigger_unregister_simple(data->rxtrigger);
1109 led_trigger_unregister_simple(data->txtrigger);
1110 led_classdev_unregister(&data->led);
1111
1112 /* This is ok since &data->led isn't actually used */
1113 wbcir_led_brightness_set(&data->led, LED_OFF);
1114
1115 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1116 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1117 release_region(data->sbase, SP_IOMEM_LEN);
1118
e258b80e
DH		 1119 kfree(data);
1120
1121 pnp_set_drvdata(device, NULL);
1122}
1123
1124static const struct pnp_device_id wbcir_ids[] = {
1125 { "WEC1022", 0 },
1126 { "", 0 }
1127};
1128MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1129
1130static struct pnp_driver wbcir_driver = {
1131 .name = WBCIR_NAME,
1132 .id_table = wbcir_ids,
1133 .probe = wbcir_probe,
1134 .remove = __devexit_p(wbcir_remove),
1135 .suspend = wbcir_suspend,
1136 .resume = wbcir_resume,
1137 .shutdown = wbcir_shutdown
1138};
1139
1140static int __init
1141wbcir_init(void)
1142{
1143 int ret;
1144
1145 switch (protocol) {
1146 case IR_PROTOCOL_RC5:
1147 case IR_PROTOCOL_NEC:
1148 case IR_PROTOCOL_RC6:
1149 break;
1150 default:
d8a10ac9 1151 pr_err("Invalid power-on protocol\n");
e258b80e
DH		 1152 }
1153
1154 ret = pnp_register_driver(&wbcir_driver);
1155 if (ret)
d8a10ac9 1156 pr_err("Unable to register driver\n");
e258b80e
DH		 1157
1158 return ret;
1159}
1160
1161static void __exit
1162wbcir_exit(void)
1163{
1164 pnp_unregister_driver(&wbcir_driver);
1165}
1166
e258b80e
DH		 1167module_init(wbcir_init);
1168module_exit(wbcir_exit);
1169
d36b6910 1170MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
5b2e303f
DH		 1171MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1172MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.296448 seconds and 5 git commands to generate.