Commit | Line | Data |
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ed85adaa AP |
1 | /* |
2 | * Elonics E4000 silicon tuner driver | |
3 | * | |
4 | * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | #include "e4000_priv.h" | |
22 | ||
c7861bb0 | 23 | static int e4000_init(struct e4000_dev *dev) |
ed85adaa | 24 | { |
f8b9b871 | 25 | struct i2c_client *client = dev->client; |
ed85adaa AP |
26 | int ret; |
27 | ||
f8b9b871 | 28 | dev_dbg(&client->dev, "\n"); |
ed85adaa AP |
29 | |
30 | /* reset */ | |
f8b9b871 | 31 | ret = regmap_write(dev->regmap, 0x00, 0x01); |
c5f51b15 | 32 | if (ret) |
ed85adaa AP |
33 | goto err; |
34 | ||
35 | /* disable output clock */ | |
f8b9b871 | 36 | ret = regmap_write(dev->regmap, 0x06, 0x00); |
c5f51b15 | 37 | if (ret) |
ed85adaa AP |
38 | goto err; |
39 | ||
f8b9b871 | 40 | ret = regmap_write(dev->regmap, 0x7a, 0x96); |
c5f51b15 | 41 | if (ret) |
ed85adaa AP |
42 | goto err; |
43 | ||
44 | /* configure gains */ | |
f8b9b871 | 45 | ret = regmap_bulk_write(dev->regmap, 0x7e, "\x01\xfe", 2); |
c5f51b15 | 46 | if (ret) |
ed85adaa AP |
47 | goto err; |
48 | ||
f8b9b871 | 49 | ret = regmap_write(dev->regmap, 0x82, 0x00); |
c5f51b15 | 50 | if (ret) |
ed85adaa AP |
51 | goto err; |
52 | ||
f8b9b871 | 53 | ret = regmap_write(dev->regmap, 0x24, 0x05); |
c5f51b15 | 54 | if (ret) |
ed85adaa AP |
55 | goto err; |
56 | ||
f8b9b871 | 57 | ret = regmap_bulk_write(dev->regmap, 0x87, "\x20\x01", 2); |
c5f51b15 | 58 | if (ret) |
ed85adaa AP |
59 | goto err; |
60 | ||
f8b9b871 | 61 | ret = regmap_bulk_write(dev->regmap, 0x9f, "\x7f\x07", 2); |
c5f51b15 | 62 | if (ret) |
ed85adaa AP |
63 | goto err; |
64 | ||
ed85adaa | 65 | /* DC offset control */ |
f8b9b871 | 66 | ret = regmap_write(dev->regmap, 0x2d, 0x1f); |
c5f51b15 | 67 | if (ret) |
85146114 AP |
68 | goto err; |
69 | ||
f8b9b871 | 70 | ret = regmap_bulk_write(dev->regmap, 0x70, "\x01\x01", 2); |
c5f51b15 | 71 | if (ret) |
ed85adaa AP |
72 | goto err; |
73 | ||
74 | /* gain control */ | |
f8b9b871 | 75 | ret = regmap_write(dev->regmap, 0x1a, 0x17); |
c5f51b15 | 76 | if (ret) |
ed85adaa AP |
77 | goto err; |
78 | ||
f8b9b871 | 79 | ret = regmap_write(dev->regmap, 0x1f, 0x1a); |
c5f51b15 | 80 | if (ret) |
ed85adaa AP |
81 | goto err; |
82 | ||
f8b9b871 | 83 | dev->active = true; |
ed85adaa | 84 | |
f8b9b871 AP |
85 | return 0; |
86 | err: | |
87 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
ed85adaa AP |
88 | return ret; |
89 | } | |
90 | ||
c7861bb0 | 91 | static int e4000_sleep(struct e4000_dev *dev) |
ed85adaa | 92 | { |
f8b9b871 | 93 | struct i2c_client *client = dev->client; |
ed85adaa AP |
94 | int ret; |
95 | ||
f8b9b871 | 96 | dev_dbg(&client->dev, "\n"); |
ed85adaa | 97 | |
f8b9b871 | 98 | dev->active = false; |
ecfb7ca3 | 99 | |
f8b9b871 | 100 | ret = regmap_write(dev->regmap, 0x00, 0x00); |
c5f51b15 | 101 | if (ret) |
ed85adaa | 102 | goto err; |
ed85adaa | 103 | |
f8b9b871 AP |
104 | return 0; |
105 | err: | |
106 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
ed85adaa AP |
107 | return ret; |
108 | } | |
109 | ||
c7861bb0 | 110 | static int e4000_set_params(struct e4000_dev *dev) |
ed85adaa | 111 | { |
f8b9b871 | 112 | struct i2c_client *client = dev->client; |
0e3a71c3 AP |
113 | int ret, i; |
114 | unsigned int div_n, k, k_cw, div_out; | |
0ed0b22d | 115 | u64 f_vco; |
85146114 | 116 | u8 buf[5], i_data[4], q_data[4]; |
ed85adaa | 117 | |
c7861bb0 AP |
118 | if (!dev->active) { |
119 | dev_dbg(&client->dev, "tuner is sleeping\n"); | |
120 | return 0; | |
121 | } | |
ed85adaa | 122 | |
ed85adaa | 123 | /* gain control manual */ |
f8b9b871 | 124 | ret = regmap_write(dev->regmap, 0x1a, 0x00); |
c5f51b15 | 125 | if (ret) |
ed85adaa AP |
126 | goto err; |
127 | ||
0e3a71c3 AP |
128 | /* |
129 | * Fractional-N synthesizer | |
130 | * | |
131 | * +----------------------------+ | |
132 | * v | | |
133 | * Fref +----+ +-------+ +------+ +---+ | |
134 | * ------> | PD | --> | VCO | ------> | /N.F | <-- | K | | |
135 | * +----+ +-------+ +------+ +---+ | |
136 | * | | |
137 | * | | |
138 | * v | |
139 | * +-------+ Fout | |
140 | * | /Rout | ------> | |
141 | * +-------+ | |
142 | */ | |
ed85adaa | 143 | for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) { |
c7861bb0 | 144 | if (dev->f_frequency <= e4000_pll_lut[i].freq) |
ed85adaa AP |
145 | break; |
146 | } | |
58f087c9 JL |
147 | if (i == ARRAY_SIZE(e4000_pll_lut)) { |
148 | ret = -EINVAL; | |
ed85adaa | 149 | goto err; |
58f087c9 | 150 | } |
ed85adaa | 151 | |
f8b9b871 | 152 | #define F_REF dev->clk |
0e3a71c3 | 153 | div_out = e4000_pll_lut[i].div_out; |
c7861bb0 | 154 | f_vco = (u64) dev->f_frequency * div_out; |
0e3a71c3 AP |
155 | /* calculate PLL integer and fractional control word */ |
156 | div_n = div_u64_rem(f_vco, F_REF, &k); | |
157 | k_cw = div_u64((u64) k * 0x10000, F_REF); | |
ed85adaa | 158 | |
f8b9b871 | 159 | dev_dbg(&client->dev, |
c7861bb0 AP |
160 | "frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n", |
161 | dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k, | |
162 | k_cw, div_out); | |
ed85adaa | 163 | |
0e3a71c3 AP |
164 | buf[0] = div_n; |
165 | buf[1] = (k_cw >> 0) & 0xff; | |
166 | buf[2] = (k_cw >> 8) & 0xff; | |
167 | buf[3] = 0x00; | |
168 | buf[4] = e4000_pll_lut[i].div_out_reg; | |
f8b9b871 | 169 | ret = regmap_bulk_write(dev->regmap, 0x09, buf, 5); |
c5f51b15 | 170 | if (ret) |
ed85adaa AP |
171 | goto err; |
172 | ||
173 | /* LNA filter (RF filter) */ | |
174 | for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) { | |
c7861bb0 | 175 | if (dev->f_frequency <= e400_lna_filter_lut[i].freq) |
ed85adaa AP |
176 | break; |
177 | } | |
58f087c9 JL |
178 | if (i == ARRAY_SIZE(e400_lna_filter_lut)) { |
179 | ret = -EINVAL; | |
ed85adaa | 180 | goto err; |
58f087c9 | 181 | } |
ed85adaa | 182 | |
f8b9b871 | 183 | ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val); |
c5f51b15 | 184 | if (ret) |
ed85adaa AP |
185 | goto err; |
186 | ||
187 | /* IF filters */ | |
188 | for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) { | |
c7861bb0 | 189 | if (dev->f_bandwidth <= e4000_if_filter_lut[i].freq) |
ed85adaa AP |
190 | break; |
191 | } | |
58f087c9 JL |
192 | if (i == ARRAY_SIZE(e4000_if_filter_lut)) { |
193 | ret = -EINVAL; | |
ed85adaa | 194 | goto err; |
58f087c9 | 195 | } |
ed85adaa AP |
196 | |
197 | buf[0] = e4000_if_filter_lut[i].reg11_val; | |
198 | buf[1] = e4000_if_filter_lut[i].reg12_val; | |
199 | ||
f8b9b871 | 200 | ret = regmap_bulk_write(dev->regmap, 0x11, buf, 2); |
c5f51b15 | 201 | if (ret) |
ed85adaa AP |
202 | goto err; |
203 | ||
204 | /* frequency band */ | |
205 | for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) { | |
c7861bb0 | 206 | if (dev->f_frequency <= e4000_band_lut[i].freq) |
ed85adaa AP |
207 | break; |
208 | } | |
58f087c9 JL |
209 | if (i == ARRAY_SIZE(e4000_band_lut)) { |
210 | ret = -EINVAL; | |
ed85adaa | 211 | goto err; |
58f087c9 | 212 | } |
ed85adaa | 213 | |
f8b9b871 | 214 | ret = regmap_write(dev->regmap, 0x07, e4000_band_lut[i].reg07_val); |
c5f51b15 | 215 | if (ret) |
ed85adaa AP |
216 | goto err; |
217 | ||
f8b9b871 | 218 | ret = regmap_write(dev->regmap, 0x78, e4000_band_lut[i].reg78_val); |
c5f51b15 | 219 | if (ret) |
ed85adaa AP |
220 | goto err; |
221 | ||
85146114 AP |
222 | /* DC offset */ |
223 | for (i = 0; i < 4; i++) { | |
224 | if (i == 0) | |
f8b9b871 | 225 | ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7e\x24", 3); |
85146114 | 226 | else if (i == 1) |
f8b9b871 | 227 | ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7f", 2); |
85146114 | 228 | else if (i == 2) |
f8b9b871 | 229 | ret = regmap_bulk_write(dev->regmap, 0x15, "\x01", 1); |
85146114 | 230 | else |
f8b9b871 | 231 | ret = regmap_bulk_write(dev->regmap, 0x16, "\x7e", 1); |
85146114 | 232 | |
c5f51b15 | 233 | if (ret) |
85146114 AP |
234 | goto err; |
235 | ||
f8b9b871 | 236 | ret = regmap_write(dev->regmap, 0x29, 0x01); |
c5f51b15 | 237 | if (ret) |
85146114 AP |
238 | goto err; |
239 | ||
f8b9b871 | 240 | ret = regmap_bulk_read(dev->regmap, 0x2a, buf, 3); |
c5f51b15 | 241 | if (ret) |
85146114 AP |
242 | goto err; |
243 | ||
244 | i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f); | |
245 | q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f); | |
246 | } | |
247 | ||
d4992da3 AP |
248 | swap(q_data[2], q_data[3]); |
249 | swap(i_data[2], i_data[3]); | |
250 | ||
f8b9b871 | 251 | ret = regmap_bulk_write(dev->regmap, 0x50, q_data, 4); |
c5f51b15 | 252 | if (ret) |
85146114 AP |
253 | goto err; |
254 | ||
f8b9b871 | 255 | ret = regmap_bulk_write(dev->regmap, 0x60, i_data, 4); |
c5f51b15 | 256 | if (ret) |
85146114 AP |
257 | goto err; |
258 | ||
ed85adaa | 259 | /* gain control auto */ |
f8b9b871 | 260 | ret = regmap_write(dev->regmap, 0x1a, 0x17); |
c5f51b15 | 261 | if (ret) |
ed85adaa | 262 | goto err; |
ed85adaa | 263 | |
f8b9b871 AP |
264 | return 0; |
265 | err: | |
266 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
ed85adaa AP |
267 | return ret; |
268 | } | |
269 | ||
c7861bb0 AP |
270 | /* |
271 | * V4L2 API | |
272 | */ | |
273 | #if IS_ENABLED(CONFIG_VIDEO_V4L2) | |
274 | static const struct v4l2_frequency_band bands[] = { | |
275 | { | |
276 | .type = V4L2_TUNER_RF, | |
277 | .index = 0, | |
278 | .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, | |
279 | .rangelow = 59000000, | |
280 | .rangehigh = 1105000000, | |
281 | }, | |
282 | { | |
283 | .type = V4L2_TUNER_RF, | |
284 | .index = 1, | |
285 | .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, | |
286 | .rangelow = 1249000000, | |
1ba90492 | 287 | .rangehigh = 2208000000UL, |
c7861bb0 AP |
288 | }, |
289 | }; | |
290 | ||
291 | static inline struct e4000_dev *e4000_subdev_to_dev(struct v4l2_subdev *sd) | |
ed85adaa | 292 | { |
c7861bb0 AP |
293 | return container_of(sd, struct e4000_dev, sd); |
294 | } | |
295 | ||
296 | static int e4000_s_power(struct v4l2_subdev *sd, int on) | |
297 | { | |
298 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
f8b9b871 | 299 | struct i2c_client *client = dev->client; |
c7861bb0 | 300 | int ret; |
ed85adaa | 301 | |
c7861bb0 | 302 | dev_dbg(&client->dev, "on=%d\n", on); |
ed85adaa | 303 | |
c7861bb0 AP |
304 | if (on) |
305 | ret = e4000_init(dev); | |
306 | else | |
307 | ret = e4000_sleep(dev); | |
308 | if (ret) | |
309 | return ret; | |
310 | ||
311 | return e4000_set_params(dev); | |
312 | } | |
313 | ||
314 | static const struct v4l2_subdev_core_ops e4000_subdev_core_ops = { | |
315 | .s_power = e4000_s_power, | |
316 | }; | |
ed85adaa | 317 | |
c7861bb0 AP |
318 | static int e4000_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v) |
319 | { | |
320 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
321 | struct i2c_client *client = dev->client; | |
322 | ||
323 | dev_dbg(&client->dev, "index=%d\n", v->index); | |
324 | ||
325 | strlcpy(v->name, "Elonics E4000", sizeof(v->name)); | |
326 | v->type = V4L2_TUNER_RF; | |
327 | v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; | |
328 | v->rangelow = bands[0].rangelow; | |
329 | v->rangehigh = bands[1].rangehigh; | |
ed85adaa AP |
330 | return 0; |
331 | } | |
332 | ||
c7861bb0 AP |
333 | static int e4000_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v) |
334 | { | |
335 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
336 | struct i2c_client *client = dev->client; | |
337 | ||
338 | dev_dbg(&client->dev, "index=%d\n", v->index); | |
339 | return 0; | |
340 | } | |
341 | ||
342 | static int e4000_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f) | |
343 | { | |
344 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
345 | struct i2c_client *client = dev->client; | |
346 | ||
347 | dev_dbg(&client->dev, "tuner=%d\n", f->tuner); | |
348 | f->frequency = dev->f_frequency; | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static int e4000_s_frequency(struct v4l2_subdev *sd, | |
353 | const struct v4l2_frequency *f) | |
354 | { | |
355 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
356 | struct i2c_client *client = dev->client; | |
357 | ||
358 | dev_dbg(&client->dev, "tuner=%d type=%d frequency=%u\n", | |
359 | f->tuner, f->type, f->frequency); | |
360 | ||
361 | dev->f_frequency = clamp_t(unsigned int, f->frequency, | |
362 | bands[0].rangelow, bands[1].rangehigh); | |
363 | return e4000_set_params(dev); | |
364 | } | |
365 | ||
366 | static int e4000_enum_freq_bands(struct v4l2_subdev *sd, | |
367 | struct v4l2_frequency_band *band) | |
368 | { | |
369 | struct e4000_dev *dev = e4000_subdev_to_dev(sd); | |
370 | struct i2c_client *client = dev->client; | |
371 | ||
372 | dev_dbg(&client->dev, "tuner=%d type=%d index=%d\n", | |
373 | band->tuner, band->type, band->index); | |
374 | ||
375 | if (band->index >= ARRAY_SIZE(bands)) | |
376 | return -EINVAL; | |
377 | ||
378 | band->capability = bands[band->index].capability; | |
379 | band->rangelow = bands[band->index].rangelow; | |
380 | band->rangehigh = bands[band->index].rangehigh; | |
381 | return 0; | |
382 | } | |
383 | ||
384 | static const struct v4l2_subdev_tuner_ops e4000_subdev_tuner_ops = { | |
385 | .g_tuner = e4000_g_tuner, | |
386 | .s_tuner = e4000_s_tuner, | |
387 | .g_frequency = e4000_g_frequency, | |
388 | .s_frequency = e4000_s_frequency, | |
389 | .enum_freq_bands = e4000_enum_freq_bands, | |
390 | }; | |
391 | ||
392 | static const struct v4l2_subdev_ops e4000_subdev_ops = { | |
393 | .core = &e4000_subdev_core_ops, | |
394 | .tuner = &e4000_subdev_tuner_ops, | |
395 | }; | |
396 | ||
adaa616f AP |
397 | static int e4000_set_lna_gain(struct dvb_frontend *fe) |
398 | { | |
f8b9b871 AP |
399 | struct e4000_dev *dev = fe->tuner_priv; |
400 | struct i2c_client *client = dev->client; | |
adaa616f AP |
401 | int ret; |
402 | u8 u8tmp; | |
1c73fc6b | 403 | |
f8b9b871 AP |
404 | dev_dbg(&client->dev, "lna auto=%d->%d val=%d->%d\n", |
405 | dev->lna_gain_auto->cur.val, dev->lna_gain_auto->val, | |
406 | dev->lna_gain->cur.val, dev->lna_gain->val); | |
adaa616f | 407 | |
f8b9b871 | 408 | if (dev->lna_gain_auto->val && dev->if_gain_auto->cur.val) |
adaa616f | 409 | u8tmp = 0x17; |
f8b9b871 | 410 | else if (dev->lna_gain_auto->val) |
adaa616f | 411 | u8tmp = 0x19; |
f8b9b871 | 412 | else if (dev->if_gain_auto->cur.val) |
adaa616f AP |
413 | u8tmp = 0x16; |
414 | else | |
415 | u8tmp = 0x10; | |
416 | ||
f8b9b871 | 417 | ret = regmap_write(dev->regmap, 0x1a, u8tmp); |
adaa616f AP |
418 | if (ret) |
419 | goto err; | |
420 | ||
f8b9b871 AP |
421 | if (dev->lna_gain_auto->val == false) { |
422 | ret = regmap_write(dev->regmap, 0x14, dev->lna_gain->val); | |
adaa616f AP |
423 | if (ret) |
424 | goto err; | |
425 | } | |
adaa616f | 426 | |
f8b9b871 AP |
427 | return 0; |
428 | err: | |
429 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
adaa616f AP |
430 | return ret; |
431 | } | |
432 | ||
433 | static int e4000_set_mixer_gain(struct dvb_frontend *fe) | |
434 | { | |
f8b9b871 AP |
435 | struct e4000_dev *dev = fe->tuner_priv; |
436 | struct i2c_client *client = dev->client; | |
adaa616f AP |
437 | int ret; |
438 | u8 u8tmp; | |
1c73fc6b | 439 | |
f8b9b871 AP |
440 | dev_dbg(&client->dev, "mixer auto=%d->%d val=%d->%d\n", |
441 | dev->mixer_gain_auto->cur.val, dev->mixer_gain_auto->val, | |
442 | dev->mixer_gain->cur.val, dev->mixer_gain->val); | |
adaa616f | 443 | |
f8b9b871 | 444 | if (dev->mixer_gain_auto->val) |
adaa616f AP |
445 | u8tmp = 0x15; |
446 | else | |
447 | u8tmp = 0x14; | |
448 | ||
f8b9b871 | 449 | ret = regmap_write(dev->regmap, 0x20, u8tmp); |
adaa616f AP |
450 | if (ret) |
451 | goto err; | |
452 | ||
f8b9b871 AP |
453 | if (dev->mixer_gain_auto->val == false) { |
454 | ret = regmap_write(dev->regmap, 0x15, dev->mixer_gain->val); | |
adaa616f AP |
455 | if (ret) |
456 | goto err; | |
457 | } | |
adaa616f | 458 | |
f8b9b871 AP |
459 | return 0; |
460 | err: | |
461 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
adaa616f AP |
462 | return ret; |
463 | } | |
464 | ||
465 | static int e4000_set_if_gain(struct dvb_frontend *fe) | |
466 | { | |
f8b9b871 AP |
467 | struct e4000_dev *dev = fe->tuner_priv; |
468 | struct i2c_client *client = dev->client; | |
adaa616f AP |
469 | int ret; |
470 | u8 buf[2]; | |
471 | u8 u8tmp; | |
1c73fc6b | 472 | |
f8b9b871 AP |
473 | dev_dbg(&client->dev, "if auto=%d->%d val=%d->%d\n", |
474 | dev->if_gain_auto->cur.val, dev->if_gain_auto->val, | |
475 | dev->if_gain->cur.val, dev->if_gain->val); | |
adaa616f | 476 | |
f8b9b871 | 477 | if (dev->if_gain_auto->val && dev->lna_gain_auto->cur.val) |
adaa616f | 478 | u8tmp = 0x17; |
f8b9b871 | 479 | else if (dev->lna_gain_auto->cur.val) |
adaa616f | 480 | u8tmp = 0x19; |
f8b9b871 | 481 | else if (dev->if_gain_auto->val) |
adaa616f AP |
482 | u8tmp = 0x16; |
483 | else | |
484 | u8tmp = 0x10; | |
485 | ||
f8b9b871 | 486 | ret = regmap_write(dev->regmap, 0x1a, u8tmp); |
adaa616f AP |
487 | if (ret) |
488 | goto err; | |
489 | ||
f8b9b871 AP |
490 | if (dev->if_gain_auto->val == false) { |
491 | buf[0] = e4000_if_gain_lut[dev->if_gain->val].reg16_val; | |
492 | buf[1] = e4000_if_gain_lut[dev->if_gain->val].reg17_val; | |
493 | ret = regmap_bulk_write(dev->regmap, 0x16, buf, 2); | |
adaa616f AP |
494 | if (ret) |
495 | goto err; | |
496 | } | |
adaa616f | 497 | |
f8b9b871 AP |
498 | return 0; |
499 | err: | |
500 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
adaa616f AP |
501 | return ret; |
502 | } | |
503 | ||
ecfb7ca3 AP |
504 | static int e4000_pll_lock(struct dvb_frontend *fe) |
505 | { | |
f8b9b871 AP |
506 | struct e4000_dev *dev = fe->tuner_priv; |
507 | struct i2c_client *client = dev->client; | |
ecfb7ca3 | 508 | int ret; |
f8b9b871 | 509 | unsigned int uitmp; |
ecfb7ca3 | 510 | |
f8b9b871 | 511 | ret = regmap_read(dev->regmap, 0x07, &uitmp); |
c5f51b15 | 512 | if (ret) |
ecfb7ca3 AP |
513 | goto err; |
514 | ||
f8b9b871 | 515 | dev->pll_lock->val = (uitmp & 0x01); |
ecfb7ca3 | 516 | |
f8b9b871 AP |
517 | return 0; |
518 | err: | |
519 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
ecfb7ca3 AP |
520 | return ret; |
521 | } | |
522 | ||
523 | static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) | |
524 | { | |
f8b9b871 AP |
525 | struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl); |
526 | struct i2c_client *client = dev->client; | |
ecfb7ca3 AP |
527 | int ret; |
528 | ||
f8b9b871 | 529 | if (!dev->active) |
bd428bbc AP |
530 | return 0; |
531 | ||
ecfb7ca3 AP |
532 | switch (ctrl->id) { |
533 | case V4L2_CID_RF_TUNER_PLL_LOCK: | |
f8b9b871 | 534 | ret = e4000_pll_lock(dev->fe); |
ecfb7ca3 AP |
535 | break; |
536 | default: | |
f8b9b871 AP |
537 | dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n", |
538 | ctrl->id, ctrl->name); | |
ecfb7ca3 AP |
539 | ret = -EINVAL; |
540 | } | |
541 | ||
542 | return ret; | |
543 | } | |
544 | ||
adaa616f AP |
545 | static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) |
546 | { | |
f8b9b871 AP |
547 | struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl); |
548 | struct i2c_client *client = dev->client; | |
adaa616f | 549 | int ret; |
1c73fc6b | 550 | |
f8b9b871 | 551 | if (!dev->active) |
bd428bbc | 552 | return 0; |
adaa616f AP |
553 | |
554 | switch (ctrl->id) { | |
555 | case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: | |
556 | case V4L2_CID_RF_TUNER_BANDWIDTH: | |
c7861bb0 AP |
557 | /* |
558 | * TODO: Auto logic does not work 100% correctly as tuner driver | |
559 | * do not have information to calculate maximum suitable | |
560 | * bandwidth. Calculating it is responsible of master driver. | |
561 | */ | |
562 | dev->f_bandwidth = dev->bandwidth->val; | |
563 | ret = e4000_set_params(dev); | |
adaa616f AP |
564 | break; |
565 | case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: | |
566 | case V4L2_CID_RF_TUNER_LNA_GAIN: | |
f8b9b871 | 567 | ret = e4000_set_lna_gain(dev->fe); |
adaa616f AP |
568 | break; |
569 | case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: | |
570 | case V4L2_CID_RF_TUNER_MIXER_GAIN: | |
f8b9b871 | 571 | ret = e4000_set_mixer_gain(dev->fe); |
adaa616f AP |
572 | break; |
573 | case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: | |
574 | case V4L2_CID_RF_TUNER_IF_GAIN: | |
f8b9b871 | 575 | ret = e4000_set_if_gain(dev->fe); |
adaa616f AP |
576 | break; |
577 | default: | |
f8b9b871 AP |
578 | dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n", |
579 | ctrl->id, ctrl->name); | |
adaa616f AP |
580 | ret = -EINVAL; |
581 | } | |
582 | ||
583 | return ret; | |
584 | } | |
585 | ||
586 | static const struct v4l2_ctrl_ops e4000_ctrl_ops = { | |
ecfb7ca3 | 587 | .g_volatile_ctrl = e4000_g_volatile_ctrl, |
adaa616f AP |
588 | .s_ctrl = e4000_s_ctrl, |
589 | }; | |
320c6387 | 590 | #endif |
adaa616f | 591 | |
c7861bb0 AP |
592 | /* |
593 | * DVB API | |
594 | */ | |
595 | static int e4000_dvb_set_params(struct dvb_frontend *fe) | |
596 | { | |
597 | struct e4000_dev *dev = fe->tuner_priv; | |
598 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
599 | ||
600 | dev->f_frequency = c->frequency; | |
601 | dev->f_bandwidth = c->bandwidth_hz; | |
602 | return e4000_set_params(dev); | |
603 | } | |
604 | ||
605 | static int e4000_dvb_init(struct dvb_frontend *fe) | |
606 | { | |
607 | return e4000_init(fe->tuner_priv); | |
608 | } | |
609 | ||
610 | static int e4000_dvb_sleep(struct dvb_frontend *fe) | |
611 | { | |
612 | return e4000_sleep(fe->tuner_priv); | |
613 | } | |
614 | ||
615 | static int e4000_dvb_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) | |
616 | { | |
617 | *frequency = 0; /* Zero-IF */ | |
618 | return 0; | |
619 | } | |
620 | ||
621 | static const struct dvb_tuner_ops e4000_dvb_tuner_ops = { | |
ed85adaa AP |
622 | .info = { |
623 | .name = "Elonics E4000", | |
624 | .frequency_min = 174000000, | |
625 | .frequency_max = 862000000, | |
626 | }, | |
627 | ||
c7861bb0 AP |
628 | .init = e4000_dvb_init, |
629 | .sleep = e4000_dvb_sleep, | |
630 | .set_params = e4000_dvb_set_params, | |
ed85adaa | 631 | |
c7861bb0 | 632 | .get_if_frequency = e4000_dvb_get_if_frequency, |
ed85adaa AP |
633 | }; |
634 | ||
28fd31f8 | 635 | static int e4000_probe(struct i2c_client *client, |
f8b9b871 | 636 | const struct i2c_device_id *id) |
ed85adaa | 637 | { |
f8b9b871 | 638 | struct e4000_dev *dev; |
28fd31f8 AP |
639 | struct e4000_config *cfg = client->dev.platform_data; |
640 | struct dvb_frontend *fe = cfg->fe; | |
ed85adaa | 641 | int ret; |
f8b9b871 | 642 | unsigned int uitmp; |
bd428bbc AP |
643 | static const struct regmap_config regmap_config = { |
644 | .reg_bits = 8, | |
645 | .val_bits = 8, | |
bd428bbc | 646 | }; |
ed85adaa | 647 | |
f8b9b871 AP |
648 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
649 | if (!dev) { | |
ed85adaa | 650 | ret = -ENOMEM; |
ed85adaa AP |
651 | goto err; |
652 | } | |
653 | ||
f8b9b871 AP |
654 | dev->clk = cfg->clock; |
655 | dev->client = client; | |
656 | dev->fe = cfg->fe; | |
657 | dev->regmap = devm_regmap_init_i2c(client, ®map_config); | |
658 | if (IS_ERR(dev->regmap)) { | |
659 | ret = PTR_ERR(dev->regmap); | |
660 | goto err_kfree; | |
bd428bbc | 661 | } |
ed85adaa AP |
662 | |
663 | /* check if the tuner is there */ | |
f8b9b871 | 664 | ret = regmap_read(dev->regmap, 0x02, &uitmp); |
c5f51b15 | 665 | if (ret) |
f8b9b871 | 666 | goto err_kfree; |
ed85adaa | 667 | |
f8b9b871 | 668 | dev_dbg(&client->dev, "chip id=%02x\n", uitmp); |
ed85adaa | 669 | |
f8b9b871 | 670 | if (uitmp != 0x40) { |
28fd31f8 | 671 | ret = -ENODEV; |
f8b9b871 | 672 | goto err_kfree; |
28fd31f8 | 673 | } |
ed85adaa AP |
674 | |
675 | /* put sleep as chip seems to be in normal mode by default */ | |
f8b9b871 | 676 | ret = regmap_write(dev->regmap, 0x00, 0x00); |
c5f51b15 | 677 | if (ret) |
f8b9b871 | 678 | goto err_kfree; |
ed85adaa | 679 | |
320c6387 | 680 | #if IS_ENABLED(CONFIG_VIDEO_V4L2) |
adaa616f | 681 | /* Register controls */ |
f8b9b871 AP |
682 | v4l2_ctrl_handler_init(&dev->hdl, 9); |
683 | dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, | |
adaa616f | 684 | V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); |
f8b9b871 | 685 | dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, |
adaa616f | 686 | V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); |
f8b9b871 AP |
687 | v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false); |
688 | dev->lna_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, | |
adaa616f | 689 | V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1); |
f8b9b871 | 690 | dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, |
adaa616f | 691 | V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10); |
f8b9b871 AP |
692 | v4l2_ctrl_auto_cluster(2, &dev->lna_gain_auto, 0, false); |
693 | dev->mixer_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, | |
adaa616f | 694 | V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1); |
f8b9b871 | 695 | dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, |
adaa616f | 696 | V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); |
f8b9b871 AP |
697 | v4l2_ctrl_auto_cluster(2, &dev->mixer_gain_auto, 0, false); |
698 | dev->if_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, | |
adaa616f | 699 | V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1); |
f8b9b871 | 700 | dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, |
adaa616f | 701 | V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); |
f8b9b871 AP |
702 | v4l2_ctrl_auto_cluster(2, &dev->if_gain_auto, 0, false); |
703 | dev->pll_lock = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops, | |
ecfb7ca3 | 704 | V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0); |
f8b9b871 AP |
705 | if (dev->hdl.error) { |
706 | ret = dev->hdl.error; | |
707 | dev_err(&client->dev, "Could not initialize controls\n"); | |
708 | v4l2_ctrl_handler_free(&dev->hdl); | |
709 | goto err_kfree; | |
adaa616f AP |
710 | } |
711 | ||
f8b9b871 | 712 | dev->sd.ctrl_handler = &dev->hdl; |
c7861bb0 AP |
713 | dev->f_frequency = bands[0].rangelow; |
714 | dev->f_bandwidth = dev->bandwidth->val; | |
715 | v4l2_i2c_subdev_init(&dev->sd, client, &e4000_subdev_ops); | |
320c6387 | 716 | #endif |
f8b9b871 | 717 | fe->tuner_priv = dev; |
c7861bb0 AP |
718 | memcpy(&fe->ops.tuner_ops, &e4000_dvb_tuner_ops, |
719 | sizeof(fe->ops.tuner_ops)); | |
f8b9b871 AP |
720 | v4l2_set_subdevdata(&dev->sd, client); |
721 | i2c_set_clientdata(client, &dev->sd); | |
36f647ba | 722 | |
f8b9b871 | 723 | dev_info(&client->dev, "Elonics E4000 successfully identified\n"); |
28fd31f8 | 724 | return 0; |
f8b9b871 AP |
725 | err_kfree: |
726 | kfree(dev); | |
ed85adaa | 727 | err: |
f8b9b871 | 728 | dev_dbg(&client->dev, "failed=%d\n", ret); |
28fd31f8 | 729 | return ret; |
ed85adaa | 730 | } |
28fd31f8 AP |
731 | |
732 | static int e4000_remove(struct i2c_client *client) | |
733 | { | |
adaa616f | 734 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
f8b9b871 | 735 | struct e4000_dev *dev = container_of(sd, struct e4000_dev, sd); |
28fd31f8 | 736 | |
13bd82d1 | 737 | dev_dbg(&client->dev, "\n"); |
1c73fc6b | 738 | |
320c6387 | 739 | #if IS_ENABLED(CONFIG_VIDEO_V4L2) |
f8b9b871 | 740 | v4l2_ctrl_handler_free(&dev->hdl); |
320c6387 | 741 | #endif |
f8b9b871 | 742 | kfree(dev); |
28fd31f8 AP |
743 | |
744 | return 0; | |
745 | } | |
746 | ||
f8b9b871 | 747 | static const struct i2c_device_id e4000_id_table[] = { |
28fd31f8 AP |
748 | {"e4000", 0}, |
749 | {} | |
750 | }; | |
f8b9b871 | 751 | MODULE_DEVICE_TABLE(i2c, e4000_id_table); |
28fd31f8 AP |
752 | |
753 | static struct i2c_driver e4000_driver = { | |
754 | .driver = { | |
28fd31f8 | 755 | .name = "e4000", |
f8b9b871 | 756 | .suppress_bind_attrs = true, |
28fd31f8 AP |
757 | }, |
758 | .probe = e4000_probe, | |
759 | .remove = e4000_remove, | |
f8b9b871 | 760 | .id_table = e4000_id_table, |
28fd31f8 AP |
761 | }; |
762 | ||
763 | module_i2c_driver(e4000_driver); | |
ed85adaa AP |
764 | |
765 | MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver"); | |
766 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); | |
767 | MODULE_LICENSE("GPL"); |