[deliverable/linux.git] / drivers / media / tuners / msi001.c

/*
 * Mirics MSi001 silicon tuner driver
 *
 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
 * Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2 of the License, or
 *    (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/gcd.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>

static const struct v4l2_frequency_band bands[] = {
	{
		.type = V4L2_TUNER_RF,
		.index = 0,
		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
		.rangelow   =   49000000,
		.rangehigh  =  263000000,
	}, {
		.type = V4L2_TUNER_RF,
		.index = 1,
		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
		.rangelow   =  390000000,
		.rangehigh  =  960000000,
	},
};

struct msi001 {
	struct spi_device *spi;
	struct v4l2_subdev sd;

	/* Controls */
	struct v4l2_ctrl_handler hdl;
	struct v4l2_ctrl *bandwidth_auto;
	struct v4l2_ctrl *bandwidth;
	struct v4l2_ctrl *lna_gain;
	struct v4l2_ctrl *mixer_gain;
	struct v4l2_ctrl *if_gain;

	unsigned int f_tuner;
};

static inline struct msi001 *sd_to_msi001(struct v4l2_subdev *sd)
{
	return container_of(sd, struct msi001, sd);
}

static int msi001_wreg(struct msi001 *s, u32 data)
{
	/* Register format: 4 bits addr + 20 bits value */
	return spi_write(s->spi, &data, 3);
};

static int msi001_set_gain(struct msi001 *s, int lna_gain, int mixer_gain,
		int if_gain)
{
	int ret;
	u32 reg;

	dev_dbg(&s->spi->dev, "lna=%d mixer=%d if=%d\n",
			lna_gain, mixer_gain, if_gain);

	reg = 1 << 0;
	reg |= (59 - if_gain) << 4;
	reg |= 0 << 10;
	reg |= (1 - mixer_gain) << 12;
	reg |= (1 - lna_gain) << 13;
	reg |= 4 << 14;
	reg |= 0 << 17;
	ret = msi001_wreg(s, reg);
	if (ret)
		goto err;

	return 0;
err:
	dev_dbg(&s->spi->dev, "failed %d\n", ret);
	return ret;
};

static int msi001_set_tuner(struct msi001 *s)
{
	int ret, i;
	unsigned int n, m, thresh, frac, vco_step, tmp, f_if1;
	u32 reg;
	u64 f_vco, tmp64;
	u8 mode, filter_mode, lo_div;

	static const struct {
		u32 rf;
		u8 mode;
		u8 lo_div;
	} band_lut[] = {
		{ 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
		{108000000, 0x42, 32}, /* VHF_MODE */
		{330000000, 0x44, 16}, /* B3_MODE */
		{960000000, 0x48,  4}, /* B45_MODE */
		{      ~0U, 0x50,  2}, /* BL_MODE */
	};
	static const struct {
		u32 freq;
		u8 filter_mode;
	} if_freq_lut[] = {
		{      0, 0x03}, /* Zero IF */
		{ 450000, 0x02}, /* 450 kHz IF */
		{1620000, 0x01}, /* 1.62 MHz IF */
		{2048000, 0x00}, /* 2.048 MHz IF */
	};
	static const struct {
		u32 freq;
		u8 val;
	} bandwidth_lut[] = {
		{ 200000, 0x00}, /* 200 kHz */
		{ 300000, 0x01}, /* 300 kHz */
		{ 600000, 0x02}, /* 600 kHz */
		{1536000, 0x03}, /* 1.536 MHz */
		{5000000, 0x04}, /* 5 MHz */
		{6000000, 0x05}, /* 6 MHz */
		{7000000, 0x06}, /* 7 MHz */
		{8000000, 0x07}, /* 8 MHz */
	};

	unsigned int f_rf = s->f_tuner;

	/*
	 * bandwidth (Hz)
	 * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
	 */
	unsigned int bandwidth;

	/*
	 * intermediate frequency (Hz)
	 * 0, 450000, 1620000, 2048000
	 */
	unsigned int f_if = 0;
	#define F_REF 24000000
	#define R_REF 4
	#define F_OUT_STEP 1

	dev_dbg(&s->spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);

	for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
		if (f_rf <= band_lut[i].rf) {
			mode = band_lut[i].mode;
			lo_div = band_lut[i].lo_div;
			break;
		}
	}

	if (i == ARRAY_SIZE(band_lut)) {
		ret = -EINVAL;
		goto err;
	}

	/* AM_MODE is upconverted */
	if ((mode >> 0) & 0x1)
		f_if1 =  5 * F_REF;
	else
		f_if1 =  0;

	for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
		if (f_if == if_freq_lut[i].freq) {
			filter_mode = if_freq_lut[i].filter_mode;
			break;
		}
	}

	if (i == ARRAY_SIZE(if_freq_lut)) {
		ret = -EINVAL;
		goto err;
	}

	/* filters */
	bandwidth = s->bandwidth->val;
	bandwidth = clamp(bandwidth, 200000U, 8000000U);

	for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
		if (bandwidth <= bandwidth_lut[i].freq) {
			bandwidth = bandwidth_lut[i].val;
			break;
		}
	}

	if (i == ARRAY_SIZE(bandwidth_lut)) {
		ret = -EINVAL;
		goto err;
	}

	s->bandwidth->val = bandwidth_lut[i].freq;

	dev_dbg(&s->spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);

	f_vco = (u64) (f_rf + f_if + f_if1) * lo_div;
	tmp64 = f_vco;
	m = do_div(tmp64, F_REF * R_REF);
	n = (unsigned int) tmp64;

	vco_step = F_OUT_STEP * lo_div;
	thresh = (F_REF * R_REF) / vco_step;
	frac = 1ul * thresh * m / (F_REF * R_REF);

	/* Find out greatest common divisor and divide to smaller. */
	tmp = gcd(thresh, frac);
	thresh /= tmp;
	frac /= tmp;

	/* Force divide to reg max. Resolution will be reduced. */
	tmp = DIV_ROUND_UP(thresh, 4095);
	thresh = DIV_ROUND_CLOSEST(thresh, tmp);
	frac = DIV_ROUND_CLOSEST(frac, tmp);

	/* calc real RF set */
	tmp = 1ul * F_REF * R_REF * n;
	tmp += 1ul * F_REF * R_REF * frac / thresh;
	tmp /= lo_div;

	dev_dbg(&s->spi->dev, "rf=%u:%u n=%d thresh=%d frac=%d\n",
				f_rf, tmp, n, thresh, frac);

	ret = msi001_wreg(s, 0x00000e);
	if (ret)
		goto err;

	ret = msi001_wreg(s, 0x000003);
	if (ret)
		goto err;

	reg = 0 << 0;
	reg |= mode << 4;
	reg |= filter_mode << 12;
	reg |= bandwidth << 14;
	reg |= 0x02 << 17;
	reg |= 0x00 << 20;
	ret = msi001_wreg(s, reg);
	if (ret)
		goto err;

	reg = 5 << 0;
	reg |= thresh << 4;
	reg |= 1 << 19;
	reg |= 1 << 21;
	ret = msi001_wreg(s, reg);
	if (ret)
		goto err;

	reg = 2 << 0;
	reg |= frac << 4;
	reg |= n << 16;
	ret = msi001_wreg(s, reg);
	if (ret)
		goto err;

	ret = msi001_set_gain(s, s->lna_gain->cur.val, s->mixer_gain->cur.val,
			s->if_gain->cur.val);
	if (ret)
		goto err;

	reg = 6 << 0;
	reg |= 63 << 4;
	reg |= 4095 << 10;
	ret = msi001_wreg(s, reg);
	if (ret)
		goto err;

	return 0;
err:
	dev_dbg(&s->spi->dev, "failed %d\n", ret);
	return ret;
};

static int msi001_s_power(struct v4l2_subdev *sd, int on)
{
	struct msi001 *s = sd_to_msi001(sd);
	int ret;

	dev_dbg(&s->spi->dev, "on=%d\n", on);

	if (on)
		ret = 0;
	else
		ret = msi001_wreg(s, 0x000000);

	return ret;
}

static const struct v4l2_subdev_core_ops msi001_core_ops = {
	.s_power                  = msi001_s_power,
};

static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
{
	struct msi001 *s = sd_to_msi001(sd);

	dev_dbg(&s->spi->dev, "index=%d\n", v->index);

	strlcpy(v->name, "Mirics MSi001", sizeof(v->name));
	v->type = V4L2_TUNER_RF;
	v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
	v->rangelow =    49000000;
	v->rangehigh =  960000000;

	return 0;
}

static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
{
	struct msi001 *s = sd_to_msi001(sd);

	dev_dbg(&s->spi->dev, "index=%d\n", v->index);
	return 0;
}

static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
{
	struct msi001 *s = sd_to_msi001(sd);

	dev_dbg(&s->spi->dev, "tuner=%d\n", f->tuner);
	f->frequency = s->f_tuner;
	return 0;
}

static int msi001_s_frequency(struct v4l2_subdev *sd,
		const struct v4l2_frequency *f)
{
	struct msi001 *s = sd_to_msi001(sd);
	unsigned int band;

	dev_dbg(&s->spi->dev, "tuner=%d type=%d frequency=%u\n",
			f->tuner, f->type, f->frequency);

	if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
		band = 0;
	else
		band = 1;
	s->f_tuner = clamp_t(unsigned int, f->frequency,
			bands[band].rangelow, bands[band].rangehigh);

	return msi001_set_tuner(s);
}

static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
		struct v4l2_frequency_band *band)
{
	struct msi001 *s = sd_to_msi001(sd);

	dev_dbg(&s->spi->dev, "tuner=%d type=%d index=%d\n",
			band->tuner, band->type, band->index);

	if (band->index >= ARRAY_SIZE(bands))
		return -EINVAL;

	band->capability = bands[band->index].capability;
	band->rangelow = bands[band->index].rangelow;
	band->rangehigh = bands[band->index].rangehigh;

	return 0;
}

static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
	.g_tuner                  = msi001_g_tuner,
	.s_tuner                  = msi001_s_tuner,
	.g_frequency              = msi001_g_frequency,
	.s_frequency              = msi001_s_frequency,
	.enum_freq_bands          = msi001_enum_freq_bands,
};

static const struct v4l2_subdev_ops msi001_ops = {
	.core                     = &msi001_core_ops,
	.tuner                    = &msi001_tuner_ops,
};

static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct msi001 *s = container_of(ctrl->handler, struct msi001, hdl);

	int ret;

	dev_dbg(&s->spi->dev,
			"id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
			ctrl->id, ctrl->name, ctrl->val,
			ctrl->minimum, ctrl->maximum, ctrl->step);

	switch (ctrl->id) {
	case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
	case V4L2_CID_RF_TUNER_BANDWIDTH:
		ret = msi001_set_tuner(s);
		break;
	case  V4L2_CID_RF_TUNER_LNA_GAIN:
		ret = msi001_set_gain(s, s->lna_gain->val,
				s->mixer_gain->cur.val, s->if_gain->cur.val);
		break;
	case  V4L2_CID_RF_TUNER_MIXER_GAIN:
		ret = msi001_set_gain(s, s->lna_gain->cur.val,
				s->mixer_gain->val, s->if_gain->cur.val);
		break;
	case  V4L2_CID_RF_TUNER_IF_GAIN:
		ret = msi001_set_gain(s, s->lna_gain->cur.val,
				s->mixer_gain->cur.val, s->if_gain->val);
		break;
	default:
		dev_dbg(&s->spi->dev, "unknown control %d\n", ctrl->id);
		ret = -EINVAL;
	}

	return ret;
}

static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
	.s_ctrl                   = msi001_s_ctrl,
};

static int msi001_probe(struct spi_device *spi)
{
	struct msi001 *s;
	int ret;

	dev_dbg(&spi->dev, "\n");

	s = kzalloc(sizeof(struct msi001), GFP_KERNEL);
	if (s == NULL) {
		ret = -ENOMEM;
		dev_dbg(&spi->dev, "Could not allocate memory for msi001\n");
		goto err_kfree;
	}

	s->spi = spi;
	s->f_tuner = bands[0].rangelow;
	v4l2_spi_subdev_init(&s->sd, spi, &msi001_ops);

	/* Register controls */
	v4l2_ctrl_handler_init(&s->hdl, 5);
	s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
			V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
	s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
			V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
	v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false);
	s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
			V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
	s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
			V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
	s->if_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
			V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
	if (s->hdl.error) {
		ret = s->hdl.error;
		dev_err(&s->spi->dev, "Could not initialize controls\n");
		/* control init failed, free handler */
		goto err_ctrl_handler_free;
	}

	s->sd.ctrl_handler = &s->hdl;
	return 0;

err_ctrl_handler_free:
	v4l2_ctrl_handler_free(&s->hdl);
err_kfree:
	kfree(s);
	return ret;
}

static int msi001_remove(struct spi_device *spi)
{
	struct v4l2_subdev *sd = spi_get_drvdata(spi);
	struct msi001 *s = sd_to_msi001(sd);

	dev_dbg(&spi->dev, "\n");

	/*
	 * Registered by v4l2_spi_new_subdev() from master driver, but we must
	 * unregister it from here. Weird.
	 */
	v4l2_device_unregister_subdev(&s->sd);
	v4l2_ctrl_handler_free(&s->hdl);
	kfree(s);
	return 0;
}

static const struct spi_device_id msi001_id[] = {
	{"msi001", 0},
	{}
};
MODULE_DEVICE_TABLE(spi, msi001_id);

static struct spi_driver msi001_driver = {
	.driver = {
		.name	= "msi001",
		.owner	= THIS_MODULE,
	},
	.probe		= msi001_probe,
	.remove		= msi001_remove,
	.id_table	= msi001_id,
};
module_spi_driver(msi001_driver);

MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
MODULE_DESCRIPTION("Mirics MSi001");
MODULE_LICENSE("GPL");
Commit	Line	Data
93203dd6 AP	1	/*
	2	* Mirics MSi001 silicon tuner driver
	3	*
	4	* Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
	5	* Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/module.h>
	19	#include <linux/gcd.h>
	20	#include <media/v4l2-device.h>
	21	#include <media/v4l2-ctrls.h>
	22
	23	static const struct v4l2_frequency_band bands[] = {
	24	{
	25	.type = V4L2_TUNER_RF,
	26	.index = 0,
	27	.capability = V4L2_TUNER_CAP_1HZ \| V4L2_TUNER_CAP_FREQ_BANDS,
	28	.rangelow = 49000000,
	29	.rangehigh = 263000000,
	30	}, {
	31	.type = V4L2_TUNER_RF,
	32	.index = 1,
	33	.capability = V4L2_TUNER_CAP_1HZ \| V4L2_TUNER_CAP_FREQ_BANDS,
	34	.rangelow = 390000000,
	35	.rangehigh = 960000000,
	36	},
	37	};
	38
	39	struct msi001 {
	40	struct spi_device *spi;
	41	struct v4l2_subdev sd;
	42
	43	/* Controls */
	44	struct v4l2_ctrl_handler hdl;
	45	struct v4l2_ctrl *bandwidth_auto;
	46	struct v4l2_ctrl *bandwidth;
	47	struct v4l2_ctrl *lna_gain;
	48	struct v4l2_ctrl *mixer_gain;
	49	struct v4l2_ctrl *if_gain;
	50
	51	unsigned int f_tuner;
	52	};
	53
	54	static inline struct msi001 sd_to_msi001(struct v4l2_subdev sd)
	55	{
	56	return container_of(sd, struct msi001, sd);
	57	}
	58
	59	static int msi001_wreg(struct msi001 *s, u32 data)
	60	{
	61	/* Register format: 4 bits addr + 20 bits value */
	62	return spi_write(s->spi, &data, 3);
	63	};
	64
65	static int msi001_set_gain(struct msi001 *s, int lna_gain, int mixer_gain,
66	int if_gain)
67	{
68	int ret;
69	u32 reg;
5fa51cc3 AP	70
5fa51cc3 AP	71	dev_dbg(&s->spi->dev, "lna=%d mixer=%d if=%d\n",
93203dd6 AP	72	lna_gain, mixer_gain, if_gain);
	73
	74	reg = 1 << 0;
	75	reg \|= (59 - if_gain) << 4;
	76	reg \|= 0 << 10;
	77	reg \|= (1 - mixer_gain) << 12;
	78	reg \|= (1 - lna_gain) << 13;
	79	reg \|= 4 << 14;
	80	reg \|= 0 << 17;
	81	ret = msi001_wreg(s, reg);
	82	if (ret)
	83	goto err;
	84
	85	return 0;
	86	err:
5fa51cc3	87	dev_dbg(&s->spi->dev, "failed %d\n", ret);
93203dd6 AP	88	return ret;
	89	};
	90
	91	static int msi001_set_tuner(struct msi001 *s)
	92	{
	93	int ret, i;
	94	unsigned int n, m, thresh, frac, vco_step, tmp, f_if1;
	95	u32 reg;
	96	u64 f_vco, tmp64;
	97	u8 mode, filter_mode, lo_div;
5fa51cc3	98
93203dd6 AP	99	static const struct {
	100	u32 rf;
	101	u8 mode;
	102	u8 lo_div;
	103	} band_lut[] = {
	104	{ 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
	105	{108000000, 0x42, 32}, /* VHF_MODE */
	106	{330000000, 0x44, 16}, /* B3_MODE */
	107	{960000000, 0x48, 4}, /* B45_MODE */
	108	{ ~0U, 0x50, 2}, /* BL_MODE */
	109	};
	110	static const struct {
	111	u32 freq;
	112	u8 filter_mode;
	113	} if_freq_lut[] = {
	114	{ 0, 0x03}, /* Zero IF */
	115	{ 450000, 0x02}, /* 450 kHz IF */
	116	{1620000, 0x01}, /* 1.62 MHz IF */
	117	{2048000, 0x00}, /* 2.048 MHz IF */
	118	};
	119	static const struct {
	120	u32 freq;
	121	u8 val;
	122	} bandwidth_lut[] = {
	123	{ 200000, 0x00}, /* 200 kHz */
	124	{ 300000, 0x01}, /* 300 kHz */
	125	{ 600000, 0x02}, /* 600 kHz */
	126	{1536000, 0x03}, /* 1.536 MHz */
	127	{5000000, 0x04}, /* 5 MHz */
	128	{6000000, 0x05}, /* 6 MHz */
	129	{7000000, 0x06}, /* 7 MHz */
	130	{8000000, 0x07}, /* 8 MHz */
	131	};
	132
	133	unsigned int f_rf = s->f_tuner;
	134
	135	/*
	136	* bandwidth (Hz)
	137	* 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
	138	*/
	139	unsigned int bandwidth;
	140
	141	/*
	142	* intermediate frequency (Hz)
	143	* 0, 450000, 1620000, 2048000
	144	*/
	145	unsigned int f_if = 0;
	146	#define F_REF 24000000
	147	#define R_REF 4
	148	#define F_OUT_STEP 1
	149
5fa51cc3	150	dev_dbg(&s->spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
93203dd6 AP	151
	152	for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
	153	if (f_rf <= band_lut[i].rf) {
	154	mode = band_lut[i].mode;
	155	lo_div = band_lut[i].lo_div;
	156	break;
	157	}
	158	}
	159
	160	if (i == ARRAY_SIZE(band_lut)) {
	161	ret = -EINVAL;
	162	goto err;
	163	}
	164
	165	/* AM_MODE is upconverted */
	166	if ((mode >> 0) & 0x1)
	167	f_if1 = 5 * F_REF;
	168	else
	169	f_if1 = 0;
	170
	171	for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
	172	if (f_if == if_freq_lut[i].freq) {
	173	filter_mode = if_freq_lut[i].filter_mode;
	174	break;
	175	}
	176	}
	177
	178	if (i == ARRAY_SIZE(if_freq_lut)) {
	179	ret = -EINVAL;
	180	goto err;
	181	}
	182
	183	/* filters */
	184	bandwidth = s->bandwidth->val;
	185	bandwidth = clamp(bandwidth, 200000U, 8000000U);
	186
	187	for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
	188	if (bandwidth <= bandwidth_lut[i].freq) {
	189	bandwidth = bandwidth_lut[i].val;
	190	break;
	191	}
	192	}
	193
	194	if (i == ARRAY_SIZE(bandwidth_lut)) {
	195	ret = -EINVAL;
	196	goto err;
	197	}
	198
	199	s->bandwidth->val = bandwidth_lut[i].freq;
	200
5fa51cc3	201	dev_dbg(&s->spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
93203dd6	202
82932d4c	203	f_vco = (u64) (f_rf + f_if + f_if1) * lo_div;
93203dd6 AP	204	tmp64 = f_vco;
	205	m = do_div(tmp64, F_REF * R_REF);
	206	n = (unsigned int) tmp64;
	207
	208	vco_step = F_OUT_STEP * lo_div;
	209	thresh = (F_REF * R_REF) / vco_step;
	210	frac = 1ul * thresh * m / (F_REF * R_REF);
	211
	212	/* Find out greatest common divisor and divide to smaller. */
	213	tmp = gcd(thresh, frac);
	214	thresh /= tmp;
	215	frac /= tmp;
	216
	217	/* Force divide to reg max. Resolution will be reduced. */
	218	tmp = DIV_ROUND_UP(thresh, 4095);
	219	thresh = DIV_ROUND_CLOSEST(thresh, tmp);
	220	frac = DIV_ROUND_CLOSEST(frac, tmp);
	221
	222	/* calc real RF set */
	223	tmp = 1ul * F_REF * R_REF * n;
	224	tmp += 1ul * F_REF * R_REF * frac / thresh;
	225	tmp /= lo_div;
	226
5fa51cc3 AP	227	dev_dbg(&s->spi->dev, "rf=%u:%u n=%d thresh=%d frac=%d\n",
5fa51cc3 AP	228	f_rf, tmp, n, thresh, frac);
93203dd6 AP	229
	230	ret = msi001_wreg(s, 0x00000e);
	231	if (ret)
	232	goto err;
	233
	234	ret = msi001_wreg(s, 0x000003);
	235	if (ret)
	236	goto err;
	237
	238	reg = 0 << 0;
	239	reg \|= mode << 4;
	240	reg \|= filter_mode << 12;
	241	reg \|= bandwidth << 14;
	242	reg \|= 0x02 << 17;
	243	reg \|= 0x00 << 20;
	244	ret = msi001_wreg(s, reg);
	245	if (ret)
	246	goto err;
	247
	248	reg = 5 << 0;
	249	reg \|= thresh << 4;
	250	reg \|= 1 << 19;
	251	reg \|= 1 << 21;
	252	ret = msi001_wreg(s, reg);
	253	if (ret)
	254	goto err;
	255
	256	reg = 2 << 0;
	257	reg \|= frac << 4;
	258	reg \|= n << 16;
	259	ret = msi001_wreg(s, reg);
	260	if (ret)
	261	goto err;
	262
	263	ret = msi001_set_gain(s, s->lna_gain->cur.val, s->mixer_gain->cur.val,
	264	s->if_gain->cur.val);
	265	if (ret)
	266	goto err;
	267
	268	reg = 6 << 0;
	269	reg \|= 63 << 4;
	270	reg \|= 4095 << 10;
	271	ret = msi001_wreg(s, reg);
	272	if (ret)
	273	goto err;
	274
	275	return 0;
	276	err:
5fa51cc3	277	dev_dbg(&s->spi->dev, "failed %d\n", ret);
93203dd6 AP	278	return ret;
	279	};
	280
	281	static int msi001_s_power(struct v4l2_subdev *sd, int on)
	282	{
	283	struct msi001 *s = sd_to_msi001(sd);
	284	int ret;
5fa51cc3 AP	285
5fa51cc3 AP	286	dev_dbg(&s->spi->dev, "on=%d\n", on);
93203dd6 AP	287
	288	if (on)
	289	ret = 0;
	290	else
	291	ret = msi001_wreg(s, 0x000000);
	292
	293	return ret;
	294	}
	295
	296	static const struct v4l2_subdev_core_ops msi001_core_ops = {
	297	.s_power = msi001_s_power,
	298	};
	299
	300	static int msi001_g_tuner(struct v4l2_subdev sd, struct v4l2_tuner v)
	301	{
	302	struct msi001 *s = sd_to_msi001(sd);
5fa51cc3 AP	303
5fa51cc3 AP	304	dev_dbg(&s->spi->dev, "index=%d\n", v->index);
93203dd6 AP	305
	306	strlcpy(v->name, "Mirics MSi001", sizeof(v->name));
	307	v->type = V4L2_TUNER_RF;
	308	v->capability = V4L2_TUNER_CAP_1HZ \| V4L2_TUNER_CAP_FREQ_BANDS;
	309	v->rangelow = 49000000;
	310	v->rangehigh = 960000000;
	311
	312	return 0;
	313	}
	314
	315	static int msi001_s_tuner(struct v4l2_subdev sd, const struct v4l2_tuner v)
	316	{
	317	struct msi001 *s = sd_to_msi001(sd);
5fa51cc3 AP	318
5fa51cc3 AP	319	dev_dbg(&s->spi->dev, "index=%d\n", v->index);
93203dd6 AP	320	return 0;
	321	}
	322
	323	static int msi001_g_frequency(struct v4l2_subdev sd, struct v4l2_frequency f)
	324	{
	325	struct msi001 *s = sd_to_msi001(sd);
5fa51cc3 AP	326
5fa51cc3 AP	327	dev_dbg(&s->spi->dev, "tuner=%d\n", f->tuner);
93203dd6 AP	328	f->frequency = s->f_tuner;
	329	return 0;
	330	}
	331
	332	static int msi001_s_frequency(struct v4l2_subdev *sd,
	333	const struct v4l2_frequency *f)
	334	{
	335	struct msi001 *s = sd_to_msi001(sd);
	336	unsigned int band;
5fa51cc3 AP	337
	338	dev_dbg(&s->spi->dev, "tuner=%d type=%d frequency=%u\n",
	339	f->tuner, f->type, f->frequency);
93203dd6 AP	340
	341	if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
	342	band = 0;
	343	else
	344	band = 1;
	345	s->f_tuner = clamp_t(unsigned int, f->frequency,
	346	bands[band].rangelow, bands[band].rangehigh);
	347
	348	return msi001_set_tuner(s);
	349	}
	350
	351	static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
	352	struct v4l2_frequency_band *band)
	353	{
	354	struct msi001 *s = sd_to_msi001(sd);
5fa51cc3 AP	355
	356	dev_dbg(&s->spi->dev, "tuner=%d type=%d index=%d\n",
	357	band->tuner, band->type, band->index);
93203dd6 AP	358
	359	if (band->index >= ARRAY_SIZE(bands))
	360	return -EINVAL;
	361
	362	band->capability = bands[band->index].capability;
	363	band->rangelow = bands[band->index].rangelow;
	364	band->rangehigh = bands[band->index].rangehigh;
	365
	366	return 0;
	367	}
	368
	369	static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
	370	.g_tuner = msi001_g_tuner,
	371	.s_tuner = msi001_s_tuner,
	372	.g_frequency = msi001_g_frequency,
	373	.s_frequency = msi001_s_frequency,
	374	.enum_freq_bands = msi001_enum_freq_bands,
	375	};
	376
	377	static const struct v4l2_subdev_ops msi001_ops = {
	378	.core = &msi001_core_ops,
	379	.tuner = &msi001_tuner_ops,
	380	};
	381
	382	static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
	383	{
	384	struct msi001 *s = container_of(ctrl->handler, struct msi001, hdl);
	385
	386	int ret;
5fa51cc3	387
93203dd6	388	dev_dbg(&s->spi->dev,
5fa51cc3 AP	389	"id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
5fa51cc3 AP	390	ctrl->id, ctrl->name, ctrl->val,
93203dd6 AP	391	ctrl->minimum, ctrl->maximum, ctrl->step);
	392
	393	switch (ctrl->id) {
	394	case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
	395	case V4L2_CID_RF_TUNER_BANDWIDTH:
	396	ret = msi001_set_tuner(s);
	397	break;
	398	case V4L2_CID_RF_TUNER_LNA_GAIN:
	399	ret = msi001_set_gain(s, s->lna_gain->val,
	400	s->mixer_gain->cur.val, s->if_gain->cur.val);
	401	break;
	402	case V4L2_CID_RF_TUNER_MIXER_GAIN:
	403	ret = msi001_set_gain(s, s->lna_gain->cur.val,
	404	s->mixer_gain->val, s->if_gain->cur.val);
	405	break;
	406	case V4L2_CID_RF_TUNER_IF_GAIN:
	407	ret = msi001_set_gain(s, s->lna_gain->cur.val,
	408	s->mixer_gain->cur.val, s->if_gain->val);
	409	break;
	410	default:
d939be3a	411	dev_dbg(&s->spi->dev, "unknown control %d\n", ctrl->id);
93203dd6 AP	412	ret = -EINVAL;
	413	}
	414
	415	return ret;
	416	}
	417
	418	static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
	419	.s_ctrl = msi001_s_ctrl,
	420	};
	421
	422	static int msi001_probe(struct spi_device *spi)
	423	{
	424	struct msi001 *s;
	425	int ret;
5fa51cc3 AP	426
5fa51cc3 AP	427	dev_dbg(&spi->dev, "\n");
93203dd6 AP	428
	429	s = kzalloc(sizeof(struct msi001), GFP_KERNEL);
	430	if (s == NULL) {
	431	ret = -ENOMEM;
	432	dev_dbg(&spi->dev, "Could not allocate memory for msi001\n");
	433	goto err_kfree;
	434	}
	435
	436	s->spi = spi;
952a70aa	437	s->f_tuner = bands[0].rangelow;
93203dd6 AP	438	v4l2_spi_subdev_init(&s->sd, spi, &msi001_ops);
	439
	440	/* Register controls */
	441	v4l2_ctrl_handler_init(&s->hdl, 5);
	442	s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
	443	V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
	444	s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
	445	V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
	446	v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false);
	447	s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
	448	V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
	449	s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
	450	V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
	451	s->if_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops,
	452	V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
	453	if (s->hdl.error) {
	454	ret = s->hdl.error;
	455	dev_err(&s->spi->dev, "Could not initialize controls\n");
	456	/* control init failed, free handler */
	457	goto err_ctrl_handler_free;
	458	}
	459
	460	s->sd.ctrl_handler = &s->hdl;
	461	return 0;
	462
	463	err_ctrl_handler_free:
	464	v4l2_ctrl_handler_free(&s->hdl);
	465	err_kfree:
	466	kfree(s);
	467	return ret;
	468	}
	469
	470	static int msi001_remove(struct spi_device *spi)
	471	{
	472	struct v4l2_subdev *sd = spi_get_drvdata(spi);
	473	struct msi001 *s = sd_to_msi001(sd);
5fa51cc3 AP	474
5fa51cc3 AP	475	dev_dbg(&spi->dev, "\n");
93203dd6 AP	476
	477	/*
	478	* Registered by v4l2_spi_new_subdev() from master driver, but we must
	479	* unregister it from here. Weird.
	480	*/
	481	v4l2_device_unregister_subdev(&s->sd);
	482	v4l2_ctrl_handler_free(&s->hdl);
	483	kfree(s);
	484	return 0;
	485	}
	486
	487	static const struct spi_device_id msi001_id[] = {
	488	{"msi001", 0},
	489	{}
	490	};
	491	MODULE_DEVICE_TABLE(spi, msi001_id);
	492
	493	static struct spi_driver msi001_driver = {
	494	.driver = {
	495	.name = "msi001",
	496	.owner = THIS_MODULE,
	497	},
	498	.probe = msi001_probe,
	499	.remove = msi001_remove,
	500	.id_table = msi001_id,
	501	};
	502	module_spi_driver(msi001_driver);
	503
	504	MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
	505	MODULE_DESCRIPTION("Mirics MSi001");
	506	MODULE_LICENSE("GPL");